24AA256/24LC256/24FC256
256K I2C Serial EEPROM
Device Selection Table
Part Number
VCC Range
Max. Clock Frequency
24AA256
1.7V-5.5V
24LC256
2.5V-5.5V
400 kHz
1.7V-5.5V
MHz(2)
24FC256
Note 1:
2:
400
1
Temp. Ranges
kHz(1)
Available Packages
I, E
MF, MS, P, SN, SM, MNY, ST, CS
I, E
MF, MS, P, SN, SM, MNY, ST
I
MF, MS, P, SN, SM, MNY, ST
100 kHz for VCC < 2.5V.
400 kHz for VCC < 2.5V.
Features
Packages
• Single Supply with Operation Down to 1.7V for
24AA256 and 24FC256 Devices, 2.5V for
24LC256 Devices
• Low-Power CMOS Technology:
- Write current: 3 mA, maximum
- Standby current: 1 µA maximum (I-temp.)
• Two-Wire Serial Interface, I2C Compatible
• Cascadable up to Eight Devices
• Schmitt Trigger Inputs for Noise Suppression
• Output Slope Control to Eliminate Ground Bounce
• 100 kHz, 400 kHz and 1 MHz Compatibility
• Page Write Time: 5 ms, maximum
• Self-Timed Erase/Write Cycle
• 64-Byte Page Write Buffer
• Hardware Write-Protect
• ESD Protection >4000V
• More than One Million Erase/Write Cycles
• Data Retention >200 years
• Factory Programming Available
• RoHS Compliant
• Temperature Ranges:
- Industrial (I):
-40C to +85C
- Extended (E):
-40C to +125C
• 8-Lead DFN, 8-Lead MSOP, 8-Lead PDIP,
8-Lead SOIC, 8-Lead SOIJ, 8-Lead TDFN,
8-Lead TSSOP and 8-Ball CSP
Description
The Microchip Technology Inc. 24XX256(1) is a 32K x 8
(256 Kbit) Serial Electrically Erasable PROM, capable
of operation across a broad voltage range (1.7V to
5.5V). It has been developed for advanced, low-power
applications such as personal communications or data
acquisition. This device also has a page write capability
of up to 64 bytes of data. This device is capable of both
random and sequential reads up to the 256K boundary.
Functional address lines allow up to eight devices on
the same bus, for up to 2 Mbit address space.
Note 1: 24XX256 is used in this document as a
generic part number for the 24AA256/
24LC256/24FC256 devices.
• Automotive AEC-Q100 Qualified
Package Types
Note
1:
8
VCC
A0
11
7
WP
A1
22
SCL
SDA
A2
6
5
VSS
33
44
(1)
88
VCC
77
66
WP
SCL
55
SDA
8-Ball CSP
(Top View)
8-Lead SOIC/SOIJ/TSSOP
(Top View)
A0
A1
1
A2
3
VSS
4
2
24XX256
1
A1 2
A2 3
VSS 4
8-Lead PDIP/MSOP
(Top View)
24XX256
A0
24XX256
8-Lead DFN/TDFN
(Top View)
8
VCC
7
WP
6
SCL
5
SDA
VCC A1 A0
2
1
4
WP
6
3
5
7
A2
8
SDA SCL VSS
Pins A0 and A1 are no connects for the MSOP package only.
1998-2019 Microchip Technology Inc.
DS20001203W-page 1
24AA256/24LC256/24FC256
Block Diagram
A0 A1A2 WP
I/O
Control
Logic
Memory
Control
Logic
HV Generator
XDEC
EEPROM
Array
Page Latches
I/O
SCL
YDEC
SDA
VCC
VSS
DS20001203W-page 2
Sense Amp.
R/W Control
1998-2019 Microchip Technology Inc.
24AA256/24LC256/24FC256
1.0
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings(†)
VCC.............................................................................................................................................................................6.5V
All inputs and outputs w.r.t. VSS ..........................................................................................................-0.6V to VCC +1.0V
Storage temperature ............................................................................................................................... -65°C to +150°C
Ambient temperature with power applied................................................................................................ -40°C to +125°C
ESD protection on all pins 4 kV
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions above those
indicated in the operational listings of this specification is not implied. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
TABLE 1-1:
DC CHARACTERISTICS
Electrical Characteristics:
Industrial (I):
VCC = +1.7V to 5.5V
Extended (E):
VCC = +1.7V to 5.5V
DC CHARACTERISTICS
Param.
Symbol
No.
Characteristic
Min.
Max.
Units
TA = -40°C to +85°C
TA = -40°C to +125°C
Conditions
D1
VIH
High-Level Input Voltage
0.7 VCC
—
V
D2
VIL
Low-Level Input Voltage
—
0.3 VCC
0.2 VCC
V
V
VCC 2.5V
VCC < 2.5V
D3
VHYS
0.05 VCC
—
V
VCC 2.5V (Note)
D4
VOL
Low-Level Output Voltage
—
0.40
V
IOL = 3.0 mA @ VCC = 4.5V
IOL = 2.1 mA @ VCC = 2.5V
D5
ILI
Input Leakage Current
—
±1
µA
VIN = VSS or VCC, WP = VSS
VIN = VSS or VCC, WP = VCC
D6
ILO
Output Leakage Current
—
±1
µA
VOUT = VSS or VCC
D7
CIN,
COUT
Pin Capacitance
(all inputs/outputs)
—
10
pF
VCC = 5.0V (Note)
TA = 25°C, FCLK = 1 MHz
ICC Read Operating Current
—
400
µA
VCC = 5.5V, SCL = 400 kHz
ICC Write
—
3
mA
VCC = 5.5V
—
1
µA
SDA = SCL = VCC = 3.6V
A0, A1, A2, WP = VSS, I-Temp.
—
1.5
µA
SDA = SCL = VCC = 5.5V
A0, A1, A2, WP = VSS, I-Temp.
—
5
µA
SDA = SCL = VCC = 5.5V
A0, A1, A2, WP = VSS, E-Temp.
D8
D9
Note:
ICCS
Hysteresis of Schmitt Trigger
Inputs (SDA, SCL pins)
Standby Current
This parameter is periodically sampled and not 100% tested.
1998-2019 Microchip Technology Inc.
DS20001203W-page 3
24AA256/24LC256/24FC256
TABLE 1-2:
AC CHARACTERISTICS
Electrical Characteristics:
Industrial (I):
VCC = +1.7V to 5.5V
Extended (E):
VCC = +1.7V to 5.5V
AC CHARACTERISTICS
Param.
Symbol
No.
1
FCLK
2
THIGH
3
TLOW
4
TR
5
TF
6
Characteristic
Clock Frequency
Clock High Time
Clock Low Time
SDA and SCL Rise Time
SDA and SCL Fall Time
THD:STA Start Condition Hold Time
7
TSU:STA Start Condition Setup Time
8
THD:DAT Data Input Hold Time
9
TSU:DAT Data Input Setup Time
10
TSU:STO Stop Condition Setup Time
Note 1:
2:
3:
4:
TA = -40°C to +85°C
TA = -40°C to +125°C
Min.
Max.
Units
Conditions
—
100
kHz
1.7V VCC 2.5V
—
400
kHz
2.5V VCC 5.5V
—
400
kHz
1.7V VCC 2.5V (24FC256)
—
1000
kHz
2.5V VCC 5.5V (24FC256)
4000
—
ns
1.7V VCC 2.5V
600
—
ns
2.5V VCC 5.5V
600
—
ns
1.7V VCC 2.5V (24FC256)
500
—
ns
2.5V VCC 5.5V (24FC256)
4700
—
ns
1.7V VCC 2.5V
1300
—
ns
2.5V VCC 5.5V
1300
—
ns
1.7V VCC 2.5V (24FC256)
500
—
ns
2.5V VCC 5.5V (24FC256)
—
1000
ns
1.7V VCC 2.5V (Note 1)
—
300
ns
2.5V VCC 5.5V (Note 1)
—
300
ns
1.7V VCC 5.5V (24FC256)
(Note 1)
—
300
ns
All except 24FC256 (Note 1)
—
100
ns
1.7V VCC 5.5V (24FC256)
(Note 1)
4000
—
ns
1.7V VCC 2.5V
600
—
ns
2.5V VCC 5.5V
600
—
ns
1.7V VCC 2.5V (24FC256)
250
—
ns
2.5V VCC 5.5V (24FC256)
4700
—
ns
1.7V VCC 2.5V
600
—
ns
2.5V VCC 5.5V
600
—
ns
1.7V VCC 2.5V (24FC256)
250
—
ns
2.5V VCC 5.5V (24FC256)
0
—
ns
Note 2
250
—
ns
1.7V VCC 2.5V
100
—
ns
2.5V VCC 5.5V
100
—
ns
1.7V VCC 5.5V (24FC256)
4000
—
ns
1.7V VCC 2.5V
600
—
ns
2.5V VCC 5.5V
600
—
ns
1.7V VCC 2.5V (24FC256)
250
—
ns
2.5V VCC 5.5V (24FC256)
Not 100% tested. CB = total capacitance of one bus line in pF.
As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
The combined TSP and VHYS specifications are due to new Schmitt Trigger inputs, which provide improved
noise spike suppression. This eliminates the need for a TI specification for standard operation.
This parameter is not tested but ensured by characterization. For endurance estimates in a specific
application, please consult the Total Endurance™ Model, which can be obtained from Microchip’s website
at www.microchip.com.
DS20001203W-page 4
1998-2019 Microchip Technology Inc.
24AA256/24LC256/24FC256
TABLE 1-2:
AC CHARACTERISTICS
AC CHARACTERISTICS (Continued)
Param.
Symbol
No.
11
Characteristic
TSU:WP WP Setup Time
12
THD:WP WP Hold Time
13
TAA
14
TBUF
15
TOF
Output Valid from Clock
Bus Free Time: The time the
bus must be free before a new
transmission can start
Output fall time from VIH
minimum to VIL maximum
CB 100 pF
Electrical Characteristics:
Industrial (I):
VCC = +1.7V to 5.5V
Extended (E):
VCC = +1.7V to 5.5V
Min.
Max.
Units
4000
—
ns
1.7V VCC 2.5V
600
—
ns
2.5V VCC 5.5V
600
—
ns
1.7V VCC 5.5V (24FC256)
4700
—
ns
1.7V VCC 2.5V
1300
—
ns
2.5V VCC 5.5V
1300
—
ns
1.7V VCC 5.5V (24FC256)
—
3500
ns
1.7 V VCC 2.5V (Note 2)
—
900
ns
2.5 V VCC 5.5V (Note 2)
—
900
ns
1.7V VCC 2.5V (24FC256)
(Note 2)
—
400
ns
2.5 V VCC 5.5V (24FC256)
(Note 2)
4700
—
ns
1.7V VCC 2.5V
1300
—
ns
2.5V VCC 5.5V
1300
—
ns
1.7V VCC 2.5V (24FC256)
500
—
ns
2.5V VCC 5.5V (24FC256)
10 + 0.1CB
250
ns
All except 24FC256 (Note 1)
ns
All except 24FC256 (Note 1)
All except 24FC256
(Notes 1 and 3)
TSP
Input Filter Spike Suppression
(SDA and SCL pins)
—
50
ns
17
TWC
Write Cycle Time
(byte or page)
—
5
ms
1,000,000
—
18
Endurance
3:
4:
Conditions
250
16
Note 1:
2:
TA = -40°C to +85°C
TA = -40°C to +125°C
cycles 25°C, 5.5V, Page mode (Note 4)
Not 100% tested. CB = total capacitance of one bus line in pF.
As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
The combined TSP and VHYS specifications are due to new Schmitt Trigger inputs, which provide improved
noise spike suppression. This eliminates the need for a TI specification for standard operation.
This parameter is not tested but ensured by characterization. For endurance estimates in a specific
application, please consult the Total Endurance™ Model, which can be obtained from Microchip’s website
at www.microchip.com.
1998-2019 Microchip Technology Inc.
DS20001203W-page 5
24AA256/24LC256/24FC256
FIGURE 1-1:
BUS TIMING DATA
5
SCL
7
SDA
IN
3
4
D3
2
8
10
9
6
16
14
13
SDA
OUT
WP
DS20001203W-page 6
(protected)
(unprotected)
11
12
1998-2019 Microchip Technology Inc.
24AA256/24LC256/24FC256
2.0
PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 2-1.
TABLE 2-1:
Name
PIN FUNCTION TABLE
DFN
(1)
MSOP
PDIP
SOIC
SOIJ
TDFN(1)
TSSOP
CSP
Function
A0
1
—
1
1
1
1
1
3
User Configurable Chip Select
A1
2
—
2
2
2
2
2
2
User Configurable Chip Select
A2
3
3
3
3
3
3
3
5
User Configurable Chip Select
VSS
4
4
4
4
4
4
4
8
Ground
SDA
5
5
5
5
5
5
5
6
Serial Address/Data I/O
SCL
6
6
6
6
6
6
6
7
Serial Clock
WP
7
7
7
7
7
7
7
4
Write-Protect Input
VCC
8
8
8
8
8
8
8
1
Power Supply
Note 1: Exposed pad on DFN/TDFN can be connected to VSS or left floating.
2.1
A0, A1, A2 Chip Address Inputs
The A0, A1 and A2 inputs are used by the 24XX256 for
multiple device operations. The levels on these inputs
are compared with the corresponding bits in the slave
address. The chip is selected if the compare is true.
Note:
For the MSOP package only, pins A0 and
A1 are not connected.
Up to eight devices (two for the MSOP package) may
be connected to the same bus by using different Chip
Select bit combinations. These inputs must be
connected to either VCC or VSS.
2.3
Serial Clock (SCL)
This input is used to synchronize the data transfer to
and from the device.
2.4
Write-Protect (WP)
This pin must be connected to either VSS or VCC. If tied
to VSS, write operations are enabled. If tied to VCC,
write operations are inhibited but read operations are
not affected.
In most applications, the chip address inputs A0, A1
and A2 are hard-wired to logic ‘0’ or logic ‘1’. For
applications in which these pins are controlled by a
microcontroller or other programmable device, the chip
address pins must be driven to logic ‘0’ or logic ‘1’
before normal device operation can proceed.
2.2
Serial Data (SDA)
This is a bidirectional pin used to transfer addresses
and data into and out of the device. It is an open-drain
terminal. Therefore, the SDA bus requires a pull-up
resistor to VCC (typical 10 k for 100 kHz, 2 k for
400 kHz and 1 MHz).
For normal data transfer, SDA is allowed to change
only during SCL low. Changes during SCL high are
reserved for indicating the Start and Stop conditions.
1998-2019 Microchip Technology Inc.
DS20001203W-page 7
24AA256/24LC256/24FC256
3.0
FUNCTIONAL DESCRIPTION
The 24XX256 supports a bidirectional two-wire bus and
data transmission protocol. A device that sends data
onto the bus is defined as a transmitter and a device
receiving data as a receiver. The bus must be
controlled by a master device which generates the
Serial Clock (SCL), controls the bus access, and
generates the Start and Stop conditions while the
24XX256 works as a slave. Both master and slave can
operate as a transmitter or receiver, but the master
device determines which mode is activated.
4.0
BUS CHARACTERISTICS
The following bus protocol has been defined:
• Data transfer may be initiated only when the bus
is not busy.
• During data transfer, the data line must remain
stable whenever the clock line is high. Changes in
the data line, while the clock line is high, will be
interpreted as a Start or Stop condition.
Accordingly, the following bus conditions have been
defined (Figure 4-1).
4.4
The state of the data line represents valid data when,
after a Start condition, the data line is stable for the
duration of the high period of the clock signal.
The data on the line must be changed during the low
period of the clock signal. There is one bit of data per
clock pulse.
Each data transfer is initiated with a Start condition and
terminated with a Stop condition. The number of the
data bytes transferred between the Start and Stop
conditions is determined by the master device and is,
theoretically, unlimited (although only the last 64 will be
stored when doing a write operation). When an overwrite does occur it will replace data in a first-in-first-out
(FIFO) principle.
4.5
Bus Not Busy (A)
Both data and clock lines remain high.
4.2
Start Data Transfer (B)
A high-to-low transition of the SDA line while the clock
(SCL) is high, determines a Start condition. All
commands must be preceded by a Start condition.
4.3
Stop Data Transfer (C)
A low-to-high transition of the SDA line, while the clock
(SCL) is high, determines a Stop condition. All
operations must end with a Stop condition.
DS20001203W-page 8
Acknowledge
Each receiving device, when addressed, is obliged to
generate an Acknowledge signal after the reception of
each byte. The master device must generate an extra
clock pulse which is associated with this Acknowledge
bit.
Note:
4.1
Data Valid (D)
The 24XX256 does not generate any
Acknowledge bits if an internal
programming cycle is in progress.
A device that acknowledges must pull down the SDA
line during the Acknowledge clock pulse in such a way
that the SDA line is stable-low during the high period of
the Acknowledge-related clock pulse. Moreover, setup
and hold times must be taken into account. During
reads, a master must signal an end of data to the slave
by NOT generating an Acknowledge bit on the last byte
that has been clocked out of the slave. In this case, the
slave (24XX256) will leave the data line high to enable
the master to generate the Stop condition.
1998-2019 Microchip Technology Inc.
24AA256/24LC256/24FC256
FIGURE 4-1:
(A)
DATA TRANSFER SEQUENCE ON THE SERIAL BUS
(B)
(D)
Start
Condition
Address or
Acknowledge
Valid
(D)
(C)
(A)
SCL
SDA
FIGURE 4-2:
Stop
Condition
Data
Allowed
to Change
ACKNOWLEDGE TIMING
Acknowledge
Bit
SCL
SDA
1
2
3
4
5
6
7
Data from transmitter
Transmitter must release the SDA line at this point,
allowing the Receiver to pull the SDA line low to
acknowledge the previous eight bits of data.
1998-2019 Microchip Technology Inc.
8
9
1
2
3
Data from transmitter
Receiver must release the SDA line
at this point so the Transmitter can
continue sending data.
DS20001203W-page 9
24AA256/24LC256/24FC256
5.0
DEVICE ADDRESSING
FIGURE 5-1:
A control byte is the first byte received following the
Start condition from the master device. The control byte
consists of a 4-bit control code. For the 24XX256, this
is set as ‘1010’ binary for read and write operations.
The next three bits of the control byte are the Chip
Select bits (A2, A1, A0). The Chip Select bits allow the
use of up to eight 24XX256 devices on the same bus
and are used to select which device is accessed. The
Chip Select bits in the control byte must correspond to
the logic levels on the corresponding A2, A1 and A0
pins for the device to respond. These bits, in effect, are
the three Most Significant bits of the word address. The
combination of the 4-bit control code and the next three
bits are called the slave address.
For the MSOP package, the A0 and A1 pins are not
connected. During device addressing, the A0 and A1
Chip Select bits (Figures 5-1 and 5-2) should be set
to ‘0’. Only two 24XX256 MSOP packages can be
connected to the same bus.
The last bit of the control byte is the Read/Write (R/W)
bit and it defines the operation to be performed. When
set to ‘1’, a read operation is selected. When set to ‘0’,
a write operation is selected. The next two bytes
received define the address of the first data byte
(Figure 5-2). Because only A14…A0 are used, the
upper address bits are a “don’t care.” The upper
address bits are transferred first, followed by the Least
Significant bits.
Following the Start condition, the 24XX256 monitors
the SDA bus checking the device type identifier being
transmitted. Upon receiving a ‘1010’ code and
appropriate device select bits, the slave device outputs
an Acknowledge signal on the SDA line. Depending on
the state of the R/W bit, the 24XX256 will select a read
or write operation.
FIGURE 5-2:
0
1
Read/Write Bit
Chip Select
Bits
Control Code
S
1
0
1
A2
0
A1
A0 R/W ACK
Slave Address
Start Bit
5.1
Acknowledge Bit
Contiguous Addressing Across
Multiple Devices
The Chip Select bits A2, A1 and A0 can be used to
expand the contiguous address space for up to 2 Mbit
by adding up to eight 24XX256 devices on the same
bus. In this case, software can use A0 of the control
byte as address bit A15; A1 as address bit A16; and A2
as address bit A17. It is not possible to sequentially
read across device boundaries.
For the MSOP package, up to two 24XX256 devices
can be added for up to 512 Kbit of address space. In
this case, software can use A2 of the control byte as
address bit A17. Bits A0 (A15) and A1 (A16) of the
control byte must always be set to a logic ‘0’ for the
MSOP.
ADDRESS SEQUENCE BIT ASSIGNMENTS
Control Byte
1
CONTROL BYTE
FORMAT
0
A
2
Control
Code
A
1
Address High Byte
A
0 R/W
x
A A A A A
14 13 12 11 10
Address Low Byte
A
9
A
8
A
7
•
•
•
•
•
•
A
0
Chip
Select
Bits
x = “don’t care” bit
DS20001203W-page 10
1998-2019 Microchip Technology Inc.
24AA256/24LC256/24FC256
6.0
WRITE OPERATIONS
6.1
Byte Write
Following the Start condition from the master, the
control code (four bits), the Chip Select (three bits) and
the R/W bit (which is a logic low) are clocked onto the
bus by the master transmitter. This indicates to the
addressed slave receiver that the address high byte will
follow after it has generated an Acknowledge bit during
the ninth clock cycle. Therefore, the next byte
transmitted by the master is the high-order byte of the
word address and will be written into the Address
Pointer of the 24XX256. The next byte is the Least
Significant Address Byte. After receiving another
Acknowledge signal from the 24XX256, the master
device will transmit the data word to be written into the
addressed memory location. The 24XX256 acknowledges again and the master generates a Stop
condition. This initiates the internal write cycle and
during this time, the 24XX256 will not generate
Acknowledge signals (Figure 6-1). If an attempt is
made to write to the array with the WP pin held high, the
device will acknowledge the command but no write
cycle will occur, no data will be written, and the device
will immediately accept a new command. After a byte
write command, the internal address counter will point
to the address location following the one that was just
written.
Note:
6.2
Note:
6.3
Page write operations are limited to
writing bytes within a single physical page,
regardless of the number of bytes
actually being written. Physical page
boundaries start at addresses that are
integer multiples of the page buffer size
(or ‘page size’) and end at addresses that
are integer multiples of page size – 1. If a
page write command attempts to write
across a physical page boundary, the
result is that the data wraps around to the
beginning of the current page (overwriting
data previously stored there), instead of
being written to the next page, as might be
expected. It is, therefore, necessary for
the application software to prevent page
write operations that would attempt to
cross a page boundary.
Write Protection
The WP pin allows the user to write-protect the entire
array (0000-7FFF) when the pin is tied to VCC. If tied to
VSS the write protection is disabled. The WP pin is
sampled at the Stop bit for every write command
(Figure 1-1). Toggling the WP pin after the Stop bit will
have no effect on the execution of the write cycle.
When doing a write of less than 64 bytes,
the data in the rest of the page is
refreshed along with the data bytes being
written. This will force the entire page to
endure a write cycle, for this reason
endurance is specified per page.
Page Write
The write control byte, word address and the first data
byte are transmitted to the 24XX256 in much the same
way as in a byte write. The exception is that instead of
generating a Stop condition, the master transmits up to
63 additional bytes, which are temporarily stored in the
on-chip page buffer, and will be written into memory
once the master has transmitted a Stop condition.
Upon receipt of each word, the six lower Address
Pointer bits, which form the byte counter, are internally
incremented by one. If the master should transmit more
than 64 bytes prior to generating the Stop condition, the
address counter will roll over and the previously
received data will be overwritten. As with the byte write
operation, once the Stop condition is received, an internal write cycle will begin (Figure 6-2). If an attempt is
made to write to the array with the WP pin held high, the
device will acknowledge the command, but no write
cycle will occur, no data will be written and the device
will immediately accept a new command.
1998-2019 Microchip Technology Inc.
DS20001203W-page 11
24AA256/24LC256/24FC256
FIGURE 6-1:
BYTE WRITE
SDA Line
S
T
A
R
T
Bus Activity
AA
S101 0A
2 10 0
Bus Activity
Master
Control
Byte
Bus Activity
Master
SDA Line
Bus Activity
S
T
O
P
Data
P
A
C
K
A
C
K
A
C
K
PAGE WRITE
S
T
A
R
T
Control
Byte
Address
High Byte
AAA
S10102 1 00
x = “don’t care” bit
7.0
Address
Low Byte
x
A
C
K
x = “don’t care” bit
FIGURE 6-2:
Address
High Byte
Address
Low Byte
S
T
O
P
Data Byte 63
Data Byte 0
P
x
A
C
K
ACKNOWLEDGE POLLING
Since the device will not acknowledge during a write
cycle, this can be used to determine when the cycle is
complete (This feature can be used to maximize bus
throughput). Once the Stop condition for a write
command has been issued from the master, the device
initiates the internally timed write cycle. ACK polling
can be initiated immediately. This involves the master
sending a Start condition, followed by the control byte
for a write command (R/W = 0). If the device is still
busy with the write cycle, then no ACK will be returned.
If no ACK is returned, the Start bit and control byte must
be resent. If the cycle is complete, then the device will
return the ACK and the master can then proceed with
the next read or write command. See Figure 7-1 for
flow diagram.
A
C
K
A
C
K
A
C
K
FIGURE 7-1:
A
C
K
ACKNOWLEDGE
POLLING FLOW
Send
Write Command
Send Stop
Condition to
Initiate Write Cycle
Send Start
Send Control Byte
with R/W = 0
Did Device
Acknowledge
(ACK = 0)?
NO
YES
Next
Operation
DS20001203W-page 12
1998-2019 Microchip Technology Inc.
24AA256/24LC256/24FC256
8.0
READ OPERATION
8.2
Random read operations allow the master to access
any memory location in a random manner. To perform
this type of read operation, the word address must first
be set. This is done by sending the word address to the
24XX256 as part of a write operation (R/W bit set
to ‘0’). Once the word address is sent, the master generates a Start condition following the Acknowledge.
This terminates the write operation, but not before the
internal Address Pointer is set. The master then issues
the control byte again, but with the R/W bit set to a one.
The 24XX256 will then issue an Acknowledge and
transmit the 8-bit data word. The master will not
acknowledge the transfer, though it does generate a
Stop condition, which causes the 24XX256 to discontinue transmission (Figure 8-2). After a random read
command, the internal address counter will point to the
address location following the one that was just read.
Read operations are initiated in much the same way as
write operations, with the exception that the R/W bit of
the control byte is set to ‘1’. There are three basic types
of read operations: current address read, random read
and sequential read.
8.1
Current Address Read
The 24XX256 contains an address counter that maintains the address of the last word accessed, internally
incremented by one. Therefore, if the previous read
access was to address n (n is any legal address), the
next current address read operation would access data
from address n + 1.
Upon receipt of the control byte with R/W bit set to ‘1’,
the 24XX256 issues an Acknowledge and transmits the
8-bit data word. The master will not acknowledge the
transfer, but does generate a Stop condition and the
24XX256 discontinues transmission (Figure 8-1).
FIGURE 8-1:
SDA Line
Control
Byte
FIGURE 8-2:
SDA Line
P
A
C
K
Sequential Read
Sequential reads are initiated in the same way as a
random read except that after the 24XX256 transmits
the first data byte, the master issues an Acknowledge
(as opposed to the Stop condition used in a random
read). This Acknowledge directs the 24XX256 to
transmit the next sequentially addressed 8-bit word
(Figure 8-3). Following the final byte transmitted to the
master, the master will NOT generate an Acknowledge,
but will generate a Stop condition.
S
T
O
P
Data
Byte
S 1 0 1 0 A AA 1
2 1 0
Bus Activity
Bus Activity
Master
8.3
CURRENT ADDRESS
READ
S
T
A
R
T
Bus Activity
Master
Random Read
N
O
To provide sequential reads, the 24XX256 contains an
internal Address Pointer which is incremented by one
at the completion of each operation. This Address
Pointer allows the entire memory contents to be serially
read during one operation. The internal Address
Pointer will automatically roll over from address 7FFF
to address 0000 if the master acknowledges the byte
received from the array address 7FFF.
A
C
K
RANDOM READ
S
T
A
R
T
Control
Byte
S1 010 AAA0
2 1 0
Bus Activity
x = “don’t care” bit
1998-2019 Microchip Technology Inc.
Address
High Byte
S
T
A
R
T
Address
Low Byte
x
A
C
K
A
C
K
A
C
K
Control
Byte
S 1 0 1 0 A A A1
2 1 0
S
T
O
P
Data
Byte
P
A
C
K
N
O
A
C
K
DS20001203W-page 13
24AA256/24LC256/24FC256
FIGURE 8-3:
Bus Activity
Master
SEQUENTIAL READ
Control
Byte
Data (n)
Data (n + 1)
S
T
O
P
Data (n + x)
Data (n + 2)
P
SDA Line
Bus Activity
DS20001203W-page 14
A
C
K
A
C
K
A
C
K
A
C
K
N
O
A
C
K
1998-2019 Microchip Technology Inc.
24AA256/24LC256/24FC256
9.0
PACKAGING INFORMATION
9.1
Package Marking Information
8-Lead DFN-S
Example
XXXXXXX
XXXXXXX
YYWW
NNN
24LC256
I/MF e3
1926
13F
8-Lead MSOP
Example
XXXXXX
YWWNNN
4L256I
92613F
8-Lead PDIP (300 mil)
Example
XXXXXXXX
XXXXXNNN
YYWW
24AA256
I/P e3 13F
1926
8-Lead SOIC (3.90 mm)
Example
XXXXXXXX
XXXXYYWW
NNN
24LC256I
SN e3 1926
13F
8-Lead SOIJ (5.28 mm)
Example
XXXXXXXX
XXXXXXXX
YYWWNNN
1998-2019 Microchip Technology Inc.
24LC256
I/SM e3
192613F
DS20001203W-page 15
24AA256/24LC256/24FC256
Package Marking Information (Continued)
8-Lead TDFN
Example
XXX
YWW
NN
EF4
1926
13
8-Lead TSSOP
Example
XXXX
XYWW
NNN
4LD
I926
13F
Example
8-Lead Chip Scale
249
A192
613F
XXX
XYYW
WNNN
1st Line Marking Codes
Part
No.
DFN
MSOP
24AA256
24AA256
4A256T(1)
24LC256
24LC256
4L256T(1)
24LC256
24FC256
24FC256
4F256T(1)
Note 1:
PDIP
SOIC
SOIJ
TDFN
TSSOP
CSP
4AD
249
I-Temp.
E-Temp.
24AA256 24AA256T(1) 24AA256
EF6
EF5
24LC256T(1)
24LC256
EF4
EF3
4LD
—
24FC256 24FC256T(1) 24FC256
EF8
—
4FD
—
T = Temperature grade (I, E)
Legend: XX...X
T
Y
YY
WW
NNN
e3
Part number or part number code
Temperature (I, E)
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code (2 characters for small packages)
JEDEC® designator for Matte Tin (Sn)
* Standard OTP marking consists of Microchip part number, year code, week code and
traceability code.
Note:
For very small packages with no room for the JEDEC® designator
e3 , the marking will only appear on the outer carton or reel label.
Note:
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
DS20001203W-page 16
1998-2019 Microchip Technology Inc.
24AA256/24LC256/24FC256
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2
2
NOTE 1
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D2
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TOP VIEW
A
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NOTE 2
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