24LC64-I/SN

24AA64/24FC64/24LC64 64-Kbit I2C Serial EEPROM Device Selection Table Part Number 24AA64 VCC Range Max. Clock Frequency Temp. Ranges 1.7V-5.5V 400 kHz(1) I, E MHz(2) 24FC64 1.7V-5.5V 1 24LC64 2.5V-5.5V 400 kHz Note 1: 2: Packages CS, MC, MS, P, SN, SM, OT, MNY, ST, X/ST I MC, MF, MS, P, SN, SM, OT, MNY, ST I, E MC, MS, P, SN, SM, OT, MNY, ST, X/ST 100 kHz for VCC < 2.5V 400 kHz for VCC < 2.5V Features Packages • Single Supply with Operation Down to 1.7V for 24AA64 and 24FC64 Devices and 2.5V for 24LC64 Devices • Low-Power CMOS Technology: - Active current: 3 mA, maximum - Standby current: 1 µA, maximum • Two-Wire Serial Interface, I2C Compatible • Packages with Three Address Pins are Cascadable Up to Eight Devices • Schmitt Trigger Inputs for Noise Suppression • Output Slope Control to Eliminate Ground Bounce • 100 kHz and 400 kHz Clock Compatibility • 1 MHz Clock for FC versions • Page Write Time: 5 ms, Maximum • Self-Timed Erase/Write Cycle • 32-Byte Page Write Buffer • Hardware Write-Protect • ESD Protection > 4,000V • More Than 1 Million Erase/Write Cycles • Data Retention > 200 Years • Factory Programming Available • RoHS Compliant • Temperature Ranges Supported: - Industrial (I): -40C to +85C - Extended (E): -40C to +125C • 5-Lead Chip Scale, 8-Lead DFN, 8-Lead DFN-S, 8-Lead MSOP, 8-Lead PDIP, 8-Lead SOIC, 8-Lead SOIJ, 5-Lead SOT-23, 8-Lead TDFN, 8-Lead TSSOP and 8-Lead X-Rotated TSSOP Description The Microchip Technology Inc. 24XX64(1) is a 64-Kbit Electrically Erasable PROM (EEPROM). The device is organized as a single block of 8K x 8-bit memory with a two-wire serial interface. Its low-voltage design permits operation down to 1.7V, with standby and active currents of only 1 µA and 3 mA, respectively. The 24XX64 also has a page write capability for up to 32 bytes of data. Functional address lines allow up to eight devices on the same bus, for up to 512-Kbit address space. Note 1: 24XX64 is used in this document as a generic part number for the 24AA64/24FC64/24LC64 devices. • Automotive AEC-Q100 Qualified Package Types CS (Chip Scale) VCC WP SCL 1 2 (1) VSS 3 4 5 SDA DFN/TDFN A0 1 A1 2 A2 3 VSS 4 MSOP/PDIP/SOIC/SOIJ/TSSOP A0 1 8 VCC A1 2 7 WP 6 SCL A2 3 6 SCL 5 SDA VSS 4 5 SDA 8 VCC 7 WP SOT-23 SCL 1 VSS 2 SDA 3 5 WP 4 WP VCC A0 VCC A1 X-Rotated TSSOP (X/ST) 1 2 3 4 8 7 6 5 SCL SDA VSS A2 (Top Down View, Balls Not Visible) Note 1: Available in I-temp, “AA” only.  1997-2022 Microchip Technology Inc. and its subsidiaries DS20001189U-page 1 24AA64/24FC64/24LC64 Block Diagram HV Generator A0 A1 A2 WP I/O Control Logic Memory Control Logic XDEC EEPROM Array Page Latches I/O SCL YDEC SDA VCC VSS DS20001189U-page 2 Sense Amp. R/W Control  1997-2022 Microchip Technology Inc. and its subsidiaries 24AA64/24FC64/24LC64 1.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings (†) VCC.............................................................................................................................................................................6.5V All inputs and outputs w.r.t. VSS ..........................................................................................................-0.3V to VCC +1.0V Storage temperature ............................................................................................................................... -65°C to +150°C Ambient temperature with power applied................................................................................................ -40°C to +125°C ESD protection on all pins  4 kV † NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. TABLE 1-1: DC CHARACTERISTICS DC CHARACTERISTICS Param. Symbol No. Characteristic Min. Typical Max. Units 0.7 VCC — — V — — 0.3 VCC V VCC  2.5V — — 0.2 VCC V VCC  2.5V 0.05 VCC — — V VCC  2.5V (Note 1) D1 VIH High-Level Input Voltage D2 VIL Low-Level Input Voltage D3 VHYS Hysteresis of Schmitt Trigger Inputs (SDA, SCL pins) D4 VOL Low-Level Output Voltage D5 ILI Input Leakage Current D6 ILO D7 CIN, COUT D8 ICC Write D9 ICC Read D10 Note 1: 2: ICCS Electrical Characteristics: Industrial (I): TA = -40°C to +85°C, VCC = +1.7V to +5.5V Extended (E): TA = -40°C to +125°C, VCC = +1.7V to +5.5V Conditions — — 0.40 V IOL = 3.0 mA @ VCC = 4.5V — — 0.40 V IOL = 2.1 mA @ VCC = 2.5V — — ±1 µA VIN = VSS or VCC, WP = VSS — — ±1 µA VIN = VSS or VCC, WP = VCC Output Leakage Current — — ±1 µA VOUT = VSS or VCC Pin Capacitance (all inputs/outputs) — — 10 pF VCC = 5.0V (Note 1) TA = 25°C, FCLK = 1 MHz — 0.1 3 mA VCC = 5.5V, SCL = 400 kHz — 0.05 400 µA VCC = 5.5V, SCL = 400 kHz — 0.01 1 µA SDA = SCL = VCC A0, A1, A2, WP = VSS, I-Temp. — — 5 µA SDA = SCL = VCC A0, A1, A2, WP = VSS, E-Temp. Operating Current Standby Current This parameter is periodically sampled and not 100% tested. Typical measurements taken at room temperature.  1997-2022 Microchip Technology Inc. and its subsidiaries DS20001189U-page 3 24AA64/24FC64/24LC64 TABLE 1-2: AC CHARACTERISTICS Electrical Characteristics: Industrial (I): VCC = +1.7V to +5.5V TA = -40°C to +85°C Extended (E): VCC = +1.7V to +5.5V TA = -40°C to +125°C AC CHARACTERISTICS Param. Symbol No. 1 FCLK 2 THIGH 3 TLOW 4 TR 5 TF Characteristic Clock Frequency Clock High Time Clock Low Time SDA and SCL Rise Time SDA and SCL Fall Time THD:STA Start Condition Hold Time 6 TSU:STA Start Condition Setup Time 7 Min. Max. Units Conditions — 100 kHz 1.7V  VCC  2.5V — 400 kHz 2.5V  VCC  5.5V — 400 kHz 1.7V  VCC  2.5V (24FC64) 2.5V  VCC  5.5V (24FC64) — 1000 kHz 4000 — ns 1.7V  VCC  2.5V 600 — ns 2.5V  VCC  5.5V 600 — ns 1.7V  VCC  2.5V (24FC64) 500 — ns 2.5V  VCC  5.5V (24FC64) 4700 — ns 1.7V  VCC  2.5V 1300 — ns 2.5V  VCC  5.5V 1300 — ns 1.7V  VCC  2.5V (24FC64) 500 — ns 2.5V  VCC  5.5V (24FC64) — 1000 ns 1.7V  VCC  2.5V (Note 1) — 300 ns 2.5V  VCC  5.5V (Note 1) — 300 ns 1.7V  VCC  5.5V (24FC64) (Note 1) — 300 ns 24AA64 and 24LC64 (Note 1) — 100 ns 1.7V  VCC  5.5V (24FC64) (Note 1) 4000 — ns 1.7V  VCC  2.5V 600 — ns 2.5V  VCC  5.5V 600 — ns 1.7V  VCC  2.5V (24FC64) 250 — ns 2.5V  VCC  5.5V (24FC64) 4700 — ns 1.7V  VCC  2.5V 600 — ns 2.5V  VCC  5.5V 600 — ns 1.7V  VCC  2.5V (24FC64) 250 — ns 2.5V  VCC  5.5V (24FC64) — ns Note 2 8 THD:DAT Data Input Hold Time 0 250 — ns 1.7V  VCC  2.5V 9 TSU:DAT Data Input Setup Time 100 — ns 2.5V  VCC  5.5V TSU:STO Stop Condition Setup Time 10 Note 1: 2: 3: 4: 100 — ns 1.7V  VCC  5.5V (24FC64) 4000 — ns 1.7V  VCC  2.5V 600 — ns 2.5V  VCC  5.5V 600 — ns 1.7V  VCC  2.5V (24FC64) 250 — ns 2.5V  VCC  5.5V (24FC64) Not 100% tested. CB = total capacitance of one bus line in pF. As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions. The combined TSP and VHYS specifications are due to new Schmitt Trigger inputs, which provide improved noise spike suppression. This eliminates the need for a TI specification for standard operation. This parameter is not tested but ensured by characterization. DS20001189U-page 4  1997-2022 Microchip Technology Inc. and its subsidiaries 24AA64/24FC64/24LC64 TABLE 1-2: AC CHARACTERISTICS Electrical Characteristics: Industrial (I): VCC = +1.7V to +5.5V TA = -40°C to +85°C Extended (E): VCC = +1.7V to +5.5V TA = -40°C to +125°C AC CHARACTERISTICS Param. Symbol No. 11 TSU:WP THD:WP 12 13 TAA 14 TBUF Characteristic WP Setup Time WP Hold Time Output Valid from Clock Bus Free Time: The time the bus must be free before a new transmission can start Min. Max. Units 4000 — ns 1.7V  VCC  2.5V 600 — ns 2.5V  VCC  5.5V 600 — ns 1.7V  VCC  5.5V (24FC64) 4700 — ns 1.7V  VCC  2.5V 1300 — ns 2.5V  VCC  5.5V 1300 — ns 1.7V  VCC  5.5V 24FC64 — 3500 ns 1.7V  VCC  2.5V (Note 2) — 900 ns 2.5V  VCC  5.5V (Note 2) — 900 ns 1.7V  VCC  2.5V (24FC64) (Note 2) — 400 ns 2.5V  VCC  5.5V (24FC64) (Note 2) 4700 — ns 1.7V  VCC  2.5V 1300 — ns 2.5V  VCC  5.5V 1300 — ns 1.7V  VCC  2.5V (24FC64) 500 — ns 2.5V  VCC  5.5V (24FC64) 10 + 0.1CB 250 ns 24AA64 and 24LC64 (Note 1) — 250 ns 24FC64 (Note 1) 24AA64 and 24LC64 (Note 1 and Note 3) 15 TOF Output Fall Time from VIH Minimum to VIL Maximum CB  100 pF 16 TSP Input Filter Spike Suppression (SDA and SCL pins) — 50 ns 17 TWC Write Cycle Time (byte or page) — 5 ms 1,000,000 — cycles 18 Endurance Note 1: 2: 3: 4: Conditions +25°C, 5.5V, Page Mode (Note 4) Not 100% tested. CB = total capacitance of one bus line in pF. As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions. The combined TSP and VHYS specifications are due to new Schmitt Trigger inputs, which provide improved noise spike suppression. This eliminates the need for a TI specification for standard operation. This parameter is not tested but ensured by characterization.  1997-2022 Microchip Technology Inc. and its subsidiaries DS20001189U-page 5 24AA64/24FC64/24LC64 FIGURE 1-1: BUS TIMING DATA 5 SCL SDA IN 7 3 4 D3 2 8 10 9 6 16 14 13 SDA OUT WP DS20001189U-page 6 (protected) (unprotected) 11 12  1997-2022 Microchip Technology Inc. and its subsidiaries 24AA64/24FC64/24LC64 2.0 PIN DESCRIPTIONS The descriptions of the pins are listed in Table 2-1. TABLE 2-1: PIN FUNCTION TABLE DFN(1) MSOP PDIP SOIC SOIJ SOT-23 TDFN(1) TSSOP Rotated TSSOP Name CS A0 — 1 1 1 1 1 — 1 1 3 Chip Address Input A1 — 2 2 2 2 2 — 2 2 4 Chip Address Input A2 — 3 3 3 3 3 — 3 3 5 Chip Address Input VSS 2 4 4 4 4 4 2 4 4 6 Ground Description SDA 5 5 5 5 5 5 3 5 5 7 Serial Address/Data I/O SCL 4 6 6 6 6 6 1 6 6 8 Serial Clock WP 3 7 7 7 7 7 5 7 7 1 Write-Protect Input VCC 1 8 8 8 8 8 4 8 8 2 Power Supply Note 1: 2.1 The exposed pad on the DFN/TDFN packages can be connected to VSS or left floating. A0, A1, A2 Chip Address Inputs The A0, A1 and A2 inputs are used by the 24XX64 for multiple device operation. The levels on these inputs are compared with the corresponding bits in the client address. The chip is selected if the compare is true. Up to eight devices may be connected to the same bus by using different Chip Select bit combinations. These inputs must be connected to either VCC or VSS. In most applications, the chip address inputs A0, A1 and A2 are hard-wired to logic ‘0’ or logic ‘1’. For applications in which these pins are controlled by a microcontroller or other programmable device, the chip address pins must be driven to logic ‘0’ or logic ‘1’ before normal device operation can proceed. Address pins are not available in the SOT-23 or Chip Scale packages. 2.2 2.3 Serial Clock (SCL) The SCL input is used to synchronize the data transfer from and to the device. 2.4 Write-Protect (WP) This pin must be connected to either VSS or VCC. If tied to VSS, write operations are enabled. If tied to VCC, write operations are inhibited but read operations are not affected. Serial Address/Data Input/Output (SDA) SDA is a bidirectional pin used to transfer addresses and data into and out of the device. Since it is an open-drain terminal, the SDA bus requires a pull-up resistor to VCC (typical 10 k for 100 kHz, 2 k for 400 kHz and 1 MHz). For normal data transfer, SDA is allowed to change only during SCL low. Changes during SCL high are reserved for indicating the Start and Stop conditions.  1997-2022 Microchip Technology Inc. and its subsidiaries DS20001189U-page 7 24AA64/24FC64/24LC64 3.0 FUNCTIONAL DESCRIPTION The 24XX64 supports a bidirectional, two-wire bus and data transmission protocol. A device that sends data onto the bus is defined as transmitter, while a device receiving data is defined as a receiver. The bus has to be controlled by a host device which generates the Serial Clock (SCL), controls the bus access and generates the Start and Stop conditions, while the 24XX64 works as client. Both host and client can operate as transmitter or receiver, but the host device determines which mode is activated. 4.0 BUS CHARACTERISTICS The following bus protocol has been defined: • Data transfer may be initiated only when the bus is not busy • During data transfer, the data line must remain stable whenever the clock line is high. Changes in the data line while the clock line is high will be interpreted as a Start or Stop condition Accordingly, the following bus conditions have been defined (Figure 4-1). 4.1 Start Data Transfer (B) A high-to-low transition of the SDA line while the clock (SCL) is high determines a Start condition. All commands must be preceded by a Start condition. 4.3 Stop Data Transfer (C) A low-to-high transition of the SDA line while the clock (SCL) is high determines a Stop condition. All operations must be ended with a Stop condition. FIGURE 4-1: (A) Data Valid (D) The state of the data line represents valid data when, after a Start condition, the data line is stable for the duration of the high period of the clock signal. The data on the line must be changed during the low period of the clock signal. There is one clock pulse per bit of data. Each data transfer is initiated with a Start condition and terminated with a Stop condition. The number of data bytes transferred between Start and Stop conditions is determined by the host device and is, theoretically, unlimited (although only the last 32 will be stored when doing a write operation). When an overwrite does occur, it will replace data in a First-In First-Out (FIFO) principle. 4.5 Acknowledge Each receiving device, when addressed, is obliged to generate an Acknowledge after the reception of each byte. The host device must generate an extra clock pulse which is associated with this Acknowledge bit. Note: Bus Not Busy (A) Both data and clock lines remain high. 4.2 4.4 The 24XX64 does not generate any Acknowledge bits if an internal programming cycle is in progress. The device that acknowledges has to pull down the SDA line during the Acknowledge clock pulse in such a way that the SDA line is stable-low during the high period of the Acknowledge-related clock pulse. Moreover, setup and hold times must be taken into account. During reads, a host must signal an end of data to the client by not generating an Acknowledge bit on the last byte that has been clocked out of the client. In this case, the client (24XX64) will leave the data line high to enable the host to generate the Stop condition. DATA TRANSFER SEQUENCE ON THE SERIAL BUS (B) (D) Start Condition Address or Acknowledge Valid (D) (C) (A) SCL SDA DS20001189U-page 8 Data Allowed to Change Stop Condition  1997-2022 Microchip Technology Inc. and its subsidiaries 24AA64/24FC64/24LC64 5.0 DEVICE ADDRESSING FIGURE 5-1: A control byte is the first byte received following the Start condition from the host device. The control byte consists of a 4-bit control code. For the 24XX64, this is set as ‘1010’ binary for read and write operations. The next three bits of the control byte are the Chip Select bits (A2, A1, A0). The Chip Select bits allow the use of up to eight 24XX64 devices on the same bus and are used to select which device is accessed. The Chip Select bits in the control byte must correspond to the logic levels on the corresponding A2, A1 and A0 pins for the device to respond. These bits are, in effect, the three Most Significant bits of the word address. The combination of the 4-bit control code and the next three bits are called the client address. For the SOT-23 and Chip Scale packages, the address pins are not available. During device addressing, the A2, A1 and A0 Chip Select bits should be set to ‘0’. The last bit of the control byte is the Read/Write (R/W) bit and it defines the operation to be performed. When set to a ‘1’, a read operation is selected. When set to a ‘0’, a write operation is selected. The next two bytes received define the address of the first data byte (Figure 5-2). Because only A12...A0 are used, the upper three address bits are “don’t care” bits. The upper address bits are transferred first, followed by the Less Significant bits. CONTROL BYTE FORMAT Read/Write Bit Chip Select Bits Control Code S 1 0 1 0 A2 A1 A0 R/W ACK Client Address Start Bit 5.1 Acknowledge Bit Contiguous Addressing Across Multiple Devices The Chip Select bits A2, A1 and A0 can be used to expand the contiguous address space for up to 512 Kbits by adding up to eight 24XX64 devices on the same bus. In this case, software can use A0 of the control byte as address bit A13; A1 as address bit A14; and A2 as address bit A15. It is not possible to sequentially read across device boundaries. The SOT-23 and Chip Scale packages do not support multiple device addressing on the same bus. Following the Start condition, the 24XX64 monitors the SDA bus, checking the device-type identifier being transmitted. Upon receiving a valid client address and the R/W bit, the client device outputs an Acknowledge signal on the SDA line. Depending on the state of the R/W bit, the 24XX64 will select a read or write operation. FIGURE 5-2: ADDRESS SEQUENCE BIT ASSIGNMENTS Control Byte 1 0 1 Control Code 0 A 2 A 1 Address High Byte A 0 R/W x Chip Select bits  1997-2022 Microchip Technology Inc. and its subsidiaries x x A A A 12 11 10 Address Low Byte A 9 A 8 A 7 • • • • • • A 0 x = “don’t care” bit DS20001189U-page 9 24AA64/24FC64/24LC64 6.0 WRITE OPERATIONS 6.1 Byte Write Following the Start condition from the host, the control code (four bits), the Chip Select (three bits) and the R/W bit (which is a logic low) are clocked onto the bus by the host transmitter. This indicates to the addressed client receiver that the address high byte will follow once it has generated an Acknowledge bit during the ninth clock cycle. Therefore, the next byte transmitted by the host is the high-order byte of the word address and will be written into the Address Pointer of the 24XX64. The next byte is the Least Significant Address byte. After receiving another Acknowledge signal from the 24XX64, the host device will transmit the data word to be written into the addressed memory location. The 24XX64 acknowledges again and the host generates a Stop condition. This initiates the internal write cycle and, during this time, the 24XX64 will not generate Acknowledge signals (Figure 6-1). If an attempt is made to write to the array with the WP pin held high, the device will acknowledge the command, but no write cycle will occur, no data will be written and the device will immediately accept a new command. After a byte Write command, the internal Address Pointer will point to the address location following the one that was just written. Note: 6.2 Page Write The write control byte, word address and the first data byte are transmitted to the 24XX64 in the same way as in a byte write. However, instead of generating a Stop condition, the host transmits up to 31 additional bytes which are temporarily stored in the on-chip page buffer and will be written into memory once the host has transmitted a Stop condition. Upon receipt of each word, the five lower Address Pointer bits, which form the byte counter, are internally incremented by one. The higher-order 8 bits of the word address remain constant. If the host should transmit more than 32 bytes prior to generating the Stop condition, the Address Pointer will roll over and the previously received data will be overwritten. As with the byte write operation, once the Stop condition is received, an internal write cycle will begin (Figure 6-2). If an attempt is made to write to the array with the WP pin held high, the device will acknowledge the command, but no write cycle will occur, no data will be written and the device will immediately accept a new command. Note: When doing a write of less than 32 bytes, the data in the rest of the page are refreshed along with the data bytes being written. This will force the entire page to endure a write cycle, for this reason endurance is specified per page. 6.3 Page write operations are limited to writing bytes within a single physical page, regardless of the number of bytes actually being written. Physical page boundaries start at addresses that are integer multiples of the page buffer size (or ‘page size’) and end at addresses that are integer multiples of page size – 1. If a page write command attempts to write across a physical page boundary, the result is that the data wrap around to the beginning of the current page (overwriting data previously stored there), instead of being written to the next page, as might be expected. It is therefore necessary for the application software to prevent page write operations that would attempt to cross a page boundary. Write Protection The WP pin allows the user to write-protect the entire array (0000-1FFF) when the pin is tied to VCC. If tied to VSS, the write protection is disabled. The WP pin is sampled at the Stop bit for every Write command (Figure 4-1). Toggling the WP pin after the Stop bit will have no effect on the execution of the write cycle. DS20001189U-page 10  1997-2022 Microchip Technology Inc. and its subsidiaries 24AA64/24FC64/24LC64 FIGURE 6-1: BYTE WRITE S T A R T Bus Activity Host Control Byte Address High Byte AA S1 010A 2 10 0 SDA Line S T O P Data xxx P A C K Bus Activity Address Low Byte A C K A C K A C K x = “don’t care” bit FIGURE 6-2: PAGE WRITE Bus Activity Host S T A R T SDA Line AA S 101 0A 2 1 00 Bus Activity Control Byte Address High Byte Address Low Byte Data Byte 0 S T O P Data Byte 31 P xxx A C K A C K A C K A C K A C K x = “don’t care” bit  1997-2022 Microchip Technology Inc. and its subsidiaries DS20001189U-page 11 24AA64/24FC64/24LC64 7.0 ACKNOWLEDGE POLLING Since the device will not acknowledge during a write cycle, this can be used to determine when the cycle is complete (this feature can be used to maximize bus throughput). Once the Stop condition for a write command has been issued from the host, the device initiates the internally-timed write cycle and ACK polling can then be initiated immediately. This involves the host sending a Start condition followed by the control byte for a write command (R/W = 0). If the device is still busy with the write cycle, then no ACK will be returned. If no ACK is returned, the Start bit and control byte must be resent. If the cycle is complete, the device will return the ACK and the host can then proceed with the next read or write operation. See Figure 7-1 for a flow diagram of this operation. FIGURE 7-1: ACKNOWLEDGE POLLING FLOW Send Write Command Send Stop Condition to Initiate Write Cycle Send Start Send Control Byte with R/W = 0 Did Device Acknowledge (ACK = 0)? No Yes Next Operation DS20001189U-page 12  1997-2022 Microchip Technology Inc. and its subsidiaries 24AA64/24FC64/24LC64 8.0 READ OPERATION Read operations are initiated in the same way as write operations, with the exception that the R/W bit of the control byte is set to one. There are three basic types of read operations: current address read, random read and sequential read. 8.1 Current Address Read The 24XX64 contains an Address Pointer that maintains the address of the last word accessed, internally incremented by one. Therefore, if the previous read access was to address ‘n’ (n is any legal address), the next current address read operation would access data from address n + 1. Upon receipt of the control byte with R/W bit set to one, the 24XX64 issues an Acknowledge and transmits the 8-bit data word. The host will not acknowledge the transfer, but does generate a Stop condition and the 24XX64 discontinues transmission (Figure 8-1). 8.2 Random Read Random read operations allow the host to access any memory location in a random manner. To perform this type of read operation, the word address must first be set. This is accomplished by sending the word address to the 24XX64 as part of a write operation (R/W bit set to ‘0’). Once the word address is sent, the host generates a Start condition following the Acknowledge. FIGURE 8-1: This terminates the write operation, but not before the internal Address Pointer is set. The host then issues the control byte again, but with the R/W bit set to a ‘1’. The 24XX64 will then issue an Acknowledge and transmit the 8-bit data word. The host will not acknowledge the transfer, but does generate a Stop condition, which causes the 24XX64 to discontinue transmission (Figure 8-2). After a random Read command, the internal Address Pointer will point to the address location following the one that was just read. 8.3 Sequential Read Sequential reads are initiated in the same way as random reads, except that once the 24XX64 transmits the first data byte, the host issues an Acknowledge as opposed to the Stop condition used in a random read. This Acknowledge directs the 24XX64 to transmit the next sequentially-addressed 8-bit word (Figure 8-3). Following the final byte being transmitted to the host, the host will NOT generate an Acknowledge, but will generate a Stop condition. To provide sequential reads, the 24XX64 contains an internal Address Pointer which is incremented by one at the completion of each operation. This Address Pointer allows the entire memory contents to be serially read during one operation. The internal Address Pointer will automatically roll over from address 1FFF to address 0000 if the host acknowledges the byte received from the array address 1FFF. CURRENT ADDRESS READ Bus Activity Host S T A R T Control Byte SDA Line S A 1 0 1 0 A2 A 1 0 1 Bus Activity  1997-2022 Microchip Technology Inc. and its subsidiaries S T O P Data Byte P A C K N O A C K DS20001189U-page 13 24AA64/24FC64/24LC64 FIGURE 8-2: Bus Activity Host SDA Line RANDOM READ S T A R T Control Byte Address High Byte S1 010AAA0 2 1 0 xxx A C K A C K Bus Activity S T A R T Address Low Byte A C K Control Byte S 1 0 1 0 A AA1 2 10 S T O P Data Byte P N O A C K A C K x = “don’t care” bit FIGURE 8-3: Bus Activity Host SEQUENTIAL READ Control Byte Data n Data n + 1 Data n + 2 S T O P Data n + x P SDA Line Bus Activity DS20001189U-page 14 A C K A C K A C K A C K N O A C K  1997-2022 Microchip Technology Inc. and its subsidiaries 24AA64/24FC64/24LC64 9.0 PACKAGING INFORMATION 9.1 Package Marking Information 5-Lead Chip Scale XW NN 8-Lead 2x3 DFN XXX YWW NN 8-Lead 5x6 DFN-S Example 72 13 Example 274 204 13 Example 24FC64 I/MF e3 2204 13F 8-Lead MSOP Example XXXXXT 4L64I YWWNNN 20413F 8-Lead PDIP (300 mil) Example XXXXXXXX T/XXXNNN YYWW 24LC64 I/P e3 13F 2204 8-Lead SOIC Example XXXXXXXT XXXXYYWW NNN 24LC64I SN e3 2204 13F 8-Lead SOIJ Example XXXXXXXX T/XXXXXX YYWWNNN 24LC64 I/SM e3 220413F  1997-2022 Microchip Technology Inc. and its subsidiaries DS20001189U-page 15 24AA64/24FC64/24LC64 5-Lead SOT-23 Example XXNN 7GNN 8-Lead 2x3 TDFN Example XXX YWW NN A74 527 I3 Example 8-Lead TSSOP XXXX 4LB TYWW I204 NNN 13F 1st Line Marking Codes Part Number DFN MSOP SOT-23 TDFN TSSOP I-Temp. E-Temp. I-Temp. E-Temp. I-Temp. E-Temp. Standard Rotated 24AA64 271 — 4A64T(1) 7HNN(2) 7WNN(2) A71 E10 4AB 4ABX 24FC64 27A — 4F64T(1) 7SNN(2) — A7A — 4FB — 275 4L64T(1) 7GNN(2) 7JNN(2) A74 A75 4LB 4LBX 24LC64 Note 1: 2: 274 T = Temperature grade (I, E) NN = Alphanumeric traceability code Legend: XX...X T Y YY WW NNN e3 Part number or part number code Temperature (I, E) Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week ‘01’) Alphanumeric traceability code (2 characters for small packages) JEDEC® designator for Matte Tin (Sn) * Standard OTP marking consists of Microchip part number, year code, week code and traceability code. Note: For very small packages with no room for the JEDEC® designator e3 , the marking will only appear on the outer carton or reel label. Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. DS20001189U-page 16  1997-2022 Microchip Technology Inc. and its subsidiaries 24AA64/24FC64/24LC64 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  1997-2022 Microchip Technology Inc. and its subsidiaries DS20001189U-page 17 24AA64/24FC64/24LC64 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS20001189U-page 18  1997-2022 Microchip Technology Inc. and its subsidiaries 24AA64/24FC64/24LC64 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  1997-2022 Microchip Technology Inc. and its subsidiaries DS20001189U-page 19 24AA64/24FC64/24LC64 /HDG3ODVWLF'XDO)ODW1R/HDG3DFNDJH0&[[PP%RG\>')1@ 1RWH )RUWKHPRVWFXUUHQWSDFNDJHGUDZLQJVSOHDVHVHHWKH0LFURFKLS3DFNDJLQJ6SHFLILFDWLRQORFDWHGDW KWWSZZZPLFURFKLSFRPSDFNDJLQJ ' $ % 1 '$780$ '$780% ( 127( ;  &  ;  &  7239,(:  & & $ $ 6($7,1* 3/$1( ; $  & 6,'(9,(: '  127(  & $ %   & $ % ( . / 1 ;E H %277209,(:   & $ % & 0LFURFKLS7HFKQRORJ\'UDZLQJ&5HY(6KHHWRI DS20001189U-page 20  1997-2022 Microchip Technology Inc. and its subsidiaries 24AA64/24FC64/24LC64 /HDG3ODVWLF'XDO)ODW1R/HDG3DFNDJH0&[[PP%RG\>')1@ 1RWH )RUWKHPRVWFXUUHQWSDFNDJHGUDZLQJVSOHDVHVHHWKH0LFURFKLS3DFNDJLQJ6SHFLILFDWLRQORFDWHGDW KWWSZZZPLFURFKLSFRPSDFNDJLQJ 127( 1RWHV     8QLWV 'LPHQVLRQ/LPLWV 1 1XPEHURI7HUPLQDOV H 3LWFK 2YHUDOO+HLJKW $ 6WDQGRII $ 7HUPLQDO7KLFNQHVV $ 2YHUDOO/HQJWK ' ([SRVHG3DG/HQJWK ' ( 2YHUDOO:LGWK ([SRVHG3DG:LGWK ( 7HUPLQDO:LGWK E / 7HUPLQDO/HQJWK 7HUPLQDOWR([SRVHG3DG . 0,1        0,//,0(7(56 120  %6&   5() %6&  %6&     0$;        3LQYLVXDOLQGH[IHDWXUHPD\YDU\EXWPXVWEHORFDWHGZLWKLQWKHKDWFKHGDUHD 3DFNDJHPD\KDYHRQHRUPRUHH[SRVHGWLHEDUVDWHQGV 3DFNDJHLVVDZVLQJXODWHG 'LPHQVLRQLQJDQGWROHUDQFLQJSHU$60(')1@ 1RWH )RUWKHPRVWFXUUHQWSDFNDJHGUDZLQJVSOHDVHVHHWKH0LFURFKLS3DFNDJLQJ6SHFLILFDWLRQORFDWHGDW KWWSZZZPLFURFKLSFRPSDFNDJLQJ ; (9  ‘9 & 627@ 1RWH )RUWKHPRVWFXUUHQWSDFNDJHGUDZLQJVSOHDVHVHHWKH0LFURFKLS3DFNDJLQJ6SHFLILFDWLRQORFDWHGDW KWWSZZZPLFURFKLSFRPSDFNDJLQJ ; 6,/.6&5((1  < = & *   ( *; 5(&200(1'('/$1'3$77(51 8QLWV 'LPHQVLRQ/LPLWV &RQWDFW3LWFK ( &RQWDFW3DG6SDFLQJ & &RQWDFW3DG:LGWK; ; &RQWDFW3DG/HQJWK; < 'LVWDQFH%HWZHHQ3DGV * 'LVWDQFH%HWZHHQ3DGV *; 2YHUDOO:LGWK = 0,1 0,//,0(7(56 120 %6&  0$;      1RWHV 'LPHQVLRQLQJDQGWROHUDQFLQJSHU$60(76623@ 1RWH )RUWKHPRVWFXUUHQWSDFNDJHGUDZLQJVSOHDVHVHHWKH0LFURFKLS3DFNDJLQJ6SHFLILFDWLRQORFDWHGDW KWWSZZZPLFURFKLSFRPSDFNDJLQJ ' $ % 1 '$780$ '$780% ( (   & % $  ;E  H & % $ 7239,(: $  & & 6($7,1* 3/$1( $ $ $ ;  & $ 6,'(9,(: + F / / 9,(:$$ 0LFURFKLS7HFKQRORJ\'UDZLQJ&5HY&6KHHWRI  1997-2022 Microchip Technology Inc. and its subsidiaries DS20001189U-page 43 24AA64/24FC64/24LC64 /HDG3ODVWLF7KLQ6KULQN6PDOO2XWOLQH67PP%RG\>76623@ 1RWH )RUWKHPRVWFXUUHQWSDFNDJHGUDZLQJVSOHDVHVHHWKH0LFURFKLS3DFNDJLQJ6SHFLILFDWLRQORFDWHGDW KWWSZZZPLFURFKLSFRPSDFNDJLQJ 8QLWV 'LPHQVLRQ/LPLWV 1XPEHURI3LQV 1 H 3LWFK 2YHUDOO+HLJKW $ 0ROGHG3DFNDJH7KLFNQHVV $ 6WDQGRII $ 2YHUDOO:LGWK ( 0ROGHG3DFNDJH:LGWK ( 2YHUDOO/HQJWK ' )RRW/HQJWK / )RRWSULQW / F /HDG7KLFNQHVV )RRW$QJOH E /HDG:LGWK 0,1        ƒ  0,//,0(7(56 120  %6&    %6&    5()  ƒ  0$;        ƒ  Notes: 3LQYLVXDOLQGH[IHDWXUHPD\YDU\EXWPXVWEHORFDWHGZLWKLQWKHKDWFKHGDUHD 'LPHQVLRQV'DQG(GRQRWLQFOXGHPROGIODVKRUSURWUXVLRQV0ROGIODVKRU SURWUXVLRQVVKDOOQRWH[FHHGPPSHUVLGH 'LPHQVLRQLQJDQGWROHUDQFLQJSHU$60(