24LC64T-I/SN

24AA64/24LC64/24FC64 64K I2C™ Serial EEPROM Device Selection Table Part Number VCC Range Max. Clock Frequency Temp. Ranges 24AA64 1.7-5.5 400 kHz(1) I, E 24LC64 2.5-5.5 400 kHz I, E 1.7-5.5 (2) 24FC64 Note 1: 2: 1 MHz • Pb-Free and RoHS Compliant • Temperature Ranges: - Industrial (I): -40°C to +85°C - Automotive (E): -40°C to +125°C Description: The Microchip Technology Inc. 24AA64/24LC64/ 24FC64 (24XX64*) is a 64 Kbit Electrically Erasable PROM. The device is organized as a single block of 8K x 8-bit memory with a 2-wire serial interface. Lowvoltage design permits operation down to 1.7V, with standby and active currents of only 1 A and 3 mA, respectively. It has been developed for advanced, lowpower applications such as personal communications or data acquisition. The 24XX64 also has a page write capability for up to 32 bytes of data. Functional address lines allow up to eight devices on the same bus, for up to 512 Kbits address space. The 24XX64 is available in the standard 8-pin PDIP, surface mount SOIC, SOIJ, TSSOP, DFN, TDFN and MSOP packages. The 24XX64 is also available in the 5-lead SOT-23, and Chip Scale packages. I 200 Years • Factory Programming Available • Packages include 8-lead PDIP, SOIC, SOIJ, TSSOP, X-Rotated TSSOP, MSOP, DFN, TDFN, 5-lead SOT-23 or Chip Scale Block Diagram HV Generator A0 A1 A2 WP I/O Control Logic Memory Control Logic EEPROM Array XDEC Page Latches I/O SCL YDEC SDA VCC VSS Sense Amp. R/W Control Package Types PDIP/MSOP/SOIC/SOIJ/TSSOP A0 1 8 VCC A1 2 7 WP A2 3 6 SCL VSS 4 5 SDA Note 1: DFN/TDFN SOT-23 X-Rotated TSSOP (X/ST) WP VCC A0 A1 1 2 3 4 Available in I-temp, “AA” only. 8 7 6 5 SCL VSS SCL SDA VSS SDA A2 1 5 A0 1 A1 2 2 3 WP 4 A2 3 VCC VSS 4 8 VCC 7 WP 6 SCL 5 SDA CS (Chip Scale)(1) VCC 1 WP SCL 2 VSS 5 SDA 3 4 (Top Down View, Balls Not Visible) * 24XX64 is used in this document as a generic part number for the 24AA64/24LC64/24FC64 devices.  1997-2012 Microchip Technology Inc. DS21189T-page 1 24AA64/24LC64/24FC64 1.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings (†) VCC .............................................................................................................................................................................6.5V All inputs and outputs w.r.t. VSS ......................................................................................................... -0.3V to VCC +1.0V Storage temperature ...............................................................................................................................-65°C to +150°C Ambient temperature with power applied ................................................................................................-40°C to +125°C ESD protection on all pins  4 kV † NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. TABLE 1-1: DC CHARACTERISTICS DC CHARACTERISTICS Param. No. Sym. Characteristic Industrial (I): TA = -40°C to +85°C, VCC = +1.7V to +5.5V Automotive (E): TA = -40°C to +125°C, VCC = +1.7V to +5.5V Min. Typ. Max. Units Conditions — — — — — — A0, A1, A2, WP, SCL and SDA pins D1 VIH High-level input voltage 0.7 VCC — — V — D2 VIL Low-level input voltage — — 0.3 VCC 0.2 VCC V V VCC  2.5V VCC  2.5V D3 VHYS Hysteresis of Schmitt Trigger inputs (SDA, SCL pins) 0.05 VCC — — V VCC  2.5V (Note 1) D4 VOL Low-level output voltage — — 0.40 V IOL = 3.0 mA @ VCC = 4.5V IOL = 2.1 mA @ VCC = 2.5V D5 ILI Input leakage current — — ±1 A VIN = VSS or VCC, WP = VSS VIN = VSS or VCC, WP = VCC D6 ILO Output leakage current — — ±1 A VOUT = VSS or VCC D7 CIN, COUT Pin capacitance (all inputs/outputs) — — 10 pF VCC = 5.0V (Note 1) TA = 25°C, FCLK = 1 MHz D8 ICC write Operating current — 0.1 3 mA VCC = 5.5V, SCL = 400 kHz — 0.05 400 A — — 0.01 — 1 5 A A D9 ICC read D10 ICCS Note 1: 2: Standby current Industrial Automotive SDA = SCL = VCC A0, A1, A2, WP = VSS This parameter is periodically sampled and not 100% tested. Typical measurements taken at room temperature. DS21189T-page 2  1997-2012 Microchip Technology Inc. 24AA64/24LC64/24FC64 TABLE 1-2: AC CHARACTERISTICS Electrical Characteristics: Industrial (I): VCC = +1.7V to 5.5V TA = -40°C to +85°C Automotive (E): VCC = +1.7V to 5.5V TA = -40°C to 125°C AC CHARACTERISTICS Param. No. Sym. Characteristic Min. Max. Units Conditions 1 FCLK Clock frequency — — — — 100 400 400 1000 kHz 1.7V  VCC  2.5V 2.5V  VCC  5.5V 1.7V  VCC  2.5V 24FC64 2.5V  VCC  5.5V 24FC64 2 THIGH Clock high time 4000 600 600 500 — — — — ns 1.7V  VCC  2.5V 2.5V  VCC  5.5V 1.7V  VCC  2.5V 24FC64 2.5V  VCC  5.5V 24FC64 3 TLOW Clock low time 4700 1300 1300 500 — — — — ns 1.7V  VCC  2.5V 2.5V  VCC  5.5V 1.7V  VCC  2.5V 24FC64 2.5V  VCC  5.5V 24FC64 4 TR SDA and SCL rise time (Note 1) — — — 1000 300 300 ns 1.7V  VCC  2.5V 2.5V  VCC  5.5V 1.7V  VCC  5.5V 24FC64 5 TF SDA and SCL fall time (Note 1) — — 300 100 ns All except, 24FC64 1.7V  VCC  5.5V 24FC64 6 THD:STA Start condition hold time 4000 600 600 250 — — — — ns 1.7V  VCC  2.5V 2.5V  VCC  5.5V 1.7V  VCC  2.5V 24FC64 2.5V  VCC  5.5V 24FC64 7 TSU:STA 4700 600 600 250 — — — — ns 1.7V  VCC  2.5V 2.5V  VCC  5.5V 1.7V  VCC  2.5V 24FC64 2.5V  VCC  5.5V 24FC64 Start condition setup time 8 THD:DAT Data input hold time 0 — ns (Note 2) 9 TSU:DAT Data input setup time 250 100 100 — — — ns 1.7V  VCC  2.5V 2.5V  VCC  5.5V 1.7V  VCC  5.5V 24FC64 10 TSU:STO Stop condition setup time 4000 600 600 250 — — — — ns 1.7 V  VCC  2.5V 2.5 V  VCC  5.5V 1.7V  VCC  2.5V 24FC64 2.5 V  VCC  5.5V 24FC64 11 TSU:WP WP setup time 4000 600 600 — — — ns 1.7V  VCC  2.5V 2.5V  VCC  5.5V 1.7V  VCC  5.5V 24FC64 12 THD:WP WP hold time 4700 1300 1300 — — — ns 1.7V  VCC  2.5V 2.5V  VCC  5.5V 1.7V  VCC  5.5V 24FC64 Note 1: Not 100% tested. CB = total capacitance of one bus line in pF. 2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions. 3: The combined TSP and VHYS specifications are due to new Schmitt Trigger inputs, which provide improved noise spike suppression. This eliminates the need for a TI specification for standard operation. 4: This parameter is not tested but ensured by characterization. For endurance estimates in a specific application, please consult the Total Endurance™ Model, which can be obtained from Microchip’s web site at www.microchip.com.  1997-2012 Microchip Technology Inc. DS21189T-page 3 24AA64/24LC64/24FC64 Electrical Characteristics: Industrial (I): VCC = +1.7V to 5.5V TA = -40°C to +85°C Automotive (E): VCC = +1.7V to 5.5V TA = -40°C to 125°C AC CHARACTERISTICS Param. No. Sym. Characteristic Min. Max. Units Conditions — — — — 3500 900 900 400 ns 1.7V  VCC  2.5V 2.5V  VCC  5.5V 1.7V  VCC  2.5V 24FC64 2.5V  VCC  5.5V 24FC64 4700 1300 1300 500 — — — — ns 1.7V  VCC  2.5V 2.5V  VCC  5.5V 1.7V  VCC  2.5V 24FC64 2.5V  VCC  5.5V 24FC64 10 + 0.1CB 250 250 ns All except, 24FC64 (Note 1) 24FC64 (Note 1) 13 TAA Output valid from clock (Note 2) 14 TBUF Bus free time: Time the bus must be free before a new transmission can start 15 TOF Output fall time from VIH minimum to VIL maximum CB  100 pF 16 TSP Input filter spike suppression (SDA and SCL pins) — 50 ns All except, 24FC64 (Notes 1 and 3) 17 TWC Write cycle time (byte or page) — 5 ms — 1,000,000 — 18 — Endurance cycles Page Mode 25°C, 5.5V (Note 4) Note 1: Not 100% tested. CB = total capacitance of one bus line in pF. 2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions. 3: The combined TSP and VHYS specifications are due to new Schmitt Trigger inputs, which provide improved noise spike suppression. This eliminates the need for a TI specification for standard operation. 4: This parameter is not tested but ensured by characterization. For endurance estimates in a specific application, please consult the Total Endurance™ Model, which can be obtained from Microchip’s web site at www.microchip.com. FIGURE 1-1: BUS TIMING DATA 5 SCL SDA IN 7 3 4 D3 2 8 10 9 6 16 14 13 SDA OUT WP DS21189T-page 4 (protected) (unprotected) 11 12  1997-2012 Microchip Technology Inc. 24AA64/24LC64/24FC64 2.0 PIN DESCRIPTIONS The descriptions of the pins are listed in Table 2-1. TABLE 2-1: PIN FUNCTION TABLE Name PDIP SOIC TSSOP Rotated DFN(1) TDFN(1) MSOP TSSOP SOT-23 CS Description A0 1 1 1 3 1 1 1 — — Chip Address Input A1 2 2 2 4 2 2 2 — — Chip Address Input A2 3 3 3 5 3 3 3 — — Chip Address Input VSS 4 4 4 6 4 4 4 2 2 Ground SDA 5 5 5 7 5 5 5 3 5 Serial Address/Data I/O SCL 6 6 6 8 6 6 6 1 4 Serial Clock WP 7 7 7 1 7 7 7 5 3 Write-Protect Input VCC 8 8 8 2 8 8 8 4 1 +1.7V to 5.5V Power Supply Note 1: The exposed pad on the DFN/TDFN packages can be connected to VSS or left floating. 2.1 A0, A1, A2 Chip Address Inputs The A0, A1 and A2 inputs are used by the 24XX64 for multiple device operation. The levels on these inputs are compared with the corresponding bits in the slave address. The chip is selected if the compare is true. Up to eight devices may be connected to the same bus by using different Chip Select bit combinations. These inputs must be connected to either VCC or VSS. In most applications, the chip address inputs A0, A1 and A2 are hard-wired to logic ‘0’ or logic ‘1’. For applications in which these pins are controlled by a microcontroller or other programmable device, the chip address pins must be driven to logic ‘0’ or logic ‘1’ before normal device operation can proceed. Address pins are not available in the SOT-23 or Chip Scale packages. 2.2 Serial Data (SDA) SDA is a bidirectional pin used to transfer addresses and data into and out of the device. Since it is an opendrain terminal, the SDA bus requires a pull-up resistor to VCC (typical 10 k for 100 kHz, 2 kfor 400 kHz). 2.3 Serial Clock (SCL) The SCL input is used to synchronize the data transfer from and to the device. 2.4 Write-Protect (WP) This pin must be connected to either VSS or VCC. If tied to VSS, write operations are enabled. If tied to VCC, write operations are inhibited but read operations are not affected. 3.0 FUNCTIONAL DESCRIPTION The 24XX64 supports a bidirectional, 2-wire bus and data transmission protocol. A device that sends data onto the bus is defined as transmitter, while a device receiving data is defined as a receiver. The bus has to be controlled by a master device which generates the Serial Clock (SCL), controls the bus access and generates the Start and Stop conditions, while the 24XX64 works as slave. Both master and slave can operate as transmitter or receiver, but the master device determines which mode is activated. For normal data transfer, SDA is allowed to change only during SCL low. Changes during SCL high are reserved for indicating the Start and Stop conditions.  1997-2012 Microchip Technology Inc. DS21189T-page 5 24AA64/24LC64/24FC64 4.0 BUS CHARACTERISTICS The following bus protocol has been defined: • Data transfer may be initiated only when the bus is not busy • During data transfer, the data line must remain stable whenever the clock line is high. Changes in the data line while the clock line is high will be interpreted as a Start or Stop condition The data on the line must be changed during the low period of the clock signal. There is one clock pulse per bit of data. Accordingly, the following bus conditions have been defined (Figure 4-1). Each data transfer is initiated with a Start condition and terminated with a Stop condition. The number of data bytes transferred between Start and Stop conditions is determined by the master device and is, theoretically, unlimited (although only the last thirty two will be stored when doing a write operation). When an overwrite does occur, it will replace data in a first-in first-out (FIFO) fashion. 4.1 4.5 Bus Not Busy (A) Each receiving device, when addressed, is obliged to generate an acknowledge after the reception of each byte. The master device must generate an extra clock pulse which is associated with this Acknowledge bit. Both data and clock lines remain high. 4.2 Start Data Transfer (B) A high-to-low transition of the SDA line while the clock (SCL) is high determines a Start condition. All commands must be preceded by a Start condition. 4.3 Stop Data Transfer (C) A low-to-high transition of the SDA line while the clock (SCL) is high determines a Stop condition. All operations must be ended with a Stop condition. 4.4 Data Valid (D) The state of the data line represents valid data when, after a Start condition, the data line is stable for the duration of the high period of the clock signal. FIGURE 4-1: (A) Acknowledge Note: The 24XX64 does not generate any Acknowledge bits if an internal programming cycle is in progress. The device that acknowledges has to pull down the SDA line during the Acknowledge clock pulse in such a way that the SDA line is stable low during the high period of the acknowledge related clock pulse. Of course, setup and hold times must be taken into account. During reads, a master must signal an end of data to the slave by not generating an Acknowledge bit on the last byte that has been clocked out of the slave. In this case, the slave (24XX64) will leave the data line high to enable the master to generate the Stop condition. DATA TRANSFER SEQUENCE ON THE SERIAL BUS (B) (D) Start Condition Address or Acknowledge Valid (D) (C) (A) SCL SDA DS21189T-page 6 Data Allowed to Change Stop Condition  1997-2012 Microchip Technology Inc. 24AA64/24LC64/24FC64 5.0 DEVICE ADDRESSING A control byte is the first byte received following the Start condition from the master device (Figure 5-1). The control byte consists of a four-bit control code. For the 24XX64, this is set as ‘1010’ binary for read and write operations. The next three bits of the control byte are the Chip Select bits (A2, A1, A0). The Chip Select bits allow the use of up to eight 24XX64 devices on the same bus and are used to select which device is accessed. The Chip Select bits in the control byte must correspond to the logic levels on the corresponding A2, A1 and A0 pins for the device to respond. These bits are, in effect, the three Most Significant bits of the word address. For the SOT-23 and Chip Scale packages, the address pins are not available. During device addressing, the A2, A1 and A0 Chip Select bits (Figure 5-2) should be set to ‘0’. The last bit of the control byte defines the operation to be performed. When set to a ‘1’, a read operation is selected. When set to a ‘0’, a write operation is selected. The next two bytes received define the address of the first data byte (Figure 5-2). Because only A12...A0 are used, the upper-three address bits are “don’t care” bits. The upper-address bits are transferred first, followed by the Less Significant bits. Following the Start condition, the 24XX64 monitors the SDA bus, checking the device-type identifier being transmitted. Upon receiving a ‘1010’ code and appropriate device-select bits, the slave device outputs an FIGURE 5-2: 0 FIGURE 5-1: CONTROL BYTE FORMAT Read/Write Bit Chip Select Bits Control Code S 1 0 1 0 A2 A1 A0 R/W ACK Slave Address Start Bit 5.1 Acknowledge Bit Contiguous Addressing Across Multiple Devices The Chip Select bits A2, A1 and A0 can be used to expand the contiguous address space for up to 512K bits by adding up to eight 24XX64 devices on the same bus. In this case, software can use A0 of the control byte as address bit A13; A1 as address bit A14; and A2 as address bit A15. It is not possible to sequentially read across device boundaries. The SOT-23 and Chip Scale packages do not support multiple device addressing on the same bus. ADDRESS SEQUENCE BIT ASSIGNMENTS Control Byte 1 Acknowledge signal on the SDA line. Depending on the state of the R/W bit, the 24XX64 will select a read or write operation. 1 Control Code 0 A 2 A 1 Address High Byte A 0 R/W Chip Select bits  1997-2012 Microchip Technology Inc. x x x A A A 12 11 10 Address Low Byte A 9 A 8 A 7 • • • • • • A 0 x = “don’t care” bit DS21189T-page 7 24AA64/24LC64/24FC64 6.0 WRITE OPERATIONS 6.1 Byte Write Following the Start condition from the master, the control code (four bits), the Chip Select (three bits) and the R/W bit (which is a logic low) are clocked onto the bus by the master transmitter. This indicates to the addressed slave receiver that the address high byte will follow once it has generated an Acknowledge bit during the ninth clock cycle. Therefore, the next byte transmitted by the master is the high-order byte of the word address and will be written into the Address Pointer of the 24XX64. The next byte is the Least Significant Address Byte. After receiving another Acknowledge signal from the 24XX64, the master device will transmit the data word to be written into the addressed memory location. The 24XX64 acknowledges again and the master generates a Stop condition. This initiates the internal write cycle and, during this time, the 24XX64 will not generate Acknowledge signals (Figure 6-1). If an attempt is made to write to the array with the WP pin held high, the device will acknowledge the command, but no write cycle will occur, no data will be written and the device will immediately accept a new command. After a byte Write command, the internal address counter will point to the address location following the one that was just written. Note: 6.2 Page Write The write control byte, word address and the first data byte are transmitted to the 24XX64 in the same way as in a byte write. However, instead of generating a Stop condition, the master transmits up to 31 additional bytes which are temporarily stored in the on-chip page buffer and will be written into memory once the master has transmitted a Stop condition. Upon receipt of each word, the five lower Address Pointer bits are internally incremented by one. If the master should transmit more than 32 bytes prior to generating the Stop condition, the address counter will roll over and the previously received data will be overwritten. As with the byte write operation, once the Stop condition is received, an internal write cycle will begin (Figure 6-2). If an attempt is made to write to the array with the WP pin held high, the device will acknowledge the command, but no write cycle will occur, no data will be written, and the device will immediately accept a new command. Note: When doing a write of less than 32 bytes the data in the rest of the page is refreshed along with the data bytes being written. This will force the entire page to endure a write cycle, for this reason endurance is specified per page. 6.3 Page write operations are limited to writing bytes within a single physical page, regardless of the number of bytes actually being written. Physical page boundaries start at addresses that are integer multiples of the page buffer size (or ‘page size’) and end at addresses that are integer multiples of [page size – 1]. If a Page Write command attempts to write across a physical page boundary, the result is that the data wraps around to the beginning of the current page (overwriting data previously stored there), instead of being written to the next page, as might be expected. It is therefore necessary for the application software to prevent page write operations that would attempt to cross a page boundary. Write Protection The WP pin allows the user to write-protect the entire array (0000-1FFF) when the pin is tied to VCC. If tied to VSS the write protection is disabled. The WP pin is sampled at the Stop bit for every Write command (Figure 4-1). Toggling the WP pin after the Stop bit will have no effect on the execution of the write cycle. DS21189T-page 8  1997-2012 Microchip Technology Inc. 24AA64/24LC64/24FC64 FIGURE 6-1: BYTE WRITE S T A R T Bus Activity Master Control Byte Address High Byte AA S1 01 0A 2 10 0 SDA Line S T O P Data xxx P A C K Bus Activity Address Low Byte A C K A C K A C K x = “don’t care” bit FIGURE 6-2: PAGE WRITE Bus Activity Master S T A R T SDA Line AA S 10 10A 2 1 0 0 Control Byte Bus Activity Address High Byte Address Low Byte Data Byte 0 S T O P Data Byte 31 P xxx A C K A C K A C K A C K A C K x = “don’t care” bit  1997-2012 Microchip Technology Inc. DS21189T-page 9 24AA64/24LC64/24FC64 7.0 ACKNOWLEDGE POLLING Since the device will not acknowledge during a write cycle, this can be used to determine when the cycle is complete (this feature can be used to maximize bus throughput). Once the Stop condition for a Write command has been issued from the master, the device initiates the internally-timed write cycle and ACK polling can then be initiated immediately. This involves the master sending a Start condition followed by the control byte for a Write command (R/W = 0). If the device is still busy with the write cycle, then no ACK will be returned. If no ACK is returned, the Start bit and control byte must be re-sent. If the cycle is complete, the device will return the ACK and the master can then proceed with the next Read or Write command. See Figure 7-1 for a flow diagram of this operation. FIGURE 7-1: ACKNOWLEDGE POLLING FLOW Send Write Command Send Stop Condition to Initiate Write Cycle Send Start Send Control Byte with R/W = 0 Did Device Acknowledge (ACK = 0)? No Yes Next Operation DS21189T-page 10  1997-2012 Microchip Technology Inc. 24AA64/24LC64/24FC64 8.0 READ OPERATION Read operations are initiated in the same way as write operations, with the exception that the R/W bit of the control byte is set to one. There are three basic types of read operations: current address read, random read and sequential read. 8.1 Current Address Read The 24XX64 contains an address counter that maintains the address of the last word accessed, internally incremented by one. Therefore, if the previous read access was to address ‘n’ (n is any legal address), the next current address read operation would access data from address n + 1. Upon receipt of the control byte with R/W bit set to one, the 24XX64 issues an acknowledge and transmits the eight-bit data word. The master will not acknowledge the transfer, but does generate a Stop condition and the 24XX64 discontinues transmission (Figure 8-1). 8.2 Random Read Random read operations allow the master to access any memory location in a random manner. To perform this type of read operation, the word address must first be set. This is accomplished by sending the word address to the 24XX64 as part of a write operation (R/W bit set to ‘0’). Once the word address is sent, the master generates a Start condition following the acknowledge. FIGURE 8-1: This terminates the write operation, but not before the internal Address Pointer is set. The master then issues the control byte again, but with the R/W bit set to a one. The 24XX64 will then issue an acknowledge and transmit the 8-bit data word. The master will not acknowledge the transfer, but does generate a Stop condition, which causes the 24XX64 to discontinue transmission (Figure 8-2). After a random Read command, the internal address counter will point to the address location following the one that was just read. 8.3 Sequential Read Sequential reads are initiated in the same way as random reads, except that once the 24XX64 transmits the first data byte, the master issues an acknowledge as opposed to the Stop condition used in a random read. This acknowledge directs the 24XX64 to transmit the next sequentially-addressed 8-bit word (Figure 8-3). Following the final byte being transmitted to the master, the master will NOT generate an acknowledge, but will generate a Stop condition. To provide sequential reads, the 24XX64 contains an internal Address Pointer which is incremented by one at the completion of each operation. This Address Pointer allows the entire memory contents to be serially read during one operation. The internal Address Pointer will automatically roll over from address 1FFF to address 0000 if the master acknowledges the byte received from the array address 1FFF. CURRENT ADDRESS READ Bus Activity Master S T A R T SDA Line S Bus Activity  1997-2012 Microchip Technology Inc. Control Byte S T O P Data (n) P A C K N O A C K DS21189T-page 11 24AA64/24LC64/24FC64 FIGURE 8-2: Bus Activity Master SDA Line RANDOM READ S T A R T Control Byte Address High Byte S1 01 0AAA0 2 1 0 xxx A C K A C K Bus Activity S T A R T Address Low Byte A C K Control Byte S 1 0 1 0 A AA1 2 10 S T O P Data Byte P N O A C K A C K x = “don’t care” bit FIGURE 8-3: Bus Activity Master SEQUENTIAL READ Control Byte Data n Data n + 1 Data n + 2 S T O P Data n + x P SDA Line Bus Activity DS21189T-page 12 A C K A C K A C K A C K N O A C K  1997-2012 Microchip Technology Inc. 24AA64/24LC64/24FC64 9.0 PACKAGING INFORMATION 9.1 Package Marking Information 8-Lead PDIP (300 mil) XXXXXXXX T/XXXNNN YYWW 8-Lead SOIC (3.90 mm) Example: 24LC64 I/P e3 13F 0527 Example: 24LC64I SN e3 0527 13F XXXXXXXT XXXXYYWW NNN 8-Lead SOIC (5.28 mm) Example: 24LC64 I/SM e3 052713F XXXXXXXX T/XXXXXX YYWWNNN 8-Lead TSSOP Example: XXXX 4LB TYWW I527 NNN 13F 8-Lead MSOP Example: XXXXXT 4L64I YWWNNN 52713F 8-Lead 2x3 DFN XXX YWW NN  1997-2012 Microchip Technology Inc. Example: 274 527 I3 DS21189T-page 13 24AA64/24LC64/24FC64 8-Lead 2x3 TDFN Example: XXX YWW NN A74 527 I3 5-Lead SOT-23 Example: XXNN 7GNN 5-Lead Chip Scale Example: 75 13 XW NN 1st Line Marking Codes Part Number TSSOP TSSOP X-Rotated MSOP 4AB 4ABX 4A64T 24LC64 4LB 4LBX 24FC64 4FB — 24AA64 Note: DFN TDFN SOT-23 I Temp. E Temp. I Temp. E Temp. I Temp. E Temp. 271 — A71 E10 7HNN 7WNN 4L64T 274 275 A74 A75 7GNN 7JNN 4F64T 27A — A7A — — — T = Temperature grade (I, E) Legend: XX...X T Y YY WW NNN e3 Part number or part number code Temperature (I, E) Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week ‘01’) Alphanumeric traceability code (2 characters for small packages) Pb-free JEDEC designator for Matte Tin (Sn) Note: For very small packages with no room for the Pb-free JEDEC designator e3 , the marking will only appear on the outer carton or reel label. Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. DS21189T-page 14  1997-2012 Microchip Technology Inc. 24AA64/24LC64/24FC64           3 &' !&" &4# *!(!!& 4%&  &#& &&255***'  '54 N NOTE 1 E1 1 3 2 D E A2 A L A1 c e eB b1 b 6&! '! 9'&! 7"')  %! 7,8. 7 7 7: ; < &  & &  = =   ##4 4!!   -  1!& &   = =  "# &  "# >#& .  - -  ##4>#& .   #& 9 * 9#>#& :   *+ 1, -    !"#$%&" '  ()"&'"!&) &#*&&&#   +%&, & !& - '! !#.#  &"#' #%!  & "! ! #%!  & "! !! &$#/ !#  '! #&   .0 1,21!'!   &$& "! **& "&&  !       * ,#& . - =