25AA020A/25LC020A
2-Kbit SPI Bus Serial EEPROM
Device Selection Table
Part Number
VCC Range
Page Size
Temp. Ranges
Packages
25AA020A
1.8V-5.5V
16 bytes
I
MC, MS, P, OT, SN, MN, ST
25LC020A
2.5V-5.5V
16 bytes
I, E
MC, MS, P, OT, SN, MN, ST
Features
Description
• Maximum Clock: 10 MHz
• Low-Power CMOS Technology:
- Maximum Write current: 5 mA at 5.5V
- Read current: 5 mA at 5.5V, 10 MHz
- Standby current: 5 µA at 5.5V
• 256 x 8-bit Organization
• 16-Byte Page
• Sequential Read
• Self-Timed Erase and Write Cycles
(5 ms maximum)
• Block Write Protection:
- Protect none, 1/4, 1/2 or all of array
• Built-In Write Protection:
- Power-on/off data protection circuitry
- Write enable latch
- Write-protect pin
• High Reliability:
- Endurance: 1M erase/write cycles
- Data retention: > 200 years
- ESD protection: > 4000V
• Temperature Ranges Supported:
- Industrial (I):
-40C to +85C
- Extended (E):
-40C to +125C
• RoHS Compliant
• Automotive AEC-Q100 Qualified
The Microchip Technology Inc. 25XX020A(1) is a 2-Kbit
Serial Electrically Erasable PROM (EEPROM). The
memory is accessed via a simple Serial Peripheral
Interface (SPI) compatible serial bus. The bus signals
required are a clock input (SCK) plus separate data in
(SI) and data out (SO) lines. Access to the device is
controlled through a Chip Select (CS) input.
Packages
• 8-Lead DFN, 8-Lead MSOP, 8-Lead PDIP,
8-Lead SOIC, 6-Lead SOT-23, 8-Lead TDFN and
8-Lead TSSOP
Pin Function Table
Name
Function
CS
Chip Select Input
SO
Serial Data Output
WP
Write-Protect Pin
VSS
Ground
SI
Serial Data Input
SCK
Serial Clock Input
HOLD
Hold Input
VCC
Supply Voltage
2003-2022 Microchip Technology Inc. and its subsidiaries
Communication to the device can be paused via the
hold pin (HOLD). While the device is paused, transitions on its inputs will be ignored, with the exception of
Chip Select, allowing the host to service higher priority
interrupts.
Note 1: 25XX020A is used in this document as a
generic part number for the 25AA020A
and 25LC020A devices.
Package Types (not to scale)
DFN/TDFN
(Top View)
CS
SO
WP
VSS
1
2
3
4
8
7
6
5
VCC
HOLD
SCK
SI
CS
SO
WP
VSS
MSOP/TSSOP
(Top View)
1
8
2
7
3
6
4
5
PDIP/SOIC
(Top View)
CS
SO
WP
VSS
1
2
3
4
8
7
6
5
VCC
HOLD
SCK
SI
VCC
HOLD
SCK
SI
SOT-23
(Top View)
SCK
1
6
VDD
VSS
SI
2
3
5
4
CS
SO
DS20001833H-page 1
25AA020A/25LC020A
1.0
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings(†)
VCC .............................................................................................................................................................................6.5V
All inputs and outputs w.r.t. VSS ......................................................................................................... -0.6V to VCC +1.0V
Storage temperature ...............................................................................................................................-65°C to +150°C
Ambient temperature under bias .............................................................................................................-40°C to +125°C
ESD protection on all pins ..........................................................................................................................................4 kV
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for an
extended period of time may affect device reliability.
TABLE 1-1:
DC CHARACTERISTICS
Electrical Characteristics:
Industrial (I): TA = -40°C to +85°C
VCC = 1.8V to 5.5V
Extended (E): TA = -40°C to +125°C VCC = 2.5V to 5.5V
DC CHARACTERISTICS
Param.
Symbol
No.
Characteristic
D001
VIH1
D002
VIL1
D003
VIL2
D004
VOL
D005
VOL
D006
VOH
High-Level Output Voltage
D007
ILI
D008
D009
D010
High-Level Input Voltage
Low-Level Input Voltage
D012
Note 1:
Max.
Units
Test Conditions
0.7 VCC
VCC +1
V
-0.3
0.3 VCC
V
VCC2.7V (Note 1)
-0.3
0.2 VCC
V
VCC < 2.7V (Note 1)
—
0.4
V
IOL = 2.1 mA
—
0.2
V
IOL = 1.0 mA, VCC < 2.5V
VCC -0.5
—
V
IOH = -400 µA
Input Leakage Current
—
±1
µA
CS = VCC, VIN = VSS or VCC
ILO
Output Leakage Current
—
±1
µA
CS = VCC, VOUT = VSS or VCC
CINT
Internal Capacitance
(all inputs and outputs)
—
7
pF
TA = +25°C, CLK = 1.0 MHz,
VCC = 5.0V (Note 1)
—
5
mA
VCC = 5.5V; FCLK = 10.0 MHz;
SO = Open
—
2.5
mA
VCC = 2.5V; FCLK = 5.0 MHz;
SO = Open
—
5
mA
VCC = 5.5V
—
3
mA
VCC = 2.5V
—
5
µA
CS = VCC = 5.5V, Inputs tied to
VCC or VSS, TA = +125°C
—
1
µA
CS = VCC = 2.5V, Inputs tied to
VCC or VSS, TA = +85°C
Low-Level Output Voltage
ICC Read
Operating Current
D011
Min.
ICC Write
ICCS
Standby Current
This parameter is periodically sampled and not 100% tested.
DS20001833H-page 2
2003-2022 Microchip Technology Inc. and its subsidiaries
25AA020A/25LC020A
TABLE 1-2:
AC CHARACTERISTICS
Electrical Characteristics:
Industrial (I):
TA = -40°C to +85°C
Extended (E): TA = -40°C to +125°C
AC CHARACTERISTICS
Param.
Symbol
No.
1
FCLK
2
TCSS
3
TCSH
4
TCSD
5
Tsu
Characteristic
Clock Frequency
CS Setup Time
CS Hold Time
CS Disable Time
Data Setup Time
6
THD
Data Hold Time
7
TR
CLK Rise Time
8
TF
CLK Fall Time
9
THI
Clock High Time
VCC = 1.8V to 5.5V
VCC = 2.5V to 5.5V
Min.
Max.
Units
Test Conditions
—
10
MHz
4.5V VCC 5.5V
—
5
MHz
2.5V VCC 4.5V
—
3
MHz
1.8V VCC 2.5V
50
—
ns
4.5V VCC 5.5V
100
—
ns
2.5V VCC 4.5V
150
—
ns
1.8V VCC 2.5V
100
—
ns
4.5V VCC 5.5V
200
—
ns
2.5V VCC 4.5V
250
—
ns
1.8V VCC 2.5V
50
—
ns
10
—
ns
4.5V VCC 5.5V
20
—
ns
2.5V VCC 4.5V
30
—
ns
1.8V VCC 2.5V
20
—
ns
4.5V VCC 5.5V
40
—
ns
2.5V VCC 4.5V
50
—
ns
1.8V VCC 2.5V
—
100
ns
Note 1
—
100
ns
Note 1
50
—
ns
4.5V VCC 5.5V
100
—
ns
2.5V VCC 4.5V
150
—
ns
1.8V VCC 2.5V
50
—
ns
4.5V VCC 5.5V
100
—
ns
2.5V VCC 4.5V
1.8V VCC 2.5V
10
TLO
Clock Low Time
150
—
ns
11
TCLD
Clock Delay Time
50
—
ns
12
TCLE
Clock Enable Time
50
—
ns
—
50
ns
4.5V VCC 5.5V
—
100
ns
2.5V VCC 4.5V
—
160
ns
1.8V VCC 2.5V
0
—
ns
Note 1
—
40
ns
4.5V VCC 5.5V (Note 1)
13
TV
14
THO
15
TDIS
16
THS
Note 1:
2:
3:
Output Valid from Clock Low
Output Hold Time
Output Disable Time
HOLD Setup Time
—
80
ns
2.5V VCC 4.5V (Note 1)
—
160
ns
1.8V VCC 2.5V (Note 1)
20
—
ns
4.5V VCC 5.5V
40
—
ns
2.5V VCC 4.5V
80
—
ns
1.8V VCC 2.5V
This parameter is periodically sampled and not 100% tested.
TWC begins on the rising edge of CS after a valid write sequence and ends when the internal write cycle is
complete.
This parameter is not tested but ensured by characterization.
2003-2022 Microchip Technology Inc. and its subsidiaries
DS20001833H-page 3
25AA020A/25LC020A
TABLE 1-2:
AC CHARACTERISTICS (CONTINUED)
Electrical Characteristics:
Industrial (I):
TA = -40°C to +85°C
Extended (E): TA = -40°C to +125°C
AC CHARACTERISTICS
Param.
Symbol
No.
17
THH
18
HOLD Hold Time
HOLD Low to Output High-Z
THZ
19
TWC
21
Note 1:
2:
3:
Min.
Max.
Units
Test Conditions
20
—
ns
4.5V VCC 5.5V
40
—
ns
2.5V VCC 4.5V
80
—
ns
1.8V VCC 2.5V
—
30
ns
4.5V VCC 5.5V (Note 1)
—
60
ns
2.5V VCC 4.5V (Note 1)
—
160
ns
1.8V VCC 2.5V (Note 1)
—
30
ns
4.5V VCC 5.5V
—
60
ns
2.5V VCC 4.5V
—
160
ns
1.8V VCC 2.5V
Internal Write Cycle Time
(byte or page)
—
5
ms
Note 2
Endurance
1M
—
HOLD High to Output Valid
THV
20
Characteristic
VCC = 1.8V to 5.5V
VCC = 2.5V to 5.5V
E/W +25°C, VCC = 5.5V, Page Mode
Cycles (Note 3)
This parameter is periodically sampled and not 100% tested.
TWC begins on the rising edge of CS after a valid write sequence and ends when the internal write cycle is
complete.
This parameter is not tested but ensured by characterization.
TABLE 1-3:
AC TEST CONDITIONS
AC Waveform
VLO = 0.2V
—
VH I = VCC - 0.2V
Note 1
VH I = 4.0V
Note 2
CL = 100 pF
—
Timing Measurement Reference Level
Input
0.5 VCC
Output
0.5 VCC
Note 1:
2:
For VCC 4.0V
For VCC 4.0V
DS20001833H-page 4
2003-2022 Microchip Technology Inc. and its subsidiaries
25AA020A/25LC020A
FIGURE 1-1:
HOLD TIMING
CS
17
16
17
16
SCK
18
SO
n+2
SI
n+2
n+1
n
19
High-Impedance
n
5
Don’t Care
n+1
n-1
n
n
n-1
HOLD
FIGURE 1-2:
SERIAL INPUT TIMING
4
CS
2
7
Mode 1,1
3
8
12
11
SCK Mode 0,0
5
SI
6
MSb in
LSb in
High-Impedance
SO
FIGURE 1-3:
SERIAL OUTPUT TIMING
CS
9
3
10
Mode 1,1
SCK
Mode 0,0
13
SO
SI
14
MSb out
15
LSb out
Don’t Care
2003-2022 Microchip Technology Inc. and its subsidiaries
DS20001833H-page 5
25AA020A/25LC020A
2.0
PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 2-1.
TABLE 2-1:
Name
PIN FUNCTION TABLE
DFN(1)
MSOP
PDIP
SOIC
SOT-23
TDFN(1)
TSSOP
Function
CS
1
1
1
1
5
1
1
Chip Select Input
SO
2
2
2
2
4
2
2
Serial Data Output
WP
3
3
3
3
—
3
3
Write-Protect Pin
Vss
4
4
4
4
2
4
4
Ground
SI
5
5
5
5
3
5
5
Serial Data Input
SCK
6
6
6
6
1
6
6
Serial Clock Input
HOLD
7
7
7
7
—
7
7
Hold Input
Vcc
8
8
8
8
6
8
8
Supply Voltage
Note 1:
2.1
The exposed pad on the DFN/TDFN packages can be connected to VSS or left floating.
Chip Select (CS)
A low level on this pin selects the device. A high level
deselects the device and forces it into Standby mode.
However, a programming cycle which is already
initiated or in progress will be completed, regardless of
the CS input signal. If CS is brought high during a
program cycle, the device will go into Standby mode as
soon as the programming cycle is complete. When the
device is deselected, SO goes to the high-impedance
state, allowing multiple parts to share the same SPI
bus.
A low-to-high transition on CS after a valid write
sequence initiates an internal write cycle. After
power-up, a low level on CS is required prior to any
sequence being initiated.
2.2
Serial Output (SO)
The SO pin is used to transfer data out of the
25XX020A. During a read cycle, data are shifted out on
this pin after the falling edge of the serial clock.
2.3
Write-Protect (WP)
The WP pin is a hardware write-protect input pin.
When it is low, all writes to the array or STATUS
register are disabled, but any other operations
function normally. When WP is high, all functions,
including nonvolatile writes, operate normally. At any
time, when WP is low, the write enable latch will be
reset and programming will be inhibited. However, if a
write cycle is already in progress, WP going low will
not change or disable the write cycle. See Table 3-4
for the Write-Protect Functionality Matrix.
2.4
2.5
Serial Clock (SCK)
The SCK is used to synchronize the communication
between a host and the 25XX020A. Instructions,
addresses or data present on the SI pin are latched on
the rising edge of the clock input, while data on the SO
pin are updated after the falling edge of the clock input.
2.6
Hold (HOLD)
The HOLD pin is used to suspend transmission to the
25XX020A while in the middle of a serial sequence
without having to retransmit the entire sequence again.
It must be held high any time this function is not being
used. Once the device is selected and a serial
sequence is underway, the HOLD pin may be pulled
low to pause further serial communication without
resetting the serial sequence.
The HOLD pin must be brought low while SCK is low,
otherwise the HOLD function will not be invoked until
the next SCK high-to-low transition. The 25XX020A
must remain selected during this sequence. The SI and
SCK levels are “don’t cares” during the time the device
is paused and transitions on these pins will be ignored.
To resume serial communication, HOLD must be
brought high while the SCK pin is low, otherwise serial
communication will not be resumed until the next SCK
high-to-low transition.
The SO line will tri-state immediately upon a
high-to-low transition of the HOLD pin and will begin
outputting again immediately upon a subsequent
low-to-high transition of the HOLD pin, independent of
the state of SCK.
Serial Input (SI)
The SI pin is used to transfer data into the device. It
receives instructions, addresses and data. Data are
latched on the rising edge of the serial clock.
DS20001833H-page 6
2003-2022 Microchip Technology Inc. and its subsidiaries
25AA020A/25LC020A
3.0
FUNCTIONAL DESCRIPTION
3.1
Principles of Operation
BLOCK DIAGRAM
STATUS
Register
The 25XX020A is a 256-byte Serial EEPROM
designed to interface directly with the Serial Peripheral
Interface (SPI) port of many of today’s popular
microcontroller families, including Microchip’s PIC®
microcontrollers. It may also interface with
microcontrollers that do not have a built-in SPI port by
using discrete I/O lines programmed properly in
software to match the SPI protocol.
The 25XX020A contains an 8-bit instruction register.
The device is accessed via the SI pin, with data being
clocked in on the rising edge of SCK. The CS pin must
be low and the HOLD pin must be high for the entire
operation.
Table 3-1 contains a list of the possible instruction
bytes and format for device operation. All instructions,
addresses and data are transferred Most Significant bit
(MSb) first, Least Significant bit (LSb) last.
I/O Control
Logic
EEPROM
Array
X
Dec
SI
SO
Y Decoder
CS
SCK
Sense Amp.
R/W Control
HOLD
WP
VCC
VSS
INSTRUCTION SET
Instruction Name
READ
WRITE
Instruction Format
Description
0000
x011(1)
Read data from memory array beginning at selected address
0000
x010(1)
Write data to memory array beginning at selected address
WRDI
0000 x100(1)
WREN
0000
x110(1)
RDSR
0000 x101(1)
Read STATUS register
WRSR
x001(1)
Write STATUS register
Note 1:
Memory
Control
Logic
Page Latches
Data (SI) are sampled on the first rising edge of SCK
after CS goes low. If the clock line is shared with other
peripheral devices on the SPI bus, the user can assert
the HOLD input and place the 25XX020A in ‘HOLD’
mode. After releasing the HOLD pin, operation will
resume from the point when the HOLD was asserted.
TABLE 3-1:
HV Generator
0000
Reset the write enable latch (disable write operations)
Set the write enable latch (enable write operations)
x = don’t care
2003-2022 Microchip Technology Inc. and its subsidiaries
DS20001833H-page 7
25AA020A/25LC020A
3.2
Read Sequence
The device is selected by pulling CS low. The 8-bit
READ instruction is transmitted to the 25XX020A
followed by an 8-bit address. See Figure 3-1 for more
details.
After the correct READ instruction and address are sent,
the data stored in the memory at the selected address
are shifted out on the SO pin. Data stored in the memory at the next address can be read sequentially by
continuing to provide clock pulses to the client.
The internal Address Pointer automatically increments
to the next higher address after each byte of data is
shifted out. When the highest address is reached
(FFh), the address counter rolls over to address 00h
allowing the read cycle to be continued indefinitely. The
read operation is terminated by raising the CS pin
(Figure 3-1).
FIGURE 3-1:
READ SEQUENCE
CS
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
SCK
Instruction
SI
0
0
0
0
0
Address Byte
0
1
1 A7 A6 A5 A4 A3 A2 A1 A0
Data Out
High-Impedance
SO
DS20001833H-page 8
7
6
5
4
3
2
1
0
2003-2022 Microchip Technology Inc. and its subsidiaries
25AA020A/25LC020A
3.3
Write Sequence
Note:
Prior to any attempt to write data to the 25XX020A, the
write enable latch must be set by issuing the WREN
instruction (Figure 3-4). This is done by setting CS low
and then clocking out the proper instruction into the
25XX020A. After all eight bits of the instruction are
transmitted, CS must be driven high to set the write
enable latch.
If the write operation is initiated immediately after the
WREN instruction without CS driven high, the data will
not be written to the array because the write enable
latch will not have been properly set.
After setting the write enable latch, the user may
proceed by driving CS low, issuing a WRITE instruction,
followed by the remainder of the address and then the
data to be written. Up to 16 bytes of data can be sent to
the device before a write cycle is necessary. The only
restriction is that all of the bytes must reside in the
same page. Additionally, a page address begins with
XXXX 0000 and ends with XXXX 1111. If the internal
address counter reaches XXXX 1111 and clock signals
continue to be applied to the chip, the address counter
will roll back to the first address of the page and
overwrite any data that previously existed in those
locations.
FIGURE 3-2:
Page write operations are limited to
writing bytes within a single physical page,
regardless of the number of bytes
actually being written. Physical page
boundaries start at addresses that are
integer multiples of the page buffer size
(or ‘page size’) and end at addresses that
are integer multiples of page size – 1. If a
Page Write command attempts to write
across a physical page boundary, the
result is that the data wrap around to the
beginning of the current page (overwriting
data previously stored there), instead of
being written to the next page as might be
expected. It is therefore necessary for the
application software to prevent page write
operations that would attempt to cross a
page boundary.
For the data to be actually written to the array, the CS
must be brought high after the Least Significant bit (D0)
of the nth data byte has been clocked in. If CS is driven
high at any other time, the write operation will not be
completed. Refer to Figure 3-2 and Figure 3-3 for more
detailed illustrations on the byte write sequence and
the page write sequence, respectively. While the write
is in progress, the STATUS register may be read to
check the status of the WIP, WEL, BP1 and BP0 bits
(Figure 3-6). Attempting to read a memory array
location will not be possible during a write cycle. Polling
the WIP bit in the STATUS register is recommended in
order to determine if a write cycle is in progress. When
the write cycle is completed, the write enable latch is
reset.
BYTE WRITE SEQUENCE
CS
0
1
2
0
0
0
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
Twc(1)
SCK
Address Byte
Instruction
SI
0
0
0 1
0 A7 A6 A5 A4 A3 A2 A1 A0 7
SO
Data Byte
6
5
4
3
2
1
0
High-Impedance
Note 1: This sequence initiates a self-timed internal write cycle on the rising edge of CS after a valid sequence.
2003-2022 Microchip Technology Inc. and its subsidiaries
DS20001833H-page 9
25AA020A/25LC020A
FIGURE 3-3:
PAGE WRITE SEQUENCE
CS
0
1
2
0
0
0
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
SCK
Address Byte
Instruction
SI
0
0
Data Byte 1
0 A7 A6 A5 A4 A3 A2 A1 A0 7
0 1
6
5
4
3
2
1
0
CS
(1)
TWC
24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
SCK
Data Byte 2
SI
7
6
5
4
3
2
Data Byte 3
1
0
7
6
5
4
3
2
Data Byte n (16 max)
1
0
7
6
5
4
3
2
1
0
Note 1: This sequence initiates a self-timed internal write cycle on the rising edge of CS after a valid sequence.
DS20001833H-page 10
2003-2022 Microchip Technology Inc. and its subsidiaries
25AA020A/25LC020A
3.4
Write Enable (WREN) and Write
Disable (WRDI)
The following is a list of conditions under which the
write enable latch will be reset:
•
•
•
•
•
The 25XX020A contains a write enable latch. See
Table 3-4 for the Write-Protect Functionality Matrix.
This latch must be set before any write operation will be
completed internally. The WREN instruction will set the
latch and the WRDI will reset the latch.
FIGURE 3-4:
Power-up
WRDI instruction successfully executed
WRSR instruction successfully executed
WRITE instruction successfully executed
WP pin is brought low
WRITE ENABLE SEQUENCE (WREN)
CS
0
1
2
3
4
5
6
7
SCK
0
SI
0
0
0
1
1
0
High-Impedance
SO
FIGURE 3-5:
0
WRITE DISABLE SEQUENCE (WRDI)
CS
0
1
2
3
4
5
6
7
SCK
SI
0
0
0
0
0
1
0
0
High-Impedance
SO
2003-2022 Microchip Technology Inc. and its subsidiaries
DS20001833H-page 11
25AA020A/25LC020A
3.5
Read Status Register Instruction
(RDSR)
The Write Enable Latch (WEL) bit indicates the status
of the write enable latch and is read-only. When set to
a ‘1’, the latch allows writes to the array, when set to
a ‘0’, the latch prohibits writes to the array. The state of
this bit can always be updated via the WREN or WRDI
commands regardless of the state of write protection
on the STATUS register. These commands are shown
in Figure 3-4 and Figure 3-5.
The Read Status Register instruction (RDSR) provides
access to the STATUS register. See Figure 3-6 for the
RDSR timing sequence. The STATUS register may be
read at any time, even during a write cycle. The
STATUS register is formatted as follows:
TABLE 3-2:
The Block Protection (BP0 and BP1) bits indicate
which blocks are currently write-protected. These bits
are set by the user issuing the WRSR instruction (see
Figure 3-7). These bits are nonvolatile and are
described in more detail in Table 3-3.
STATUS REGISTER
7
6
5
4
3
2
1
0
–
–
–
–
W/R
W/R
R
R
X
X
X
X
BP1
BP0 WEL WIP
Note 1:
See Figure 3-6 for the RDSR timing sequence.
W/R = writable/readable. R = read-only.
The Write-In-Process (WIP) bit indicates whether the
25XX020A is busy with a write operation. When set to
a ‘1’, a write is in progress, when set to a ‘0’, no write
is in progress. This bit is read-only.
FIGURE 3-6:
READ STATUS REGISTER TIMING SEQUENCE (RDSR)
CS
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
1
0
SCK
Instruction
SI
0
0
0
0
0
High-Impedance
SO
DS20001833H-page 12
1
0
1
Data from STATUS register
7
6
5
4
3
2
2003-2022 Microchip Technology Inc. and its subsidiaries
25AA020A/25LC020A
3.6
Write Status Register Instruction
(WRSR)
TABLE 3-3:
The Write Status Register instruction (WRSR) allows
the user to write to the nonvolatile bits in the STATUS
register as shown in Table 3-2. Four levels of
protection for the array are selectable by writing to the
appropriate bits in the STATUS register. The user has
the ability to write-protect none, one, two or all four of
the segments of the array as shown in Table 3-3. See
Figure 3-7 for the WRSR timing sequence.
TABLE 3-4:
ARRAY PROTECTION
BP1
BP0
Array Addresses
Write-Protected
0
0
none
0
1
upper 1/4
(C0h-FFh)
1
0
upper 1/2
(80h-FFh)
1
1
all
(00h-FFh)
WRITE-PROTECT FUNCTIONALITY MATRIX
WP
(pin 3)
WEL
(SR bit 1)
Protected Blocks
Unprotected Blocks
STATUS Register
0 (low)
x
Protected
Protected
Protected
1 (high)
0
Protected
Protected
Protected
1 (high)
1
Protected
Writable
Writable
Note 1:
x = don’t care
FIGURE 3-7:
WRITE STATUS REGISTER TIMING SEQUENCE (WRSR)
CS
(1)
TWC
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
1
0
SCK
Instruction
SI
0
0
0
0
Data to STATUS register
0
0
0
1
7
6
5
4
3
2
High-Impedance
SO
Note 1: This sequence initiates a self-timed internal write cycle on the rising edge of CS after a valid sequence.
2003-2022 Microchip Technology Inc. and its subsidiaries
DS20001833H-page 13
25AA020A/25LC020A
4.0
DATA PROTECTION
The following protection has been implemented to
prevent inadvertent writes to the array:
• The write enable latch is reset on power-up
• A write enable instruction must be issued to set
the write enable latch
• After a byte write, page write or STATUS register
write, the write enable latch is reset
• CS must be set high after the proper number of
clock cycles to start an internal write cycle
• Access to the array during an internal write cycle
is ignored and programming is continued
5.0
POWER-ON STATE
The 25XX020A powers on in the following state:
• The device is in low-power Standby mode
(CS = 1)
• The write enable latch is reset
• SO is in high-impedance state
• A high-to-low-level transition on CS is required to
enter active state
DS20001833H-page 14
2003-2022 Microchip Technology Inc. and its subsidiaries
25AA020A/25LC020A
6.0
PACKAGING INFORMATION
6.1
Package Marking Information
8-Lead 2X3 DFN
XXX
YWW
NN
8-Lead MSOP (150 mil)
XXXXXXT
YWWNNN
8-Lead PDIP (300 mil)
XXXXXXX
T/XXXNNN
YYWW
Example
411
147
13
Example
5L2AI
14713F
Example
25AA020A
I/P e3 13F
2147
8-Lead SOIC
Example
XXXXXXXT
XXXXYYWW
NNN
25AA02AI
SN e3 2147
13F
6-Lead SOT-23
Example
XXNN
2213
8-Lead 2x3 TDFN
Example
XXX
YWW
NN
C14
147
13
8-Lead TSSOP
Example
XXXX
TYWW
NNN
2003-2022 Microchip Technology Inc. and its subsidiaries
5A2A
I147
13F
DS20001833H-page 15
25AA020A/25LC020A
1st Line Marking Codes
Part Number
DFN
I-Temp.
E-Temp.
MSOP
SOT-23
I-Temp.
TDFN
E-Temp.
I-Temp.
TSSOP
E-Temp.
Standard
25AA020A
411
—
5A2AT
22NN
—
C11
—
5A2A
25LC020A
414
415
5L2AT
25NN
26NN
C14
C15
5L2A
Legend: XX...X
T
Y
YY
WW
NNN
e3
Part number or part number code
Temperature (I, E)
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code (2 characters for small packages)
RoHS-compliant JEDEC® designator for Matte Tin (Sn)
Note:
For very small packages with no room for the RoHS-compliant JEDEC®
designator e3 , the marking will only appear on the outer carton or reel label.
Note:
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
DS20001833H-page 16
2003-2022 Microchip Technology Inc. and its subsidiaries
25AA020A/25LC020A
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