25AA256T-I/SN

25AA256/25LC256 256K SPI Bus Serial EEPROM Device Selection Table Part Number VCC Range Page Size Temp. Ranges 25LC256 2.5V-5.5V 64 Bytes I, E MF, P, SN, SM, ST 25AA256 1.8V-5.5V 64 Bytes I, E MF, P, SN, SM, ST Features Packages Pin Function Table • Maximum Clock 10 MHz • Low-Power CMOS Technology: - Maximum Write current: 5 mA at 5.5V, 10 MHz - Read current: 6 mA at 5.5V, 10 MHz - Standby current: 1 µA at 5.5V • 32,768 x 8-Bit Organization • 64-Byte Page • Self-Timed Erase and Write Cycles (5 ms maximum) • Block Write Protection: - Protect none, 1/4, 1/2 or all of array • Built-In Write Protection: - Power-on/off data protection circuitry - Write enable latch - Write-protect pin • Sequential Read • High Reliability: - Endurance: 1,000,000 erase/write cycles - Data retention: > 200 years - ESD protection: > 4000V • Temperature Ranges Supported: - Industrial (I): -40C to +85C - Extended (E): -40°C to +125°C Name Function CS Chip Select Input SO Serial Data Output WP Write-Protect VSS Ground SI Serial Data Input SCK Serial Clock Input HOLD Hold Input VCC Supply Voltage Description The Microchip Technology Inc. 25AA256/25LC256 (25XX256(1)) are 256-Kbit Serial Electrically Erasable PROMs. The memory is accessed via a simple Serial Peripheral Interface (SPI) compatible serial bus. The bus signals required are a clock input (SCK) plus separate data in (SI) and data out (SO) lines. Access to the device is controlled through a Chip Select (CS) input. Communication to the device can be paused via the hold pin (HOLD). While the device is paused, transitions on its inputs will be ignored, with the exception of Chip Select, allowing the host to service higher priority interrupts. • RoHS Compliant • Automotive AEC-Q100 Qualified Note 1: 25XX256 is used in this document as a generic part number for the 25AA256/25LC256 devices. Packages • 8-Lead DFN-S, 8-Lead PDIP, 8-Lead SOIC, 8-Lead SOIJ and 8-Lead TSSOP Package Types (not to scale) DFN-S CS SO WP VSS PDIP/SOIC 1 8 2 7 3 6 4 5 VCC HOLD SCK SI CS SO WP Vss 1 2 3 4  2003-2021 Microchip Technology Inc. Vcc HOLD HOLD VCC 6 SCK CS SO 5 SI 8 7 TSSOP Rotated TSSOP 1 8 2 7 3 6 4 5 SCK CS SI SO VSS WP WP VSS 1 8 2 7 3 6 4 5 VCC HOLD SCK SI DS20001822J-page 1 25AA256/25LC256 1.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings (†) VCC .............................................................................................................................................................................6.5V All inputs and outputs w.r.t. VSS ......................................................................................................... -0.6V to VCC +1.0V Storage temperature ...............................................................................................................................-65°C to +150°C Ambient temperature under bias .............................................................................................................-40°C to +125°C ESD protection on all pins ..........................................................................................................................................4 kV † NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for an extended period of time may affect device reliability. TABLE 1-1: DC CHARACTERISTICS DC CHARACTERISTICS Industrial (I): TA = -40°C to +85°C VCC = 1.8V to 5.5V Extended (E): TA = -40°C to +125°C VCC = 1.8V to 5.5V Param. Symbol No. Minimum Maximum Units D001 VIH Characteristic High-Level Input Voltage Test Conditions 0.7 VCC VCC +1 V -0.3 0.3 VCC V VCC2.5V -0.3 0.2 VCC V VCC < 2.5V Low-Level Output Voltage — 0.4 V IOL = 2.1 mA, VCC = 4.5V — 0.2 V IOL = 1.0 mA, VCC = 2.5V High-Level Output Voltage VCC -0.5 — V IOH = -400 µA D002 VIL D003 VIL D004 VOL D005 VOL D006 VOH D007 ILI Input Leakage Current — ±1 µA CS = VCC, VIN = VSS or VCC D008 ILO Output Leakage Current — ±1 µA CS = VCC, VOUT = VSS or VCC D009 CINT Internal Capacitance (All Inputs and Outputs) — 7 pF TA = 25°C, FCLK = 1.0 MHz, VCC = 5.0V (Note 2) — 6 mA D010 ICC Read VCC = 5.5V; FCLK = 10.0 MHz; SO = Open — 2.5 mA VCC = 2.5V; FCLK = 5.0 MHz; SO = Open — 5 mA VCC = 5.5V — 3 mA VCC = 2.5V — 5 µA CS = VCC = 5.5V, Inputs tied to VCC or VSS, +125°C — 1 µA CS = VCC = 5.5V, Inputs tied to VCC or VSS, +85°C D011 Low-Level Input Voltage Operating Current ICC Write D012 ICCS Standby Current Note 1: 2: Typical measurements taken at room temperature (+25°C). This parameter is periodically sampled and not 100% tested. DS20001822J-page 2  2003-2021 Microchip Technology Inc. 25AA256/25LC256 TABLE 1-2: AC CHARACTERISTICS Industrial (I): TA = -40°C to +85°C VCC = 1.8V to 5.5V Extended (E): TA = -40°C to +125°C VCC = 1.8V to 5.5V AC CHARACTERISTICS Param. Symbol No. 1 FCLK 2 TCSS 3 TCSH 4 TCSD 5 TSU Characteristic Clock Frequency CS Setup Time CS Hold Time CS Disable Time Data Setup Time 6 THD Data Hold Time 7 TR CLK Rise Time 8 TF CLK Fall Time 9 THI Clock High Time Minimum Maximum Units Test Conditions — 10 MHz 4.5V Vcc  5.5V — 5 MHz 2.5V Vcc  4.5V — 3 MHz 1.8V Vcc  2.5V 50 — ns 4.5V Vcc  5.5V 100 — ns 2.5V Vcc  4.5V 150 — ns 1.8V Vcc  2.5V 100 — ns 4.5V Vcc  5.5V 200 — ns 2.5V Vcc  4.5V 250 — ns 1.8V Vcc  2.5V 50 — ns 10 — ns 4.5V Vcc  5.5V 20 — ns 2.5V Vcc  4.5V 30 — ns 1.8V Vcc  2.5V 20 — ns 4.5V Vcc  5.5V 40 — ns 2.5V Vcc  4.5V 50 — ns 1.8V Vcc  2.5V — 100 ns Note 1 — 100 ns Note 1 50 — ns 4.5V Vcc  5.5V 100 — ns 2.5V Vcc  4.5V 150 — ns 1.8V Vcc  2.5V 50 — ns 4.5V Vcc  5.5V 100 — ns 2.5V Vcc  4.5V 1.8V Vcc  2.5V 10 TLO Clock Low Time 150 — ns 11 TCLD Clock Delay Time 50 — ns 12 TCLE Clock Enable Time 50 — ns — 50 ns 4.5V Vcc  5.5V — 100 ns 2.5V Vcc  4.5V — 160 ns 1.8V Vcc  2.5V 0 — ns Note 1 — 40 ns 4.5V Vcc  5.5V (Note 1) — 80 ns 2.5V Vcc  4.5V (Note 1) — 160 ns 1.8V Vcc  2.5V (Note 1) 20 — ns 4.5V Vcc  5.5V 40 — ns 2.5V Vcc  4.5V 80 — ns 1.8V Vcc  2.5V 13 14 15 16 TV THO TDIS THS Output Valid from Clock Low Output Hold Time Output Disable Time HOLD Setup Time Note 1: This parameter is periodically sampled and not 100% tested. 2: TWC begins on the rising edge of CS after a valid write sequence and ends when the internal write cycle is complete. 3: This parameter is not tested but ensured by characterization.  2003-2021 Microchip Technology Inc. DS20001822J-page 3 25AA256/25LC256 TABLE 1-2: AC CHARACTERISTICS (CONTINUED) Industrial (I): TA = -40°C to +85°C VCC = 1.8V to 5.5V Extended (E): TA = -40°C to +125°C VCC = 1.8V to 5.5V AC CHARACTERISTICS Param. Symbol No. 17 THH 18 HOLD Low to Output High-Z THV 20 Minimum Maximum HOLD Hold Time THZ 19 Characteristic HOLD High to Output Valid TWC 21 Units Test Conditions 20 — ns 4.5V Vcc  5.5V 40 — ns 2.5V Vcc  4.5V 80 — ns 1.8V Vcc  2.5V — 30 ns 4.5V Vcc  5.5V (Note 1) — 60 ns 2.5V Vcc  4.5V (Note 1) — 160 ns 1.8V Vcc  2.5V (Note 1) — 30 ns 4.5V Vcc  5.5V — 60 ns 2.5V Vcc  4.5V — 160 ns 1.8V Vcc  2.5V ms Note 2 Internal Write Cycle Time — 5 Endurance 1M — E/W Cycles +25°C, VCC = 5.5V (Note 3) Note 1: This parameter is periodically sampled and not 100% tested. 2: TWC begins on the rising edge of CS after a valid write sequence and ends when the internal write cycle is complete. 3: This parameter is not tested but ensured by characterization. TABLE 1-3: AC TEST CONDITIONS AC Waveform VLO = 0.2V — VH I = VCC – 0.2V Note 1 VH I = 4.0V Note 2 CL = 50 pF — Timing Measurement Reference Level Input 0.5 VCC Output 0.5 VCC Note 1: 2: For VCC  4.0V For VCC > 4.0V DS20001822J-page 4  2003-2021 Microchip Technology Inc. 25AA256/25LC256 FIGURE 1-1: HOLD TIMING CS 17 16 17 16 SCK 18 SO n+2 SI n+2 n+1 n 19 High-Impedance n 5 Don’t Care n+1 n-1 n n n-1 HOLD FIGURE 1-2: SERIAL INPUT TIMING 4 CS 2 7 Mode 1,1 SCK 3 8 12 11 Mode 0,0 5 SI 6 MSb in LSb in High-Impedance SO FIGURE 1-3: SERIAL OUTPUT TIMING CS 9 3 10 Mode 1,1 SCK Mode 0,0 13 SO 14 MSB out SI  2003-2021 Microchip Technology Inc. 15 LSB out Don’t Care DS20001822J-page 5 25AA256/25LC256 2.0 PIN DESCRIPTIONS The descriptions of the pins are listed in Table 2-1. TABLE 2-1: PIN FUNCTION TABLE DFN-S(1) PDIP SOIC TSSOP Rotated TSSOP CS 1 1 1 1 3 Chip Select Input SO 2 2 2 2 4 Serial Data Output WP 3 3 3 3 5 Write-Protect Pin VSS 4 4 4 4 6 Ground SI 5 5 5 5 7 Serial Data Input SCK 6 6 6 6 8 Serial Clock Input HOLD 7 7 7 7 1 Hold Input VCC 8 8 8 8 2 Supply Voltage Name Note 1: 2.1 Exposed pad on DFN-S package can be connected to VSS or left floating. Chip Select (CS) A low level on this pin selects the device. A high level deselects the device and forces it into Standby mode. However, a programming cycle which is already initiated or in progress will be completed, regardless of the CS input signal. If CS is brought high during a program cycle, the device will go into Standby mode as soon as the programming cycle is complete. When the device is deselected, SO goes to the high-impedance state, allowing multiple parts to share the same SPI bus. A low-to-high transition on CS after a valid write sequence initiates an internal write cycle. After power-up, a low level on CS is required prior to any sequence being initiated. 2.2 Serial Output (SO) The SO pin is used to transfer data out of the 25XX256. During a read cycle, data are shifted out on this pin after the falling edge of the serial clock. 2.3 Function Write-Protect (WP) This pin is used in conjunction with the WPEN bit in the STATUS register to prohibit writes to the nonvolatile bits in the STATUS register. When WP is low and WPEN is high, writing to the nonvolatile bits in the STATUS register is disabled. All other operations function normally. When WP is high, all functions, including writes to the nonvolatile bits in the STATUS register, operate normally. If the WPEN bit is set, WP low during a STATUS register write sequence will disable writing to the STATUS register. If an internal write cycle has already begun, WP going low will have no effect on the write. The WP pin function is blocked when the WPEN bit in the STATUS register is low. This allows the user to install the 25XX256 in a system with WP pin grounded and still be able to write to the STATUS register. The WP pin functions will be enabled when the WPEN bit is set high. DS20001822J-page 6 2.4 Serial Input (SI) The SI pin is used to transfer data into the device. It receives instructions, addresses and data. Data are latched on the rising edge of the serial clock. 2.5 Serial Clock (SCK) The SCK is used to synchronize the communication between a host and the 25XX256. Instructions, addresses or data present on the SI pin are latched on the rising edge of the clock input, while data on the SO pin is updated after the falling edge of the clock input. 2.6 Hold (HOLD) The HOLD pin is used to suspend transmission to the 25XX256 while in the middle of a serial sequence without having to retransmit the entire sequence again. It must be held high any time this function is not being used. Once the device is selected and a serial sequence is underway, the HOLD pin may be pulled low to pause further serial communication without resetting the serial sequence. The HOLD pin must be brought low while SCK is low, otherwise the HOLD function will not be invoked until the next SCK high-to-low transition. The 25XX256 must remain selected during this sequence. The SI and SCK levels are "don't cares" during the time the device is paused and any transitions on these pins will be ignored. To resume serial communication, HOLD must be brought high while the SCK pin is low, otherwise serial communication will not be resumed until the next SCK high-to-low transition. The SO line will tri-state immediately upon a high-to-low transition of the HOLD pin and will begin outputting again immediately upon a subsequent low-to-high transition of the HOLD pin, independent of the state of SCK.  2003-2021 Microchip Technology Inc. 25AA256/25LC256 3.0 FUNCTIONAL DESCRIPTION 3.1 Principles of Operation BLOCK DIAGRAM The 25XX256 is a 32,768-byte Serial EEPROM designed to interface directly with the Serial Peripheral Interface (SPI) port of many of today’s popular micro controller families, including Microchip’s PIC® microcontrollers. It may also interface with microcontrollers that do not have a built-in SPI port by using discrete I/O lines programmed properly in firmware to match the SPI protocol. The 25XX256 contains an 8-bit instruction register. The device is accessed via the SI pin, with data being clocked in on the rising edge of SCK. The CS pin must be low and the HOLD pin must be high for the entire operation. Table 3-1 contains a list of the possible instruction bytes and format for device operation. All instructions, addresses and data are transferred MSb first, LSb last. Data (SI) are sampled on the first rising edge of SCK after CS goes low. If the clock line is shared with other peripheral devices on the SPI bus, the user can assert the HOLD input and place the 25XX256 in HOLD mode. After releasing the HOLD pin, operation will resume from the point when the HOLD was asserted. TABLE 3-1: STATUS Register I/O Control Logic HV Generator Memory Control Logic EEPROM Array X Dec Page Latches SI SO Y Decoder CS SCK Sense Amp. R/W Control HOLD WP VCC VSS INSTRUCTION SET Instruction Name Instruction Format Description READ 0000 0011 Read data from memory array beginning at selected address WRITE 0000 0010 Write data to memory array beginning at selected address WRDI 0000 0100 Reset the write enable latch (disable write operations) WREN 0000 0110 Set the write enable latch (enable write operations) RDSR 0000 0101 Read STATUS register WRSR 0000 0001 Write STATUS register  2003-2021 Microchip Technology Inc. DS20001822J-page 7 25AA256/25LC256 3.2 Read Sequence Once the write enable latch is set, the user may proceed by setting the CS low, issuing a WRITE instruction, followed by the 16-bit address, with the first MSb of the address being a “don’t care” bit and then the data to be written. Up to 64 bytes of data can be sent to the device before a write cycle is necessary. The only restriction is that all of the bytes must reside in the same page. The device is selected by pulling CS low. The 8-bit READ instruction is transmitted to the 25XX256 followed by the 16-bit address, with the first MSb of the address being a “don’t care” bit. After the correct READ instruction and address are sent, the data stored in the memory at the selected address are shifted out on the SO pin. The data stored in the memory at the next address can be read sequentially by continuing to provide clock pulses. The internal Address Pointer is automatically incremented to the next higher address after each byte of data is shifted out. When the highest address is reached (7FFFh), the address counter rolls over to address 0000h allowing the read cycle to be continued indefinitely. The read operation is terminated by raising the CS pin (Figure 3-1). 3.3 Note: Page write operations are limited to writing bytes within a single physical page, regardless of the number of bytes actually being written. Physical page boundaries start at addresses that are integer multiples of the page buffer size (or ‘page size’) and, end at addresses that are integer multiples of page size – 1. If a page write command attempts to write across a physical page boundary, the result is that the data wraps around to the beginning of the current page (overwriting data previously stored there), instead of being written to the next page as might be expected. It is therefore necessary for the application software to prevent page write operations that would attempt to cross a page boundary. Write Sequence Prior to any attempt to write data to the 25XX256, the write enable latch must be set by issuing the WREN instruction (Figure 3-4). This is done by setting CS low and then clocking out the proper instruction into the 25XX256. After all eight bits of the instruction are transmitted, the CS must be brought high to set the write enable latch. If the write operation is initiated immediately after the WREN instruction without CS being brought high, the data will not be written to the array because the write enable latch will not have been properly set. FIGURE 3-1: For the data to be actually written to the array, the CS must be brought high after the Least Significant bit (D0) of the nth data byte has been clocked in. If CS is brought high at any other time, the write operation will not be completed. Refer to Figure 3-2 and Figure 3-3 for more detailed illustrations on the byte write sequence and the page write sequence, respectively. While the write is in progress, the STATUS register may be read to check the status of the Write-In-Process (WIP) bit (Figure 3-6). A read attempt of a memory array location will not be possible during a write cycle. When the write cycle is completed, the write enable latch is reset. READ SEQUENCE CS 0 1 2 3 4 5 6 7 8 9 10 11 21 22 23 24 25 26 27 28 29 30 31 SCK Instruction SI 0 0 0 0 0 16-bit Address 0 1 1 15 14 13 12 2 1 0 Data Out High-Impedance SO DS20001822J-page 8 7 6 5 4 3 2 1 0  2003-2021 Microchip Technology Inc. 25AA256/25LC256 FIGURE 3-2: BYTE WRITE SEQUENCE CS (1) Twc 0 1 2 0 0 0 3 4 8 5 6 7 9 10 11 21 22 23 24 25 26 27 28 29 30 31 0 1 0 15 14 13 12 SCK Instruction SI 0 0 16-bit Address Data Byte 2 1 0 7 6 5 4 3 2 1 0 High-Impedance SO Note 1: This sequence initiates a self-timed internal write cycle on the rising edge of CS after a valid sequence. FIGURE 3-3: PAGE WRITE SEQUENCE CS 0 1 2 3 4 5 6 7 8 9 10 11 21 22 23 24 25 26 27 28 29 30 31 SCK Instruction SI 0 0 0 0 0 16-bit Address 0 1 0 15 14 13 12 Data Byte 1 2 1 0 7 6 5 4 3 2 1 0 CS (1) Twc 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 SCK Data Byte 2 SI 7 6 5 4 3 2 Data Byte 3 1 0 7 6 5 4 3 2 Data Byte n (64 max) 1 0 7 6 5 4 3 2 1 0 Note 1: This sequence initiates a self-timed internal write cycle on the rising edge of CS after a valid sequence.  2003-2021 Microchip Technology Inc. DS20001822J-page 9 25AA256/25LC256 3.4 Write Enable (WREN) and Write Disable (WRDI) The following is a list of conditions under which the write enable latch will be reset: • • • • The 25XX256 contains a write enable latch. See Table 5-1 for the Write-Protect Functionality Matrix. This latch must be set before any write operation will be completed internally. The WREN instruction will set the latch and the WRDI will reset the latch. FIGURE 3-4: Power-up WRDI instruction successfully executed WRSR instruction successfully executed WRITE instruction successfully executed WRITE ENABLE SEQUENCE (WREN) CS 0 1 2 3 4 5 6 7 SCK 0 SI 0 0 0 1 1 0 High-Impedance SO FIGURE 3-5: 0 WRITE DISABLE SEQUENCE (WRDI) CS 0 1 2 3 4 5 6 7 SCK SI 0 0 0 0 0 1 10 0 High-Impedance SO DS20001822J-page 10  2003-2021 Microchip Technology Inc. 25AA256/25LC256 3.5 Read STATUS Register Instruction (RDSR) The Write Enable Latch (WEL) bit indicates the STATUS of the write enable latch and is read-only. When set to a ‘1’, the latch allows writes to the array, when set to a ‘0’, the latch prohibits writes to the array. The state of this bit can always be updated via the WREN or WRDI commands, regardless of the state of write protection on the STATUS register. These commands are shown in Figure 3-4 and Figure 3-5. The Read STATUS Register instruction (RDSR) pr ovides access to the STATUS register. The STATUS register may be read at any time, even during a write cycle. The STATUS register is formatted as follows: TABLE 3-2: STATUS REGISTER 7 6 5 4 3 2 1 0 W/R - - - W/R W/R R R x x x BP1 BP0 WEL WIP WPEN Note 1: The Block Protection (BP0 and BP1) bits indicate which blocks are currently write-protected. These bits are set by the user issuing the WRSR instruction. These bits are nonvolatile and are shown in Table 3-3. See Figure 3-6 for the RDSR timing sequence. W/R = writable/readable. R = read-only. The Write-In-Process (WIP) bit indicates whether the 25XX256 is busy with a write operation. When set to a ‘1’, a write is in progress, when set to a ‘0’, no write is in progress. This bit is read-only. FIGURE 3-6: READ STATUS REGISTER TIMING SEQUENCE (RDSR) CS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 1 0 SCK Instruction SI 0 0 0 0 0 High-Impedance SO Note: 1 0 1 Data from STATUS Register 7 6 5 4 3 2 Bits 7-1 of the STATUS register are undetermined during a write cycle.  2003-2021 Microchip Technology Inc. DS20001822J-page 11 25AA256/25LC256 3.6 Write STATUS Register Instruction (WRSR) See Figure 3-7 for the WRSR timing sequence. TABLE 3-3: The Write STATUS Register instruction (WRSR) allows the user to write to the nonvolatile bits in the STATUS register as shown in Table 3-2. The user is able to select one of four levels of protection for the array by writing to the appropriate bits in the STATUS register. The array is divided up into four segments. The user has the ability to write-protect none, one, two or all four of the segments of the array. The partitioning is controlled as shown in Table 3-3. BP1 BP0 Array Addresses Write Protected 0 0 none 0 1 upper 1/4 (6000h-7FFFh) 1 0 upper 1/2 (4000h-7FFFh) 1 1 all (0000h-7FFFh) The Write-Protect Enable (WPEN) bit is a nonvolatile bit that is available as an enable bit for the WP pin. The Write-Protect (WP) pin and the Write-Protect Enable (WPEN) bit in the STATUS register control the programmable hardware write-protect feature. Hardware write protection is enabled when WP pin is low and the WPEN bit is high. Hardware write protection is disabled when either the WP pin is high or the WPEN bit is low. When the chip is hardware Write-Protected, only writes to nonvolatile bits in the STATUS register are disabled. See Table 5-1 for a matrix of functionality on the WPEN bit. FIGURE 3-7: ARRAY PROTECTION WRITE STATUS REGISTER TIMING SEQUENCE (WRSR) CS Twc 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 1 0 (1) SCK Instruction SI 0 0 0 0 Data to STATUS Register 0 0 0 1 7 6 5 4 3 2 High-Impedance SO Note 1: This sequence initiates a self-timed internal write cycle on the rising edge of CS after a valid sequence. DS20001822J-page 12  2003-2021 Microchip Technology Inc. 25AA256/25LC256 4.0 DATA PROTECTION 5.0 The following protection has been implemented to prevent inadvertent writes to the array: • The write enable latch is reset on power-up • A write enable instruction must be issued to set the write enable latch • After a byte write, page write or STATUS register write, the write enable latch is reset • CS must be set high after the proper number of clock cycles to start an internal write cycle • Access to the array during an internal write cycle is ignored and programming is continued TABLE 5-1: POWER-ON STATE The 25XX256 powers on in the following state: • The device is in low-power Standby Mode (CS = 1) • The write enable latch is reset • SO is in high-impedance state • A high-to-low-level transition on cs is required to enter active state WRITE-PROTECT FUNCTIONALITY MATRIX WEL (SR bit 1) WPEN (SR bit 7) WP pin Protected Blocks Unprotected Blocks STATUS Register 0 x x Protected Protected Protected 1 0 x Protected Writable Writable 1 1 0 (low) Protected Writable Protected 1 1 1 (high) Protected Writable Writable Note 1: x = don’t care  2003-2021 Microchip Technology Inc. DS20001822J-page 13 25AA256/25LC256 6.0 PACKAGING INFORMATION 6.1 Package Marking Information 8-Lead DFN-S Example XXXXXXX T/XXXXX YYWW NNN 25LC256 I/MF e3 2117 13F 8-Lead PDIP Example XXXXXXXX T/XXXNNN YYWW 8-Lead SOIC Example XXXXXXXT XXXXYYWW NNN 25LC256I SN e3 2117 13F 8-Lead SOIJ Example XXXXXXXX TXXXXXXX YYWWNNN 8-Lead TSSOP XXXX TYWW NNN DS20001822J-page 14 25LC256 I/P e3 13F 2117 25LC256 I/SM e3 211713F Example 5LE I117 13F  2003-2021 Microchip Technology Inc. 25AA256/25LC256 1st Line Marking Codes Device DFN-S PDIP SOIC SOIJ TSSOP Rotated TSSOP 25AA256 25AA256 25AA256 25AA256T 25AA256 5AE 5AEX 25LC256 25LC256 25LC256 25LC256T 25LC256 5LE 5LEX Legend: XX...X T Y YY WW NNN e3 Part number or part number code Temperature (I, E) Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week ‘01’) Alphanumeric traceability code (2 characters for small packages) RoHS-compliant JEDEC designator for Matte Tin (Sn) Note: For very small packages with no room for the RoHS-compliant JEDEC designator e3 , the marking will only appear on the outer carton or reel label. Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information.  2003-2021 Microchip Technology Inc. DS20001822J-page 15 25AA256/25LC256 /HDG3ODVWLF'XDO)ODW1R/HDG3DFNDJH0)[PP%RG\>')16@ 6DZ6LQJXODWHG 1RWH )RUWKHPRVWFXUUHQWSDFNDJHGUDZLQJVSOHDVHVHHWKH0LFURFKLS3DFNDJLQJ6SHFLILFDWLRQORFDWHGDW KWWSZZZPLFURFKLSFRPSDFNDJLQJ ' $ % 1 '$780$ '$780% ( 127( ;  &  ;  & & 6($7,1* 3/$1(  7239,(: $  & $ ; $  & 6,'(9,(:  '  & $ %   127( & $ % ( . / 1 ;E H %277209,(:   & $ % & 0LFURFKLS7HFKQRORJ\'UDZLQJ&5HY&6KHHWRI DS20001822J-page 16  2003-2021 Microchip Technology Inc. 25AA256/25LC256 /HDG3ODVWLF'XDO)ODW1R/HDG3DFNDJH0)[PP%RG\>')16@ 6DZ6LQJXODWHG 1RWH )RUWKHPRVWFXUUHQWSDFNDJHGUDZLQJVSOHDVHVHHWKH0LFURFKLS3DFNDJLQJ6SHFLILFDWLRQORFDWHGDW KWWSZZZPLFURFKLSFRPSDFNDJLQJ 1RWHV     8QLWV 'LPHQVLRQ/LPLWV 1 1XPEHURI7HUPLQDOV H 3LWFK $ 2YHUDOO+HLJKW 6WDQGRII $ 7HUPLQDO7KLFNQHVV $ 2YHUDOO/HQJWK ' ([SRVHG3DG/HQJWK ' ( 2YHUDOO:LGWK ([SRVHG3DG:LGWK ( E 7HUPLQDO:LGWK / 7HUPLQDO/HQJWK . 7HUPLQDOWR([SRVHG3DG 0,1        0,//,0(7(56 120  %6&   5() %6&  %6&     0$;        3LQYLVXDOLQGH[IHDWXUHPD\YDU\EXWPXVWEHORFDWHGZLWKLQWKHKDWFKHGDUHD 3DFNDJHPD\KDYHRQHRUHPRUHH[SRVHGWLHEDUVDWHQGV 3DFNDJHLVVDZVLQJXODWHG 'LPHQVLRQLQJDQGWROHUDQFLQJSHU$60(')16@ 6DZ6LQJXODWHG 1RWH )RUWKHPRVWFXUUHQWSDFNDJHGUDZLQJVSOHDVHVHHWKH0LFURFKLS3DFNDJLQJ6SHFLILFDWLRQORFDWHGDW KWWSZZZPLFURFKLSFRPSDFNDJLQJ ; (9  ‘9 &