25CSM04
4-Mbit SPI Serial EEPROM with 128-Bit Serial Number
and Enhanced Write Protection
Features
• 4-Mbit Serial EEPROM:
- 524,288 x 8 organization
- Page size of 256 bytes
- Byte or sequential reads
- Byte or page writes
- Self-timed write cycle (5 ms maximum)
• Security Register:
- Preprogrammed 128-bit serial number
- 256-byte user-programmable lockable ID
page
• Built-in Error Correction Code (ECC) Logic:
- ECC Status bit via the STATUS register
• JEDEC® SPI Manufacturer Read ID Support
• High-Speed Clock Frequency:
- 8 MHz at VCC ≥ 3.0V
- 5 MHz at VCC ≥ 2.5V
• Legacy Write Protection Mode:
- Block protection functionality (quarter, half or
entire memory array)
• Enhanced Write Protection Mode:
- User-definable memory partitions
- Each partition can be set independently and
have unique protection behavior
• Low-Power CMOS Technology:
- Voltage range: 2.5V to 5.5V
- Write current: 3.0 mA at 5.0V
- Read current: 3.0 mA at 5.0V, 8 MHz
- Standby current: 1.0 µA at 2.5V (I-Temp.)
• High Reliability:
- More than one million erase/write cycles
- Built-in ECC logic for increased reliability
- Data retention: >100 years
- ESD protection: >4000V
• Available Temperature Ranges:
- Industrial (I): -40°C to +85°C
Package Types (not to scale)
8-Lead SOIC
(Top View)
CS
1
8
VCC
SO
2
7
HOLD
WP
3
6
SCK
VSS
4
5
SI
8-Ball CSP
(Top View)
8-Pad TDFN
(Top View)
CS 1
SO 2
WP 3
VSS 4
8 VCC
7 HOLD
6 SCK
VCC
HOLD
5 SI
SCK
SI
CS
SO
WP
VSS
Pin Function Table
Name
Function
CS
Chip Select Input
SO
Serial Data Output
WP
Write-Protect Pin
VSS
Ground
SI
Serial Data Input
SCK
Serial Clock Input
HOLD
Hold Input
VCC
Supply Voltage
Packages
• 8-Lead SOIC, 8-Pad TDFN and 8-Ball CSP
packages
2019-2020 Microchip Technology Inc.
DS20005817C-page 1
25CSM04
General Description
The Microchip Technology Inc. 25CSM04 provides
4 Mbits of Serial EEPROM utilizing the Serial
Peripheral Interface (SPI) compatible bus. The device
is organized as 524,288 bytes of 8 bits each
(512 Kbyte) and is optimized for use in consumer and
industrial applications where reliable and dependable
nonvolatile memory storage is essential. The
25CSM04 is capable of operation across a broad
voltage range (2.5V to 5.5V).
The bus signals required are a clock input (SCK) plus
separate data in (SI) and data out (SO) lines. Access to
the device is controlled through a Chip Select (CS)
input. Communication to the device can be paused via
the HOLD pin. While the device is paused, transitions
on its inputs will be ignored, with the exception of Chip
Select, allowing the host to service higher priority
interrupts.
The 25CSM04 features a nonvolatile Security register
independent of the 4 Mbit main memory array. The first
half of the Security register is read-only and contains a
factory-programmed, globally unique 128-bit serial
number in the first 16 bytes. The 128-bit serial number
is unique across the entire CS series of Serial
EEPROM products and eliminates the time consuming
step of performing and ensuring serialization of a
product on a manufacturing line. The 128-bit read-only
serial number is followed by an additional 256 bytes of
user-programmable EEPROM.
The user-programmable section of the Security
register can later be permanently write-protected via a
software sequence.
The 25CSM04 features a configurable write protection
scheme which allows the user to select Legacy Write
Protection mode or Enhanced Write Protection mode.
Legacy Write Protection mode enables the Block
Protection function via the STATUS register. Enhanced
Write Protection mode segments the memory into
independent partitions. Each partition can be
configured to inhibit writing based on the status of the
Memory Partition register setting.
For added reliability the 25CSM04 uses a built-in Error
Correction Code (ECC) scheme. This scheme can
correct up to one incorrectly read bit within four bytes
read out. Additionally, the 25CSM04 includes a flag in
the STATUS register to report if any errors were
detected and corrected in the most recent memory
array read sequence.
The 25CSM04 features an identification register that
contains identification information that can be read
from the device. This enables the application to
electronically query and identify the 25CSM04 while it
is in the system. The identification method and the
instruction opcode comply with the JEDEC® standard
for “Manufacturer and Device ID Read Methodology for
SPI Compatible Serial Interface Memory Devices”. The
type of information that can be read from the device
includes the JEDEC defined Manufacturer ID, the
vendor-specific Device ID, and the vendor-specific
Extended Device Information (EDI).
Bus Connections for the 25CSM04
2019-2020 Microchip Technology Inc.
DS20005817C-page 2
25CSM04
Block Diagram
Memory
System Control
Module
CS
High Voltage
Generation
Circuit
Power
On Reset
Generator
VCC
Pause
Operation
Control
HOLD
Register Bank:
SO
EEPROM Array
1 page
Row Decoder
STATUS Register
Security Register
Memory Partition Registers
Identification Register
Address Register
and Counter
Security Register
Column Decoder
WP
Data Register
SCK
Data Output
Buffer
VSS
Write Protection
Control
2019-2020 Microchip Technology Inc.
SI
DS20005817C-page 3
25CSM04
1.0
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings (†)
VCC...........................................................................................................................................................................6.25V
All inputs and outputs w.r.t. VSS ...........................................................................................................0.6V to VCC +1.0V
Storage temperature ...............................................................................................................................-65°C to +150°C
Ambient temperature under bias.............................................................................................................-40°C to +120°C
ESD protection on all pins.......................................................................................................................................... 4 kV
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
TABLE 1-1:
DC CHARACTERISTICS
Electrical Characteristics:
Industrial (I):
TA = -40°C to +85°C, VCC = +2.5V to 5.5V
DC CHARACTERISTICS
Param.
Symbol
No.
Characteristic
Min.
Max.
Units
Test Conditions
VIH
High-Level Input Voltage
VCC X 0.7
VCC + 1
V
D002
VIL
Low-Level Input Voltage
-0.3
VCC X 0.3
V
VCC ≥ 2.5V
D003
VOL
Low-Level Output Voltage
—
0.4
V
IOL = 3.0 mA, 3.6V ≤ VCC ≤ 5.5V
D004
VOL
Low-Level Output Voltage
—
0.2
V
IOL = 0.15 mA, 2.5V ≤ VCC ≤ 3.6V
D005
VOH
High-Level Output Voltage
VCC - 0.5
—
V
IOH = -100 µA
D001
D006
ILI
Input Leakage Current
—
±1.0
µA
CS = VCC, VIN = VSS or VCC
D007
ILO
Output Leakage Current
—
±1.0
µA
CS = VCC, VOUT = VSS or VCC
D008
CINT
Internal Capacitance
(all inputs and outputs)
—
7.0
pF
TA = 25°C, FCLK = 1.0 MHz,
VCC = 5.0V (Note 1)
—
3.0
mA
VCC = 5.0V, SCK = 8 MHz,
SO = Open
—
2.0
mA
VCC ≤ 3.0V, SCK = 5 MHz,
SO = Open
—
3.0
mA
VCC = 5.0V
—
2.0
µA
VCC = 5.0V, CS = VCC,
VIN = VCC or VSS
—
1.0
µA
VCC = 2.5V, CS = VCC,
VIN = VCC or VSS
D009
D010
D011
Note 1:
ICCREAD Operating Current
ICCWRITE Operating Current
ICCS
Standby Current
This parameter is not tested but ensured by characterization.
2019-2020 Microchip Technology Inc.
DS20005817C-page 4
25CSM04
TABLE 1-2:
AC CHARACTERISTICS
AC CHARACTERISTICS
Param.
Symbol
No.
1
FCLK
2
TCSS
3
TCSH
4
TCSD
5
TSU
6
THD
Industrial (I):
Characteristic
Clock Frequency
CS Setup Time
CS Hold Time
CS Disable Time
Data Setup Time
Data Hold Time
TA = -40°C to +85°C
VCC = 2.5V to 5.5V
Min.
Max.
Units
Test Conditions
—
8
MHz
VCC ≥ 3.0V
—
5
MHz
VCC ≥ 2.5V
30
—
ns
VCC ≥ 3.0V
60
—
ns
VCC ≥ 2.5V
30
—
ns
VCC ≥ 3.0V
60
—
ns
VCC ≥ 2.5V
30
—
ns
VCC ≥ 3.0V
60
—
ns
VCC ≥ 2.5V
10
—
ns
VCC ≥ 3.0V
20
—
ns
VCC ≥ 2.5V
10
—
ns
VCC ≥ 3.0V
20
—
ns
VCC ≥ 2.5V
7
TR
CLK Rise Time
50
—
ns
Note 1
8
TF
CLK Fall Time
50
—
ns
Note 1
9
THI
Clock High Time
40
—
ns
VCC ≥ 3.0V
80
—
ns
VCC ≥ 2.5V
40
—
ns
VCC ≥ 3.0V
80
—
ns
VCC ≥ 2.5V
10
TLO
Clock Low Time
11
TCLD
Clock Delay Time
50
—
ns
12
TCLE
Clock Enable Time
50
—
ns
13
TV
Output Valid from Clock Low
—
40
ns
VCC ≥ 3.0V
—
80
ns
VCC ≥ 2.5V
14
THO
Output Hold Time
0
—
ns
Note 1
15
TDIS
Output Disable Time
—
40
ns
VCC ≥ 3.0V
—
80
ns
VCC ≥ 2.5V
16
THS
HOLD Setup Time
10
—
ns
VCC ≥ 3.0V
20
—
ns
VCC ≥ 2.5V
17
THH
HOLD Hold Time
10
—
ns
VCC ≥ 3.0V
20
—
ns
VCC ≥ 2.5V
18
THZ
HOLD Low to Output High Z
40
—
ns
VCC ≥ 3.0V (Note 1)
80
—
ns
VCC ≥ 2.5V (Note 1)
19
THV
HOLD High to Output Valid
40
—
ns
VCC ≥ 3.0V
80
—
ns
VCC ≥ 2.5V
20
TWC
Internal Write Cycle Time
—
5
ms
Note 2
Note 1: This parameter is not tested but ensured by characterization.
2: TWC begins on the rising edge of CS after a valid write sequence and ends when the internal write cycle is
complete.
2019-2020 Microchip Technology Inc.
DS20005817C-page 5
25CSM04
FIGURE 1-1:
INPUT TEST WAVEFORMS
AND MEASUREMENT
LEVELS
0.9 VCC
AC
Driving
Level
VCC/2
FIGURE 1-2:
OUTPUT TEST LOAD
Device
under
Test
AC
Measurement
Level
30 pF
0.1 VCC
Note:
tR, tF < 2 ns (10% to 90%)
FIGURE 1-3:
SERIAL INPUT TIMING
4
CS
2
7
Mode 1,1
8
3
12
11
SCK Mode 0,0
5
SI
6
MSB in
LSB in
High-Impedance
SO
FIGURE 1-4:
SERIAL OUTPUT TIMING
CS
9
3
10
Mode 0,0
SCK
13
SO
Mode 1,1
14
MSB out
SI
2019-2020 Microchip Technology Inc.
15
LSB out
Don’t Care
DS20005817C-page 6
25CSM04
FIGURE 1-5:
HOLD TIMING
CS
17
16
17
16
SCK
18
SO
n+2
SI
n+2
n+1
n
High-Impedance
19
n
5
Don’t Care
n+1
n-1
n
n
n-1
HOLD
TABLE 1-3:
EEPROM CELL PERFORMANCE CHARACTERISTICS
Operation
Write Endurance(1,2)
(1)
Test Condition
Min.
Max.
TA = 25°C, 2.5V ≤ VCC ≤ 5.5V
1,000,000
—
Write Cycles
TA = 55°C
100
—
Years
Data Retention
Units
Note 1: Performance is determined through characterization and the qualification process.
2: Due to the memory array architecture, the write cycle endurance is specified for write sequences in groups
of four data bytes. The beginning of any 4-byte boundaries can be determined by multiplying any integer
(N) by four (i.e., 4*N). The end address can be found by adding three to the beginning value (i.e., 4*N+3).
See Section 8.2 “Error Correction Code (ECC) Architecture” for more details on this implementation.
2019-2020 Microchip Technology Inc.
DS20005817C-page 7
25CSM04
1.1
Power-Up Requirements and
Default Conditions
During a power-up sequence, the VCC supplied to the
25CSM04 should monotonically rise from VSS to the
minimum VCC level as specified in Table 1-1 with a
slew rate no faster than 0.1 V/µs.
1.1.1
DEVICE POWER-ON RESET
TABLE 1-4:
POWER-UP CONDITIONS
Symbol
Parameter
Min.
Max.
Units
TVCSL
Minimum VCC to Chip Select Low Time
100
—
µs
VPOR
Power-on Reset Threshold Voltage
—
1.5
V
TPOFF
Minimum time at VCC = 0V between power cycles
1
—
ms
1.1.2
To prevent spurious events from happening during a
power-up sequence, the 25CSM04 includes a
Power-on Reset (POR) circuit. Upon power-up, the
device will not respond to any instructions until the VCC
level crosses the internal voltage threshold (VPOR) that
brings the device out of Reset and into Standby mode.
SOFTWARE RESET
The 25CSM04 includes a Software Device Reset
(SRST) instruction that gives the user the opportunity to
reset the device to its power-on default behavior
(Section 1.2 “Device Default State”) without the need
to power cycle the device. To execute this Reset, first,
the CS pin must be driven low to select the device and
then a 7Ch opcode is clocked in on the SI pin.
Microchip recommends that CS follows the rise of VCC
at power-up through the use of a pull-up resistor. The
system designer must ensure that no instruction is sent
to the device and CS is driven high until the VCC supply
reaches a stable value greater than the minimum VCC
level. Once VCC has surpassed the minimum level, the
SPI master must wait at least TVCSL before asserting
the CS pin. See Table 1-4 for the values associated
with these power-up parameters.
Then the CS pin can be driven high and the Reset
mechanism will engage. The Reset will have internally
completed by the time the minimum TCSD time is
satisfied.
Note:
If an event occurs in the system where the VCC level
supplied to the 25CSM04 drops below the maximum
VPOR level specified, it is recommended that a full
power cycle sequence be performed by first driving the
VCC pin to VSS, waiting at least the minimum TPOFF
time, and then performing a new power-up sequence in
compliance with the requirements defined in this
section.
FIGURE 1-6:
The SRST instruction cannot interrupt the
device while it is in a Busy state
(Section 6.1.4 “Ready/Busy Status
Latch”).
SOFTWARE DEVICE RESET (SRST) INSTRUCTION
CS
0
1
2
3
4
5
6
7
SCK
SRST Opcode (7Ch)
SI
0
MSB
SO
2019-2020 Microchip Technology Inc.
1
1
1
1
1
0
0
High-Impedance
DS20005817C-page 8
25CSM04
1.2
Device Default State
1.2.1
unlocked and set to logic ‘1’ resulting in 256 bytes of
FFh data. In the various device registers, the following
nonvolatile bits are set:
POWER-UP DEFAULT STATE
• Write Protection Enable (WPEN) bit in the
STATUS register is set to logic ‘0’ allowing writing
to the STATUS register. (See Table 1-5).
• Block Write-Protect (BP[1:0] bits in the STATUS
register are logic ‘0’ indicating no write protection
set when in Legacy mode. (See Table 1-5).
• Write Protection Mode (WPM) bit in the STATUS
register is set to logic ‘0’, indicating the device is
set for Legacy Write Protection mode. (See
Table 1-6).
• Freeze Memory Protection Configuration (FMPC)
bit in the STATUS register is set to logic ‘0’,
indicating the Memory Partition Registers (MPRs)
and the Write Protection Mode (WPM) bit are not
locked and can be changed. (See Table 1-6).
• Protect Address Boundary Protection (PABP) bit
in the STATUS register is set to logic ‘0’, indicating the partition endpoint address value in each
MPR can be modified. (See Table 1-6).
• Memory Partition Registers (MPR0-MPR7) are
set to 00h, indicating that the entire 4 Mbit
memory can be written. (See Table 1-7).
The 25CSM04 default state upon power-up consists of:
• Standby mode (CS = HIGH)
• A high-to-low level transition on CS is required to
enter the active state
• Write Enable Latch (WEL) bit in the STATUS
register = 0
• Error Correction State Latch (ECS) bit in the
STATUS register = 0
• Partition Register Write Enable Latch (PREL) bit
in the STATUS register = 0
• Ready/Busy (RDY/BUSY) bit in the STATUS
register = 0, indicating the device is ready to
accept a new instruction
1.2.2
DEVICE FACTORY DEFAULT
CONDITION
The 25CSM04 is shipped to the customer with the
EEPROM array set to an all FFh data pattern (logic ‘1’
state).
The Security register contains a preprogrammed,
128-bit serial number in the lower 16 bytes. The
user-programmable portion (lockable ID page) is
TABLE 1-5:
STATUS REGISTER NONVOLATILE BITS – BYTE 0 (FACTORY DEFAULT)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
WPEN
Reserved
Reserved
Reserved
BP1
BP0
WEL
RDY/BUSY
0
0
0
TABLE 1-6:
STATUS REGISTER NONVOLATILE BITS – BYTE 1 (FACTORY DEFAULT)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
WPM
ECS
FMPC
PREL
PABP
Reserved
Reserved
RDY/BUSY
0
TABLE 1-7:
MPR No.
0
0
MEMORY PARTITION REGISTERS (FACTORY DEFAULT)
Bit 7
Bit 6
Bit 5
Bit 4
A18
A17
A16
Partition Behavior
MPR0
MPR1
MPR2
MPR3
MPR4
MPR5
MPR6
MPR7
Bit 3
Bit 2
Bit 1
Bit 0
A15
A14
A13
Partition Endpoint Address
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
2019-2020 Microchip Technology Inc.
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DS20005817C-page 9
25CSM04
2.0
PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 2-1.
TABLE 2-1:
Name
PIN FUNCTION TABLE
8-Lead SOIC
8-Pad TDFN
8-Ball CSP
Function
CS
1
1
1
Chip Select Input
SO
2
2
2
Serial Data Output
WP
3
3
3
Write-Protect
VSS
4
4
4
Ground
SI
5
5
5
Serial Data Input
SCK
6
6
6
Serial Clock Input
HOLD
7
7
7
Hold Input
VCC
8
8
8
Device Power Supply
2.1
Chip Select (CS)
Asserting the CS pin selects the device. When the CS
pin is deasserted, the device will be deselected and
placed in Standby mode, and the SO pin will be in a
high-impedance state. When the device is deselected,
data will not be accepted on the SI pin.
A high-to-low transition on the CS pin is required to
start a sequence and a low-to-high transition is
required to end a sequence. For write sequences, the
device will not enter Standby mode until the completion
of the self-timed internal write cycle.
2.2
Serial Data Output (SO)
2.5
Serial Clock (SCK)
The Serial Clock (SCK) pin is used to provide a clock
signal to the device and is used to synchronize the flow
of data to and from the device. Instructions, addresses
and data present on SI pin are always latched in on the
rising edge of SCK, while output data on the SO pin is
always clocked out on the falling edge of SCK.
2.6
Hold (HOLD)
When the device is selected and a serial communication sequence is underway, HOLD can be used to
pause the communication with the master device without resetting the serial sequence.
The SO pin is used to shift data out from the device.
Data on the SO pin is always clocked out on the falling
edge of SCK. The SO pin is in a high-impedance state
whenever the device is deselected (CS is deasserted)
as well as when the Hold function is engaged.
2.3
Write-Protect Pin (WP)
The Write-Protect (WP) pin can be used to protect the
STATUS register and memory array contents via the
Block Protection modes when Legacy Write Protection
mode is enabled.
When Enhanced Write Protection mode is enabled, the
WP pin can be used to protect any memory zone in
accordance with how its corresponding Memory
Partition registers are programmed.
2.4
Serial Data Input (SI)
Instructions, addresses, and data are latched by the
25CSM04 on the rising edge of the Serial Clock (SCK)
line via the Serial Data Input (SI) pin.
2019-2020 Microchip Technology Inc.
DS20005817C-page 10
25CSM04
3.0
MEMORY ORGANIZATION
3.1
EEPROM Organization
The 25CSM04 is internally organized as 2,048 pages
of 256 bytes each.
3.2
Device Registers
The 25CSM04 contains four types of registers that
modulate device operation and/or report on the current
status of the device. These registers are:
• STATUS register
• Security register
• Memory Partition registers (eight total)
• Identification register
3.2.1
STATUS REGISTER
The STATUS register is a 16-bit combination of volatile
and nonvolatile bits. It is used to modify the write protection functions as well as store various aspects of the
current status of the device. Details about the STATUS
register are covered in Section 6.0 “STATUS Register”.
3.2.2
SECURITY REGISTER
The Security register is split into a read-only section
and a user-programmable lockable ID page section.
The read-only section contains a preprogrammed,
globally unique, 128-bit serial number.
3.2.3
MEMORY PARTITION REGISTERS
The 25CSM04 is equipped with eight Memory Partition
registers. Each register is an 8-bit nonvolatile register
which can be programmed with an ending address for
the partition as well as determine the behavior of that
partition. The partition protection can be set to one of
four levels:
•
•
•
•
Unprotected
Software write-protected
Hardware write-protected by the WP pin
Software write-protected with locked memory
partition register
A complete description of the Memory Partition register
function can be found in Section 10.0 “Memory Partition Functionality”.
3.2.4
IDENTIFICATION REGISTER
The Identification register is a 40-bit nonvolatile,
read-only register that contains device identification
data in compliance with the JEDEC® standard for
“Manufacturer and Device ID Read Methodology for
SPI Compatible Serial Interface Memory Devices”. The
contents and format of the Identification register can be
reviewed in Section 11.1 “Reading the Identification
Register”.
The user-programmable (lockable ID page) section of
the Security register is ideal for applications that need
to irreversibly protect critical or sensitive application
data from ever being altered. See Section 9.0
“Security Register” for more details about the
Security register.
FIGURE 3-1:
MEMORY ORGANIZATION
Memory Address Range
Protection Features
Legacy Write Protection
4-Mbit
EEPROM
4-Mbit Address Range:
000000h–07FFFFh
• Block Protection (BP bits in STATUS register)
• Hardware Write Protection
(WP pin via STATUS register)
Enhanced Write Protection
• User-Definable Memory Partitioning (WP Pin or
Software Write Protection)
4-Kbit
Security
Register
128-bit Serial Number
Address Range
(000000h–00000Fh)
Reserved for Future Use (FFh)
Address Range
(000010h–0000FFh)
User-Programmable Lockable ID Page
Address Range (000100h–0001FFh)
2019-2020 Microchip Technology Inc.
Read-Only
Permanently Lockable by
Software
DS20005817C-page 11
25CSM04
4.0
FUNCTIONAL DESCRIPTION
4.1
Device Operation
The SPI protocol defines a total of four modes of
operation (Mode 0, 1, 2, or 3) with each mode differing
in respect to the SCK polarity and phase and how the
polarity and phase control the flow of data on the SPI
bus. The 25CSM04 supports the two most common
modes, SPI Mode 0 and 3. With SPI Modes 0 and 3,
data is always latched in on the rising edge of SCK and
always output on the falling edge of SCK. The only
difference between SPI Modes 0 and 3 is the polarity of
the SCK signal when in the inactive state (when the SPI
master is in Standby mode and not transferring any
data). SPI Mode 0 is defined as a low SCK while CS is
not asserted (high) and SPI Mode 3 has SCK high in
the inactive state. The SCK Idle state must match when
the CS is deasserted both before and after the
communication sequence in SPI Mode 0 and 3.
The 25CSM04 is controlled by a set of instructions that
are sent from a host controller, commonly referred to as
the SPI master. The SPI master communicates with the
25CSM04 via the SPI bus which is comprised of four
signal lines:
•
•
•
•
Chip Select (CS)
Serial Clock (SCK)
Serial Input (SI)
Serial Output (SO)
The figures in this document depict Mode 0 with a solid
line on SCK while CS is inactive and Mode 3 with a
dotted line.
FIGURE 4-1:
SPI MODE 0 AND MODE 3
CS
SCK
SI
Mode 3
Mode 3
Mode 0
Mode 0
MSB
SO
4.2
MSB
Interfacing the 25CSM04 on the
SPI Bus
Communication to and from the 25CSM04 must be
initiated by the SPI master device. The SPI master
device must generate the serial clock for the 25CSM04
on the SCK pin. The 25CSM04 always operates as a
slave due to the fact that the Serial Clock pin (SCK) is
always an input.
4.2.1
LSB
SELECTING THE DEVICE
The 25CSM04 is selected when the CS pin is low.
When the device is not selected, data will not be
accepted via the SI pin and the SO pin will remain in a
high-impedance state.
2019-2020 Microchip Technology Inc.
4.2.2
LSB
SENDING DATA TO THE DEVICE
The 25CSM04 uses the Serial Data Input (SI) pin to
receive information. All instructions, addresses, and
data input bytes are clocked into the device with the
Most Significant bit (MSb) first. The SI pin begins
sampling on the first rising edge of the SCK line after
the CS has been asserted.
4.2.3
RECEIVING DATA FROM THE
DEVICE
Data output from the device is transmitted on the Serial
Data Output (SO) pin with the MSb output first. The SO
data is latched on the falling edge of the first SCK clock
cycle after the instruction and address bytes, if necessary, have been clocked into the device.
DS20005817C-page 12
25CSM04
4.3
Device Opcodes
4.3.1
SERIAL OPCODE
After the device is selected by driving CS low, the first
byte sent must be the opcode that defines the
sequence to be performed.
The 25CSM04 utilizes an 8-bit instruction register. The
list of instructions and their operation opcodes are
contained in Table 4-1. All instructions, addresses, and
data are transferred with the MSb first and are initiated
with a high-to-low CS transition.
TABLE 4-1:
INSTRUCTION SET FOR 25CSM04
Instruction
Instruction Description
Opcode
Address Data
Bytes
Bytes
Reference
Section
STATUS Register Instructions
Read STATUS Register
05h
WRBP
Write Ready/Busy Poll
08h
WREN
Set Write Enable Latch (WEL)
06h
WRDI
Reset Write Enable Latch (WEL)
04h
WRSR
Write STATUS Register
01h
READ
Read from EEPROM Array
03h
Write to EEPROM Array (1 to 256 bytes)
02h
RDEX
LOCK
RDSR
WRITE
Read from the Security Register
83h
Write to the Security Register
82h
Lock the Security Register (permanent)
82h
CHLK
Check Lock Status of Security Register
83h
RMPR
Read Contents of Memory Partition Registers
31h
Set Memory Partition Write Enable Latch
07h
0Ah
WMPR
Write Memory Partition Registers
32h
Protect Partition Address Boundaries
34h
FRZR
Freeze Memory Protection Configuration (permanent)
37h
PPAB
6.2
1
6.1.4.1
0000 0110
0
0
5.1
0000 0100
0
0
5.2
0000 0001
0
1 or 2
6.3
0000 0011
3
1+
7.1
0000 0010
3
1+
8.0
1000 0011
3
1+
9.1
1000 0010
3
1+
9.2
1000 0010
3
1
9.2.1
1000 0011
3
1
9.2.2
0011 0001
3
1
10.3
0
0
10.2.1
0000 1010
0
0
10.2.2
0011 0010
3
1
10.2.3
3
1
10.1.3
0011 0111
3
1
4.5.4
1001 1111
0
5
11.1
0111 1100
0
0
1.1.2
Memory Partition Register Instructions
Reset Memory Partition Write Enable Latch
PRWE
1 or 2
0
EEPROM and Security Register Instructions
WREX
PRWD
0
0000 1000
0000 0101
0000 0111
0011 0100
Identification Register Instructions
SPID
Read the SPI Manufacturer ID Data
SRST
Software Device Reset
9Fh
Device Reset Instruction
2019-2020 Microchip Technology Inc.
7Ch
DS20005817C-page 13
25CSM04
4.4
Hold Function
The HOLD pin is used to pause the serial
communication with the device without having to stop
or reset the clock sequence. The Hold mode, however,
does not have an effect on the internal write cycle.
Therefore, if a write cycle is in progress, asserting the
HOLD pin will not pause the sequence and the write
cycle will continue until it is finished.
The Hold mode can only be entered while the CS pin is
asserted. The Hold mode is activated by asserting the
HOLD pin during the SCK low pulse. If the HOLD pin is
asserted during the SCK high pulse, then the Hold
mode will not be started until the beginning of the next
SCK low pulse. The device will remain in the Hold
mode as long as the HOLD pin and CS pin are
asserted.
FIGURE 4-2:
While in Hold mode, the SO pin will be in a high-impedance state. In addition, both the SI pin and the SCK pin
will be ignored. The WP pin, however, can still be
asserted or deasserted while in the Hold mode.
To end the Hold mode and resume serial communication, the HOLD pin must be deasserted during the SCK
low pulse. If the HOLD pin is deasserted during the
SCK high pulse, then the Hold mode will not end until
the beginning of the next SCK low pulse.
If the CS pin is deasserted while the HOLD pin is still
asserted, then any sequence that may have been
started will be aborted.
HOLD MODE
CS
SCK
Hold
Hold
Hold
HOLD
4.5
Write Protection
The 25CSM04 write protection schemes are first
controlled by the state of Write Protection Mode (WPM)
bit in the STATUS register (bit 7, byte 1). The device
can be set for either Legacy Write Protection mode or
Enhanced Write Protection mode by the state of the
WPM bit.
The write protection mode can be made permanent by
executing the FRZR instruction. This can be done in
both Legacy Write Protection mode and Enhanced
Write Protection mode. Refer to Section 4.5.4 “Freeze
Memory Protection Configuration (FRZR)” for
details.
4.5.1
LEGACY WRITE PROTECTION
MODE
In Legacy Write Protection mode, the EEPROM array
can only be programmed in accordance with how the
Block Protect bits in the STATUS register are
programmed. Refer to Section 6.1.5 “Write
Protection Mode Bit” for details.
2019-2020 Microchip Technology Inc.
Additionally, the contents of the STATUS register can
be protected by enabling the Write-Protect Enable
(WPEN) bit in the STATUS register.
When the WPEN function is enabled, the STATUS register contents will be protected when the WP pin is
asserted (low). Details about the WPEN function are
provided in Section 6.1.1 “Write-Protect Enable Bit”.
4.5.2
ENHANCED WRITE PROTECTION
MODE
In Enhanced Write Protection mode, the EEPROM
protection is determined by the contents of the Memory
Partition Registers (MPR). Each MPR can be
programmed to specify the ending address of a given
partition as well as to set the desired protection
behavior of that partition.
Full details about the Memory Partition registers can be
found in Section 10.0 “Memory Partition Functionality”.
Note:
If Enhanced Write Protection mode is
disabled, the MPRs will be ignored
regardless of their configured behavior.
DS20005817C-page 14
25CSM04
4.5.3
WRITE-PROTECT PIN FUNCTION
Before a FRZR instruction can be issued, first a WREN
instruction must be issued to set the WEL bit in the
STATUS register to a logic ‘1’, followed by a PRWE
instruction to set the PREL bit to a logic ‘1’ as well.
Once these two steps are complete, the FRZR instruction can be sent to the device.
While in both Legacy Write Protection mode and
Enhanced Write Protection mode, writing to the
STATUS register and the Memory Partition registers
can be inhibited by enabling the WPEN bit in the
STATUS register. When the WPEN function is enabled,
the contents of these registers will be protected when
the WP pin is asserted (low). In order for these
registers to be protected, the WP pin must be asserted
for the entire CS valid time. Details about the WPEN
function are provided in Section 6.1.2 “Block
Write-Protect Bits”.
Note:
To freeze the state of the Memory Protection Configuration with the FRZR instruction, the CS pin must be
driven low, followed by sending an opcode of 37h to the
device on the SI line. Next, an address of AA40h is
sent, followed by a confirmation data byte of D2h. Upon
deasserting the CS pin, the device will begin a
self-timed internal write cycle to set the FMPC bit,
freeze all eight Memory Partition registers, and the
Write Protection Mode (WPM) bit in the STATUS register.
If the internal write cycle has already been initiated, WP
pin going low will have no effect on any write sequence.
The WP pin function is blocked when the WPEN bit in
the STATUS register is a logic ‘0’. This will allow the
user to install the 25CSM04 device in a system with the
WP pin tied to VSS and still be able to write to the
STATUS register. All WP pin functions are enabled
when the WPEN bit is set to a logic ‘1’.
4.5.4
FREEZE MEMORY PROTECTION
CONFIGURATION (FRZR)
Once the write cycle is completed, the PREL bit and
WEL bit in the STATUS register will be reset back to the
logic ‘0’ state, the WPM STATUS register bit (bit 7, byte
1) will be permanently set to its current state, and the
FMPC STATUS register bit (bit 5, byte 1) will be permanently set to a logic ‘1’ to indicate that the Memory Protection Configuration has been frozen. If the registers
and WPM bit have already been frozen, any attempt to
issue the FRZR instruction will be ignored. The device
will return to the Idle state once the CS pin has been
deasserted.
The current state of the Memory Partition registers and
write protection mode can be permanently frozen so
that no further modification of their contents is possible.
This is accomplished by the use of the Freeze Memory
Protection Configuration (FRZR) instruction. For additional information on the Memory Partition registers,
refer to Section 10.0 “Memory Partition Functionality”.
Note:
The Write-Protect Enable (WPEN) and
Block Protection (BP[1:0]) bits are not
affected by the FRZR instruction.
FIGURE 4-3:
The FRZR instruction will be ignored if the
WPEN Bit (byte 0, bit 7) of the STATUS
register is set to a logic ‘1’ and the WP pin
is asserted.
Note:
If the CS pin is deasserted before the end
of the 40-bit sequence, the instruction will
be aborted and no write cycle will take
place.
FREEZE MEMORY PROTECTION CONFIGURATION (FRZR) SEQUENCE
CS
TWC(1)
0
1
2
3
4
5
6
7
8
29 30 31 32 33 34 35 36 37 38 39
9 10 11 12
SCK
Address Bits A23-A0(2)
FRZR Opcode (37h)
SI
0
0 1
MSB
1
0 1
X X
MSB
X
X X
X
0 0 0 0
1 1 0
MSB
1 0 0
1 0
High-Impedance
SO
Note
1 1
Data In (D2h)
1:
This sequence initiates a self-timed internal write cycle on the rising edge of CS after a valid sequence.
2:
Address bits A23-A16 are ignored. Address bits A15-A0 must be set to AA40h.
2019-2020 Microchip Technology Inc.
DS20005817C-page 15
25CSM04
5.0
WRITE ENABLE AND DISABLE
The WEL bit will be reset to a logic ‘0’ in the following
circumstances:
5.1
Write Enable Instruction (WREN)
• Upon power-up as the power-on default condition
is the Write Disable state (Section 1.2.2 “Device
Factory Default Condition”)
• The successful completion of any write sequence
(WRITE, WRSR, WREX, LOCK, WMPR, PPAB, FRZR)
• Executing a Write Disable (WRDI) instruction
(Section 5.2
“Write
Disable
Instruction
(WRDI)”)
• Executing a Software Device Reset (SRST)
instruction
The Write Enable Latch (WEL) bit of the STATUS
register must be set to a logic ‘1’ prior to each WRSR,
WRITE, WREX, LOCK, PPWE, WMPR, PPAB, and FRZR
instructions. Some of these sequences need further
instructions prior to being executed and are noted in
their corresponding section. The WEL bit is set to a
logic ‘1’ by sending a WREN (06h) instruction to the
25CSM04. First, the CS pin is driven low to select the
device and then a 06h instruction is clocked in on the
SI pin. Then the CS pin is driven high. The WEL bit will
be immediately updated in the STATUS register to a
logic ‘1’.
FIGURE 5-1:
WRITE ENABLE (WREN) INSTRUCTION
CS
0
1
2
3
4
5
6
7
SCK
WREN Opcode (06h)
0
SI
0
0
0
0
1
1
0
MSB
High-Impedance
SO
5.2
Write Disable Instruction (WRDI)
To protect the device against inadvertent write
sequences, the Write Disable (04h) instruction disables
all programming modes by setting the WEL bit to a
logic ‘0’. The WRDI instruction is independent of the
WP pin state.
FIGURE 5-2:
WRITE DISABLE (WRDI) INSTRUCTION
CS
0
1
2
3
4
5
6
7
SCK
WRDI Opcode (04h)
SI
SO
2019-2020 Microchip Technology Inc.
0
0
0
0
0
1
0
0
MSB
High-Impedance
DS20005817C-page 16
25CSM04
6.0
STATUS REGISTER
6.1
Status Register Bit Definition
The 25CSM04 includes a 2-byte STATUS register
which is a combination of six nonvolatile bits of
EEPROM and five volatile latches. The STATUS
register bits modulate various features of the device as
shown in Register 6-1 and Register 6-2. These bits can
be read or modified by specific instructions that are
detailed in the subsequent sections.
REGISTER 6-1:
STATUS REGISTER (BYTE 0)
R/W
U-0
U-0
U-0
R/W
R/W
R-0
R-0
WPEN
—
—
—
BP1
BP0
WEL
RDY/BSY
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
WPEN: Write-Protect Enable bit
1 = Write-Protect pin is enabled
0 = Write-Protect pin is ignored
bit 6-4
Unimplemented: Read as ‘0’
bit 3-2
BP[1:0]: Block Protection bits (see Table 6-2)
00 = No array write protection
01 = Upper quarter memory array protection
10 = Upper half memory array protection
11 = Entire memory array protection
bit 1
bit 0
x = Bit is unknown
WEL: Write Enable Latch bit
1 = WREN has been executed and device is enabled for writing
0 = Device is not write-enabled
RDY/BSY: Ready/Busy Status Latch bit
1 = Device is busy with an internal write cycle
0 = Device is ready for a new sequence
2019-2020 Microchip Technology Inc.
DS20005817C-page 17
25CSM04
REGISTER 6-2:
STATUS REGISTER (BYTE 1)
R/W-1
R-0
R
R-0
R
U-0
U-0
R-0
WPM
ECS
FMPC
PREL
PABP
—
—
RDY/BSY
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2-1
bit 0
Note 1:
2:
6.1.1
x = Bit is unknown
WPM: Write Protection Mode bit(1)
1 = Enhanced Write Protection mode selected
0 = Legacy Write Protection mode selected
ECS: Error Correction State Latch bit
1 = The previously executed read sequence did require the Error Correction Code (ECC)
0 = The previous executed read sequence did not require the Error Correction Code (ECC)
FMPC: Freeze Memory Protection Configuration bit(2)
1 = Memory Partition registers and write protection mode are permanently frozen and cannot be
modified
0 = Memory Partition registers and write protection mode are not frozen and are modifiable
PREL: Partition Register Write Enable Latch bit
1 = PRWE has been executed and WMPR, FRZR and PPAB instructions are enabled
0 = WMPR, FRZR and PPAB instructions are disabled
PABP: Partition Address Boundary Protection bit
1 = Partition Address Endpoints set in Memory Partition registers cannot be modified
0 = Partition Address Endpoints set in Memory Partition registers are modifiable
Unimplemented: Read as ‘0’
RDY/BSY: Ready/Busy Status Latch bit
1 = Device is busy with an internal write cycle
0 = Device is ready for a new sequence
If the FMPC bit is set to a logic ‘1’, the WPM bit is read-only.
Once the FMPC bit has been set, it cannot be cleared.
WRITE-PROTECT ENABLE BIT
The Write-Protect Enable (WPEN) bit in the STATUS
register (byte 0, bit 7) can be used in conjunction with
the WP pin to inhibit writing to the various registers
within the device.
The device is hardware write-protected when both the
WP pin is low and the WPEN bit has been set to a
logic ‘1’. The affected registers depend on the write
protection mode selected.
The write protection mode is determined by the WPM
bit in the STATUS register (bit 7, byte 1). Hardware
write protection is disabled when either the WP pin is
deasserted (high) or the WPEN bit is a logic ‘0’.
Table 6-1 describes which registers will be protected
from being modified. The WP pin must be asserted
(low) to enable any protection capabilities.
2019-2020 Microchip Technology Inc.
DS20005817C-page 18
25CSM04
TABLE 6-1:
REGISTER BEHAVIOR IN LEGACY WRITE PROTECTION AND ENHANCED WRITE
PROTECTION MODES
Write Protection
Mode
WPEN Bit
STATUS Register
Memory Partition
Registers
0
Not Protected
Not Protected
Protected
Protected
X
Not Protected
Not Protected
Low
Legacy or
Enhanced
Note:
WP Pin
Low
1
High
When the WPEN bit is a logic ‘1’, it cannot be changed back to a logic ‘0’, as long as the WP pin is asserted
(low).
When the device is hardware write-protected, the
nonvolatile bits of the STATUS register (WPEN, BP1,
BP0, WPM, FMPC, PABP) become read-only and the
Write STATUS Register (WRSR), Freeze Memory
Protection Configuration (FRZR), and Protect Partition
Address Boundaries (PPAB), Write Memory Partition
Registers (WMPR), and Lock the Security Register
(LOCK) instructions will not be accepted.
6.1.2
BLOCK WRITE-PROTECT BITS
The 25CSM04 contains four levels of EEPROM write
protection using the Block Protection function. The
nonvolatile Block Write-Protect bits (BP1, BP0) are
located in bits three and two of the first STATUS
register byte and define the region of the EEPROM and
Security register that are to be treated as read-only.
These values are only valid if the device has been set
to Legacy Write Protection mode via the WPM STATUS
register bit (byte 1, bit 7).
TABLE 6-2:
Level
0
1
2
3
Note:
The four levels of array protection are:
• Level 0 – No portion of the EEPROM is protected,
while the lower 256 bytes of the Security register
are read-only.
• Level 1 – The upper quarter address range is
write-protected meaning the highest order 1 Mbits
in the EEPROM are read-only. The lower
256 bytes of the Security register are read-only.
• Level 2 – The upper half address range is
write-protected meaning the highest order 2 Mbits
in the EEPROM are read-only. The lower
256 bytes of the Security register are read-only.
• Level 3 – Both the EEPROM and Security
register are write-protected meaning all
addresses are read-only.
The address ranges that are protected for each Block
Write Protection level and corresponding STATUS
register control bits are shown in Table 6-2.
BLOCK WRITE-PROTECT BITS
STATUS Register Byte 0
Bits [3:2]
BP1
BP0
0
0
0
1
1
0
1
1
Protected Address Range
Memory Region
25CSM04
EEPROM
None
Security Register
00000h-000FFh
EEPROM
60000h-7FFFFh
Security Register
00000h-000FFh
EEPROM
40000h-7FFFFh
Security Register
00000h-000FFh
EEPROM
00000h-7FFFFh
Security Register
00000h-001FFh
The Block Protection mechanism will only function with the WPM bit of the STATUS register (bit 7, byte 1)
set to a logic ‘0’, indicating Legacy Write Protection mode. If the WPM is set to logic ‘1’, the device will
respond in accordance with the Enhanced Write Protection mode. For more details on the Enhanced Write
Protection mode, refer to Section 10.1 “Enhanced Write Protection Mode”.
2019-2020 Microchip Technology Inc.
DS20005817C-page 19
25CSM04
6.1.3
WRITE ENABLE LATCH
A logic ‘0’ bit in this position indicates the device is
ready to accept new instructions.
Enabling and disabling writing to any nonvolatile register, the EEPROM array, and the Security register is
accomplished through the Write Enable instruction
(WREN) as shown in Section 5.1 “Write Enable
Instruction (WREN)” and the Write Disable instruction
(WRDI) as shown in Section 5.2 “Write Disable
Instruction (WRDI)”. These functions change the
state of the Write Enable Latch (WEL) bit (byte 0, bit 1)
in the STATUS register.
6.1.4
6.1.4.1
The Write Ready/Busy Poll (WRBP) instruction provides
direct access to the Ready/Busy STATUS register bit in
an 8-bit format. The WRBP instruction can be used after
any nonvolatile write sequence as a means to check if
the device has completed its internal write cycle.
This instruction will return an FFh value when the
device is still busy completing the write cycle or a 00h
value if the device is no longer in a write cycle.
READY/BUSY STATUS LATCH
The Ready/Busy Status Latch (RDY/BSY) is used to
indicate whether the device is currently active in a nonvolatile write sequence. This bit is read-only and automatically updated by the device. This bit is provided in
bit 0 of both STATUS register bytes.
Refer to Section 8.3 “Polling Routine” for a
description on implementing a polling routine.
Continuous reading of the WRBP state is supported
and the value output by the device will be updated
every eight bits.
A logic ‘1’ bit indicates that the device is currently busy
performing a nonvolatile write sequence. During this
time, only the Read STATUS Register (RDSR) and the
Write Ready/Busy Poll (WRBP) instructions will be executed by the device.
FIGURE 6-1:
Write Ready/Busy Poll
WRITE READY/BUSY POLL (WRBP) SEQUENCE
CS
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
D1
D0
SCK
WRBP Opcode (08h)
SI
0
0
0
0
1
0
0
0
MSB
SO
High-Impedance
FFh or 00h Data Out
D7
D6
D5
D4
D3
D2
MSB
6.1.5
WRITE PROTECTION MODE BIT
The 25CSM04 write protection behavior is controlled
by the nonvolatile Write Protection Mode (WPM) bit in
the STATUS register. This bit is located in bit 7, byte 1
of the STATUS register. A logic ‘0’ indicates the device
is in Legacy Write Protection mode whereas a logic ‘1’
indicates the device is in Enhanced Write Protection
mode.
The write protection modes control how the contents of
the EEPROM and Security register as well as the
various nonvolatile registers in the device can be
inhibited from writing. An overview of the two protection
modes can be found in Section 4.5 “Write
Protection”. Details on which nonvolatile registers are
protected, in conjunction with the WP pin, can be found
in Section 6.1.1 “Write-Protect Enable Bit”.
2019-2020 Microchip Technology Inc.
The WPM bit in the STATUS register can only be
modified using the WRSR instruction as described in
Section 6.3 “Write STATUS Register (WRSR)”.
Write protection mode can be made permanent by
executing the FRZR instruction. This can be done in
both Legacy Write Protection mode and Enhanced
Write Protection mode. Refer to Section 4.5.4 “Freeze
Memory Protection Configuration (FRZR)” for
additional information.
DS20005817C-page 20
25CSM04
6.1.6
ERROR CORRECTION STATE
LATCH
6.1.8
The Error Correction State (ECS) bit is located in byte
1, bit 6 of the STATUS register. This bit indicates
whether the on-chip Error Correction Code (ECC) logic
scheme was invoked during the previous read
sequence. For more information related to ECC, refer
to Section 8.2 “Error Correction Code (ECC)
Architecture”.
The ECS bit will be set to logic ‘0’ unless the previously
executed read sequence required the use of the ECC
logic scheme. When this occurs the ECS bit will set to
logic ‘1’.
The ECS bit will continue to read a logic ‘1’ until another
read sequence occurs where the use of the ECC logic
scheme was not required, a Power-on Reset (POR)
event occurs, or a Software Device Reset (SRST)
instruction is sent to the 25CSM04.
6.1.7
FREEZE MEMORY PROTECTION
CONFIGURATION BIT
The Freeze Memory Protection Configuration (FMPC)
bit resides in byte 1, bit 5 of the STATUS register. This
bit is nonvolatile and One-Time-Programmable (OTP)
with a factory default value of a logic ‘0’.
This bit can only be set to a logic ‘1’ as a result of the
Freeze Memory Protection Configuration (FRZR)
instruction
(Section 4.5.4
“Freeze
Memory
Protection Configuration (FRZR)”). This bit cannot
be modified with a Write STATUS Register (WRSR)
instruction. Once this bit has been permanently set to a
logic ‘1’, the memory configuration cannot be changed.
FIGURE 6-2:
PARTITION ADDRESS BOUNDARY
PROTECTION BIT
The Partition Address Boundary Protection (PABP) bit
is located in byte 1, bit 3 of the STATUS register. This
bit can be read through an RDSR instruction but can
only be set or cleared through a Protect Partition
Address Boundary sequence (see Section 10.1.3
“Protecting the Partition Endpoint Addresses”).
When programmed to a Logic ‘1’, the address range
bits in the Memory Partition registers are read-only and
cannot be modified but the behavior bits can still be
modified.
If the Freeze Memory Protection Configuration bit has
been programmed to a logic ‘1’, the address range and
behavior bits are permanently read-only and cannot be
modified regardless of the state of the PABP bit.
6.2
Read STATUS Register (RDSR)
The Read STATUS Register (RDSR) instruction
provides access to the contents of the STATUS
register. The STATUS register is read by asserting the
CS pin followed by sending in a 05h opcode. The
device will return the 16-bit STATUS register value on
the SO pin.
The STATUS register can be continuously read for data
by continuing to read beyond the first 16-bit value
returned. The 25CSM04 will update the value of the
volatile bits (RDY/BSY, WEL, and PREL) in the
STATUS register at byte boundaries, thereby allowing
new STATUS register volatile bit values to be read
without having to issue a new RDSR instruction.
A new RDSR instruction needs to be initiated in order for
the nonvolatile bits (WPEN, BP0, BP1 and WPM) in the
STATUS register to be updated.
READ STATUS REGISTER (RDSR) SEQUENCE
CS
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
SCK
RDSR Opcode (05h)
SI
SO
0
0
0
0
0
1
High-Impedance
2019-2020 Microchip Technology Inc.
0
1
STATUS Register Byte 0
STATUS Register Byte 1
D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
DS20005817C-page 21
25CSM04
6.3
Write STATUS Register (WRSR)
The Write STATUS Register (WRSR) instruction enables
the SPI master to change selected bits of the STATUS
register. Before a WRSR sequence can be initiated, a
WREN instruction must be executed to set the WEL bit
to logic ‘1’. Upon completion of a WREN instruction, a
WRSR sequence can be executed.
The WRSR instruction will only modify:
• Byte 0: bit 7, bit 3, and bit 2
• Byte 1: bit 7
These modifiable bits are the Write-Protect Enable
(WPEN) bit, the Block Protect (BP1, BP0) bits, and the
Write Protection Mode (WPM) bit.
When writing to the STATUS register, byte 0 must
always be written. Byte 1 can optionally be written to
utilize Enhanced Write Protection mode.
Note:
If the CS pin is deasserted at somewhere
other than the end of an 8-bit byte boundary, the sequence will be aborted and no
write cycle will take place.
The 25CSM04 will not respond to instructions other
than a RDSR or a WRBP after a WRSR sequence until
the self-timed internal write cycle has completed. When
the write cycle has completed, the WEL bit in the
STATUS register is reset to a logic ‘0’.
These four bits are nonvolatile cells that have the same
properties and functions as regular EEPROM cells.
Their values are retained while power is removed from
the device. While FMPC (byte 1, bit 5) and PABP
(byte 1, bit 3) of the STATUS register are also
nonvolatile bits, they are modified through dedicated
instructions. Refer to Section 6.1.7 “Freeze Memory
Protection Configuration Bit” and Section 10.1.3
“Protecting the Partition Endpoint Addresses” for
more details about these requirements.
FIGURE 6-3:
WRITE STATUS REGISTER (WRSR) SEQUENCE
CS
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
TWC(1)
SCK
SI
SO
WRSR Opcode
STATUS Register Byte
STATUS Register Byte
0 0 0 0 0 0 0 1 D7 X X X D3 D2 X X D7 X X X X X X X
MSB
MSB
MSB
Optional
High-Impedance
Note 1: This sequence initiates a self-timed internal write cycle on the rising
edge of CS after a valid sequence.
2019-2020 Microchip Technology Inc.
DS20005817C-page 22
25CSM04
7.0
READ SEQUENCES
7.1
Reading from the EEPROM
Reading the EEPROM contents can be done whenever
the device is not in an internal write cycle, as indicated
by the Ready/Busy bit of the STATUS register. To read
the EEPROM, first the CS line is pulled low to select the
device and the READ (03h) instruction is transmitted via
the SI line followed by the 24-bit address to be read.
Address bits A23 through A19 are “don’t care” bits
because they do not fall within the addressable
memory range.
FIGURE 7-1:
Upon completion of the 24-bit address, any data on the
SI line will be ignored. The data (D7–D0) at the
specified address is then shifted out onto the SO line. If
only one byte is to be read, the CS line should be driven
high after the data is clocked out.
The read sequence can be continued since the byte
address is automatically incremented and data will
continue to be shifted out. When the highest address is
reached, the address counter will “rollover” to the
lowest address (000000h) allowing the entire memory
to be read in one continuous read cycle regardless of
the starting address.
The read sequence can be terminated at any point of
the sequence (drive CS high).
READ EEPROM (READ) SEQUENCE
CS
0
1
2
3
4
5
6
7
8
9 10 11 12
29 30 31 32 33 34 35 36 37 38 39 40 41
SCK
READ Opcode (03h)
SI
0 0 0 0 0 0
MSB
SO
High-Impedance
Address Bits A23-A0
1 1 X X X X X A
A A A
MSB
Data Byte 1
D7 D6 D5 D4 D3 D2 D1 D0 D7 D6
MSB
2019-2020 Microchip Technology Inc.
MSB
DS20005817C-page 23
25CSM04
8.0
WRITE SEQUENCES
Address bits A23 through A19 are “don’t care” bits
because they do not fall within the addressable
memory range.
In order to program the EEPROM in the 25CSM04, the
device must be write-enabled via the Write Enable
instruction (WREN). If the device is not write-enabled,
the device will ignore the WRITE instruction and will
return to the Standby state when CS is brought high.
The address of the memory location(s) to be
programmed must be outside the protected address
range(s) selected by the Block Write Protection level or
the contents of the various Memory Partition registers.
During an internal write cycle, all instructions will be
ignored except the RDSR and the WRBP instructions.
8.1
Programming will start after the CS pin is brought high.
The low-to-high transition of the CS pin must occur
during the SCK low time (mode 0) and SCK high time
(mode 3) immediately after clocking in the D0 (LSB)
data bit.
Note:
Write Instruction Sequences
8.1.1
The 25CSM04 is automatically returned to the Write
Disable state (STATUS register bit WEL = 0) at the
completion of a write cycle.
BYTE WRITE
Once a WREN instruction has been completed, a byte
write sequence can be performed as shown in
Figure 8-1. After the CS line is pulled low to select the
device, the WRITE (02h) instruction is transmitted via
the SI line followed by the 24-bit address and the data
(D7-D0) to be programmed.
FIGURE 8-1:
If the CS pin is deasserted at somewhere
other than the end of an 8-bit byte
boundary, the sequence will be aborted
and no write cycle will take place.
BYTE WRITE SEQUENCE
CS
TWC(1)
0
1
2
3
4
5
6
7
8
9 10 11 12
29 30 31 32 33 34 35 36 37 38 39
SCK
WRITE Opcode (02h)
SI
0
0 0
MSB
0
0 0
1 0
X X X X X
8.1.2
A
A A A A D7 D6 D5 D4 D3 D2 D1 D0
MSB
MSB
High-Impedance
SO
Note
Data In
Address Bits A23-A0
1:
This sequence initiates a self-timed internal write cycle on the rising edge of CS after a valid sequence.
PAGE WRITE
A page write sequence is the same as a byte write,
however allowing up to 256 bytes to be written in the
same write cycle, provided that all bytes are in the
same page of the memory array (where addresses A18
through A8 are the same). Partial page writes of less
than 256 bytes are allowed. After each byte of data is
received, the eight lowest order address bits are
internally incremented by one and the remaining
address bits will remain constant.
Upon completion of a write cycle, the 25CSM04
automatically returns to the Write Disable state
(STATUS register bit WEL = 0).
Note:
If the CS pin is deasserted at somewhere
other than the end of an 8-bit byte
boundary, the sequence will be aborted
and no write cycle will take place.
If more bytes of data are transmitted than what will fit to
the end of that memory page, the address counter will
“rollover” to the beginning of the same page and only
the last 256 bytes of data received will be written to the
device.
2019-2020 Microchip Technology Inc.
DS20005817C-page 24
25CSM04
FIGURE 8-2:
PAGE WRITE SEQUENCE
CS
TWC(1)
0
1
2
3
4
5
6
7
8
9
29 30 31 32 33 34 35 36 37 38 39
SCK
WRITE Opcode (02h)
SI
0 0
0
0
0 0
Address Bits A23-A0
1 0 X X
MSB
X
A
A
MSB
8.2
1:
A D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
MSB
MSB
This sequence initiates a self-timed internal write cycle on the rising edge of CS after a valid sequence.
Error Correction Code (ECC)
Architecture
The 25CSM04 incorporates a built-in Error Correction
Code (ECC) logic scheme. The EEPROM array is
internally organized as a group of four connected bytes
plus an additional six ECC parity bits of EEPROM.
These 38 bits are referred to as the internal physical
data word. During a read sequence, the ECC logic
compares each 4-byte physical data word with its
corresponding six ECC parity bits. If a single bit out of
the 4-byte region happens to read incorrectly, the ECC
logic will detect the bad bit and replace it with a correct
value before the data is serially clocked out. This
architecture significantly improves the reliability of the
25CSM04 versus a device that does not utilize ECC.
It is important to note that data is always physically
written to the part at the internal physical data word
level, regardless of the number of bytes written. Writing
single bytes is still possible with the byte write
sequence, but internally, the other three bytes within
the 4-byte location where the single byte was written,
along with the six ECC parity bits will be updated. Due
to this architecture, the 25CSM04 EEPROM write
endurance is rated at the internal physical data word
level (4-byte word). The system designer needs to
optimize the application writing algorithms to observe
these internal word boundaries in order to maximize
the endurance.
8.3
Data In Byte n (256 max.)
High-Impedance
SO
Note
Data In Byte 1
Polling Routine
A polling routine can be implemented to optimize time
sensitive applications that would not prefer to wait the
fixed maximum write cycle time (TWC). This method
allows the application to query whether the Serial
EEPROM has completed the write sequence. This
polling routine should be initiated once the internally
timed write sequence has begun.
2019-2020 Microchip Technology Inc.
The polling routine is repeatedly sending Read
STATUS Register (RDSR) or Write Ready/Busy Poll
(WRBP) instructions to determine if the device has
completed its self-timed internal write cycle (see
Figure 8-3). If the RDY/BSY bit = 1 from RDSR or FFh
from WRBP the write cycle is still in progress.
If RDY/BSY bit = 0 from RDSR or 00h from WRBP this
indicates the write cycle has ended. If the device is still
in a busy state, repeated RDSR or WRBP instructions
can be executed until the RDY/BSY bit = 0 or the WRBP
instruction returns a 00h, signaling that the device is
ready to execute a new instruction. Only the RDSR and
WRBP instructions are enabled during the write cycle.
FIGURE 8-3:
POLLING FLOW
Send Valid Write
Instruction
Deassert CS High to
Initiate a Write Cycle
Send RDSR/WRBP
Instruction to the Device
Is WRBP = 00h or is
RDY/BSY = 0?
NO
YES
Next Sequence
DS20005817C-page 25
25CSM04
9.0
SECURITY REGISTER
The Security register is segmented into one 256-byte
read-only page and one 256-byte user-programmable
lockable ID page. The user-programmable lockable ID
page supports both byte write and page write
sequences. The user-programmable lockable ID page
may be permanently locked at any time with the LOCK
instruction. The Security register lock state can be
verified at any time with CHLK instruction.
TABLE 9-1:
SECURITY REGISTER ORGANIZATION
Security Register Byte Number
0
1
...
254
255
256
Factory-Programmed (Read-only)
0-15: Device Serial Number
16-255: Reserved for Future Use
9.1
Reading the Security register contents from 25CSM04
follows a similar sequence to reading the EEPROM but
a different opcode and specific address data is
required. To read the Security register, first drive the CS
low to select the device, then send the RDEX (83h)
instruction via the SI line followed by the 24-bit address
to be read.
Address bits A23 through A9 are “don’t
care” bits, except A10 which must be a
logic ‘0’.
FIGURE 9-1:
...
510
511
User-Programmable (Lockable)
Reading from the Security
Register
Note:
257
Upon completion of the 24-bit address, any data on the
SI line will be ignored. The data (D7 – D0) at the
specified address is then shifted out onto the SO line. If
only one byte is to be read, the CS line should be driven
high after the data comes out. The read sequence can
be continued since the byte address is automatically
incremented and data will continue to be shifted out.
When the highest address is reached (0001FFh), the
address counter will “rollover” to the lowest address
(000000h) allowing the entire Security register to be
read in one continuous read cycle regardless of the
starting address.
READ SECURITY REGISTER (RDEX) SEQUENCE
CS
0
1
2
3
4
5
6
7
8
9 10 11 12
29 30 31 32 33 34 35 36 37 38 39 40 41
SCK
Address Bits A23-A0(1)
RDEX Opcode (83h)
SI
1 0 0 0 0 0
MSB
SO
1 1 X X X X X X
A A A
MSB
High-Impedance
Data Byte 1
D7 D6 D5 D4 D3 D2 D1 D0 D7 D6
MSB
MSB
Note 1: Address bit A10 must be ‘0’ to read the Security register.
2019-2020 Microchip Technology Inc.
DS20005817C-page 26
25CSM04
9.1.1
READING THE
FACTORY-PROGRAMMED 128-BIT
SERIAL NUMBER
The Security register contains a factory-programmed,
globally unique, read-only 128-bit serial number. This
serial number is unique across all varieties of Microchip
CS series EEPROM and it is located in the lower 16
bytes of the Security register (bytes 0h-Fh). Reading
the serial number is accomplished in the same way as
the reading of any other data in the Security register.
Note:
9.2
To ensure a unique number, the 128-bit
serial number must be read from the
starting address. Additionally, the entire
serial number must be read to realize a
completely unique value.
Writing to the Security Register
Executing a write sequence to the Security register is
identical to the EEPROM as described in Section 8.1.1
“Byte Write” and Section 8.1.2 “Page Write” with the
exception that the WREX (82h) instruction is used and
A10 must be a logic ‘0’ and A8 must be a logic ‘1’ in
order to write the user-programmable lockable ID page.
In Legacy Write Protection mode, the Security register
is write-protected when the BP [1:0] bits (byte 0, bits
3-2) of the STATUS register = 11. There is no
dependency on the WPEN bit (byte 0, bit 7) of the
STATUS register or the WP pin.
The user-programmable lockable ID page of the
Security register can also be permanently locked such
that its contents also become read-only. This is
accomplished with LOCK instruction. Determining if the
device has previously been locked can be determined
with the CHLK instruction. If the Security register is
locked, any subsequent WREX instructions will be
ignored.
Note:
9.2.1
LOCKING THE SECURITY
REGISTER
The upper 256 bytes of the Security register are
shipped by Microchip in a user-programmable state.
Once
the
desired
data
is
written,
the
user-programmable lockable ID page of the Security
register can be permanently write-protected with the
LOCK instruction.
Note:
The LOCK instruction will be ignored if the
WPEN bit (byte 0, bit 7) of the STATUS
register is set to a logic ‘1’ and the WP pin
is asserted.
The LOCK instruction is irreversible and will
permanently prevent all future write sequences to the
upper 256 bytes of the Security register on the
25CSM04, thereby rendering the entire 512-byte
Security register read-only.
Note:
Once the Security register has been
locked, it is not possible to unlock it.
The LOCK instruction emulates a write sequence in that
a WREN instruction must first be sent to set the WEL bit
in the STATUS register to logic ‘1’. As shown in
Figure 9-4, the LOCK (82h) instruction is clocked in on
the SI line, followed by a dummy address where bits
A23 through A0 are “don’t care” bits with the exception
that bit A10 must be set to ‘1’. Finally, a confirmation
data byte of xxxxxx1xb is sent and the self-timed
internal write cycle will begin once the CS pin is driven
high.
Note:
If the CS pin is deasserted before the end
of the 40-bit sequence, the sequence will
be aborted and no write cycle will take
place.
If the CS pin is deasserted at somewhere
other than the end of an 8-bit byte boundary, the sequence will be aborted and no
write cycle will take place.
2019-2020 Microchip Technology Inc.
DS20005817C-page 27
25CSM04
FIGURE 9-2:
WRITE SECURITY REGISTER (WREX) BYTE WRITE SEQUENCE
CS
TWC(1)
0
1
2
3
4
5
6
7
29 30 31 32 33 34 35 36 37 38 39
9 10 11 12
8
SCK
Address Bits A23-A0(2)
WREX Opcode (82h)
SI
1
0 0
0
MSB
0 0
1 0
X X
X
MSB
X X
X
Data In
A A A A D7 D6 D5 D4 D3 D2 D1 D0
MSB
High-Impedance
SO
Note
1:
This sequence initiates a self-timed internal write cycle on the rising edge of CS after a valid sequence.
2:
A23 through A9 are “don't care” bits, except A10 which must be a logic ‘0’ and A8 which must be a logic ‘1’ to address the
second Security register byte that is user programmable.
FIGURE 9-3:
WRITE SECURITY REGISTER (WREX) PAGE WRITE SEQUENCE
CS
TWC(1)
0
1
2
3
4
5
6
7
8
9
29 30 31 32 33 34 35 36 37 38 39
SCK
Address Bits A23-A0(2)
WREX Opcode (82h)
SI
1 0
0
0
0 0
1 0 X X
MSB
A
X
MSB
A
Data In Byte 1
Data In Byte n (256 max.)
A D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
MSB
MSB
High-Impedance
SO
Note 1:
2:
This sequence initiates a self-timed internal write cycle on the rising edge of CS after a valid sequence.
A23 through A9 are “don't care” bits, except A10 which must be a logic ‘0’ and A8 which must be a logic ‘1’ to address
the second Security register byte that is user programmable.
FIGURE 9-4:
LOCK SECURITY REGISTER (LOCK) SEQUENCE
CS
TWC(1)
0
1
2
3
4
5
6
7
8
9 10 11 12
29 30 31 32 33 34 35 36 37 38 39
SCK
Address Bits A23-A0 (2)
LOCK Opcode (82h)
SI
1
0 0
MSB
0
0 0
X X X X X
MSB
X
X X X X
X X X
MSB
X X X
1 X
High-Impedance
SO
Note
1 0
Data In (xxxxxx1xb)
1:
This sequence initiates a self-timed internal write cycle on the rising edge of CS after a valid sequence.
2:
A23 through A0 are “don't care” bits, except A10 which must be a logic ‘1’.
2019-2020 Microchip Technology Inc.
DS20005817C-page 28
25CSM04
9.2.2
DETERMINING THE LOCK STATE
OF THE SECURITY REGISTER
To determine whether or not the user-programmable
lockable ID page of the Security register is locked, the
25CSM04 includes a CHLK instruction to check the lock
state. To determine the lock status, the opcode 83h
must be clocked into the device on the SI line. The
address bit A10 must be equal to logic ‘1’ while the
other address bits are “don’t care”. Data bit 0 of the
data byte clocked out on the SO line determines the
lock state, the other bits of the data byte are “don’t care”
bits. A data response of xxxxxxx1b indicates the
region is locked, while a xxxxxxx0b response
indicates that the region is not locked.
FIGURE 9-5:
CHECK SECURITY REGISTER LOCK (CHLK) SEQUENCE
CS
0
1
2
3
4
5
6
7
8
9 10 11 12
29 30 31 32 33 34 35 36 37 38 39 40 41
SCK
Address Bits A23-A0(1)
RDEX Opcode (83h)
SI
1 0 0 0 0 0
MSB
SO
High-Impedance
1 1 X X X X X X
A A A
MSB
Data Out
D7 D6 D5 D4 D3 D2 D1 D0
MSB
xxxxxxx1b = Locked
xxxxxxx0b = Unlocked
Note 1: A23 through A0 are “don’t care” bits, except A10 which must be a logic ‘1’.
2019-2020 Microchip Technology Inc.
DS20005817C-page 29
25CSM04
10.0
MEMORY PARTITION
FUNCTIONALITY
The write-protect functionality of the 25CSM04 can be
configured for Legacy Write Protection mode or
Enhanced Write Protection mode with the WPM bit of
the STATUS register (see Section 6.1.5 “Write
Protection Mode Bit”). Changing this bit is
accomplished with a WRSR sequence. If WPM is set to
a logic ‘0’, then the device is set for Legacy Write
Protection mode. If WPM is a logic ‘1’, Enhanced Write
Protection mode is enabled.
Note:
The write protection mode can be made
permanent by executing the FRZR instruction. This can be done in both Legacy
Write Protection mode and Enhanced
Write Protection mode. Refer to
Section 4.5.4 “Freeze Memory Protection Configuration (FRZR)” for additional information.
10.1.1
MEMORY PARTITIONING
OVERVIEW
Through the use of the device’s eight MPRs, the
EEPROM array can be divided into as many as nine
partitions. Each MPR specifies one of four types of
protection behaviors for their corresponding partitions.
The Memory Partition register contents specify the six
Most Significant bits of the memory array address (A18
through A13) corresponding to the endpoint of a given
partition where A12 through A0 are a logic ‘1’. This
creates an available partition size in 32-page (8 Kbyte)
increments meaning the partition can be set as small as
64-Kbit (213 x 8). However, each partition can be
uniquely sized to fit the application requirements.
Figure 10-1 provides a map of the available partition
points.
Note:
If Enhanced Write Protection mode is
disabled, the MPRs will be ignored
regardless of their configured behavior.
When the device is set for Legacy Write Protection
mode, the EEPROM and Security register are
protected based upon the Block Protection bits in the
STATUS register. This functionality is described in
Section 6.1.2 “Block Write-Protect Bits”.
10.1
Enhanced Write Protection Mode
The device incorporates an Enhanced Write Protection
mode which is enabled by setting the WPM bit of the
STATUS register (byte 0, bit 7) to a logic ‘1’. When the
device is set to Enhanced Write Protection mode, the
STATUS register and Memory Partition registers are
protected from any modification when the WPEN bit is
set to a logic ‘1’ and the WP pin is asserted.
Setting the 25CSM04 for Enhanced Write Protection
mode enables its eight Memory Partition Registers
(MPR0 through MPR7). These are 8-bit registers that
control the memory organization in terms of writable
addresses ranges and the type of protection behavior.
2019-2020 Microchip Technology Inc.
DS20005817C-page 30
25CSM04
FIGURE 10-1:
25CSM04 MEMORY PARTITION MAP
4-Mbit (512-Kbyte) EEPROM
(256 bytes per page x 2,048 pages)
Beginning
Address
Ending
Address
Available Partition Point:
A18:A13 [000000b]
32 Pages
00000h
01FFFh
64-Kbit
Available Partition Point:
A18:A13 [000001b]
32 Pages
02000h
03FFFh
64-Kbit
Available Partition Point:
A18:A13 [000010b]
32 Pages
04000h
05FFFh
64-Kbit
Available Partition Point:
A18:A13 [000011b]
32 Pages
06000h
07FFFh
64-Kbit
32 Pages
7C000h
7DFFFh
64-Kbit
32 Pages
7E000h
7FFFFh
64-Kbit
Available Partition Point:
A18:A13 [111110b]
Available Partition Point:
A18:A13 [111111b]
10.1.2
MEMORY PARTITION REGISTER
ORGANIZATION
Each MPR is an 8-bit nonvolatile register. The MPR
organization is shown in Register 10-1. The four types
of protection behavior are defined by the contents of bit
7 and bit 6 of each MPR (see Register 10-1). Each partition can have a unique behavior.
Note:
When the Partition Behavior bits are
written to 11b, that MPR will become permanently read-only (ROM) and its contents
cannot
be
changed
(see
Register 10-1).
Bit 5 though bit 0 contain the Partition Endpoint
Address of A18:A13, where A12:A0 are a logic ‘1’. For
example, if the first partition of the memory array is
desired to stop after 128-Kbit of memory, that endpoint
address is 03FFFh. The corresponding A18:A13
address bits to be loaded into MPR0 are therefore
000001b.
The eight MPRs are each decoded sequentially by the
device, starting with MPR0. Each MPR should be set to
a Partition Endpoint Address greater than the ending
address of the previous MPR. If a higher order MPR
sets a Partition Endpoint Address less than or equal to
the ending address of a lower order MPR, that higher
order MPR is ignored and no protection is set by its
contents.
An example use case is provided in Table 10-1.
2019-2020 Microchip Technology Inc.
DS20005817C-page 31
25CSM04
REGISTER 10-1:
MEMORY PARTITION REGISTERS
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PB1
PB0
A18
A17
A16
A15
A14
A13
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
PB[1:0]: Partition Behavior bits(1)
00 = Partition is open and writing is permitted.
01 = Partition is always write-protected but can be reversed at a later time (software write-protected).
10 = Partition is write-protected only when WP pin is asserted (hardware write-protected).
11 = Partition is software write-protected and Memory Partition register is permanently locked.
bit 7-6
A[18:13]: Partition Endpoint Address bits(1, 2)
000000 = Endpoint address of partition is set to 01FFFh.
000001 = Endpoint address of partition is set to 03FFFh.
•
•
•
111110 = Endpoint address of partition is set to 7DFFFh.
111111 = Endpoint address of partition is set to 7FFFFh.
bit 5-0
Note 1: The Memory Partition registers cannot be written if the FMPC bit has been set.
2: The Partition Endpoint Address bits cannot be written if the PABP bit has been set.
TABLE 10-1:
EXAMPLE USE OF MEMORY PARTITION REGISTERS
Register Content
Partition
Behavior Bits
(Bit 7-6)
Partition
Protection
Register
Protection
Partition
Ending
Address Bits
(Bit 5-0)
Partition
Ending
Memory
Address
Partition Size and
Address Range
MPR0
43h
01b
Software
Protection
Unlocked
000011b
07FFFh
256-Kbit partition
000000h-007FFFh
MPR1
C4h
11b
Software
Protection
Locked
000100b
09FFFh
64-Kbit partition
008000h-009FFFh
00b
Unprotected
Unlocked
Hardware
Protection
Unlocked
MPR2(1)
03h
MPR3
8Fh
10b
000011b
001111b
07FFFh
01FFFFh
Register ignored
704-Kbit partition
00A000h-01FFFFh
Note 1: In this example, MPR2 is ignored because its Partition Endpoint Address was not greater than the ending
address specified by MPR1.
10.1.3
PROTECTING THE PARTITION
ENDPOINT ADDRESSES
The 25CSM04 includes the ability to protect the
Partition Endpoint Addresses specified in the device’s
eight MPRs from being modified. When the protection
is enabled, the Partition Behavior bits of the MPR can
still be modified. As shown in Table 10-2, this function
becomes redundant if the FMPC bit in the STATUS
register (bit 5, byte 1) is a logic ‘1’ as the result of a
FRZR sequence (see Section 4.5.4 “Freeze Memory
Protection Configuration (FRZR)”) since the FRZR
sequence locks all Partition Endpoint Addresses and
Partition Behavior bits.
2019-2020 Microchip Technology Inc.
Note:
The PPAB instruction will be ignored if the
WPEN bit (byte 0, bit 7) of the STATUS
register is set to a logic ‘1’ and the WP pin
is asserted.
DS20005817C-page 32
25CSM04
Once the Partition Endpoint Addresses are
programmed to the desired values, it is recommended
that addresses be protected to prevent unintentional
modification. This is accomplished by executing the
Protect Partition Address Boundary (PPAB) instruction
which will modify the PABP bit in the STATUS register
(bit 3, byte 1).
Note:
The starting address of each partition is
determined by the endpoint address
boundary of the previous partition
(00000h for MPR0). Changing the
address boundary of an MPR can affect
the assigned write-protection behavior for
individual array locations by reassigning
their associated partition.
TABLE 10-2:
MEMORY PARTITION REGISTER PROTECTION MATRIX
FMPC
PABP
0
Partition Behavior Bits
Writable
Writable
Writable
Protected
Permanently-Protected
Permanently-Protected
0
0
1
1
x
To execute the PPAB instruction, first a WREN instruction
and then a PRWE instruction must be sent to enable
write sequences (see Section 10.2 “Writing to the
Memory Partition Registers”). This will set the WEL
and PREL bits to a logic ‘1’.
Using a data byte of FFh will protect the Partition
Endpoint Addresses from being changed by setting the
PABP bit in the STATUS register to logic ‘1’. Sending a
data byte of 00h will unprotect these addresses by
clearing the PABP bit in the STATUS register to
logic ‘0’.
Next, as shown in Figure 10-2, the PPAB (34h)
instruction is clocked in on the SI line, followed by any
24-bit address that ends with CC55h in the Least
Significant 16 bits. Finally, a data byte of 00h or FFh is
sent and the self-timed internal write cycle will begin
once the CS pin is driven high.
FIGURE 10-2:
Partition Endpoint Address Bits
Note:
If the CS pin is deasserted before the end
of the 40-bit sequence, the sequence will
be aborted and no write cycle will take
place.
PROTECT PARTITION ADDRESS BOUNDARIES (PPAB) SEQUENCE
CS
TWC(1)
0
1
2
3
4
5
6
7
8
9 10 11 12
29 30 31 32 33 34 35 36 37 38 39
SCK
Address Bits A23-A0(2)
PPAP Opcode (34h)
SI
0
0 1
MSB
1
0 1
X X X X X
MSB
X
0 1 0 1 D7 D6 D5 D4 D3 D2 D1 D0
MSB
High-Impedance
SO
Note
0 0
Data In (00h or FFh(3))
1:
This sequence initiates a self-timed internal write cycle on the rising edge of CS after a valid sequence.
2:
Address bits A23-A16 are ignored. Address bits A15-A0 must be set to CC55h.
3:
A data byte of FFh will set the PABP bit, while a data byte of 00h will clear the PABP bit.
2019-2020 Microchip Technology Inc.
DS20005817C-page 33
25CSM04
10.1.4
10.2
ADDRESS LOCATION OF THE
MEMORY PARTITION REGISTERS
When attempting to access any of the device’s eight
MPRs, the address of each MPR is embedded in bit
position A18:A16 of the 24-bit address sent to the
device.
10.2.1
MEMORY PARTITION
REGISTER ADDRESS
LOCATION
Memory Partition
Register Number
A18
A17
A16
MPR0
0
0
0
0
1
0
MPR1
0
MPR2
MPR3
0
MPR4
0
0
1
MPR7
1
0
1
MPR6
1
1
1
MPR5
FIGURE 10-3:
0
1
1
1
MEMORY PARTITION REGISTER
WRITE ENABLE (PRWE)
Prior to any write sequence to protect an address
boundary, or FRZR instruction, the WEL and PREL bits
in the STATUS register must be set to ‘1’. This is
accomplished by first sending a WREN (06h) instruction,
see Section 6.1.4 “Ready/Busy Status Latch”)
followed by a PRWE (07h) instruction, as shown in
Figure 10-3. Once both bits are set to ‘1’, the MPRs can
be programmed with the WMPR instruction, the Partition
Endpoint Addresses can be set with the PPAB
instruction, or the contents of all MPRs can be
permanently locked with the FRZR instruction. Upon
completion of any of these instructions, the PREL and
WEL bits are automatically reset to logic ‘0’.
The remaining 21 address bits (A23-A19 and A15-A0)
are ignored. Table 10-3 depicts the values needed to
be sent in the A18 through A16 positions.
TABLE 10-3:
Writing to the Memory Partition
Registers
0
1
1
PARTITION REGISTER WRITE ENABLE (PRWE) INSTRUCTION
CS
0
1
2
3
4
5
6
7
SCK
PRWE Opcode (07h)
SI
0
0
0
0
0
1
1
1
MSB
SO
2019-2020 Microchip Technology Inc.
High-Impedance
DS20005817C-page 34
25CSM04
10.2.2
MEMORY PARTITION REGISTER
WRITE DISABLE (PRWD)
A Partition Register Write Disable (PRWD) instruction is
also available (opcode 0Ah) which will reset the PREL
bit in the STATUS register to a logic ‘0’ state.
FIGURE 10-4:
PARTITION REGISTER WRITE DISABLE (PRWD) INSTRUCTION
CS
0
1
2
3
4
5
6
7
SCK
PRWD Opcode (0Ah)
0
SI
0
0
0
1
0
1
0
MSB
High-Impedance
SO
10.2.3
WRITING TO THE MEMORY
PARTITION REGISTERS
Following the address information, a data byte using
the register definition shown in Register 10-1 must be
sent to the device followed by deasserting the CS line.
The device will enter an internal write cycle and once
complete, the WEL and PREL STATUS register bits are
automatically reset to logic ‘0’.
Once the WEL and PREL bits in the STATUS register
have been set to ‘1’, the Memory Partition registers can
be programmed provided that the FMPC bit in the
STATUS register has not already been set to a logic ‘1’
by executing the FRZR sequence (Section 4.5.4
“Freeze
Memory
Protection
Configuration
(FRZR)”).
Any additional data clocked into the device after the
first byte of data will cause the instruction to be ignored
as only one MPR can be programmed at a time.
Termination of the sequence at somewhere other than
an 8-bit boundary will cause the instruction to be
ignored. This sequence is depicted in Figure 10-5.
Writing to the MPRs uses the WMPR instruction. To
issue the WMPR instruction, the CS pin must first be
asserted and then the opcode 32h must be clocked into
the device on the SI line, followed by three address
bytes containing the Memory Partition register address
that corresponds with the desired Memory Partition
register number embedded in bits A18, A17 and A16
(Table 10-3).
FIGURE 10-5:
The MPR Partition Endpoint Address values must be
loaded sequentially in each register as the eight MPRs
are decoded sequentially by the device, starting with
MPR0. If a higher order MPR sets a Partition Endpoint
Address less than or equal to the ending address of a
lower order MPR, that higher order MPR is ignored and
no behavior is set by its contents.
WRITE MEMORY PARTITION REGISTERS (WMPR) SEQUENCE
CS
TWC(1)
0
1
2
3
4
5
6
7
8
9 10 11 12
29 30 31 32 33 34 35 36 37 38 39
SCK
Address Bits A23-A0
(MPR in A18-A16)(2)
WMPR Opcode (32h)
SI
0
0 1
MSB
1
0 0
1 0
X X X X
MSB
X X X X D7 D6 D5 D4 D3 D2 D1 D0
MSB
High-Impedance
SO
Note
X A18
Data In
1:
This sequence initiates a self-timed internal write cycle on the rising edge of CS after a valid sequence.
2:
Address bits A23-A19 and A15-A0 are ignored.
2019-2020 Microchip Technology Inc.
DS20005817C-page 35
25CSM04
10.3
Reading the Memory Partition
Registers
The contents of the Memory Partition registers can be
read with the Read Memory Partition Register (RMPR)
instruction. Their contents can be read irrespective of
the FMPC bit in the STATUS register.
To determine the MPR contents, first the device must
be selected with the CS line and then the opcode 31h
must be clocked into the device on the SI line, followed
by the 24-bit Memory Partition register address.
The address for each Memory Partition register is
embedded into the first address byte sent to the device,
in bit positions A18 through A16 (see Table 10-3). The
device will then begin to clock data out on the SO line.
Only one MPR can be read at a time. This sequence is
depicted in Figure 10-6.
FIGURE 10-6:
READ MEMORY PARTITION REGISTER (RMPR) SEQUENCE
CS
0
1
2
3
4
5
6
7
8
9 10 11 12
29 30 31 32 33 34 35 36 37 38 39
SCK
Address Bits A23-A0(1)
RMPR Opcode (31h)
SI
0
0
MSB
1
1
0
0
SO
0
1
X
X
MSB
X
X X A18
High-Impedance
X
X
X
MPR Value
D7 D6 D5 D4 D3 D2 D1 D0
Note 1: Address bits A23-A19 and A15-A0 are ignored.
2019-2020 Microchip Technology Inc.
DS20005817C-page 36
25CSM04
11.0
IDENTIFICATION REGISTER
The fourth byte output will be the Extended Device
Information (EDI) String Length which, for the
25CSM04, will be 01h indicating one byte of EDI data
follows.
The Identification register contains identification
information that can be read from the device to enable
systems to electronically query and identify the
25CSM04 while it is in system.
After one byte of EDI data is output, the SO pin will go
into a high-impedance state; therefore, additional clock
cycles will have no effect on the SO pin and no data will
be output. As indicated in the JEDEC® standard,
reading the EDI String Length and any subsequent
data is optional.
The identification method and the instruction opcode
comply with the JEDEC® standard for “Manufacturer
and Device ID Read Methodology for SPI Compatible
Serial Interface Memory Devices”. The type of
information that can be read from the device includes
the JEDEC® defined Manufacturer ID, the
vendor-specific Device ID, and the vendor-specific
Extended Device Information (EDI).
11.1
Deasserting the CS pin will terminate the Manufacturer
and Device ID read sequence and put the SO pin into
a high-impedance state. The CS pin can be deasserted
at any time and does not require that a full byte of data
be read. This sequence is depicted in Figure 11-1.
Reading the Identification
Register
To read the identification information, the CS pin must
first be asserted and the 9Fh opcode (SPID) must be
clocked into the device. After the opcode has been
clocked in, the device will begin outputting the
identification data on the SO pin during the subsequent
clock cycles. The first byte output will be the
Manufacturer ID followed by two bytes of Device ID
information.
MANUFACTURER AND DEVICE ID DETAILS
Data Type
Manufacturer ID
Device ID (Part 1)
Device ID (Part 2)
Byte
No.
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Hex
Value
1
JEDEC® Assigned Code
29h
JEDEC® Code: 0010 1001
(29h for Microchip)
2
EDI Length
4
EDI Byte 1
Device Revision
5
FIGURE 11-1:
0
0
1
0
1
0
0
1
1
1
0
0
1
1
0
0
CCh
4-Mbit Density Code
0
0
0
0
0
0
0
0
00h
Reserved for Future Use
01h
Indicates one EDI byte
0
0
0
0
0
0
0
0
00h
First generation, SPI 4-Mbit
device
Family Code
3
Details
Sub Code
0
0
0
Density Code
Product Variant
0
0
0
0
1
READ IDENTIFICATION REGISTER (SPID) SEQUENCE
CS
0
SCK
Note:
7
8
14 15 16
22 23 24
30 31 32
47
38 39 40
SPID Opcode
SI
SO
6
9Fh
High-Impedance
Each transition
2019-2020 Microchip Technology Inc.
Manufacturer
ID
Device ID
Byte 1
29h
CCh
Device ID
Byte 2
00h
EDI String
Length
01h
EDI Data
Byte 1
00h
shown for SI and SO represents one byte (8 bits).
DS20005817C-page 37
25CSM04
12.0
PACKAGING INFORMATION
12.1
Package Marking Information
8-Lead SOIC
Example
XXYYWW
25CSM04
SN2004
13F
8-Pad 5x6 TDFN
Example
25CSM04
XXXXXXX
YYWWNNN
25CSM04
MF
200413F
8-Ball CSP
Example
25CSM04
XXXXXXX
25CSM04
CS0668MY
200413F
YYWWNNN
Part Number
25CSM04
Legend: XX...X
Y
YY
WW
NNN
*
Note:
1st Line Marking Codes
SOIC
TDFN
CSP
25CSM04
25CSM04
25CSM04
Customer-specific information
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
This package is RoHs compliant. The JEDEC® designator
can be found on the outer packaging for this package.
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
2019-2020 Microchip Technology Inc.
DS20005817C-page 38
25CSM04
8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm (.150 In.) Body [SOIC]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2X
0.10 C A–B
D
A
D
NOTE 5
N
E
2
E1
2
E1
E
2X
0.10 C A–B
2X
0.10 C A–B
NOTE 1
2
1
e
B
NX b
0.25
C A–B D
NOTE 5
TOP VIEW
0.10 C
C
A A2
SEATING
PLANE
8X
A1
SIDE VIEW
0.10 C
h
R0.13
h
R0.13
H
SEE VIEW C
VIEW A–A
0.23
L
(L1)
VIEW C
Microchip Technology Drawing No. C04-057-SN Rev F Sheet 1 of 2
2019-2020 Microchip Technology Inc.
DS20005817C-page 39
25CSM04
8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm (.150 In.) Body [SOIC]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Units
Dimension Limits
Number of Pins
N
e
Pitch
Overall Height
A
Molded Package Thickness
A2
§
Standoff
A1
Overall Width
E
Molded Package Width
E1
Overall Length
D
Chamfer (Optional)
h
Foot Length
L
Footprint
L1
Foot Angle
c
Lead Thickness
b
Lead Width
Mold Draft Angle Top
Mold Draft Angle Bottom
MIN
1.25
0.10
0.25
0.40
0°
0.17
0.31
5°
5°
MILLIMETERS
NOM
8
1.27 BSC
6.00 BSC
3.90 BSC
4.90 BSC
1.04 REF
-
MAX
1.75
0.25
0.50
1.27
8°
0.25
0.51
15°
15°
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. § Significant Characteristic
3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or
protrusions shall not exceed 0.15mm per side.
4. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
5. Datums A & B to be determined at Datum H.
Microchip Technology Drawing No. C04-057-SN Rev F Sheet 2 of 2
2019-2020 Microchip Technology Inc.
DS20005817C-page 40
25CSM04
8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm (.150 In.) Body [SOIC]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
SILK SCREEN
C
Y1
X1
E
RECOMMENDED LAND PATTERN
Units
Dimension Limits
E
Contact Pitch
Contact Pad Spacing
C
Contact Pad Width (X8)
X1
Contact Pad Length (X8)
Y1
MIN
MILLIMETERS
NOM
1.27 BSC
5.40
MAX
0.60
1.55
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Microchip Technology Drawing C04-2057-SN Rev F
2019-2020 Microchip Technology Inc.
DS20005817C-page 41
25CSM04
8-Lead Plastic Very, Very Thin Small Outline No-Lead (MF) - 5x6 mm Body [TDFN-S]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
D
A
B
N
(DATUM A)
(DATUM B)
E
NOTE 1
2X
0.15 C
1
2
2X
0.15 C
TOP VIEW
A1
0.10 C
C
A
SEATING
PLANE
A3
SIDE VIEW
0.08 C
0.10
C A B
D2
e
1
2
0.10
C A B
NOTE 1
E2
K
N
8Xb
0.10
0.05
SEE DETAIL A
C A B
C
BOTTOM VIEW
Microchip Technology Drawing C04-210B Sheet 1 of 2
2019-2020 Microchip Technology Inc.
DS20005817C-page 42
25CSM04
8-Lead Plastic Very, Very Thin Small Outline No-Lead (MF) - 5x6 mm Body [TDFN-S]
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Note:
(DATUM A)
L
e/2
e
DETAIL A
Units
Dimension Limits
N
Number of Terminals
e
Pitch
A
Overall Height
Standoff
A1
A3
Terminal Thickness
D
Overall Width
D2
Exposed Pad Width
E
Overall Length
E2
Exposed Pad Length
b
Terminal Width
L
Terminal Length
Terminal-to-Exposed-Pad
K
MIN
0.70
0.00
0.35
0.50
0.20
MILLIMETERS
NOM
8
1.27 BSC
0.75
0.02
0.20 REF
5.00 BSC
4.00 BSC
6.00 BSC
3.40 BSC
0.42
0.60
-
MAX
0.80
0.05
0.48
0.70
-
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Package is saw singulated
3. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-210B Sheet 2 of 2
2019-2020 Microchip Technology Inc.
DS20005817C-page 43
25CSM04
8-Lead Plastic Very, Very Thin Small Outline No-Lead (MF) - 5x6 mm Body [TDFN-S]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
C
X2
E
X1
Y2
Y1
SILK SCREEN
RECOMMENDED LAND PATTERN
Units
Dimension Limits
Contact Pitch
E
Optional Center Pad Width
X2
Optional Center Pad Length
Y2
Contact Pad Spacing
C
Contact Pad Width (X8)
X1
Contact Pad Length (X8)
Y1
MIN
MILLIMETERS
NOM
1.27 BSC
MAX
3.50
4.10
5.70
0.45
1.10
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Microchip Technology Drawing C04-2210A
2019-2020 Microchip Technology Inc.
DS20005817C-page 44
25CSM04
8-Ball Wafer Level Chip Scale Package (CS) - [WLCSP]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
D
A
B
(DATUM A)
4
3
NOTE1
E
(DATUM B)
2
1
0.010 C
A1 CORNER
A
B
C
D
TOP VIEW
0.010 C
A4
A2
C
SEATING
PLANE
A
A1
SIDE VIEW
A
A1 CORNER
B
0.015 C
C
D
1
2
d1
NOTE 1
d2
3
4
8X Øb
0.05
0.015
e
C A B
C
e
e1
BOTTOM VIEW
Microchip Technology Drawing C04-21241 Rev B Sheet 1 of 2
2019-2020 Microchip Technology Inc.
DS20005817C-page 45
25CSM04
8-Ball Wafer Level Chip Scale Package (CS) - [WLCSP]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Units
Dimension Limits
A
Overall Height
Bump Height
A1
A2
Body Height
A4
Backside Laminate Thickness
D
Length
E
Width
d1
Bump Pitch
d2
Bump Pitch
e
Bump Pitch
e1
Bump Pitch
b
Bump Diameter
MILLIMETERS
NOM
0.315
0.100
0.190
0.025
See Note 3
See Note 3
1.00 BSC
1.40 BSC
0.50 BSC
2.10 BSC
0.185
0.175
MIN
0.275
0.085
0.175
0.015
MAX
0.355
0.115
0.205
0.035
0.200
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
3. Please contact your local Microchip representative for details.
Microchip Technology Drawing C04-21241 Rev B Sheet 2 of 2
2019-2020 Microchip Technology Inc.
DS20005817C-page 46
25CSM04
8-Ball Wafer Level Chip Scale Package (CS) - [WLCSP]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
C1
E1
E2
C2
E3
SILK SCREEN
E2
ØX
E1
E4
RECOMMENDED LAND PATTERN
Units
Dimension Limits
Contact Pitch
E1
Contact Pitch
E2
E3
Contact Pitch
Contact Pitch
E4
Contact Pad Spacing
C1
Contact Pad Spacing
C2
Contact Pad Diameter (X8)
X1
MIN
MILLIMETERS
NOM
0.50 BSC
0.20 BSC
1.00 BSC
1.10 BSC
2.10 BSC
1.40 BSC
MAX
0.17
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Microchip Technology Drawing C04-23241 Rev B
2019-2020 Microchip Technology Inc.
DS20005817C-page 47
25CSM04
APPENDIX A:
REVISION HISTORY
Revision C (04/2020)
Removed Preliminary status; Removed redundant
“factory default” notes; Updated SOIC package
drawing to latest revision.
Revision B (01/2020)
Added Package Drawing for Wafer Level Chip Scale
Package (WLSCP).
Revision A (10/2019)
Initial release of this document.
2019-2020 Microchip Technology Inc.
DS20005817C-page 48
25CSM04
THE MICROCHIP WEBSITE
CUSTOMER SUPPORT
Microchip provides online support via our website at
www.microchip.com. This website is used as a means
to make files and information easily available to
customers. Accessible by using your favorite Internet
browser, the website contains the following information:
Users of Microchip products can receive assistance
through several channels:
• Product Support – Data sheets and errata, application notes and sample programs, design
resources, user’s guides and hardware support
documents, latest software releases and archived
software
• General Technical Support – Frequently Asked
Questions (FAQ), technical support requests,
online discussion groups, Microchip consultant
program member listing
• Business of Microchip – Product selector and
ordering guides, latest Microchip press releases,
listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives
•
•
•
•
Distributor or Representative
Local Sales Office
Field Application Engineer (FAE)
Technical Support
Customers should contact their distributor, representative or Field Application Engineer (FAE) for support.
Local sales offices are also available to help customers. A listing of sales offices and locations is included in
the back of this document.
Technical support is available through the website
at: http://microchip.com/support
CUSTOMER CHANGE NOTIFICATION
SERVICE
Microchip’s customer notification service helps keep
customers current on Microchip products. Subscribers
will receive e-mail notification whenever there are
changes, updates, revisions or errata related to a specified product family or development tool of interest.
To register, access the Microchip website at
www.microchip.com. Under “Support”, click on “Customer Change Notification” and follow the registration instructions.
2019-2020 Microchip Technology Inc.
DS20005817C-page 49
25CSM04
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
[X]
PART NO.
Device
(1)
Tape and Reel
Option
X
/XX
Temperature
Range
Package
Device:
25CSM04 = 4-Mbit SPI Serial EEPROM with Security Register
Tape and Reel
Option:
Blank
T
= Standard packaging (tube or tray)
= Tape and Reel(1)
Temperature
Range:
I
= -40C to +85C (Industrial)
Package:
SN
MF
=
=
CS0668 =
8-Lead Plastic Small Outline – Narrow (3.90 mm)
8-Pad Ultra Thin, Dual Flat, No Lead
(5.0 mm x 6.0 mm x 0.6 mm)
8-Bump, Extremely Thin, Fine Pitch, Wafer Level
Chip Scale Package
Examples:
a) 25CSM04T-I/SN
b)
c)
d)
e)
= 4-Mbit, 2.5V-5.5V SPI
Serial EEPROM, Tape
and Reel, Industrial
Temp., SOIC package.
25CSM04-I/SN
= 4-Mbit, 2.5V-5.5V SPI
Serial EEPROM, Industrial Temp., SOIC package.
25CSM04T-I/MF
= 4-Mbit, 2.5V-5.5V SPI
Serial EEPROM, Tape
and Reel, Industrial
Temp., TDFN package.
25CSM04-I/MF
= 4-Mbit, 2.5V-5.5V SPI
Serial EEPROM, Industrial Temp., TDFN package.
25CSM04T-I/CS0668 = 4-Mbit, 2.5V-5.5V SPI
Serial EEPROM, Tape
and Reel, Industrial
Temp., CSP package.
Note
2019-2020 Microchip Technology Inc.
1:
Tape and Reel identifier only appears in
the catalog part number description. This
identifier is used for ordering purposes
and is not printed on the device package.
Check with your Microchip Sales Office
for package availability with the Tape and
Reel option.
DS20005817C-page 50
25CSM04
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
•
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights unless otherwise stated.
Trademarks
The Microchip name and logo, the Microchip logo, Adaptec,
AnyRate, AVR, AVR logo, AVR Freaks, BesTime, BitCloud, chipKIT,
chipKIT logo, CryptoMemory, CryptoRF, dsPIC, FlashFlex,
flexPWR, HELDO, IGLOO, JukeBlox, KeeLoq, Kleer, LANCheck,
LinkMD, maXStylus, maXTouch, MediaLB, megaAVR, Microsemi,
Microsemi logo, MOST, MOST logo, MPLAB, OptoLyzer,
PackeTime, PIC, picoPower, PICSTART, PIC32 logo, PolarFire,
Prochip Designer, QTouch, SAM-BA, SenGenuity, SpyNIC, SST,
SST Logo, SuperFlash, Symmetricom, SyncServer, Tachyon,
TempTrackr, TimeSource, tinyAVR, UNI/O, Vectron, and XMEGA
are registered trademarks of Microchip Technology Incorporated in
the U.S.A. and other countries.
APT, ClockWorks, The Embedded Control Solutions Company,
EtherSynch, FlashTec, Hyper Speed Control, HyperLight Load,
IntelliMOS, Libero, motorBench, mTouch, Powermite 3, Precision
Edge, ProASIC, ProASIC Plus, ProASIC Plus logo, Quiet-Wire,
SmartFusion, SyncWorld, Temux, TimeCesium, TimeHub,
TimePictra, TimeProvider, Vite, WinPath, and ZL are registered
trademarks of Microchip Technology Incorporated in the U.S.A.
Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any
Capacitor, AnyIn, AnyOut, BlueSky, BodyCom, CodeGuard,
CryptoAuthentication, CryptoAutomotive, CryptoCompanion,
CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average
Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial
Programming, ICSP, INICnet, Inter-Chip Connectivity, JitterBlocker,
KleerNet, KleerNet logo, memBrain, Mindi, MiWi, MPASM, MPF,
MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach,
Omniscient Code Generation, PICDEM, PICDEM.net, PICkit,
PICtail, PowerSmart, PureSilicon, QMatrix, REAL ICE, Ripple
Blocker, SAM-ICE, Serial Quad I/O, SMART-I.S., SQI,
SuperSwitcher, SuperSwitcher II, Total Endurance, TSHARC,
USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and
ZENA are trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated in
the U.S.A.
The Adaptec logo, Frequency on Demand, Silicon Storage
Technology, and Symmcom are registered trademarks of Microchip
Technology Inc. in other countries.
GestIC is a registered trademark of Microchip Technology Germany
II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in
other countries.
All other trademarks mentioned herein are property of their
respective companies.
© 2019-2020, Microchip Technology Incorporated, All Rights
Reserved.
For information regarding Microchip’s Quality Management Systems,
please visit www.microchip.com/quality.
2019-2020 Microchip Technology Inc.
ISBN: 978-1-5224-6002-2
DS20005817C-page 51
Worldwide Sales and Service
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2019-2020 Microchip Technology Inc.
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Sweden - Stockholm
Tel: 46-8-5090-4654
UK - Wokingham
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Fax: 44-118-921-5820
DS20005817C-page 52
02/28/20
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