25LC080CT-I/MS

25AA080C/D, 25LC080C/D 8-Kbit SPI Bus Serial EEPROM Device Selection Table Part Number VCC Range Page Size Temp. Ranges Packages 1.8V-5.5V 16 bytes I MS, P, SN, MN, ST 25LC080C 2.5V-5.5V 16 bytes I, E MS, P, SN, MN, ST 25AA080D 1.8V-5.5V 32 bytes I MS, P, SN, MN, ST 25LC080D 2.5V-5.5V 32 bytes I, E MS, P, SN, MN, ST 25AA080C Features Pin Function Table • 10 MHz Maximum Clock Speed • Low-Power CMOS Technology: - Maximum Write current: 5 mA at 5.5V - Read current: 5 mA at 5.5V, 10 MHz - Standby current: 5 µA at 5.5V • 1024 x 8-bit Organization • 16-Byte Page (“C” version devices) • 32-Byte Page (“D” version devices) • Self-Timed Erase and Write Cycles (5 ms maximum) • Block Write Protection: - Protect none, 1/4, 1/2 or all of array • Built-In Write Protection: - Power-on/off data protection circuitry - Write enable latch - Write-protect pin • Sequential Read • High Reliability: - Endurance: > 1M erase/write cycles - Data retention: > 200 years - ESD protection: > 4000V • Temperature Ranges Supported: - Industrial (I): -40C to +85C - Extended (E): -40°C to +125°C • RoHS Compliant • Automotive AEC-Q100 Qualified Name Function CS Chip Select Input SO Serial Data Output WP Write-Protect Pin VSS Ground SI Serial Data Input SCK Serial Clock Input HOLD Hold Input VCC Supply Voltage Description The Microchip Technology Inc. 25XX080C/D(1) are 8-Kbit Serial Electrically Erasable PROMs (EEPROM). The memory is accessed via a simple Serial Peripheral Interface (SPI) compatible serial bus. The bus signals required are a clock input (SCK) plus separate data in (SI) and data out (SO) lines. Access to the device is controlled through a Chip Select (CS) input. Communication to the device can be paused via the hold pin (HOLD). While the device is paused, transitions on its inputs will be ignored, with the exception of Chip Select, allowing the host to service higher priority interrupts. Packages Note 1: 25XX080C/D is used in this document as a generic part number for the 25AA080C/D and 25LC080C/D devices. 8-Lead MSOP, 8-Lead PDIP, 8-Lead SOIC, 8-Lead TDFN and 8-Lead TSSOP Package Types (not to scale) MSOP/TSSOP (Top View) CS SO WP VSS 1 2 3 4 8 7 6 5 TDFN (Top View) PDIP/SOIC (Top View) VCC HOLD SCK SI  2009-2021 Microchip Technology Inc. and its subsidiaries CS SO WP VSS 1 2 3 4 8 7 6 5 VCC HOLD SCK SI CS SO WP VSS 1 2 3 4 8 7 6 5 VCC HOLD SCK SI DS20002151C-page 1 25AA080C/D, 25LC080C/D 1.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings (†) VCC .............................................................................................................................................................................6.5V All inputs and outputs w.r.t. VSS ......................................................................................................... -0.6V to VCC +1.0V Storage temperature ...............................................................................................................................-65°C to +150°C Ambient temperature under bias .............................................................................................................-40°C to +125°C ESD protection on all pins ..........................................................................................................................................4 kV † NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for an extended period of time may affect device reliability. TABLE 1-1: DC CHARACTERISTICS Electrical Characteristics: Industrial (I): TA = -40°C to +85°C VCC = 1.8V to 5.5V Extended (E): TA = -40°C to +125°C VCC = 2.5V to 5.5V DC CHARACTERISTICS Param. Symbol No. D001 VIH1 Characteristic High-Level Input Voltage D002 VIL1 D003 VIL2 D004 VOL1 D005 VOL2 D006 VOH High-Level Output Voltage D007 ILI D008 D009 D010 Low-Level Input Voltage Low-Level Output Voltage D012 Note 1: Max. Units Test Conditions 0.7 VCC VCC+1 V -0.3 0.3 VCC V -0.3 0.2 VCC V VCC < 2.7V (Note 1) — 0.4 V IOL = 2.1 mA IOL = 1.0 mA, VCC < 2.5V VCC2.7V (Note 1) — 0.2 V VCC-0.5 — V IOH = -400 µA Input Leakage Current — ±1 µA CS = VCC, VIN = VSS or VCC ILO Output Leakage Current — ±1 µA CS = VCC, VOUT = VSS or VCC CINT Internal Capacitance (all inputs and outputs) — 7 pF TA = +25°C, CLK = 1.0 MHz, VCC = 5.0V (Note 1) — 5 mA VCC = 5.5V; FCLK = 10.0 MHz; SO = Open — 2.5 mA VCC = 2.5V; FCLK = 5.0 MHz; SO = Open — 5 mA VCC = 5.5V — 3 mA VCC = 2.5V — 5 µA CS = VCC = 5.5V, Inputs tied to VCC or VSS, TA = +125°C — 1 µA CS = VCC = 5.5V, Inputs tied to VCC or VSS, TA = +85°C ICC Read Operating Current D011 Min. ICC Write ICCS Standby Current This parameter is periodically sampled and not 100% tested. DS20002151C-page 2  2009-2021 Microchip Technology Inc. and its subsidiaries 25AA080C/D, 25LC080C/D TABLE 1-2: AC CHARACTERISTICS Electrical Characteristics: Industrial (I): TA = -40°C to +85°C VCC = 1.8V to 5.5V Extended (E): TA = -40°C to +125°C VCC = 2.5V to 5.5V AC CHARACTERISTICS Param. No. 1 Symbol FCLK 2 TCSS 3 TCSH 4 TCSD 5 Tsu Characteristic Clock Frequency CS Setup Time CS Hold Time CS Disable Time Data Setup Time 6 THD Data Hold Time 7 TR CLK Rise Time 8 TF CLK Fall Time 9 THI Clock High Time Min. Max. Units Test Conditions — 10 MHz 4.5V VCC  5.5V — 5 MHz 2.5V VCC  4.5V — 3 MHz 1.8V VCC  2.5V 50 — ns 4.5V VCC  5.5V 100 — ns 2.5V VCC  4.5V 150 — ns 1.8V VCC  2.5V 100 — ns 4.5V VCC  5.5V 200 — ns 2.5V VCC  4.5V 250 — ns 1.8V VCC  2.5V 50 — ns 10 — ns 4.5V VCC  5.5V 20 — ns 2.5V VCC  4.5V 30 — ns 1.8V VCC  2.5V 20 — ns 4.5V VCC  5.5V 40 — ns 2.5V VCC  4.5V 50 — ns 1.8V VCC  2.5V — 2 µs Note 1 — 2 µs Note 1 50 — ns 4.5V VCC  5.5V 100 — ns 2.5V VCC  4.5V 150 — ns 1.8V VCC  2.5V 50 — ns 4.5V VCC  5.5V 100 — ns 2.5V VCC  4.5V 1.8V VCC  2.5V 10 TLO Clock Low Time 150 — ns 11 TCLD Clock Delay Time 50 — ns 12 TCLE Clock Enable Time 50 — ns — 50 ns 4.5V VCC  5.5V — 100 ns 2.5V VCC  4.5V — 160 ns 1.8V VCC  2.5V 13 TV 14 THO 15 TDIS Note 1: 2: 3: Output Valid from Clock Low Output Hold Time Output Disable Time 0 — ns Note 1 — 40 ns 4.5V VCC  5.5V (Note 1) — 80 ns 2.5V VCC  4.5V (Note 1) — 160 ns 1.8V VCC  2.5V (Note 1) This parameter is periodically sampled and not 100% tested. TWC begins on the rising edge of CS after a valid write sequence and ends when the internal write cycle is complete. This parameter is not tested but ensured by characterization.  2009-2021 Microchip Technology Inc. and its subsidiaries DS20002151C-page 3 25AA080C/D, 25LC080C/D TABLE 1-2: AC CHARACTERISTICS (CONTINUED) Electrical Characteristics: Industrial (I): TA = -40°C to +85°C VCC = 1.8V to 5.5V Extended (E): TA = -40°C to +125°C VCC = 2.5V to 5.5V AC CHARACTERISTICS Param. No. Symbol 16 THS 17 HOLD Setup Time HOLD Hold Time THH 18 Characteristic HOLD Low to Output High-Z THZ Min. Max. Units Test Conditions 20 — ns 4.5V VCC  5.5V 40 — ns 2.5V VCC  4.5V 80 — ns 1.8V VCC  2.5V 20 — ns 4.5V VCC  5.5V 40 — ns 2.5V VCC  4.5V 80 — ns 1.8V VCC  2.5V — 30 ns 4.5V VCC  5.5V (Note 1) — 60 ns 2.5V VCC  4.5V (Note 1) — 160 ns 1.8V VCC  2.5V (Note 1) — 30 ns 4.5V VCC  5.5V — 60 ns 2.5V VCC  4.5V 19 THV HOLD High to Output Valid — 160 ns 1.8V VCC  2.5V 20 TWC Internal Write Cycle Time — 5 ms Note 2 Endurance 1M — 21 Note 1: 2: 3: E/W +25°C, VCC = 5.5V, Page Mode Cycles (Note 3) This parameter is periodically sampled and not 100% tested. TWC begins on the rising edge of CS after a valid write sequence and ends when the internal write cycle is complete. This parameter is not tested but ensured by characterization. TABLE 1-3: AC TEST CONDITIONS AC Waveform VLO = 0.2V — VH I = VCC - 0.2V Note 1 VH I = 4.0V Note 2 CL = 50 pF — Timing Measurement Reference Level Input 0.5 VCC Output 0.5 VCC Note 1: 2: For VCC  4.0V For VCC > 4.0V DS20002151C-page 4  2009-2021 Microchip Technology Inc. and its subsidiaries 25AA080C/D, 25LC080C/D FIGURE 1-1: HOLD TIMING CS 17 16 17 16 SCK 18 SO n+2 SI n+2 n+1 n 19 High-Impedance n 5 Don’t Care n+1 n-1 n n n-1 HOLD FIGURE 1-2: SERIAL INPUT TIMING 4 CS 2 7 Mode 1,1 3 8 12 11 SCK Mode 0,0 5 SI 6 MSb in LSb in High-Impedance SO FIGURE 1-3: SERIAL OUTPUT TIMING CS 9 3 10 Mode 1,1 SCK Mode 0,0 13 SO SI 14 MSb out 15 LSb out Don’t Care  2009-2021 Microchip Technology Inc. and its subsidiaries DS20002151C-page 5 25AA080C/D, 25LC080C/D 2.0 PIN DESCRIPTIONS The descriptions of the pins are listed in Table 2-1. TABLE 2-1: Name PIN FUNCTION TABLE MSOP PDIP SOIC TDFN(1) TSSOP Function CS 1 1 1 1 1 Chip Select Input SO 2 2 2 2 2 Serial Data Output WP 3 3 3 3 3 Write-Protect Pin VSS 4 4 4 4 4 Ground SI 5 5 5 5 5 Serial Data Input SCK 6 6 6 6 6 Serial Clock Input HOLD 7 7 7 7 7 Hold Input 8 8 8 8 8 Supply Voltage VCC Note 1: 2.1 Exposed pad on TDFN package can be connected to VSS or left floating. Chip Select (CS) A low level on this pin selects the device. A high level deselects the device and forces it into Standby mode. However, a programming cycle which is already initiated or in progress will be completed, regardless of CS input signal. If CS is brought high during a program cycle, the device will go into Standby mode as soon as the programming cycle is complete. When the device is deselected, SO goes to the high-impedance state, allowing multiple parts to share the same SPI bus. A low-to-high transition on CS after a valid write sequence initiates an internal write cycle. After power-up, a low level on CS is required prior to any sequence being initiated. 2.2 Serial Output (SO) The SO pin is used to transfer data out of the 25XX080C/D. During a read cycle, data are shifted out on this pin after the falling edge of the serial clock. 2.3 Write-Protect (WP) This pin is used in conjunction with the WPEN bit in the STATUS register to prohibit writes to the nonvolatile bits in the STATUS register. When WP is low and WPEN is high, writing to the nonvolatile bits in the STATUS register is disabled. All other operations function normally. When WP is high, all functions, including writes to the nonvolatile bits in the STATUS register, operate normally. If the WPEN bit is set, WP low during a STATUS register write sequence will disable writing to the STATUS register. If an internal write cycle has already begun, WP going low will have no effect on the write. The WP pin function is blocked when the WPEN bit in the STATUS register is low. This allows the user to install the 25XX080C/D in a system with WP pin grounded and still be able to write to the STATUS register. The WP pin functions will be enabled when the WPEN bit is set high. DS20002151C-page 6 2.4 Serial Input (SI) The SI pin is used to transfer data into the device. It receives instructions, addresses and data. Data are latched on the rising edge of the serial clock. 2.5 Serial Clock (SCK) The SCK is used to synchronize the communication between a host and the 25XX080C/D. Instructions, addresses or data present on the SI pin are latched on the rising edge of the clock input, while data on the SO pin are updated after the falling edge of the clock input. 2.6 Hold (HOLD) The HOLD pin is used to suspend transmission to the 25XX080C/D while in the middle of a serial sequence without having to retransmit the entire sequence again. It must be held high any time this function is not being used. Once the device is selected and a serial sequence is underway, the HOLD pin may be pulled low to pause further serial communication without resetting the serial sequence. The HOLD pin must be brought low while SCK is low, otherwise the HOLD function will not be invoked until the next SCK high-to-low transition. The 25XX080C/D must remain selected during this sequence. The SI and SCK levels are “don’t cares” during the time the device is paused and transitions on these pins will be ignored. To resume serial communication, HOLD must be brought high while the SCK pin is low, otherwise serial communication will not be resumed until the next SCK high-to-low transition. The SO line will tri-state immediately upon a high-to-low transition of the HOLD pin and will begin outputting again immediately upon a subsequent low-to-high transition of the HOLD pin, independent of the state of SCK.  2009-2021 Microchip Technology Inc. and its subsidiaries 25AA080C/D, 25LC080C/D 3.0 FUNCTIONAL DESCRIPTION 3.1 Principles of Operation Block Diagram STATUS Register The 25XX080C/D are 1024 byte Serial EEPROMs designed to interface directly with the Serial Peripheral Interface (SPI) Port of many of today’s popular microcontroller families, including Microchip’s PIC® microcontrollers. It may also interface with microcontrollers that do not have a built-in Synchronous Serial Port by using discrete I/O lines programmed properly in firmware to match the SPI protocol. The 25XX080C/D contains an 8-bit instruction register. The device is accessed via the SI pin, with data being clocked in on the rising edge of SCK. The CS pin must be low and the HOLD pin must be high for the entire operation. Table 3-1 contains a list of the possible instruction bytes and format for device operation. All instructions, addresses and data are transferred Most Significant bit (MSB) first, Least Significant bit (LSB) last. I/O Control Logic Memory Control Logic EEPROM Array X Dec Page Latches SI SO Y Decoder CS SCK Sense Amp. R/W Control HOLD WP Data (SI) are sampled on the first rising edge of SCK after CS goes low. If the clock line is shared with other peripheral devices on the SPI bus, the user can assert the HOLD input and place the 25XX080C/D in ‘HOLD’ mode. After releasing the HOLD pin, operation will resume from the point when the HOLD was asserted. TABLE 3-1: HV Generator VCC VSS INSTRUCTION SET Instruction Name Instruction Format READ 0000 0011 Read data from memory array beginning at selected address WRITE 0000 0010 Write data to memory array beginning at selected address WRDI 0000 0100 Reset the write enable latch (disable write operations) WREN 0000 0110 Set the write enable latch (enable write operations) RDSR 0000 0101 Read STATUS register WRSR 0000 0001 Write STATUS register  2009-2021 Microchip Technology Inc. and its subsidiaries Description DS20002151C-page 7 25AA080C/D, 25LC080C/D 3.2 Read Sequence The device is selected by pulling CS low. The 8-bit READ instruction is transmitted to the 25XX080C/D followed by the 16-bit address, with the six MSBs of the address being “don’t care” bits. See Figure 3-1 for more details. After the correct READ instruction and address are sent, the data stored in the memory at the selected address are shifted out on the SO pin. The data stored in the memory at the next address can be read sequentially by continuing to provide clock pulses. The internal Address Pointer is automatically incremented to the next higher address after each byte of data is shifted out. When the highest address is reached (03FFh), the address counter rolls over to address 0000h allowing the read cycle to be continued indefinitely. The read operation is terminated by raising the CS pin (Figure 3-1). FIGURE 3-1: READ SEQUENCE CS 0 1 2 3 4 5 6 7 8 9 10 11 21 22 23 24 25 26 27 28 29 30 31 SCK Instruction SI 0 0 0 0 0 16-bit Address 0 1 1 15 14 13 12 2 1 0 Data Out High-Impedance SO DS20002151C-page 8 7 6 5 4 3 2 1 0  2009-2021 Microchip Technology Inc. and its subsidiaries 25AA080C/D, 25LC080C/D 3.3 Write Sequence Note: Page write operations are limited to writing bytes within a single physical page, regardless of the number of bytes actually being written. Physical page boundaries start at addresses that are integer multiples of the page buffer size (or ‘page size’) and end at addresses that are integer multiples of page size – 1. If a Page Write command attempts to write across a physical page boundary, the result is that the data wrap around to the beginning of the current page (overwriting data previously stored there), instead of being written to the next page as might be expected. It is therefore necessary for the application software to prevent page write operations that would attempt to cross a page boundary. Prior to any attempt to write data to the 25XX080C/D, the write enable latch must be set by issuing the WREN instruction (Figure 3-4). This is done by setting CS low and then clocking out the proper instruction into the 25XX080C/D. After all eight bits of the instruction are transmitted, the CS must be brought high to set the write enable latch. If the write operation is initiated immediately after the WREN instruction without CS being brought high, the data will not be written to the array because the write enable latch will not have been properly set. Once the write enable latch is set, the user may proceed by setting the CS low, issuing a WRITE instruction, followed by the 16-bit address, with the six MSBs of the address being “don’t care” bits and then the data to be written. Up to 16 bytes (25XX080C) or 32 bytes (25XX080D) of data can be sent to the device before a write cycle is necessary. The only restriction is that all of the bytes must reside in the same page. FIGURE 3-2: For the data to be actually written to the array, the CS must be brought high after the Least Significant bit (D0) of the nth data byte has been clocked in. If CS is brought high at any other time, the write operation will not be completed. Refer to Figure 3-2 and Figure 3-3 for more detailed illustrations on the byte write sequence and the page write sequence, respectively. While the write is in progress, the STATUS register may be read to check the status of the WPEN, WIP, WEL, BP1 and BP0 bits (Figure 3-6). A read attempt of a memory array location will not be possible during a write cycle. Polling the WIP bit in the STATUS register is recommended in order to determine if a write cycle is in progress. When the write cycle is completed, the write enable latch is reset. BYTE WRITE SEQUENCE CS (1) TWC 0 1 2 3 4 5 6 7 8 9 10 11 21 22 23 24 25 26 27 28 29 30 31 SCK Instruction SI 0 0 0 0 0 16-bit Address 0 1 0 15 14 13 12 Data Byte 2 1 0 7 6 5 4 3 2 1 0 High-Impedance SO Note 1: This sequence initiates a self-timed internal write cycle on the rising edge of CS after a valid sequence.  2009-2021 Microchip Technology Inc. and its subsidiaries DS20002151C-page 9 25AA080C/D, 25LC080C/D FIGURE 3-3: PAGE WRITE SEQUENCE CS 0 1 2 0 0 0 3 4 5 6 7 8 9 10 11 21 22 23 24 25 26 27 28 29 30 31 SCK Instruction SI 0 0 16-bit Address 0 1 0 15 14 13 12 Data Byte 1 2 1 0 7 6 5 4 3 2 1 0 CS (1) TWC 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 SCK Data Byte 2 SI 7 6 5 4 3 2 Data Byte n (32/16 max) Data Byte 3 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Note 1: This sequence initiates a self-timed internal write cycle on the rising edge of CS after a valid sequence. DS20002151C-page 10  2009-2021 Microchip Technology Inc. and its subsidiaries 25AA080C/D, 25LC080C/D 3.4 Write Enable (WREN) and Write Disable (WRDI) The following is a list of conditions under which the write enable latch will be reset: • • • • The 25XX080C/D contains a write enable latch. See Table 3-4 for the Write-Protect Functionality Matrix. This latch must be set before any write operation will be completed internally. The WREN instruction will set the latch and the WRDI will reset the latch. FIGURE 3-4: Power-up WRDI instruction successfully executed WRSR instruction successfully executed WRITE instruction successfully executed WRITE ENABLE SEQUENCE (WREN) CS 0 1 2 3 4 5 6 7 SCK 0 SI 0 0 0 1 1 0 High-Impedance SO FIGURE 3-5: 0 WRITE DISABLE SEQUENCE (WRDI) CS 0 1 2 3 4 5 6 7 SCK SI 0 0 0 0 0 1 10 0 High-Impedance SO  2009-2021 Microchip Technology Inc. and its subsidiaries DS20002151C-page 11 25AA080C/D, 25LC080C/D 3.5 Read Status Register (RDSR) Instruction The Write Enable Latch (WEL) bit indicates the status of the write enable latch and is read only. When set to a ‘1’, the latch allows writes to the array or the STATUS register, when set to a ‘0’, the latch prohibits writes to the array or the STATUS register. The state of this bit can always be updated via the WREN or WRDI commands regardless of the state of write protection on the STATUS register. These commands are shown in Figure 3-4 and Figure 3-5. The Read Status Register (RDSR) instruction provides access to the STATUS register. The STATUS register may be read at any time, even during a write cycle. The STATUS register is formatted as follows: TABLE 3-2: STATUS REGISTER 7 6 5 4 3 2 1 0 W/R – – – W/R W/R R R WPEN X X X BP1 BP0 WEL WIP Note 1: The Block Protection (BP0 and BP1) bits indicate which blocks are currently write-protected. These bits are set by the user issuing the WRSR instruction (see Figure 3-7). These bits are nonvolatile and are described in more detail in Table 3-3. W/R = writable/readable. R = read-only. See Figure 3-6 for the RDSR timing sequence. The Write-In-Process (WIP) bit indicates whether the 25XX080C/D is busy with a write operation. When set to a ‘1’, a write is in progress, when set to a ‘0’, no write is in progress. This bit is read-only. FIGURE 3-6: READ STATUS REGISTER TIMING SEQUENCE (RDSR) CS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 1 0 SCK Instruction SI 0 0 0 0 0 High-Impedance SO DS20002151C-page 12 1 0 1 Data from STATUS Register 7 6 5 4 3 2  2009-2021 Microchip Technology Inc. and its subsidiaries 25AA080C/D, 25LC080C/D 3.6 Write Status Register (WRSR) Instruction Hardware write protection is enabled when WP pin is low and the WPEN bit is high. Hardware write protection is disabled when either the WP pin is high or the WPEN bit is low. When the chip is hardware write-protected, only writes to nonvolatile bits in the STATUS register are disabled. See Table 3-4 for a matrix of functionality on the WPEN bit. The Write Status Register (WRSR) instruction allows the user to write to the nonvolatile bits in the STATUS register as shown in Table 3-2. The user is able to select one of four levels of protection for the array by writing to the appropriate bits in the STATUS register. The array is divided up into four segments. The user has the ability to write-protect none, one, two or all four of the segments of the array. The partitioning is controlled as shown in Table 3-3. See Figure 3-7 for the WRSR timing sequence. TABLE 3-3: The Write-Protect Enable (WPEN) bit is also a nonvolatile bit that is available as an enable bit for the WP pin. The Write-Protect (WP) pin and the Write-Protect Enable (WPEN) bit in the STATUS register control the programmable hardware write-protect feature. TABLE 3-4: ARRAY PROTECTION BP1 BP0 Array Addresses Write-Protected 0 0 none 0 1 upper 1/4 (0300h-03FFh) 1 0 upper 1/2 (0200h-03FFh) 1 1 all (0000h-03FFh) WRITE-PROTECT FUNCTIONALITY MATRIX WEL (SR bit 1) WPEN (SR bit 7) WP (pin 3) Protected Blocks Unprotected Blocks STATUS Register 0 x x Protected Protected Protected 1 0 x Protected Writable Writable 1 1 0 (low) Protected Writable Protected 1 1 (high) Protected Writable Writable 1 Note 1: x = don’t care FIGURE 3-7: WRITE STATUS REGISTER TIMING SEQUENCE (WRSR) CS (1) TWC 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 1 0 SCK Instruction SI 0 0 0 0 Data to STATUS register 0 0 0 1 7 6 5 4 3 2 High-Impedance SO Note 1: This sequence initiates a self-timed internal write cycle on the rising edge of CS after a valid sequence.  2009-2021 Microchip Technology Inc. and its subsidiaries DS20002151C-page 13 25AA080C/D, 25LC080C/D 4.0 DATA PROTECTION The following protection has been implemented to prevent inadvertent writes to the array: • The write enable latch is reset on power-up • A write enable instruction must be issued to set the write enable latch • After a byte write, page write or STATUS register write, the write enable latch is reset • CS must be set high after the proper number of clock cycles to start an internal write cycle • Access to the array during an internal write cycle is ignored and programming is continued 5.0 POWER-ON STATE The 25XX080C/D powers on in the following state: • The device is in low-power Standby mode (CS = 1) • The write enable latch is reset • SO is in high-impedance state • A high-to-low-level transition on CS is required to enter active state DS20002151C-page 14  2009-2021 Microchip Technology Inc. and its subsidiaries 25AA080C/D, 25LC080C/D 6.0 PACKAGING INFORMATION 6.1 Package Marking Information 8-Lead MSOP (150 mil) Example XXXXXXT YWWNNN 5L8DI 14213F 8-Lead PDIP (300 mil) Example 25LC080D I/P e3 13F 2142 XXXXXXX T/XXXNNN YYWW 8-Lead SOIC Example XXXXXXXT XXXXYYWW NNN 25LC08DI SN e3 2142 13F 8-Lead 2x3 TDFN Example XXX YWW NN C44 142 13 8-Lead TSSOP Example XXXX TYWW NNN 5L8D I142 13F 1st Line Marking Codes Part Number TDFN MSOP PDIP SOIC 25AA080C 5A8CT 25AA080C 25AA08CT 25AA080D 5A8DT 25AA080D 25AA08DT 25LC080C 5L8CT 25LC080C 25LC08CT 25LC080D 5L8DT 25LC080D 25LC08DT C44  2009-2021 Microchip Technology Inc. and its subsidiaries TSSOP I-Temp. E-Temp. C31 — 5A8C C41 — 5A8D C34 C34 5L8C C44 5L8D DS20002151C-page 15 25AA080C/D, 25LC080C/D Legend: XX...X T Y YY WW NNN e3 Part number or part number code Temperature (I, E) Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week ‘01’) Alphanumeric traceability code (2 characters for small packages) RoHS-compliant JEDEC® designator for Matte Tin (Sn) Note: For very small packages with no room for the RoHS-compliant JEDEC® designator e3 , the marking will only appear on the outer carton or reel label. Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. DS20002151C-page 16  2009-2021 Microchip Technology Inc. and its subsidiaries 25AA080C/D, 25LC080C/D Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2009-2021 Microchip Technology Inc. and its subsidiaries DS20002151C-page 17 25AA080C/D, 25LC080C/D Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS20002151C-page 18  2009-2021 Microchip Technology Inc. and its subsidiaries 25AA080C/D, 25LC080C/D Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2009-2021 Microchip Technology Inc. and its subsidiaries DS20002151C-page 19 25AA080C/D, 25LC080C/D 8-Lead Plastic Dual In-Line (P) - 300 mil Body [PDIP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D A N B E1 NOTE 1 1 2 TOP VIEW E A2 A C PLANE L c A1 e eB 8X b1 8X b .010 C SIDE VIEW END VIEW Microchip Technology Drawing No. C04-018-P Rev E Sheet 1 of 2 DS20002151C-page 20  2009-2021 Microchip Technology Inc. and its subsidiaries 25AA080C/D, 25LC080C/D 8-Lead Plastic Dual In-Line (P) - 300 mil Body [PDIP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging ALTERNATE LEAD DESIGN (NOTE 5) DATUM A DATUM A b b e 2 e 2 e e Units Dimension Limits Number of Pins N e Pitch Top to Seating Plane A Molded Package Thickness A2 Base to Seating Plane A1 Shoulder to Shoulder Width E Molded Package Width E1 Overall Length D Tip to Seating Plane L c Lead Thickness b1 Upper Lead Width b Lower Lead Width eB Overall Row Spacing § MIN .115 .015 .290 .240 .348 .115 .008 .040 .014 - INCHES NOM 8 .100 BSC .130 .310 .250 .365 .130 .010 .060 .018 - MAX .210 .195 .325 .280 .400 .150 .015 .070 .022 .430 Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. § Significant Characteristic 3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" per side. 4. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. 5. Lead design above seating plane may vary, based on assembly vendor. Microchip Technology Drawing No. C04-018-P Rev E Sheet 2 of 2  2009-2021 Microchip Technology Inc. and its subsidiaries DS20002151C-page 21 25AA080C/D, 25LC080C/D 8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm (.150 In.) Body [SOIC] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2X 0.10 C A–B D A D NOTE 5 N E 2 E1 2 E1 E 2X 0.10 C A–B 2X 0.10 C A–B NOTE 1 2 1 e B NX b 0.25 C A–B D NOTE 5 TOP VIEW 0.10 C C A A2 SEATING PLANE 8X A1 SIDE VIEW 0.10 C h R0.13 h R0.13 H SEE VIEW C VIEW A–A 0.23 L (L1) VIEW C Microchip Technology Drawing No. C04-057-SN Rev F Sheet 1 of 2 DS20002151C-page 22  2009-2021 Microchip Technology Inc. and its subsidiaries 25AA080C/D, 25LC080C/D 8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm (.150 In.) Body [SOIC] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Units Dimension Limits Number of Pins N e Pitch Overall Height A Molded Package Thickness A2 § Standoff A1 Overall Width E Molded Package Width E1 Overall Length D Chamfer (Optional) h Foot Length L Footprint L1 Foot Angle c Lead Thickness b Lead Width Mold Draft Angle Top Mold Draft Angle Bottom MIN 1.25 0.10 0.25 0.40 0° 0.17 0.31 5° 5° MILLIMETERS NOM 8 1.27 BSC 6.00 BSC 3.90 BSC 4.90 BSC 1.04 REF - MAX 1.75 0.25 0.50 1.27 8° 0.25 0.51 15° 15° Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. § Significant Characteristic 3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15mm per side. 4. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. 5. Datums A & B to be determined at Datum H. Microchip Technology Drawing No. C04-057-SN Rev F Sheet 2 of 2  2009-2021 Microchip Technology Inc. and its subsidiaries DS20002151C-page 23 25AA080C/D, 25LC080C/D 8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm (.150 In.) Body [SOIC] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging SILK SCREEN C Y1 X1 E RECOMMENDED LAND PATTERN Units Dimension Limits E Contact Pitch Contact Pad Spacing C Contact Pad Width (X8) X1 Contact Pad Length (X8) Y1 MIN MILLIMETERS NOM 1.27 BSC 5.40 MAX 0.60 1.55 Notes: 1. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. Microchip Technology Drawing C04-2057-SN Rev F DS20002151C-page 24  2009-2021 Microchip Technology Inc. and its subsidiaries 25AA080C/D, 25LC080C/D 8-Lead Plastic Dual Flat, No Lead Package (MN) – 2x3x0.8 mm Body [TDFN] With 1.4x1.3 mm Exposed Pad (JEDEC Package type WDFN) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D A B N (DATUM A) (DATUM B) E NOTE 1 2X 0.15 C 1 2 2X 0.15 C TOP VIEW 0.10 C C (A3) A SEATING PLANE 8X 0.08 C A1 SIDE VIEW 0.10 C A B D2 L 1 2 0.10 C A B NOTE 1 E2 K N 8X b e 0.10 0.05 C A B C BOTTOM VIEW Microchip Technology Drawing No. C04-129-MN Rev E Sheet 1 of 2  2009-2021 Microchip Technology Inc. and its subsidiaries DS20002151C-page 25 25AA080C/D, 25LC080C/D 8-Lead Plastic Dual Flat, No Lead Package (MN) – 2x3x0.8 mm Body [TDFN] With 1.4x1.3 mm Exposed Pad (JEDEC Package type WDFN) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Units Dimension Limits N Number of Pins e Pitch A Overall Height Standoff A1 Contact Thickness A3 D Overall Length Overall Width E Exposed Pad Length D2 Exposed Pad Width E2 b Contact Width Contact Length L Contact-to-Exposed Pad K MIN 0.70 0.00 1.35 1.25 0.20 0.25 0.20 MILLIMETERS NOM 8 0.50 BSC 0.75 0.02 0.20 REF 2.00 BSC 3.00 BSC 1.40 1.30 0.25 0.30 - MAX 0.80 0.05 1.45 1.35 0.30 0.45 - Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Package may have one or more exposed tie bars at ends. 3. Package is saw singulated 4. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Microchip Technology Drawing No. C04-129-MN Rev E Sheet 2 of 2 DS20002151C-page 26  2009-2021 Microchip Technology Inc. and its subsidiaries 25AA080C/D, 25LC080C/D 8-Lead Plastic Dual Flat, No Lead Package (MN) – 2x3x0.8 mm Body [TDFN] With 1.4x1.3 mm Exposed Pad (JEDEC Package type WDFN) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging X2 EV 8 ØV C Y2 EV Y1 1 2 SILK SCREEN X1 E RECOMMENDED LAND PATTERN Units Dimension Limits E Contact Pitch Optional Center Pad Width X2 Optional Center Pad Length Y2 Contact Pad Spacing C Contact Pad Width (X8) X1 Contact Pad Length (X8) Y1 Thermal Via Diameter V Thermal Via Pitch EV MIN MILLIMETERS NOM 0.50 BSC MAX 1.60 1.50 2.90 0.25 0.85 0.30 1.00 Notes: 1. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. 2. For best soldering results, thermal vias, if used, should be filled or tented to avoid solder loss during reflow process Microchip Technology Drawing No. C04-129-MN Rev. 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