25LC080D-E/P

25LC080C/25LC080D/25LC160C/ 25LC160D/25LC320A/25LC640A/ 25LC128/25LC256 8K-256K SPI Serial EEPROM High-Temp Family Data Sheet Features • Maximum Clock: 5 MHz • Low-Power CMOS Technology: - Write current: 5 mA at 5.5V (maximum) - Read current: 5 mA at 5.5V, 5 MHz - Standby current: 10 µA at 5.5V • 1,024 x 8 through 32,768 x 8-bit Organization • Byte and Page-Level Write Operations • Self-Timed Erase and Write Cycles (6 ms maximum) • Block Write Protection: - Protect none, 1/4, 1/2 or all of array • Built-in Write Protection: - Power-on/off data protection circuitry - Write enable latch - Write-protect pin • Sequential Read • High Reliability: - Endurance: >1,000,000 erase/write cycles - Data retention: >200 years - ESD protection: >4000V • Temperature Range Supported: - Extended (H): -40°C to +150°C Communication to the device can be paused via the hold pin (HOLD). While the device is paused, transitions on its inputs will be ignored, with the exception of Chip Select, allowing the host to service higher priority interrupts. Note 1: 25LCXXX is used in this document as a generic part number for the 25LC080C/25LC080D/25LC160C/25LC 160D/25LC320A/25LC640A/25LC128/2 5LC256 devices. Packages • 8-Lead SOIC Package Types (not to scale) 8-Lead SOIC (Top View) CS 1 8 VCC SO 2 7 HOLD WP 3 6 SCK VSS 4 5 SI • RoHS Compliant • Automotive AEC-Q100 Qualified Description Microchip Technology Inc. 25LCXXX(1) devices are Mid-density 8- through 256-Kbit Serial Electrically Erasable PROMs (EEPROM). The devices are organized in blocks of x8-bit memory and support the Serial Peripheral Interface (SPI) compatible serial bus architecture. Byte-level and page-level functions are supported. The bus signals required are a clock input (SCK) plus separate data in (SI) and data out (SO) lines. Access to the device is controlled through a Chip Select (CS) input. Pin Function Table Name CS Chip Select Input SO Serial Data Output WP Write-Protect VSS Ground SI Serial Data Input SCK Serial Clock Input HOLD VCC  2009-2021 Microchip Technology Inc. Function Hold Input Supply Voltage DS20002131E-page 1 25LC080C/25LC080D/25LC160C/25LC160D/25LC320A/25LC640A/ 25LC128/25LC256 DEVICE SELECTION TABLE Part Number Density (bits) Organization VCC Range Max. Speed Page Size (MHz) (Bytes) Temp. Range Package 25LC080C 8K 1,024 x 8 2.5V-5.5V 5 25LC080D 8K 1,024 x 8 2.5V-5.5V 5 16 H SN 32 H SN 25LC160C 16K 2,048 x 8 2.5V-5.5V 25LC160D 16K 2,048 x 8 2.5V-5.5V 5 16 H SN 5 32 H SN 25LC320A 32K 4,096 x 8 2.5V-5.5V 5 32 H SN 25LC640A 64K 8,192 x 8 2.5V-5.5V 5 32 H SN 25LC128 128K 16,384 x 8 2.5V-5.5V 5 64 H SN 25LC256 256K 32,768 x 8 2.5V-5.5V 5 64 H SN DS20002131E-page 2  2009-2021 Microchip Technology Inc. 25LC080C/25LC080D/25LC160C/25LC160D/25LC320A/25LC640A/ 25LC128/25LC256 1.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings(†) VCC.............................................................................................................................................................................6.5V All inputs and outputs w.r.t. VSS ..........................................................................................................-0.6V to VCC +1.0V Storage temperature ............................................................................................................................... -65°C to +155°C Ambient temperature under bias......................................................................................................... -40°C to +150°C(1) ESD protection on all pins.......................................................................................................................................... 4 kV Note 1: AEC-Q100 reliability testing for devices intended to operate at +150°C is 1,000 hours. Any design in which the total operating time between +125°C and +150°C will be greater than 1,000 hours is not warranted without prior written approval from Microchip Technology Inc. † NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for an extended period of time may affect device reliability. TABLE 1-1: DC CHARACTERISTICS Electrical Characteristics: Extended (H): TA = -40°C to +150°C VCC = 2.5V to 5.5V DC CHARACTERISTICS Param. Symbol No. D001 VIH1 D002 VIL1 D003 VIL2 D004 VOL1 D005 VOL2 D006 VOH Characteristic High-Level Input Voltage Low-Level Input Voltage Low-Level Output Voltage High-Level Output Voltage Min. Max. Units Test Conditions 0.7 VCC VCC + 1 V -0.3 0.3VCC V -0.3 0.2VCC V VCC < 2.7V — 0.4 V IOL = 2.1 mA VCC≥2.7V — 0.2 V IOL = 1.0 mA VCC – 0.5 — V IOH = -400 µA D007 ILI Input Leakage Current — ±2 µA CS = VCC, VIN = VSS or VCC D008 ILO Output Leakage Current — ±2 µA CS = VCC, VOUT = VSS or VCC D009 CINT Internal Capacitance (all inputs and outputs) — 7 pF TA = 25°C, CLK = 1.0 MHz, VCC = 5.0V (Note 1) — 5 mA D010 ICC Read Operating Current VCC = 5.5V; FCLK = 5.0 MHz; SO = Open — 2.5 mA VCC = 2.5V; FCLK = 3.0 MHz; SO = Open D011 ICC Write Operating Current — 5 mA VCC = 5.5V — 3 mA VCC = 2.5V D012 ICCS Standby Current — 10 µA CS = VCC = 5.5V, Inputs tied to VCC or VSS, +150°C Note 1: This parameter is periodically sampled and not 100% tested.  2009-2021 Microchip Technology Inc. DS20002131E-page 3 25LC080C/25LC080D/25LC160C/25LC160D/25LC320A/25LC640A/ 25LC128/25LC256 TABLE 1-2: AC CHARACTERISTICS Electrical Characteristics: Extended (H): TA = -40°C to +150°C VCC = 2.5V to 5.5V AC CHARACTERISTICS Param. Symbol No. 1 FCLK 2 TCSS Characteristic Clock Frequency CS Setup Time 3 TCSH CS Hold Time 4 TCSD CS Disable Time 5 TSU Data Setup Time 6 THD Data Hold Time Min. Max. Units Test Conditions — 5 MHz 4.5V ≤ Vcc ≤ 5.5V — 3 MHz 2.5V ≤ Vcc < 4.5V 100 — ns 4.5V ≤Vcc ≤ 5.5V 150 — ns 2.5V ≤Vcc < 4.5V 200 — ns 4.5V ≤ Vcc ≤ 5.5V 250 — ns 2.5V ≤ Vcc < 4.5V 50 — ns 20 — ns 4.5V ≤ Vcc ≤ 5.5V 30 — ns 2.5V ≤ Vcc < 4.5V 40 — ns 4.5V ≤ Vcc ≤ 5.5V 50 — ns 2.5V ≤ Vcc < 4.5V 7 TR CLK Rise Time — 2 µs Note 1 8 TF CLK Fall Time — 2 µs Note 1 9 THI Clock High Time 100 — ns 4.5V ≤ Vcc ≤ 5.5V 150 — ns 2.5V ≤ Vcc < 4.5V 10 TLO Clock Low Time 100 — ns 4.5V ≤ Vcc ≤ 5.5V 150 — ns 2.5V ≤ Vcc < 4.5V 11 TCLD Clock Delay Time 50 — ns 12 TCLE Clock Enable Time 50 — ns 13 TV — 100 ns 4.5V ≤ Vcc ≤ 5.5V — 160 ns 2.5V ≤ Vcc < 4.5V 14 THO 15 TDIS 16 THS 17 THH 18 THZ Output Valid from Clock Low Output Hold Time Output Disable Time HOLD Setup Time HOLD Hold Time HOLD Low to Output High-Z 0 — ns Note 1 — 80 ns 4.5V ≤ Vcc ≤ 5.5V (Note 1) — 160 ns 2.5V ≤ Vcc < 4.5V (Note 1) 40 — ns 4.5V ≤ Vcc ≤ 5.5V 80 — ns 2.5V ≤ Vcc < 4.5V 40 — ns 4.5V ≤ Vcc ≤ 5.5V 80 — ns 2.5V ≤ Vcc < 4.5V — 60 ns 4.5V ≤ Vcc ≤ 5.5V (Note 1) — 160 ns 2.5V ≤ Vcc < 4.5V (Note 1) — 60 ns 4.5V ≤ Vcc ≤ 5.5V 19 THV HOLD High to Output Valid — 160 ns 2.5V ≤ Vcc < 4.5V 20 TWC Internal Write Cycle Time — 6 ms Note 2 Endurance 1M — 21 Note 1: 2: 3: E/W Page mode, +25°C, VCC = 5.5V Cycles (Note 3) This parameter is periodically sampled and not 100% tested. TWC begins on the rising edge of CS after a valid write sequence and ends when the internal write cycle is complete. This parameter is not tested but ensured by characterization. DS20002131E-page 4  2009-2021 Microchip Technology Inc. 25LC080C/25LC080D/25LC160C/25LC160D/25LC320A/25LC640A/ 25LC128/25LC256 TABLE 1-3: AC TEST CONDITIONS AC Waveform VLO = 0.2V VH I = VCC – 0.2V Note 1 VH I = 4.0V Note 2 CL = 50 pF Timing Measurement Reference Level Input 0.5 VCC Output 0.5 VCC Note 1: 2: For VCC ≤ 4.0V For VCC > 4.0V FIGURE 1-1: HOLD TIMING CS 17 16 17 16 SCK 18 SO n+2 SI n+2 n+1 n 19 High-Impedance n 5 Don’t Care n+1 n-1 n n n-1 HOLD FIGURE 1-2: SERIAL INPUT TIMING 4 CS 12 2 7 Mode 1,1 3 8 11 SCK Mode 0,0 5 SI 6 MSb in SO  2009-2021 Microchip Technology Inc. LSb in High-Impedance DS20002131E-page 5 25LC080C/25LC080D/25LC160C/25LC160D/25LC320A/25LC640A/ 25LC128/25LC256 FIGURE 1-3: SERIAL OUTPUT TIMING CS 9 3 10 Mode 1,1 SCK Mode 0,0 13 SO SI DS20002131E-page 6 14 MSb out 15 LSb out Don’t Care  2009-2021 Microchip Technology Inc. 25LC080C/25LC080D/25LC160C/25LC160D/25LC320A/25LC640A/ 25LC128/25LC256 2.0 PIN DESCRIPTIONS The descriptions of the pins are listed in Table 2-1. TABLE 2-1: 2.1 PIN FUNCTION TABLE Name SOIC Function CS 1 Chip Select Input SO 2 Serial Data Output WP 3 Write-Protect Pin VSS 4 Ground SI 5 Serial Data Input SCK 6 Serial Clock Input HOLD 7 Hold Input VCC 8 Supply Voltage Chip Select (CS) A low level on this pin selects the device. A high level deselects the device and forces it into Standby mode. However, a programming cycle which is already initiated or in progress will be completed, regardless of the CS input signal. If CS is brought high during a program cycle, the device will go into Standby mode as soon as the programming cycle is complete. When the device is deselected, SO goes to the high-impedance state, allowing multiple parts to share the same SPI bus. A low-to-high transition on CS after a valid write sequence initiates an internal write cycle. After power-up, a low level on CS is required prior to any sequence being initiated. 2.2 Serial Output (SO) The SO pin is used to transfer data out of the 25LCXXX. During a read cycle, data are shifted out on this pin after the falling edge of the serial clock. 2.3 Write-Protect (WP) This pin is used in conjunction with the WPEN bit in the STATUS register to prohibit writes to the nonvolatile bits in the STATUS register. When WP is low and WPEN is high, writing to the nonvolatile bits in the STATUS register is disabled. All other operations function normally. When WP is high, all functions, including writes to the nonvolatile bits in the STATUS register, operate normally. If the WPEN bit is set, WP low during a STATUS register write sequence will disable writing to the STATUS register. If an internal write cycle has already begun, WP going low will have no effect on the write. The WP pin function is blocked when the WPEN bit in the STATUS register is low. This allows the user to install the 25LCXXX in a system with WP pin grounded and still be able to write to the STATUS register. The WP pin functions will be enabled when the WPEN bit is set high.  2009-2021 Microchip Technology Inc. 2.4 Serial Input (SI) The SI pin is used to transfer data into the device. It receives instructions, addresses and data. Data are latched on the rising edge of the serial clock. 2.5 Serial Clock (SCK) The SCK is used to synchronize the communication between a host and the 25LCXXX. Instructions, addresses or data present on the SI pin are latched on the rising edge of the clock input, while data on the SO pin are updated after the falling edge of the clock input. 2.6 Hold (HOLD) The HOLD pin is used to suspend transmission to the 25LCXXX while in the middle of a serial sequence without having to retransmit the entire sequence again. It must be held high any time this function is not being used. Once the device is selected and a serial sequence is underway, the HOLD pin may be pulled low to pause further serial communication without resetting the serial sequence. The HOLD pin must be brought low while SCK is low, otherwise the HOLD function will not be invoked until the next SCK high-to-low transition. The 25LCXXX must remain selected during this sequence. The SI and SCK levels are “don't cares” during the time the device is paused and any transitions on these pins will be ignored. To resume serial communication, HOLD must be brought high while the SCK pin is low, otherwise serial communication will not be resumed until the next SCK high-to-low transition. The SO line will tri-state immediately upon a high-to-low transition of the HOLD pin, and will begin outputting again immediately upon a subsequent low-to-high transition of the HOLD pin, independent of the state of SCK. DS20002131E-page 7 25LC080C/25LC080D/25LC160C/25LC160D/25LC320A/25LC640A/ 25LC128/25LC256 3.0 FUNCTIONAL DESCRIPTION 3.1 Principles of Operation Block Diagram STATUS Register The 25LCXXX are Mid-Density Serial EEPROMs designed to interface directly with the Serial Peripheral Interface (SPI) port of many of today’s popular microcontroller families, including Microchip’s PIC® microcontrollers. 25LCXXX may also interface with microcontrollers that do not have a built-in SPI port by using discrete I/O lines programmed properly in firmware to match the SPI protocol. The 25LCXXX contains an 8-bit instruction register. The device is accessed via the SI pin, with data being clocked in on the rising edge of SCK. The CS pin must be low and the HOLD pin must be high for the entire operation. Table 3-1 contains a list of the possible instruction bytes and format for device operation. All instructions, addresses and data are transferred Most Significant bit (MSb) first, Least Significant bit (LSb) last. Data (SI) are sampled on the first rising edge of SCK after CS goes low. If the clock line is shared with other peripheral devices on the SPI bus, the user can assert the HOLD input and place the 25LCXXX in ‘HOLD’ mode. After releasing the HOLD pin, operation will resume from the point when the HOLD was asserted. TABLE 3-1: I/O Control Logic HV Generator Memory Control Logic EEPROM Array X Dec Page Latches SI SO Y Decoder CS SCK Sense Amp. R/W Control HOLD WP VCC VSS INSTRUCTION SET Instruction Name Instruction Format READ 0000 0011 Read data from memory array beginning at selected address WRITE 0000 0010 Write data to memory array beginning at selected address WRDI 0000 0100 Reset the write enable latch (disable write operations) WREN 0000 0110 Set the write enable latch (enable write operations) RDSR 0000 0101 Read STATUS register WRSR 0000 0001 Write STATUS register DS20002131E-page 8 Description  2009-2021 Microchip Technology Inc. 25LC080C/25LC080D/25LC160C/25LC160D/25LC320A/25LC640A/ 25LC128/25LC256 3.2 Read Sequence The device is selected by pulling CS low. The 8-bit READ instruction is transmitted to the 25LCXXX followed by the 16-bit address. After the correct READ instruction and address are sent, the data stored in the memory at the selected address are shifted out on the SO pin. The data stored in the memory at the next address can be read sequentially by continuing to provide clock pulses. The internal Address Pointer is automatically incremented to the next higher address after each byte of data is shifted out. When the highest address is reached, the address counter rolls over to address 0000h allowing the read cycle to be continued indefinitely. The read operation is terminated by raising the CS pin (Figure 3-1). FIGURE 3-1: READ SEQUENCE CS 0 1 2 0 0 0 3 4 5 6 7 8 9 10 11 0 1 1 15 14 13 12 21 22 23 24 25 26 27 28 29 30 31 SCK Instruction SI 0 0 16-bit Address 2 1 0 Data Out High-Impedance SO  2009-2021 Microchip Technology Inc. 7 6 5 4 3 2 1 0 DS20002131E-page 9 25LC080C/25LC080D/25LC160C/25LC160D/25LC320A/25LC640A/ 25LC128/25LC256 3.3 Write Sequence Note: Page write operations are limited to writing bytes within a single physical page, regardless of the number of bytes actually being written. Physical page boundaries start at addresses that are integer multiples of the page buffer size (or ‘page size’) and, end at addresses that are integer multiples of page size – 1. If a Page Write command attempts to write across a physical page boundary, the result is that the data wrap around to the beginning of the current page (overwriting data previously stored there), instead of being written to the next page as might be expected. It is therefore necessary for the application software to prevent page write operations that would attempt to cross a page boundary. Prior to any attempt to write data to the 25LCXXX, the write enable latch must be set by issuing the WREN instruction (Figure 3-4). This is done by setting CS low and then clocking out the proper instruction into the 25LCXXX. After all eight bits of the instruction are transmitted, the CS must be brought high to set the write enable latch. If the write operation is initiated immediately after the WREN instruction without CS being brought high, the data will not be written to the array because the write enable latch will not have been properly set. Once the write enable latch is set, the user may proceed by setting the CS low, issuing a WRITE instruction, followed by the 16-bit address, and then the data to be written. Depending upon the density, a page of data that ranges from 16 bytes to 64 bytes can be sent to the device before a write cycle is necessary. The only restriction is that all of the bytes must reside in the same page. FIGURE 3-2: For the data to be actually written to the array, the CS must be brought high after the Least Significant bit (D0) of the nth data byte has been clocked in. If CS is brought high at any other time, the write operation will not be completed. Refer to Figure 3-2 and Figure 3-3 for more detailed illustrations on the byte write sequence and the page write sequence, respectively. While the write is in progress, the STATUS register may be read to check the status of the WPEN, WIP, WEL, BP1 and BP0 bits (Figure 3-6). A read attempt of a memory array location will not be possible during a write cycle. When the write cycle is completed, the write enable latch is reset. BYTE WRITE SEQUENCE CS Twc(1) 0 1 2 0 0 0 3 4 8 5 6 7 9 10 11 0 1 0 15 14 13 12 21 22 23 24 25 26 27 28 29 30 31 SCK Instruction SI 0 0 16-bit Address Data Byte 2 1 0 7 6 5 4 3 2 1 0 High-Impedance SO Note 1: This sequence initiates a self-timed internal write cycle on the rising edge of CS after a valid sequence. DS20002131E-page 10  2009-2021 Microchip Technology Inc. 25LC080C/25LC080D/25LC160C/25LC160D/25LC320A/25LC640A/ 25LC128/25LC256 FIGURE 3-3: PAGE WRITE SEQUENCE CS 0 1 2 3 4 5 6 7 8 9 10 11 21 22 23 24 25 26 27 28 29 30 31 SCK Instruction SI 0 0 0 0 0 16-bit Address 0 1 0 15 14 13 12 Data Byte 1 2 1 0 7 6 5 4 3 2 1 0 CS Twc(1) 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 SCK Data Byte 2 SI 7 6 5 4 3 2 Data Byte 3 1 0 7 6 5 4 3 2 Data Byte n (16/32/64 max) 1 0 7 6 5 4 3 2 1 0 Note 1: This sequence initiates a self-timed internal write cycle on the rising edge of CS after a valid sequence.  2009-2021 Microchip Technology Inc. DS20002131E-page 11 25LC080C/25LC080D/25LC160C/25LC160D/25LC320A/25LC640A/ 25LC128/25LC256 3.4 Write Enable (WREN) and Write Disable (WRDI) The following is a list of conditions under which the write enable latch will be reset: • • • • The 25LCXXX contains a write enable latch. See Table 3-5 for the Write-Protect Functionality Matrix. This latch must be set before any write operation will be completed internally. The WREN instruction will set the latch and the WRDI will reset the latch. FIGURE 3-4: Power-up WRDI instruction successfully executed WRSR instruction successfully executed WRITE instruction successfully executed WRITE ENABLE SEQUENCE (WREN) CS 0 1 2 3 4 5 6 7 SCK 0 SI 0 0 0 1 1 0 High-Impedance SO FIGURE 3-5: 0 WRITE DISABLE SEQUENCE (WRDI) CS 0 1 2 3 4 5 6 7 SCK SI 0 0 0 0 0 1 10 0 High-Impedance SO DS20002131E-page 12  2009-2021 Microchip Technology Inc. 25LC080C/25LC080D/25LC160C/25LC160D/25LC320A/25LC640A/ 25LC128/25LC256 3.5 Read Status Register Instruction (RDSR) The Write Enable Latch (WEL) bit indicates the status of the write enable latch and is read-only. When set to a ‘1’, the latch allows writes to the array, when set to a ‘0’, the latch prohibits writes to the array. The state of this bit can always be updated via the WREN or WRDI commands regardless of the state of write protection on the STATUS register. These commands are shown in Figure 3-4 and Figure 3-5. The Read Status Register instruction (RDSR) provides access to the STATUS register. The STATUS register may be read at any time, even during a write cycle. The STATUS register is formatted as seen in Table 3-2. TABLE 3-2: 7 W/R WPEN Note 1: 6 STATUS REGISTER 5 4 3 2 1 0 — — — W/R W/R R R X BP1 BP0 WEL WIP X X The Block Protection (BP0 and BP1) bits indicate which blocks are currently write-protected. These bits are set by the user issuing the WRSR instruction. These bits are nonvolatile and are shown in Table 3-3. See Figure 3-6 for the RDSR timing sequence. W/R = writable/readable. R = read-only. The Write-In-Process (WIP) bit indicates whether the 25LCXXX is busy with a write operation. When set to a ‘1’, a write is in progress, when set to a ‘0’, no write is in progress. This bit is read-only. FIGURE 3-6: READ STATUS REGISTER TIMING SEQUENCE (RDSR) CS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 1 0 SCK Instruction SI 0 0 0 0 0 High-Impedance SO  2009-2021 Microchip Technology Inc. 1 0 1 Data from STATUS Register 7 6 5 4 3 2 DS20002131E-page 13 25LC080C/25LC080D/25LC160C/25LC160D/25LC320A/25LC640A/ 25LC128/25LC256 3.6 Write Status Register Instruction (WRSR) The Write-Protect Enable (WPEN) bit is a nonvolatile bit that is available as an enable bit for the WP pin. The Write-Protect (WP) pin and the Write-Protect Enable (WPEN) bit in the STATUS register control the programmable hardware write-protect feature. Hardware write protection is enabled when WP pin is low and the WPEN bit is high. Hardware write protection is disabled when either the WP pin is high or the WPEN bit is low. When the chip is hardware write-protected, only writes to nonvolatile bits in the STATUS register are disabled. See Table 3-5 for a matrix of functionality on the WPEN bit. The Write Status Register instruction (WRSR) allows the user to write to the nonvolatile bits in the STATUS register as shown in Table 3-2. The user is able to select one of four levels of protection for the array by writing to the appropriate bits in the STATUS register. The array is divided up into four segments. The user has the ability to write-protect none, one, two or all four of the segments of the array. The partitioning is controlled as shown in Table 3-3. See Figure 3-7 for the WRSR timing sequence. TABLE 3-3: ARRAY PROTECTION BP1 BP0 Array Addresses Write-Protected Array Addresses Unprotected 0 0 None All 0 1 Upper 1/4 Lower 3/4 1 0 Upper 1/2 Lower 1/2 1 All None 1 TABLE 3-4: ARRAY PROTECTED ADDRESS LOCATIONS Density Upper 1/4 Upper 1/2 All 8K 300h-3FFh 200h-3FFh 000h-3FFh 16K 600h-7FFh 400h-7FFh 000h-7FFh 32K C00h-FFFh 800h-FFFh 000h-FFFh 0000h-1FFFh 64K 1800h-1FFFh 1000h-1FFFh 128K 3000h-3FFFh 2000h-3FFFh 0000h-3FFFh 256K 6000h-7FFFh 4000h-7FFFh 0000h-7FFFh TABLE 3-5: WRITE-PROTECT FUNCTIONALITY MATRIX WEL (SR bit 1) WPEN (SR bit 7) WP (pin 3) Protected Blocks Unprotected Blocks STATUS Register 0 x x Protected Protected Protected 1 0 x Protected Writable Writable 1 1 0 (low) Protected Writable Protected 1 1 (high) Protected Writable Writable 1 Note 1: x = don’t care DS20002131E-page 14  2009-2021 Microchip Technology Inc. 25LC080C/25LC080D/25LC160C/25LC160D/25LC320A/25LC640A/ 25LC128/25LC256 FIGURE 3-7: WRITE STATUS REGISTER TIMING SEQUENCE (WRSR) CS (1) TWC 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 1 0 SCK Instruction SI 0 0 0 0 Data to STATUS Register 0 0 0 1 7 6 5 4 3 2 High-Impedance SO Note 1: This sequence initiates a self-timed internal write cycle on the rising edge of CS after a valid sequence. 4.0 DATA PROTECTION The following protection has been implemented to prevent inadvertent writes to the array: • The write enable latch is reset on power-up • A write enable instruction must be issued to set the write enable latch • After a byte write, page write or STATUS register write, the write enable latch is reset • CS must be set high after the proper number of clock cycles to start an internal write cycle • Access to the array during an internal write cycle is ignored and programming is continued 5.0 POWER-ON STATE The 25LCXXX powers on in the following state: • The device is in low-power Standby mode (CS = 1) • The write enable latch is reset • SO is in high-impedance state • A high-to-low level transition on CS is required to enter active state  2009-2021 Microchip Technology Inc. DS20002131E-page 15 25LC080C/25LC080D/25LC160C/25LC160D/25LC320A/25LC640A/ 25LC128/25LC256 6.0 PACKAGING INFORMATION 6.1 Package Marking Information 8-Lead SOIC Example XXXXXXXT XXXXYYWW NNN 25LC32AH SN e3 2128 13F 1st Line Marking Codes Note 1: Device SOIC 25LC080C 25LC08CT 25LC080D 25LC08DT 25LC160C 25LC16CT 25LC160D 25LC16DT 25LC320A 25LC32AT 25LC640A 25L640AT 25LC128 25LC128T 25LC256 25LC256T T = Temperature Grade (H). Legend: XX...X Y YY WW NNN e3 Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week ‘01’) Alphanumeric traceability code RoHS compliant JEDEC designator for Matte Tin (Sn) Note: For very small packages with no room for the RoHS compliant JEDEC designator e3 , the marking will only appear on the outer carton or reel label. Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. DS20002131E-page 16  2009-2021 Microchip Technology Inc. 25LC080C/25LC080D/25LC160C/25LC160D/25LC320A/25LC640A/ 25LC128/25LC256 8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm (.150 In.) Body [SOIC] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2X 0.10 C A–B D A D NOTE 5 N E 2 E1 2 E1 E 2X 0.10 C A–B 2X 0.10 C A–B NOTE 1 2 1 e B NX b 0.25 C A–B D NOTE 5 TOP VIEW 0.10 C C A A2 SEATING PLANE 8X A1 SIDE VIEW 0.10 C h R0.13 h R0.13 H SEE VIEW C VIEW A–A 0.23 L (L1) VIEW C Microchip Technology Drawing No. C04-057-SN Rev F Sheet 1 of 2  2009-2021 Microchip Technology Inc. DS20002131E-page 17 25LC080C/25LC080D/25LC160C/25LC160D/25LC320A/25LC640A/ 25LC128/25LC256 8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm (.150 In.) Body [SOIC] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Units Dimension Limits Number of Pins N e Pitch Overall Height A Molded Package Thickness A2 § Standoff A1 Overall Width E Molded Package Width E1 Overall Length D Chamfer (Optional) h Foot Length L Footprint L1 Foot Angle c Lead Thickness b Lead Width Mold Draft Angle Top Mold Draft Angle Bottom MIN 1.25 0.10 0.25 0.40 0° 0.17 0.31 5° 5° MILLIMETERS NOM 8 1.27 BSC 6.00 BSC 3.90 BSC 4.90 BSC 1.04 REF - MAX 1.75 0.25 0.50 1.27 8° 0.25 0.51 15° 15° Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. § Significant Characteristic 3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15mm per side. 4. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. 5. Datums A & B to be determined at Datum H. Microchip Technology Drawing No. C04-057-SN Rev F Sheet 2 of 2 DS20002131E-page 18  2009-2021 Microchip Technology Inc. 25LC080C/25LC080D/25LC160C/25LC160D/25LC320A/25LC640A/ 25LC128/25LC256 8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm (.150 In.) Body [SOIC] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging SILK SCREEN C Y1 X1 E RECOMMENDED LAND PATTERN Units Dimension Limits E Contact Pitch Contact Pad Spacing C Contact Pad Width (X8) X1 Contact Pad Length (X8) Y1 MIN MILLIMETERS NOM 1.27 BSC 5.40 MAX 0.60 1.55 Notes: 1. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. Microchip Technology Drawing C04-2057-SN Rev F  2009-2021 Microchip Technology Inc. DS20002131E-page 19 25LC080C/25LC080D/25LC160C/25LC160D/25LC320A/25LC640A/ 25LC128/25LC256 APPENDIX A: REVISION HISTORY Revision E (08/2021) Added Product Identification System section for Automotive; Updated SOIC package drawings; Replaced terminology “Master” and “Slave” with “Host” and “Client”, respectively; Reformatted some sections for better readability. Revision D (09/2018) Removed Preliminary status; Minor typographical corrections. Revision C (06/2009) Revised Features: Endurance and Package; Revised Table 1-2, Para. 21. Revision B (04/2009) Revised part number from 25XX to 25LCXXX; Added Note 1 to Electrical Characteristics. Revision A (01/2009) Initial release of this document. DS20002131E-page 20  2009-2021 Microchip Technology Inc. 25LC080C/25LC080D/25LC160C/25LC160D/25LC320A/25LC640A/ 25LC128/25LC256 THE MICROCHIP WEBSITE CUSTOMER SUPPORT Microchip provides online support via our website at www.microchip.com. This website is used as a means to make files and information easily available to customers. Accessible by using your favorite Internet browser, the website contains the following information: Users of Microchip products can receive assistance through several channels: • Product Support – Data sheets and errata, application notes and sample programs, design resources, user’s guides and hardware support documents, latest software releases and archived software • General Technical Support – Frequently Asked Questions (FAQ), technical support requests, online discussion groups, Microchip consultant program member listing • Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives • • • • Distributor or Representative Local Sales Office Field Application Engineer (FAE) Technical Support Customers should contact their distributor, representative or Field Application Engineer (FAE) for support. Local sales offices are also available to help customers. A listing of sales offices and locations is included in the back of this document. Technical support is available through the website at: http://microchip.com/support CUSTOMER CHANGE NOTIFICATION SERVICE Microchip’s customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, access the Microchip website at www.microchip.com. Under “Support”, click on “Customer Change Notification” and follow the registration instructions.  2009-2021 Microchip Technology Inc. DS20002131E-page 21 25LC080C/25LC080D/25LC160C/25LC160D/25LC320A/25LC640A/ 25LC128/25LC256 PRODUCT IDENTIFICATION SYSTEM (NON-AUTOMOTIVE) To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. [X] PART NO. Device Device: (1) Tape and Reel Option -X /XX Temperature Range Package 25LC080C 25LC080D 25LC160C 25LC160D 25LC320A 25LC640A 25LC128 25LC256 = 8-Kbit, 2.5V, SPI Serial EEPROM, 32-Byte Page = 8-Kbit, 2.5V, SPI Serial EEPROM, 32-Byte Page = 16-Kbit, 2.5V, SPI Serial EEPROM, 16-Byte Page = 16-Kbit, 2.5V, SPI Serial EEPROM, 32-Byte Page = 32-Kbit, 2.5V, SPI Serial EEPROM = 64-Kbit, 2.5V, SPI Serial EEPROM = 128-Kbit, 2.5V, SPI Serial EEPROM = 256-Kbit, 2.5V, SPI Serial EEPROM Tape and Reel Option: Blank T = Standard packaging (tube or tray) = Tape and Reel(1) Temperature Range: H = -40C to +150C (Extended) Package: SN = 8-Lead Plastic Small Outline – Narrow, 3.90 mm Body SOIC Examples: a) b) c) d) e) f) g) h) Note DS20002131E-page 22 25LC080CT-H/SN = 8-Kbit, 2.5V Serial EEPROM, 16-Byte Page, Tape and Reel, Extended Temp., SOIC Package. 25LC080D-H/SN = 8-Kbit, 2.5V Serial EEPROM, 32-Byte Page, Extended Temp., SOIC Package. 25LC160CT-H/SN = 16-Kbit, 2.5V Serial EEPROM, 16-Byte Page, Tape and Reel, Extended Temp., SOIC package. 25LC160D-H/SN = 16-Kbit, 2.5V Serial EEPROM, 32-Byte Page, Extended Temp., SOIC package. 25LC320AT-H/SN = 32-Kbit, 2.5V Serial EEPROM, Tape and Reel, Extended Temp., SOIC package. 25LC640A-H/SN = 64-Kbit, 2.5V Serial EEPROM, Extended Temp., SOIC Package. 25LC128T-H/SN = 128-Kbit, 2.5V Serial EEPROM, Tape and Reel, Extended Temp., SOIC Package. 25LC256-H/SN = 256-Kbit, 2.5V Serial EEPROM, Extended Temp., SOIC package. 1: Tape and Reel identifier only appears in the catalog part number description. This identifier is used for ordering purposes and is not printed on the device package. Check with your Microchip Sales Office for package availability with the Tape and Reel option.  2009-2021 Microchip Technology Inc. 25LC080C/25LC080D/25LC160C/25LC160D/25LC320A/25LC640A/ 25LC128/25LC256 PRODUCT IDENTIFICATION SYSTEM (AUTOMOTIVE) To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. [X] PART NO. Device Device: (1) Tape and Reel Option 25LC080C 25LC080D 25LC160C 25LC160D 25LC320A 25LC640A 25LC128 25LC256 -X /XX Temperature Range Package XXX (2,3) Variant = 8-Kbit, 2.5V, SPI Serial EEPROM, 32-Byte Page = 8-Kbit, 2.5V, SPI Serial EEPROM, 32-Byte Page = 16-Kbit, 2.5V, SPI Serial EEPROM, 16-Byte Page = 16-Kbit, 2.5V, SPI Serial EEPROM, 32-Byte Page = 32-Kbit, 2.5V, SPI Serial EEPROM = 64-Kbit, 2.5V, SPI Serial EEPROM = 128-Kbit, 2.5V, SPI Serial EEPROM = 256-Kbit, 2.5V, SPI Serial EEPROM Examples: a) b) c) d) e) Tape and Reel Option: Blank T = Standard packaging (tube or tray) = Tape and Reel(1) Temperature Range: H = -40C to +150C (AEC-Q100 Grade 0) Package: SN = 8-Lead Plastic Small Outline – Narrow, 3.90 mm Body SOIC Variant:(2,3) 16KVAO 16KVXX Note 25LC080C-H/SNVAO = 8-Kbit, 2.5V Serial EEPROM, 16-Byte Page, Automotive Grade 0, SOIC package. 25LC080CT-H/SNVAO = 8-Kbit, 2.5V Serial EEPROM, 16-Byte Page, Tape and Reel, Automotive Grade 0, SOIC package. 25LC160CT-H/SN16KVAO = 16-Kbit, 2.5V Serial EEPROM, 16-Byte Page, Tape and Reel, Automotive Grade 0, SOIC package. 25LC320A-H/SN16KVAO = 32-Kbit, 2.5V Serial EEPROM, Automotive Grade 0, SOIC package. 25LC320AT-H/SN16KVAO = 32-Kbit, 2.5V Serial EEPROM, Tape and Reel, Automotive Grade 0, SOIC package. 1: Tape and Reel identifier only appears in the catalog part number description. This identifier is used for ordering purposes and is not printed on the device package. Check with your Microchip Sales Office for package availability with the Tape and Reel option. 2: The VAO/VXX automotive variants have been designed, manufactured, tested and qualified in accordance with AEC-Q100 requirements for automotive applications. 3: For customers requesting a PPAP, a customerspecific part number will be generated and provided. A PPAP is not provided for VAO part numbers = Standard Automotive, 16K Process = Customer-Specific Automotive, 16K Process  2009-2021 Microchip Technology Inc. DS20002131E-page 23 Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specifications contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is secure when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods being used in attempts to breach the code protection features of the Microchip devices. We believe that these methods require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Attempts to breach these code protection features, most likely, cannot be accomplished without violating Microchip's intellectual property rights. • Microchip is willing to work with any customer who is concerned about the integrity of its code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of its code. Code protection does not mean that we are guaranteeing the product is "unbreakable." Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip's code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication is provided for the sole purpose of designing with and using Microchip products. Information regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. THIS INFORMATION IS PROVIDED BY MICROCHIP "AS IS". MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION INCLUDING BUT NOT LIMITED TO ANY IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE OR WARRANTIES RELATED TO ITS CONDITION, QUALITY, OR PERFORMANCE. IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE INFORMATION OR ITS USE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THE INFORMATION OR ITS USE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THE INFORMATION. Use of Microchip devices in life support and/or safety applications is entirely at the buyer's risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights unless otherwise stated. Trademarks The Microchip name and logo, the Microchip logo, Adaptec, AnyRate, AVR, AVR logo, AVR Freaks, BesTime, BitCloud, chipKIT, chipKIT logo, CryptoMemory, CryptoRF, dsPIC, FlashFlex, flexPWR, HELDO, IGLOO, JukeBlox, KeeLoq, Kleer, LANCheck, LinkMD, maXStylus, maXTouch, MediaLB, megaAVR, Microsemi, Microsemi logo, MOST, MOST logo, MPLAB, OptoLyzer, PackeTime, PIC, picoPower, PICSTART, PIC32 logo, PolarFire, Prochip Designer, QTouch, SAM-BA, SenGenuity, SpyNIC, SST, SST Logo, SuperFlash, Symmetricom, SyncServer, Tachyon, TimeSource, tinyAVR, UNI/O, Vectron, and XMEGA are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. AgileSwitch, APT, ClockWorks, The Embedded Control Solutions Company, EtherSynch, FlashTec, Hyper Speed Control, HyperLight Load, IntelliMOS, Libero, motorBench, mTouch, Powermite 3, Precision Edge, ProASIC, ProASIC Plus, ProASIC Plus logo, QuietWire, SmartFusion, SyncWorld, Temux, TimeCesium, TimeHub, TimePictra, TimeProvider, WinPath, and ZL are registered trademarks of Microchip Technology Incorporated in the U.S.A. Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut, Augmented Switching, BlueSky, BodyCom, CodeGuard, CryptoAuthentication, CryptoAutomotive, CryptoCompanion, CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average Matching, DAM, ECAN, Espresso T1S, EtherGREEN, IdealBridge, In-Circuit Serial Programming, ICSP, INICnet, Intelligent Paralleling, Inter-Chip Connectivity, JitterBlocker, maxCrypto, maxView, memBrain, Mindi, MiWi, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, PowerSmart, PureSilicon, QMatrix, REAL ICE, Ripple Blocker, RTAX, RTG4, SAM-ICE, Serial Quad I/O, simpleMAP, SimpliPHY, SmartBuffer, SMART-I.S., storClad, SQI, SuperSwitcher, SuperSwitcher II, Switchtec, SynchroPHY, Total Endurance, TSHARC, USBCheck, VariSense, VectorBlox, VeriPHY, ViewSpan, WiperLock, XpressConnect, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. The Adaptec logo, Frequency on Demand, Silicon Storage Technology, and Symmcom are registered trademarks of Microchip Technology Inc. in other countries. GestIC is a registered trademark of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. © 2009-2021, Microchip Technology Incorporated, All Rights Reserved. For information regarding Microchip’s Quality Management Systems, please visit www.microchip.com/quality. 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