25LC1024
1-Mbit SPI Bus Serial EEPROM
Device Selection Table
Part Number
VCC Range
Page Size
Temp. Ranges
Packages
25LC1024
2.5V-5.5V
256 Bytes
I, E
MF, P, SM
Features
• 20 MHz Maximum Clock Speed
• Byte and Page-Level Write Operations:
- 256-byte page
- 6 ms maximum write cycle time
- No page or sector erase required
• Low-Power CMOS Technology:
- Maximum Write current: 5 mA at 5.5V,
20 MHz
- Read current: 7 mA at 5.5V, 20 MHz
- Standby current: 1 µA at 2.5V
(Deep power-down)
• Electronic Signature for Device ID
• Self-Timed Erase and Write Cycles:
- Page Erase (6 ms maximum)
- Sector Erase (10 ms maximum)
- Chip Erase (10 ms maximum)
• Sector Write Protection (32K byte/sector):
- Protect none, 1/4, 1/2 or all of array
• Built-In Write Protection:
- Power-on/off data protection circuitry
- Write enable latch
- Write-protect pin
• High Reliability:
- Endurance: 1M erase/write cycles
- Data Retention: >200 years
- ESD Protection: >4000V
• Temperature Ranges Supported:
- Industrial (I):
-40C to +85C
- Extended (E):
-40°C to +125°C
• RoHS Compliant
• Automotive AEC-Q100 Qualified
Pin Function Table
Name
CS
Function
Chip Select Input
SO
Serial Data Output
WP
Write-Protect
VSS
Ground
SI
Serial Data Input
SCK
Serial Clock Input
HOLD
VCC
Hold Input
Supply Voltage
Description
The Microchip Technology Inc. 25LC1024 is a
1024-Kbit serial EEPROM memory with byte-level and
page-level serial EEPROM functions. It also features
Page, Sector and Chip erase instructions typically
associated with Flash-based products. These instructions are not required for byte or page write operations.
The memory is accessed via a simple Serial Peripheral
Interface (SPI) compatible serial bus. The bus signals
required are a clock input (SCK) plus separate data in
(SI) and data out (SO) lines. Access to the device is
controlled by a Chip Select (CS) input.
Communication to the device can be paused via the
hold pin (HOLD). While the device is paused, transitions on its inputs will be ignored, with the exception of
Chip Select, allowing the host to service higher priority
interrupts.
Packages
8-Lead DFN-S, 8-Lead PDIP and 8-Lead SOIJ
Package Types (not to scale)
8-Lead DFN-S
(Top View)
CS
SO
WP
VSS
2007-2021 Microchip Technology Inc.
1
2
3
4
PDIP/SOIJ
(Top View)
8 VCC
CS 1
8 VCC
7 HOLD SO 2
7 HOLD
6 SCK WP 3
6 SCK
VSS 4
5 SI
5 SI
DS20002064E-page 1
25LC1024
1.0
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings (†)
VCC .............................................................................................................................................................................6.5V
All inputs and outputs w.r.t. VSS ......................................................................................................... -0.6V to VCC +1.0V
Storage temperature ...............................................................................................................................-65°C to +150°C
Ambient temperature under bias .............................................................................................................-40°C to +125°C
ESD protection on all pins ..........................................................................................................................................4 kV
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for an
extended period of time may affect device reliability.
TABLE 1-1:
DC CHARACTERISTICS
Industrial (I):
Extended (E):
DC CHARACTERISTICS
Param.
Symbol
No.
Characteristic
Max.
Units
Test Conditions
D001
VIH1
D002
VIL1
D003
VIL2
D004
VOL
Low-level Output Voltage
D005
VOH
High-Level Output Voltage
D006
ILI
Input Leakage Current
—
±1
µA
CS = VCC, VIN = VSS or VCC
D007
ILO
Output Leakage Current
—
±1
µA
CS = VCC, VOUT = VSS or VCC
D008
CINT
Internal Capacitance
(all inputs and outputs)
—
7
pF
TA = +25°C, CLK = 1.0 MHz,
VCC = 5.0V (Note 1)
—
10
mA
VCC = 5.5V; FCLK = 20.0 MHz;
SO = Open
—
5
mA
VCC = 2.5V; FCLK = 10.0 MHz;
SO = Open
—
7
mA
VCC = 5.5V
—
5
mA
VCC = 2.5V
—
20
µA
CS = VCC = 5.5V, Inputs tied to
VCC or VSS, +125°C
—
12
µA
CS = VCC = 5.5V, Inputs tied to
VCC or VSS, +85°C
—
1
µA
CS = VCC = 2.5V, Inputs tied to
VCC or VSS, +85°C
—
2
µA
CS = VCC = 2.5V, Inputs tied to
VCC or VSS, +125°C
D009
High-Level Input Voltage
Min.
TA = -40°C to +85°C VCC = 2.5V to 5.5V
TA = -40°C to +125°C VCC = 2.5V to 5.5V
Low-Level Input Voltage
D011
D012
Note 1:
VCC +1
V
-0.3
0.3 VCC
V
-0.3
0.2 VCC
V
VCC < 2.7V
—
0.4
V
IOL = 2.1 mA
VCC -0.2
—
V
IOH = -400 µA
ICC Read
Operating Current
D010
0.7 VCC
ICC Write
ICCS
ICCSPD
Standby Current
Deep Power-Down Current
VCC2.7V
This parameter is periodically sampled and not 100% tested.
DS20002064E-page 2
2007-2021 Microchip Technology Inc.
25LC1024
TABLE 1-2:
AC CHARACTERISTICS
Industrial (I): TA = -40°C to +85°C VCC = 2.5V to 5.5V
Extended (E):TA = -40°C to +125°C VCC = 2.5V to 5.5V
AC CHARACTERISTICS
Param.
Symbol
No.
Characteristic
1
FCLK
Clock Frequency
2
TCSS
CS Setup Time
3
TCSH
CS Hold Time
4
TCSD
CS Disable Time
5
Tsu
Data Setup Time
6
THD
Data Hold Time
7
TR
CLK Rise Time
8
TF
CLK Fall Time
9
THI
Clock High Time
Min.
Max.
Units
Conditions
—
20
MHz
4.5V VCC 5.5V (I)
—
10
MHz
2.5V VCC 5.5V (I, E)
25
—
ns
4.5V VCC 5.5V (I)
50
—
ns
2.5V VCC 5.5V (I, E)
50
—
ns
4.5V VCC 5.5V (I)
100
—
ns
2.5V VCC 5.5V (I, E)
50
—
ns
5
—
ns
4.5V VCC 5.5V (I)
10
—
ns
2.5V VCC 5.5V (I, E)
10
—
ns
4.5V VCC 5.5V (I)
20
—
ns
2.5V VCC 5.5V (I, E)
—
20
ns
Note 1
—
20
ns
Note 1
25
—
ns
4.5V VCC 5.5V (I)
50
—
ns
2.5V VCC 5.5V (I, E)
25
—
ns
4.5V VCC 5.5V (I)
2.5V VCC 5.5V (I, E)
10
TLO
Clock Low Time
50
—
ns
11
TCLD
Clock Delay Time
50
—
ns
12
TCLE
Clock Enable Time
50
—
ns
—
25
ns
4.5V VCC 5.5V (I)
—
50
ns
2.5V VCC 5.5V (I, E)
0
—
ns
Note 1
—
25
ns
4.5V VCC 5.5V (I)
—
50
ns
2.5V VCC 5.5V (I, E)
10
—
ns
4.5V VCC 5.5V (I)
20
—
ns
2.5V VCC 5.5V (I, E)
10
—
ns
4.5V VCC 5.5V (I)
20
—
ns
2.5V VCC 5.5V (I, E)
—
15
ns
4.5V VCC 5.5V (I)
—
30
ns
2.5V VCC 5.5V (I, E)
(Note 1)
—
15
ns
4.5V VCC 5.5V (I)
—
30
ns
2.5V VCC 5.5V (I, E)
µs
13
TV
Output Valid from Clock Low
14
THO
Output Hold Time
15
TDIS
Output Disable Time
16
THS
HOLD Setup Time
17
THH
HOLD Hold Time
18
THZ
HOLD Low to Output High-Z
19
THV
HOLD High to Output Valid
20
TREL
CS High to Standby Mode
—
100
21
TPD
CS High to Deep Power-Down
—
100
µs
22
TCE
Chip Erase Cycle Time
—
10
ms
23
TSE
Sector Erase Cycle Time
—
10
ms
Note 1:
2:
This parameter is periodically sampled and not 100% tested.
This parameter is not tested but established by characterization and qualification.
2007-2021 Microchip Technology Inc.
DS20002064E-page 3
25LC1024
TABLE 1-2:
AC CHARACTERISTICS (CONTINUED)
Industrial (I): TA = -40°C to +85°C VCC = 2.5V to 5.5V
Extended (E):TA = -40°C to +125°C VCC = 2.5V to 5.5V
AC CHARACTERISTICS
Param.
Symbol
No.
24
TWC
25
Note 1:
2:
Characteristic
Min.
Max.
Units
Conditions
Internal Write Cycle Time
—
6
ms
Byte or Page mode and Page
Erase
Endurance
1M
—
E/W Page mode, +25°C, 5.5V
Cycles (Note 2)
This parameter is periodically sampled and not 100% tested.
This parameter is not tested but established by characterization and qualification.
TABLE 1-3:
AC TEST CONDITIONS
AC Waveform
VLO = 0.2V
—
VH I = VCC - 0.2V
Note 1
VH I = 4.0V
Note 2
CL = 30 pF
—
Timing Measurement Reference Level
Input
0.5 VCC
Output
Note 1:
2:
0.5 VCC
For VCC 4.0V
For VCC > 4.0V
DS20002064E-page 4
2007-2021 Microchip Technology Inc.
25LC1024
FIGURE 1-1:
HOLD TIMING
CS
17
16
17
16
SCK
18
SO
n+2
SI
n+2
n+1
n
19
High-Impedance
n
5
Don’t Care
n+1
n-1
n
n
n-1
HOLD
FIGURE 1-2:
SERIAL INPUT TIMING
4
CS
2
7
Mode 1,1
3
8
12
11
SCK Mode 0,0
5
SI
6
MSb in
LSb in
High-Impedance
SO
FIGURE 1-3:
SERIAL OUTPUT TIMING
CS
9
3
10
Mode 1,1
SCK
Mode 0,0
13
SO
14
MSb out
SI
2007-2021 Microchip Technology Inc.
15
LSb out
Don’t Care
DS20002064E-page 5
25LC1024
2.0
PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 2-1.
TABLE 2-1:
PIN FUNCTION TABLE
Name
8-Lead PDIP
1
1
1
Chip Select Input
2
2
2
Serial Data Output
WP
3
3
3
Write-Protect Pin
VSS
4
4
4
Ground
SI
5
5
5
Serial Data Input
SCK
6
6
6
Serial Clock Input
HOLD
7
7
7
Hold Input
VCC
8
8
8
Supply Voltage
The exposed pad on DFN-S package can be connected to VSS or left floating.
Chip Select (CS)
Serial Output (SO)
The SO pin is used to transfer data out of the
25LC1024. During a read cycle, data are shifted out on
this pin after the falling edge of the serial clock.
2.3
Function
CS
A low level on this pin selects the device. A high level
deselects the device and forces it into Standby mode.
However, a programming cycle which is already
initiated or in progress will be completed, regardless of
the CS input signal. If CS is brought high during a
program cycle, the device will go into Standby mode as
soon as the programming cycle is complete. When the
device is deselected, SO goes to the high-impedance
state, allowing multiple parts to share the same SPI
bus. A low-to-high transition on CS after a valid write
sequence initiates an internal write cycle. After
power-up, a low level on CS is required prior to any
sequence being initiated.
2.2
8-Lead SOIJ
SO
Note 1:
2.1
8-Lead DFN-S(1)
Write-Protect (WP)
This pin is used in conjunction with the WPEN bit in the
STATUS register to prohibit writes to the nonvolatile
bits in the STATUS register. When WP is low and
WPEN is high, writing to the nonvolatile bits in the
STATUS register is disabled. All other operations
function normally. When WP is high, all functions,
including writes to the nonvolatile bits in the STATUS
register, operate normally. If the WPEN bit is set, WP
low during a STATUS register write sequence will
disable writing to the STATUS register. If an internal
write cycle has already begun, WP going low will have
no effect on the write.
The WP pin function is blocked when the WPEN bit in
the STATUS register is low. This allows the user to
install the 25LC1024 in a system with WP pin grounded
and still be able to write to the STATUS register.
DS20002064E-page 6
The WP pin functions will be enabled when the WPEN
bit is set high.
2.4
Serial Input (SI)
The SI pin is used to transfer data into the device. It
receives instructions, addresses and data. Data are
latched on the rising edge of the serial clock.
2.5
Serial Clock (SCK)
The SCK is used to synchronize the communication
between a host and the 25LC1024. Instructions,
addresses or data present on the SI pin are latched on
the rising edge of the clock input, while data on the SO
pin are updated after the falling edge of the clock input.
2.6
Hold (HOLD)
The HOLD pin is used to suspend transmission to the
25LC1024 while in the middle of a serial sequence
without having to retransmit the entire sequence again.
It must be held high any time this function is not being
used. Once the device is selected and a serial
sequence is underway, the HOLD pin may be pulled
low to pause further serial communication without
resetting the serial sequence.
The HOLD pin must be brought low while SCK is low,
otherwise the HOLD function will not be invoked until
the next SCK high-to-low transition. The 25LC1024
must remain selected during this sequence. The SI and
SCK levels are “don’t cares” during the time the device
is paused and any transitions on these pins will be
ignored. To resume serial communication, HOLD must
be brought high while the SCK pin is low, otherwise
serial communication will not be resumed until the next
SCK high-to-low transition.
The SO line will tri-state immediately upon a
high-to-low transition of the HOLD pin and will begin
outputting again immediately upon a subsequent
low-to-high transition of the HOLD pin, independent of
the state of SCK.
2007-2021 Microchip Technology Inc.
25LC1024
3.0
FUNCTIONAL DESCRIPTION
3.1
Principles of Operation
BLOCK DIAGRAM
STATUS
Register
The 25LC1024 is a 131,072-byte Serial EEPROM
designed to interface directly with the Serial Peripheral
Interface (SPI) port of many of today’s popular
microcontroller families, including Microchip’s PIC®
microcontrollers. It may also interface with microcontrollers that do not have a built-in SPI port by using
discrete I/O lines programmed properly in firmware to
match the SPI protocol.
The 25LC1024 contains an 8-bit instruction register.
The device is accessed via the SI pin, with data being
clocked in on the rising edge of SCK. The CS pin must
be low and the HOLD pin must be high for the entire
operation.
Table 3-1 contains a list of the possible instruction
bytes and format for device operation. All instructions,
addresses and data are transferred MSb first, LSb last.
I/O Control
Logic
Memory
Control
Logic
EEPROM
Array
X
Dec
Page Latches
SI
SO
Y Decoder
CS
SCK
Sense Amp.
R/W Control
HOLD
WP
Data (SI) is sampled on the first rising edge of SCK
after CS goes low. If the clock line is shared with other
peripheral devices on the SPI bus, the user can assert
the HOLD input and place the 25LC1024 in ‘HOLD’
mode. After releasing the HOLD pin, operation will
resume from the point when the HOLD was asserted.
TABLE 3-1:
HV Generator
VCC
VSS
INSTRUCTION SET
Instruction Name
Instruction Format
READ
0000 0011
Read data from memory array beginning at selected address
WRITE
0000 0010
Write data to memory array beginning at selected address
WREN
0000 0110
Set the write enable latch (enable write operations)
WRDI
0000 0100
Reset the write enable latch (disable write operations)
RDSR
0000 0101
Read STATUS register
WRSR
0000 0001
Write STATUS register
PE
0100 0010
Page Erase – erase one page in memory array
SE
1101 1000
Sector Erase – erase one sector in memory array
CE
1100 0111
Chip Erase – erase all sectors in memory array
RDID
1010 1011
Release from Deep power-down and read electronic signature
DPD
1011 1001
Deep Power-Down mode
2007-2021 Microchip Technology Inc.
Description
DS20002064E-page 7
25LC1024
3.2
Read Sequence
The device is selected by pulling CS low. The 8-bit
READ instruction is transmitted to the 25LC1024
followed by the 24-bit address, with seven MSBs of the
address being “don’t care” bits. After the correct READ
instruction and address are sent, the data stored in the
memory at the selected address is shifted out on the
SO pin.
The data stored in the memory at the next address can
be read sequentially by continuing to provide clock
pulses. The internal Address Pointer is automatically
incremented to the next higher address after each byte
of data is shifted out. When the highest address is
reached (1FFFFh), the address counter rolls over to
address, 00000h, allowing the read cycle to be continued indefinitely. The read operation is terminated by
raising the CS pin (Figure 3-1).
FIGURE 3-1:
READ SEQUENCE
CS
0
1
2
3
4
5
6
7
8
9 10 11
29 30 31 32 33 34 35 36 37 38 39
SCK
Instruction
SI
0
0
0
0
0
24-bit Address
0
1
1 23 22 21 20
2
1
0
Data Out
High-Impedance
SO
DS20002064E-page 8
7
6
5
4
3
2
1
0
2007-2021 Microchip Technology Inc.
25LC1024
3.3
Write Sequence
Note:
Page write operations are limited to
writing bytes within a single physical page,
regardless of the number of bytes
actually being written. Physical page
boundaries start at addresses that are
integer multiples of the page buffer size
(or ‘page size’) and end at addresses that
are integer multiples of page size – 1. If a
Page Write command attempts to write
across a physical page boundary, the
result is that the data wrap around to the
beginning of the current page (overwriting
data previously stored there), instead of
being written to the next page as might be
expected. It is therefore necessary for the
application software to prevent page write
operations that would attempt to cross a
page boundary.
Prior to any attempt to write data to the 25LC1024, the
write enable latch must be set by issuing the WREN
instruction (Figure 3-4). This is done by setting CS low
and then clocking out the proper instruction into the
25LC1024. After all eight bits of the instruction are
transmitted, the CS must be brought high to set the
write enable latch. If the write operation is initiated
immediately after the WREN instruction without CS
being brought high, the data will not be written to the
array because the write enable latch will not have been
properly set.
A write sequence includes an automatic, self-timed
erase cycle. It is not required to erase any portion of the
memory prior to issuing a write command.
Once the write enable latch is set, the user may
proceed by setting the CS low, issuing a WRITE instruction, followed by the 24-bit address, with seven MSBs
of the address being “don’t care” bits, and then the data
to be written. Up to 256 bytes of data can be sent to the
device before a write cycle is necessary. The only
restriction is that all of the bytes must reside in the
same page.
Note:
When doing a write of less than 256 bytes,
the data in the rest of the page are
refreshed along with the data bytes being
written. This will force the entire page to
endure a write cycle and for this reason
endurance is specified per page.
FIGURE 3-2:
For the data to be actually written to the array, the CS
must be brought high after the Least Significant bit (D0)
of the nth data byte has been clocked in. If CS is
brought high at any other time, the write operation will
not be completed. Refer to Figure 3-2 and Figure 3-3
for more detailed illustrations on the byte write
sequence and the page write sequence, respectively.
While the write is in progress, the STATUS register may
be read to check the status of the WPEN, WIP, WEL,
BP1 and BP0 bits (Figure 3-6). A read attempt of a
memory array location will not be possible during a
write cycle. When the write cycle is completed, the
write enable latch is reset.
BYTE WRITE SEQUENCE
CS
(1)
TWC
0
1
2
3
4
5
6
7
8
9 10 11
29 30 31 32 33 34 35 36 37 38 39
SCK
Instruction
SI
0
0
0
0
0
24-bit Address
0
1
0 23 22 21 20
Data Byte
2
1
0
7
6
5
4
3
2
1
0
High-Impedance
SO
Note 1: This sequence initiates a self-timed internal write cycle on the rising edge of CS after a valid sequence.
2007-2021 Microchip Technology Inc.
DS20002064E-page 9
25LC1024
FIGURE 3-3:
PAGE WRITE SEQUENCE
CS
0
1
2
3
4
5
6
7
8
9 10 11
29 30 31 32 33 34 35 36 37 38 39
SCK
Instruction
SI
0
0
0
0
0
24-bit Address
0 1
0 23 22 21 20
Data Byte 1
2
1
0
7
6
5
4
3
2
1
0
CS
(1)
TWC
40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
SCK
Data Byte 2
SI
7
6
5
4
3
2
Data Byte n (256 max)
Data Byte 3
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Note 1: This sequence initiates a self-timed internal write cycle on the rising edge of CS after a valid sequence.
DS20002064E-page 10
2007-2021 Microchip Technology Inc.
25LC1024
3.4
Write Enable (WREN) and Write
Disable (WRDI)
The following is a list of conditions under which the
write enable latch will be reset:
•
•
•
•
•
•
•
The 25LC1024 contains a write enable latch. See
Table 3-4 for the Write-Protect Functionality Matrix.
This latch must be set before any write operation will be
completed internally. The WREN instruction will set the
latch, and the WRDI will reset the latch.
FIGURE 3-4:
Power-up
WRDI instruction successfully executed
WRSR instruction successfully executed
WRITE instruction successfully executed
PE instruction successfully executed
SE instruction successfully executed
CE instruction successfully executed
WRITE ENABLE SEQUENCE (WREN)
CS
0
1
2
3
4
5
6
7
SCK
0
SI
0
0
0
1
1
0
High-Impedance
SO
FIGURE 3-5:
0
WRITE DISABLE SEQUENCE (WRDI)
CS
0
1
2
3
4
5
6
7
SCK
SI
0
0
0
0
0
1
10
0
High-Impedance
SO
2007-2021 Microchip Technology Inc.
DS20002064E-page 11
25LC1024
3.5
Read STATUS Register Instruction
(RDSR)
The Write Enable Latch (WEL) bit indicates the status
of the write enable latch and is read-only. When set to
a ‘1’, the latch allows writes to the array, when set to
a ‘0’, the latch prohibits writes to the array. The state of
this bit can always be updated via the WREN or WRDI
commands regardless of the state of write protection
on the STATUS register. These commands are shown
in Figure 3-4 and Figure 3-5.
The Read STATUS Register instruction (RDSR) provides access to the STATUS register. The STATUS register may be read at any time, even during a write cycle.
The STATUS register is formatted as follows:
TABLE 3-2:
The Block Protection (BP0 and BP1) bits indicate
which blocks are currently write-protected. These bits
are set by the user issuing the WRSR instruction. These
bits are nonvolatile and are shown in Table 3-3.
STATUS REGISTER
7
6
5
4
3
2
1
0
W/R
–
–
–
W/R
W/R
R
R
WPEN
X
X
X
BP1
BP0
WEL
WIP
Note 1:
W/R = writable/readable. R = read-only.
See Figure 3-6 for the RDSR timing sequence.
The Write-In-Process (WIP) bit indicates whether the
25LC1024 is busy with a write operation. When set to
a ‘1’, a write is in progress, when set to a ‘0’, no write
is in progress. This bit is read-only.
FIGURE 3-6:
READ STATUS REGISTER TIMING SEQUENCE (RDSR)
CS
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
1
0
SCK
Instruction
SI
0
0
0
0
0
High-Impedance
SO
DS20002064E-page 12
1
0
1
Data from STATUS register
7
6
5
4
3
2
2007-2021 Microchip Technology Inc.
25LC1024
3.6
Write STATUS Register Instruction
(WRSR)
The Write-Protect Enable (WPEN) bit is a nonvolatile
bit that is available as an enable bit for the WP pin. The
Write-Protect (WP) pin and the Write-Protect Enable
(WPEN) bit in the STATUS register control the
programmable
hardware
write-protect
feature.
Hardware write protection is enabled when WP pin is
low and the WPEN bit is high. Hardware write
protection is disabled when either the WP pin is high or
the WPEN bit is low. When the chip is hardware
write-protected, only writes to nonvolatile bits in the
STATUS register are disabled. See Table 3-4 for a
matrix of functionality on the WPEN bit.
The Write STATUS Register instruction (WRSR) allows
the user to write to the nonvolatile bits in the STATUS
register as shown in Table 3-2. The user is able to
select one of four levels of protection for the array by
writing to the appropriate bits in the STATUS register.
The array is divided up into four segments. The user
has the ability to write-protect none, one, two or all four
of the segments of the array. The partitioning is
controlled as shown in Table 3-3.
See Figure 3-7 for the WRSR timing sequence.
TABLE 3-3:
ARRAY PROTECTION
BP1
BP0
Array Addresses Write-Protected
Array Addresses Unprotected
0
0
none
All (Sectors 0, 1, 2 & 3)
(00000h-1FFFFh)
0
1
Upper 1/4 (Sector 3)
(18000h-1FFFFh)
Lower 3/4 (Sectors 0, 1 & 2)
(00000h-17FFFh)
1
0
Upper 1/2 (Sectors 2 & 3)
(10000h-1FFFFh)
Lower 1/2 (Sectors 0 & 1)
(00000h-0FFFFh)
1
1
All (Sectors 0, 1, 2 & 3)
(00000h-1FFFFh)
none
TABLE 3-4:
WRITE-PROTECT FUNCTIONALITY MATRIX
WEL
(SR bit 1)
WPEN
(SR bit 7)
WP
(pin 3)
Protected Blocks
Unprotected Blocks
STATUS Register
0
x
x
Protected
Protected
Protected
1
0
x
Protected
Writable
Writable
1
1
0 (low)
Protected
Writable
Protected
1
1 (high)
Protected
Writable
Writable
1
Note 1:
x = don’t care
FIGURE 3-7:
WRITE STATUS REGISTER TIMING SEQUENCE (WRSR)
CS
(1)
TWC
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
1
0
SCK
Instruction
SI
0
0
0
0
Data to STATUS register
0
0
0
1
7
6
5
4
3
2
High-Impedance
SO
Note 1: This sequence initiates a self-timed internal write cycle on the rising edge of CS after a valid sequence.
2007-2021 Microchip Technology Inc.
DS20002064E-page 13
25LC1024
3.7
PAGE ERASE
The Page Erase instruction will erase all bits (FFh)
inside the given page. A Write Enable (WREN) instruction must be given prior to attempting a Page Erase.
This is done by setting CS low and then clocking out
the proper instruction into the 25LC1024. After all eight
bits of the instruction are transmitted, the CS must be
brought high to set the write enable latch.
CS must then be driven high after the last bit if the
address or the Page Erase will not execute. Once the
CS is driven high, the self-timed Page Erase cycle is
started. The WIP bit in the STATUS register can be
read to determine when the Page Erase cycle is
complete.
If a Page Erase instruction is given to an address that
has been protected by the Block Protect bits (BP0,
BP1), then the sequence will be aborted and no erase
will occur.
The Page Erase instruction is entered by driving CS
low, followed by the instruction code (Figure 3-8) and
three address bytes. Any address inside the page to
be erased is a valid address.
FIGURE 3-8:
PAGE ERASE SEQUENCE
CS
(1)
TWC
0
1
2
3
4
5
6
7
8
9 10 11
29 30 31
SCK
Instruction
SI
0
1
0
0
0
24-bit Address
0
1
0 23 22 21 20
2
1
0
High-Impedance
SO
Note 1: This sequence initiates a self-timed internal write cycle on the rising edge of CS after a valid sequence.
DS20002064E-page 14
2007-2021 Microchip Technology Inc.
25LC1024
3.8
SECTOR ERASE
The Sector Erase instruction will erase all bits (FFh)
inside the given sector. A Write Enable (WREN) instruction must be given prior to attempting a Sector Erase.
This is done by setting CS low and then clocking out
the proper instruction into the 25LC1024. After all eight
bits of the instruction are transmitted, the CS must be
brought high to set the write enable latch.
CS must then be driven high after the last bit if the
address or the Sector Erase will not execute. Once the
CS is driven high, the self-timed Sector Erase cycle is
started. The WIP bit in the STATUS register can be
read to determine when the Sector Erase cycle is
complete.
If a sector erase instruction is given to an address that
has been protected by the Block Protect bits (BP0,
BP1), then the sequence will be aborted and no erase
will occur.
The Sector Erase instruction is entered by driving CS
low, followed by the instruction code (Figure 3-9) and
three address bytes. Any address inside the sector to
be erased is a valid address.
FIGURE 3-9:
See Table 3-3 for Sector Addressing.
SECTOR ERASE SEQUENCE
CS
TSE
0
1
2
3
4
5
6
7
8
9 10 11
(1)
29 30 31
SCK
Instruction
SI
1
1
0
1
1
24-bit Address
0
0
0 23 22 21 20
2
1
0
High-Impedance
SO
Note 1: This sequence initiates a self-timed internal write cycle on the rising edge of CS after a valid sequence.
3.9
CHIP ERASE
The Chip Erase instruction will erase all bits (FFh) in
the array. A Write Enable (WREN) instruction must be
given prior to executing a Chip Erase. This is done by
setting CS low and then clocking out the proper
instruction into the 25LC1024. After all eight bits of the
instruction are transmitted, the CS must be brought
high to set the write enable latch.
The Chip Erase instruction is entered by driving the
CS low, followed by the instruction code (Figure 3-10)
onto the SI line.
2007-2021 Microchip Technology Inc.
The CS pin must be driven high after the eighth bit of
the instruction code has been given or the Chip Erase
instruction will not be executed. Once the CS pin is
driven high, the self-timed Chip Erase instruction
begins. While the device is executing the Chip Erase
instruction, the WIP bit in the STATUS register can be
read to determine when the Chip Erase instruction is
complete.
The Chip Erase instruction is ignored if either of the
Block Protect bits (BP0, BP1) are not 0, meaning 1/4,
1/2 or all of the array is protected.
DS20002064E-page 15
25LC1024
FIGURE 3-10:
CHIP ERASE SEQUENCE
CS
TCE
0
1
2
3
4
5
6
(1)
7
SCK
1
SI
1
0
0
0
1
1
1
High-Impedance
SO
Note 1: This sequence initiates a self-timed internal write cycle on the rising edge of CS after a valid sequence.
3.10
DEEP POWER-DOWN MODE
Deep Power-Down mode of the 25LC1024 is its lowest
power consumption state. The device will not respond
to any of the Read or Write commands while in Deep
Power-Down mode and therefore it can be used as an
additional software write protection feature.
All instructions given during Deep Power-Down mode
are ignored except the Read Electronic Signature
Command (RDID). The RDID command will release
the device from Deep power-down and output the
electronic signature on the SO pin; then it returns the
device to Standby mode after delay (TREL).
The Deep Power-Down mode is entered by driving CS
low, followed by the instruction code (Figure 3-11) onto
the SI line, followed by driving CS high.
Deep Power-Down mode automatically releases at
device power-down. Once power is restored to the
device, it will power-up in the Standby mode.
If the CS pin is not driven high after the eighth bit of the
instruction code has been given, the device will not
execute Deep power-down. Once the CS line is driven
high, there is a delay (TDP) before the current settles
to its lowest consumption.
FIGURE 3-11:
DEEP POWER-DOWN SEQUENCE
CS
0
1
2
3
4
5
6
7
SCK
SI
1
0
1
1
1
0
0
1
High-Impedance
SO
DS20002064E-page 16
2007-2021 Microchip Technology Inc.
25LC1024
3.11
RELEASE FROM DEEP
POWER-DOWN AND READ
ELECTRONIC SIGNATURE
Release from Deep Power-Down mode and Read
Electronic Signature is entered by driving CS low,
followed by the RDID instruction code (Figure 3-12)
and then a dummy address of 24 bits (A23-A0). After
the last bit of the dummy address is clocked in, the
8-bit electronic signature is clocked out on the SO
pin.
Once the device has entered Deep Power-Down
mode, all instructions are ignored except the release
from Deep Power-down and Read Electronic Signature command. This command can also be used when
the device is not in Deep Power-down to read the electronic signature out on the SO pin unless another command is being executed such as Erase, Program or
Write STATUS register.
FIGURE 3-12:
After the signature has been read out at least once,
the sequence can be terminated by driving CS high.
The device will then return to Standby mode and will
wait to be selected so it can be given new instructions.
If additional clock cycles are sent after the electronic
signature has been read once, it will continue to output
the signature on the SO line until the sequence is
terminated.
RELEASE FROM DEEP POWER-DOWN AND READ ELECTRONIC SIGNATURE
CS
0
1
2
3
4
5
6
7
8
9 10 11
29 30 31 32 33 34 35 36 37 38 39
SCK
Instruction
SI
1
0
1
0
1
24-bit Address
0
1
1 23 22 21 20
2
1
0
Electronic Signature Out
High-Impedance
7
SO
0
6
5
4
3
2
1
0
0
1
0
1
0
0
1
Manufacturers ID 0x29
Driving CS high after the 8-bit RDID command, but
before the Electronic Signature has been transmitted,
will still ensure the device will be taken out of Deep
Power-Down mode. However, there is a delay TREL
that occurs before the device returns to Standby mode
(ICCS), as shown in Figure 3-13.
FIGURE 3-13:
RELEASE FROM DEEP POWER-DOWN AND READ ELECTRONIC SIGNATURE
CS
0
1
2
3
4
5
6
0
1
7
TREL
SCK
Instruction
SI
1
0
1
0
1
1
High-Impedance
SO
2007-2021 Microchip Technology Inc.
DS20002064E-page 17
25LC1024
4.0
DATA PROTECTION
The following protection has been implemented to
prevent inadvertent writes to the array:
• The write enable latch is reset on power-up
• A write enable instruction must be issued to set
the write enable latch
• After a byte write, page write or STATUS register
write, the write enable latch is reset
• CS must be set high after the proper number of
clock cycles to start an internal write cycle
• Access to the array during an internal write cycle
is ignored and programming is continued
5.0
POWER-ON STATE
The 25LC1024 powers on in the following state:
• The device is in low-power Standby mode
(CS = 1)
• The write enable latch is reset
• SO is in high-impedance state
A high-to-low level transition on CS is required to enter
active state
DS20002064E-page 18
2007-2021 Microchip Technology Inc.
25LC1024
6.0
PACKAGING INFORMATION
6.1
Package Marking Information
8-Lead DFN-S
Example
XXXXXXX
T/XXXXX
YYWW
NNN
5LC1024
I/MF e3
2128
13F
8-Lead PDIP
Example
XXXXXXXX
T/XXXNNN
YYWW
25LC1024
I/P e3 13F
2128
8-Lead SOIJ
Example
XXXXXXXX
T/XXXXXX
YYWWNNN
25LC1024
I/SM e3
212813F
1st Line Marking Codes
Device
25LC1024
Legend: XX...X
T
Y
YY
WW
NNN
e3
DFN-S
PDIP
SOIJ
5LC1024
25LC1024
25LC1024
Part number or part number code
Temperature (I, E)
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code (2 characters for small packages)
RoHS compliant JEDEC designator for Matte Tin (Sn)
Note:
For very small packages with no room for the RoHS compliant JEDEC designator
e3 , the marking will only appear on the outer carton or reel label.
Note:
In the event the full Microchip part number cannot be marked on one line, it will be
carried over to the next line, thus limiting the number of available characters for
customer-specific information.
2007-2021 Microchip Technology Inc.
DS20002064E-page 19
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2007-2021 Microchip Technology Inc.
25LC1024
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