25AA128/25LC128
128K SPI Bus Serial EEPROM
Device Selection Table
VCC Range
Page Size
25AA128
1.8V-5.5V
64 Byte
I
MF, P, SN, SM, ST
25LC128
2.5V-5.5V
64 Byte
I, E
MF, P, SN, SM, ST
Part Number
Features
Temp. Ranges
Packages
Pin Function Table
Name
• Maximum Clock: 10 MHz
• Low-Power CMOS Technology:
- Write current (maximum): 5 mA at 5.5V,
10 MHz
- Read current: 5 mA at 5.5V, 10 MHz
- Standby current: 5 µA at 5.5V
• 16,384 x 8-Bit Organization
• 64-Byte Page
• Self-Timed Erase and Write Cycles
(5 ms maximum)
• Block Write Protection:
- Protect none, 1/4, 1/2 or all of array
• Built-In Write Protection:
- Power-on/off data protection circuitry
- Write enable latch
- Write-protect pin
• Sequential Read
• High Reliability:
- Endurance: 1,000,000 erase/write cycles
- Data retention: >200 years
- ESD protection: >4000V
• RoHS Compliant
• Temperature Ranges;
- Industrial (I):
-40C to +85C
- Extended (E):
-40°C to +125°C
Function
CS
Chip Select Input
SO
Serial Data Output
WP
Write-Protect
VSS
Ground
SI
Serial Data Input
SCK
Serial Clock Input
Hold Input
HOLD
Supply Voltage
VCC
Description
The Microchip Technology Inc. 25XX128(1) is a
128 Kbit Serial Electrically Erasable PROM. The memory is accessed via a simple Serial Peripheral Interface
(SPI) compatible serial bus. The bus signals required
are a clock input (SCK) plus separate data in (SI) and
data out (SO) lines. Access to the device is controlled
through a Chip Select (CS) input.
Communication to the device can be paused via the
hold pin (HOLD). While the device is paused,
transitions on its inputs will be ignored, with the
exception of Chip Select, allowing the host to service
higher priority interrupts.
Note 1: 25XX128 is used in this document as a
generic part number for the 25AA128/
25LC128 devices.
• Automotive AEC-Q100 Qualified
Packages
• 8-Lead DFN, 8-Lead PDIP, 8-Lead SOIC,
8-Lead SOIJ and 8-Lead TSSOP
8-Lead DFN
(Top View)
8-Lead PDIP/SOIC/SOIJ
(Top View)
CS 1
8
VCC
CS
11
88
VCC
SO 2
WP 3
VSS 4
7
HOLD
SO
22
77
SCK
SI
WP
33
66
HOLD
SCK
VSS
44
55
SI
6
5
2003-2019 Microchip Technology Inc.
8-Lead TSSOP
(Top View)
CS
SO
WP
VSS
1
2
3
4
8
7
6
5
8-Lead X-Rotated TSSOP
(Top View)
VCC
HOLD
SCK
SI
HOLD
VCC
CS
SO
1
2
3
4
8
7
6
5
SCK
SI
VSS
WP
DS20001831F-page 1
25AA128/25LC128
1.0
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings (†)
VCC.............................................................................................................................................................................6.5V
All inputs and outputs w.r.t. VSS ..........................................................................................................-0.6V to VCC +1.0V
Storage temperature ................................................................................................................................. -65°C to 150°C
Ambient temperature under bias............................................................................................................... -40°C to 125°C
ESD protection on all pins.......................................................................................................................................... 4 kV
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for an
extended period of time may affect device reliability.
TABLE 1-1:
DC CHARACTERISTICS
Param.
Symbol
No.
D1
TA = -40°C to +85°C
TA = -40°C to +125°C
Industrial (I):
Extended (E):
DC CHARACTERISTICS
Characteristic
Min.
Max.
Units
VCC = 1.8V to 5.5V
VCC = 2.5V to 5.5V
Conditions
VIH
High-Level Input Voltage
0.7 VCC
VCC+1
V
Low-Level Input Voltage
-0.3
0.3 VCC
V
VCC2.7V
-0.3
0.2 VCC
V
VCC < 2.7V
—
0.4
V
IOL = 2.1 mA
—
0.2
V
IOL = 1.0 mA, VCC < 2.5V
VCC -0.5
—
V
IOH = -400 µA
D2
VIL1
D3
VIL2
D4
VOL
D5
VOL
D6
VOH
D7
ILI
Input Leakage Current
—
±1
µA
CS = VCC, VIN = VSS or VCC
D8
ILO
Output Leakage Current
—
±1
µA
CS = VCC, VOUT = VSS or VCC
D9
CINT
Internal Capacitance
(all inputs and outputs)
—
7
pF
TA = 25°C, CLK = 1.0 MHz,
VCC = 5.0V (Note)
—
5
mA
VCC = 5.5V, FCLK = 10.0 MHz,
SO = Open
—
2.5
mA
VCC = 2.5V, FCLK = 5.0 MHz
SO = Open
D10
D11
D12
Note:
Low-Level Output Voltage
High-Level Output Voltage
ICC Read Operating Current
ICC Write Operating Current
ICCS
Standby Current
—
5
mA
VCC = 5.5V
—
3
mA
VCC = 2.5V
—
5
µA
CS = VCC = 5.5V, Inputs tied to VCC
or VSS, 125°C
—
1
µA
CS = VCC = 5.5V, Inputs tied to VCC
or VSS, 85°C
This parameter is periodically sampled and not 100% tested.
2003-2019 Microchip Technology Inc.
DS20001831F-page 2
25AA128/25LC128
TABLE 1-2:
AC CHARACTERISTICS
Param.
Symbol
No.
1
FCLK
TCSS
2
3
TCSH
TA = -40°C to +85°C
TA = -40°C to +125°C
Industrial (I):
Extended (E):
AC CHARACTERISTICS
Characteristic
Clock Frequency
CS Setup Time
CS Hold Time
VCC = 1.8V to 5.5V
VCC = 2.5V to 5.5V
Min.
Max.
Units
Conditions
—
10
MHz
4.5V Vcc 5.5V
—
5
MHz
2.5V Vcc 4.5V
—
3
MHz
1.8V Vcc 2.5V
50
—
ns
4.5V Vcc 5.5V
100
—
ns
2.5V Vcc 4.5V
150
—
ns
1.8V Vcc 2.5V
100
—
ns
4.5V Vcc 5.5V
200
—
ns
2.5V Vcc 4.5V
250
—
ns
1.8V Vcc 2.5V
4
TCSD
CS Disable Time
50
—
ns
5
TSU
Data Setup Time
10
—
ns
4.5V Vcc 5.5V
20
—
ns
2.5V Vcc 4.5V
30
—
ns
1.8V Vcc 2.5V
20
—
ns
4.5V Vcc 5.5V
40
—
ns
2.5V Vcc 4.5V
6
THD
Data Hold Time
50
—
ns
1.8V Vcc 2.5V
7
TR
CLK Rise Time
—
100
ns
Note 1
8
TF
CLK Fall Time
—
100
ns
Note 1
9
THI
Clock High Time
50
—
ns
4.5V Vcc 5.5V
100
—
ns
2.5V Vcc 4.5V
150
—
ns
1.8V Vcc 2.5V
50
—
ns
4.5V Vcc 5.5V
100
—
ns
2.5V Vcc 4.5V
1.8V Vcc 2.5V
10
TLO
Clock Low Time
150
—
ns
11
TCLD
Clock Delay Time
50
—
ns
12
TCLE
Clock Enable Time
50
—
ns
13
TV
Output Valid from Clock
Low
—
50
ns
4.5V Vcc 5.5V
—
100
ns
2.5V Vcc 4.5V
—
160
ns
1.8V Vcc 2.5V
14
THO
Output Hold Time
0
—
ns
Note 1
15
TDIS
Output Disable Time
—
40
ns
4.5V Vcc 5.5V (Note 1)
—
80
ns
2.5V Vcc 4.5V (Note 1)
—
160
ns
1.8V Vcc 2.5V (Note 1)
Note 1:
2:
3:
This parameter is periodically sampled and not 100% tested.
TWC begins on the rising edge of CS after a valid write sequence and ends when the internal write cycle is
complete.
This parameter is not tested but ensured by characterization. For endurance estimates in a specific
application, please consult the Total Endurance™ Model which can be obtained from Microchip’s website:
www.microchip.com.
2003-2019 Microchip Technology Inc.
DS20001831F-page 3
25AA128/25LC128
TABLE 1-2:
AC CHARACTERISTICS (CONTINUED)
Param.
Symbol
No.
16
THS
17
THH
THZ
18
19
THV
20
TWC
21
Characteristic
HOLD Setup Time
HOLD Hold Time
HOLD Low to Output
High-Z
HOLD High to Output
Valid
VCC = 1.8V to 5.5V
VCC = 2.5V to 5.5V
Min.
Max.
Units
Conditions
20
—
ns
4.5V Vcc 5.5V
40
—
ns
2.5V Vcc 4.5V
80
—
ns
1.8V Vcc 2.5V
20
—
ns
4.5V Vcc 5.5V
40
—
ns
2.5V Vcc 4.5V
80
—
ns
1.8V Vcc 2.5V
—
30
ns
4.5V Vcc 5.5V (Note 1)
—
60
ns
2.5V Vcc 4.5V (Note 1)
—
160
ns
1.8V Vcc 2.5V (Note 1)
—
30
ns
4.5V Vcc 5.5V
—
60
ns
2.5V Vcc 4.5V
—
160
ns
1.8V Vcc 2.5V
—
5
ms
Note 2
1,000,000
—
Internal Write Cycle Time
Endurance
Note 1:
2:
TA = -40°C to +85°C
TA = -40°C to +125°C
Industrial (I):
Extended (E):
AC CHARACTERISTICS
E/W Page mode, 25°C, VCC = 5.5V
Cycles (Note 3)
This parameter is periodically sampled and not 100% tested.
TWC begins on the rising edge of CS after a valid write sequence and ends when the internal write cycle is
complete.
This parameter is not tested but ensured by characterization. For endurance estimates in a specific
application, please consult the Total Endurance™ Model which can be obtained from Microchip’s website:
www.microchip.com.
3:
TABLE 1-1:
AC TEST CONDITIONS
AC Waveform:
VLO = 0.2V
VHI = VCC - 0.2V
VHI
= 4.0V
Note 1
Note 2
CL = 50 pF
Timing Measurement Reference Level
Input
0.5 VCC
Output
Note 1:
2:
0.5 VCC
For VCC 4.0V
For VCC > 4.0V
2003-2019 Microchip Technology Inc.
DS20001831F-page 4
25AA128/25LC128
FIGURE 1-1:
HOLD TIMING
CS
17
16
17
16
SCK
18
SO
n+2
SI
n+2
n+1
n
19
High-Impedance
n
5
Don’t Care
n+1
n-1
n
n
n-1
HOLD
FIGURE 1-2:
SERIAL INPUT TIMING
4
CS
2
7
Mode 1,1
3
8
12
11
SCK Mode 0,0
5
SI
6
MSB in
LSB in
High-Impedance
SO
FIGURE 1-3:
SERIAL OUTPUT TIMING
CS
9
3
10
Mode 1,1
SCK
Mode 0,0
13
SO
14
MSB out
SI
2003-2019 Microchip Technology Inc.
15
LSB out
Don’t Care
DS20001831F-page 5
25AA128/25LC128
2.0
PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 2-1.
TABLE 2-1:
Name
CS
PIN FUNCTION TABLE
DFN(1)
PDIP
SOIC
1
1
1
SOIJ TSSOP
1
1
X-Rotated TSSOP
3
Function
Chip Select Input
SO
2
2
2
2
2
4
Serial Data Output
WP
3
3
3
3
3
5
Write-Protect Pin
VSS
4
4
4
4
4
6
Ground
SI
5
5
5
5
5
7
Serial Data Input
SCK
6
6
6
6
6
8
Serial Clock Input
HOLD
7
7
7
7
7
1
Hold Input
8
8
8
8
8
2
Supply Voltage
VCC
Note 1:
2.1
The exposed pad on the DFN package can be connected to VSS or left floating.
Chip Select (CS)
A low level on this pin selects the device. A high level
deselects the device and forces it into Standby mode.
However, a programming cycle which is already
initiated or in progress will be completed, regardless of
the CS input signal. If CS is brought high during a
program cycle, the device will go into Standby mode as
soon as the programming cycle is complete. When the
device is deselected, SO goes to the high-impedance
state, allowing multiple parts to share the same SPI
bus. A low-to-high transition on CS after a valid write
sequence initiates an internal write cycle. After powerup, a low level on CS is required prior to any sequence
being initiated.
2.2
Serial Output (SO)
The SO pin is used to transfer data out of the 25XX128.
During a read cycle, data is shifted out on this pin after
the falling edge of the serial clock.
2.3
Write-Protect (WP)
This pin is used in conjunction with the WPEN bit in the
STATUS register to prohibit writes to the nonvolatile
bits in the STATUS register. When WP is low and
WPEN is high, writing to the nonvolatile bits in the
STATUS register is disabled. All other operations
function normally. When WP is high, all functions,
including writes to the nonvolatile bits in the STATUS
register, operate normally. If the WPEN bit is set, WP
low during a STATUS register write sequence will disable writing to the STATUS register. If an internal write
cycle has already begun, WP going low will have no
effect on the write.
The WP pin function is blocked when the WPEN bit in
the STATUS register is low. This allows the user to
install the 25XX128 in a system with WP pin grounded
and still be able to write to the STATUS register.
2003-2019 Microchip Technology Inc.
The WP pin functions will be enabled when the WPEN
bit is set high.
2.4
Serial Input (SI)
The SI pin is used to transfer data into the device. It
receives instructions, addresses and data. Data is
latched on the rising edge of the serial clock.
2.5
Serial Clock (SCK)
The SCK is used to synchronize the communication
between a master and the 25XX128. Instructions,
addresses or data present on the SI pin are latched on
the rising edge of the clock input, while data on the SO
pin is updated after the falling edge of the clock input.
2.6
Hold (HOLD)
The HOLD pin is used to suspend transmission to the
25XX128 while in the middle of a serial sequence without having to retransmit the entire sequence again. It
must be held high any time this function is not being
used. Once the device is selected and a serial
sequence is underway, the HOLD pin may be pulled
low to pause further serial communication without
resetting the serial sequence. The HOLD pin must be
brought low while SCK is low, otherwise the HOLD
function will not be invoked until the next SCK high-tolow transition. The 25XX128 must remain selected
during this sequence. The SI, SCK and SO pins are in
a high-impedance state during the time the device is
paused and transitions on these pins will be ignored. To
resume serial communication, HOLD must be brought
high while the SCK pin is low, otherwise serial
communication will not resume. Lowering the HOLD
line at any time will tri-state the SO line.
DS20001831F-page 6
25AA128/25LC128
3.0
FUNCTIONAL DESCRIPTION
3.1
Principles of Operation
The 25AA128/25LC128 is a 16,384 byte Serial
EEPROM designed to interface directly with the Serial
Peripheral Interface (SPI) port of many of today’s popular microcontroller families, including Microchip’s
PIC® microcontrollers. It may also interface with microcontrollers that do not have a built-in SPI port by using
discrete I/O lines programmed properly in firmware to
match the SPI protocol.
The 25AA128/25LC128 contains an 8-bit instruction
register. The device is accessed via the SI pin, with
data being clocked in on the rising edge of SCK. The
CS pin must be low and the HOLD pin must be high for
the entire operation.
Table 3-1 contains a list of the possible instruction
bytes and format for device operation. All instructions,
addresses and data are transferred MSB first, LSB last.
Data (SI) is sampled on the first rising edge of SCK
after CS goes low. If the clock line is shared with other
peripheral devices on the SPI bus, the user can assert
the HOLD input and place the 25AA128/25LC128 in
‘HOLD’ mode. After releasing the HOLD pin, operation
will resume from the point when the HOLD was
asserted.
3.2
Read Sequence
The device is selected by pulling CS low. The 8-bit
READ instruction is transmitted to the 25AA128/
25LC128 followed by the 16-bit address, with two
MSBs of the address being “don’t care” bits. After the
correct READ instruction and address are sent, the data
stored in the memory at the selected address is shifted
out on the SO pin. The data stored in the memory at the
next address can be read sequentially by continuing to
provide clock pulses. The internal Address Pointer is
automatically incremented to the next higher address
after each byte of data is shifted out. When the highest
address is reached (3FFFh), the address counter rolls
over to address 0000h, allowing the read cycle to be
continued indefinitely. The read operation is terminated
by raising the CS pin (Figure 3-1).
2003-2019 Microchip Technology Inc.
3.3
Write Sequence
Prior to any attempt to write data to the 25AA128/
25LC128, the write enable latch must be set by issuing
the WREN instruction (Figure 3-4). This is done by setting CS low and then clocking out the proper instruction
into the 25AA128/25LC128. After all eight bits of the
instruction are transmitted, the CS must be brought
high to set the write enable latch. If the write operation
is initiated immediately after the WREN instruction without CS being brought high, the data will not be written
to the array because the write enable latch will not have
been properly set.
Once the write enable latch is set, the user may
proceed by setting the CS low, issuing a WRITE
instruction, followed by the 16-bit address, with two
MSBs of the address being “don’t care” bits, and then
the data to be written. Up to 64 bytes of data can be
sent to the device before a write cycle is necessary.
The only restriction is that all of the bytes must reside
in the same page.
Note:
Page write operations are limited to
writing bytes within a single physical page,
regardless of the number of bytes
actually being written. Physical page
boundaries start at addresses that are
integer multiples of the page buffer size
(or ‘page size’) and, end at addresses that
are integer multiples of page size – 1. If a
Page Write command attempts to write
across a physical page boundary, the
result is that the data wraps around to the
beginning of the current page (overwriting
data previously stored there), instead of
being written to the next page as might be
expected. It is therefore necessary for the
application software to prevent page write
operations that would attempt to cross a
page boundary.
For the data to be actually written to the array, the CS
must be brought high after the Least Significant bit (D0)
of the nth data byte has been clocked in. If CS is
brought high at any other time, the write operation will
not be completed. Refer to Figure 3-2 and Figure 3-3
for more detailed illustrations on the byte write
sequence and the page write sequence, respectively.
While the write is in progress, the STATUS register may
be read to check the status of the Write-in-Process
(WIP) bit (Figure 3-6). A read attempt of a memory
array location will not be possible during a write cycle.
When the write cycle is completed, the write enable
latch is reset.
DS20001831F-page 7
25AA128/25LC128
BLOCK DIAGRAM
STATUS
Register
HV Generator
Memory
Control
Logic
I/O Control
Logic
EEPROM
Array
X
Dec
Page Latches
SI
SO
Y Decoder
CS
SCK
Sense Amp.
R/W Control
HOLD
WP
VCC
VSS
TABLE 3-1:
INSTRUCTION SET
Instruction Name
Instruction Format
READ
0000 0011
Read data from memory array beginning at selected address
WRITE
0000 0010
Write data to memory array beginning at selected address
WRDI
0000 0100
Reset the write enable latch (disable write operations)
WREN
0000 0110
Set the write enable latch (enable write operations)
RDSR
0000 0101
Read STATUS register
WRSR
0000 0001
Write STATUS register
FIGURE 3-1:
Description
READ SEQUENCE
CS
0
1
2
3
4
5
6
7
8
9 10 11
21 22 23 24 25 26 27 28 29 30 31
SCK
Instruction
SI
0
0
0
0
0
16-bit Address
0
1
1 15 14 13 12
2
1
0
Data Out
High-Impedance
SO
2003-2019 Microchip Technology Inc.
7
6
5
4
3
2
1
0
DS20001831F-page 8
25AA128/25LC128
FIGURE 3-2:
BYTE WRITE SEQUENCE
CS
Twc
0
1
2
3
4
5
6
7
8
9 10 11
21 22 23 24 25 26 27 28 29 30 31
SCK
Instruction
SI
0
0
0
0
0
16-bit Address
0
2
0 15 14 13 12
1
Data Byte
1
0
7
6
5
4
3
2
1
0
High-Impedance
SO
FIGURE 3-3:
PAGE WRITE SEQUENCE
CS
0
1
2
3
4
5
6
7
8
9 10 11
21 22 23 24 25 26 27 28 29 30 31
SCK
Instruction
SI
0
0
0
0
0
16-bit Address
0 1
Data Byte 1
2
0 15 14 13 12
1
0
7
6
5
4
3
2
1
0
CS
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
SCK
Data Byte 2
SI
7
6
5
4
3
2
2003-2019 Microchip Technology Inc.
Data Byte 3
1
0
7
6
5
4
3
2
Data Byte n (64 max)
1
0
7
6
5
4
3
2
1
0
DS20001831F-page 9
25AA128/25LC128
3.4
Write Enable (WREN) and Write
Disable (WRDI)
The following is a list of conditions under which the
write enable latch will be reset:
•
•
•
•
The 25AA128/25LC128 contains a write enable latch.
See Table 3-2 for the write-protect functionality matrix.
This latch must be set before any write operation will be
completed internally. The WREN instruction will set the
latch, and the WRDI will reset the latch.
FIGURE 3-4:
Power-up
WRDI instruction successfully executed
WRSR instruction successfully executed
WRITE instruction successfully executed
WRITE ENABLE SEQUENCE (WREN)
CS
0
1
2
3
4
5
6
7
SCK
0
SI
0
0
0
1
1
0
High-Impedance
SO
FIGURE 3-5:
0
WRITE DISABLE SEQUENCE (WRDI)
CS
0
1
2
3
4
5
6
7
SCK
SI
0
0
0
0
0
1
0
0
High-Impedance
SO
2003-2019 Microchip Technology Inc.
DS20001831F-page 10
25AA128/25LC128
3.5
Read STATUS Register Instruction
(RDSR)
The Write Enable Latch (WEL) bit indicates the status
of the write enable latch and is read-only. When set to
a ‘1’, the latch allows writes to the array, when set to a
‘0’, the latch prohibits writes to the array. The state of
this bit can always be updated via the WREN or WRDI
commands regardless of the state of write protection
on the STATUS register. These commands are shown
in Figure 3-4 and Figure 3-5.
The Read STATUS Register instruction (RDSR)
provides access to the STATUS register. The STATUS
register may be read at any time, even during a write
cycle. The STATUS register is formatted as follows:
TABLE 3-2:
7
W/R
WPEN
Note:
STATUS REGISTER
The Block Protection (BP0 and BP1) bits indicate
which blocks are currently write-protected. These bits
are set by the user issuing the WRSR instruction. These
bits are nonvolatile, and are shown in Table 3-1.
6 5 4
3
2
1
0
– – – W/R W/R
R
R
X X X BP1 BP0 WEL WIP
W/R = writable/readable. R = read-only.
See Figure 3-6 for the RDSR timing sequence.
The Write-In-Process (WIP) bit indicates whether the
25AA128/25LC128 is busy with a write operation.
When set to a ‘1’, a write is in progress, when set to
a ‘0’, no write is in progress. This bit is read-only.
FIGURE 3-6:
READ STATUS REGISTER TIMING SEQUENCE (RDSR)
CS
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
1
0
SCK
Instruction
SI
0
0
0
0
0
High-Impedance
SO
Note:
1
0
1
Data from STATUS Register
7
6
5
4
3
2
Bits 7-1 of the STATUS register are undetermined during a write cycle.
2003-2019 Microchip Technology Inc.
DS20001831F-page 11
25AA128/25LC128
3.6
Write STATUS Register (WRSR)
The Write STATUS Register (WRSR) instruction allows
the user to write to the nonvolatile bits in the STATUS
register as shown in Table 3-2. The user is able to
select one of four levels of protection for the array by
writing to the appropriate bits in the STATUS register.
The array is divided up into four segments. The user
has the ability to write-protect none, one, two, or all four
of the segments of the array. The partitioning is controlled as shown in Table 3-1.
TABLE 3-1:
The Write-Protect Enable (WPEN) bit is a nonvolatile
bit that is available as an enable bit for the WP pin. The
Write-Protect (WP) pin and the Write-Protect Enable
(WPEN) bit in the STATUS register control the
programmable hardware write-protect feature. Hardware write protection is enabled when WP pin is low
and the WPEN bit is high. Hardware write protection is
disabled when either the WP pin is high or the WPEN
bit is low. When the chip is hardware write-protected,
only writes to nonvolatile bits in the STATUS register
are disabled. See Table 3-2 for a matrix of functionality
on the WPEN bit.
ARRAY PROTECTION
Array Addresses
Write-Protected
BP1
BP0
0
0
none
0
1
upper 1/4
(3000h-3FFFh)
1
0
upper 1/2
(2000h-3FFFh)
1
1
all
(0000h-3FFFh)
See Figure 3-7 for the WRSR timing sequence.
FIGURE 3-7:
WRITE STATUS REGISTER TIMING SEQUENCE (WRSR)
CS
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
1
0
SCK
Instruction
SI
0
0
0
0
Data to STATUS Register
0
0
0
1
7
6
5
4
3
2
High-Impedance
SO
Note:
An internal write cycle (TWC) is initiated on the rising edge of CS after a valid write STATUS register
sequence.
2003-2019 Microchip Technology Inc.
DS20001831F-page 12
25AA128/25LC128
3.7
Data Protection
3.8
Power-On State
The following protection has been implemented to
prevent inadvertent writes to the array:
The 25AA128/25LC128 powers on in the following
state:
• The write enable latch is reset on power-up
• A write enable instruction must be issued to set
the write enable latch
• After a byte write, page write or STATUS register
write, the write enable latch is reset
• CS must be set high after the proper number of
clock cycles to start an internal write cycle
• Access to the array during an internal write cycle
is ignored and programming is continued
• The device is in low-power Standby mode
(CS = 1)
• The write enable latch is reset
• SO is in high-impedance state
• A high-to-low-level transition on CS is required to
enter active state
TABLE 3-2:
WRITE-PROTECT FUNCTIONALITY MATRIX
WEL
(SR bit 1)
WPEN
(SR bit 7)
WP
(pin 3)
Protected Blocks
Unprotected Blocks
STATUS Register
0
x
x
Protected
Protected
Protected
1
0
x
Protected
Writable
Writable
1
1
0 (low)
Protected
Writable
Protected
1
1 (high)
Protected
Writable
Writable
1
Note:
x = don’t care
2003-2019 Microchip Technology Inc.
DS20001831F-page 13
25AA128/25LC128
4.0
PACKAGING INFORMATION
4.1
Package Marking Information
8-Lead DFN-S
Example
25LC128
I/MF e3
1934
13F
XXXXXXX
T/XXXXX
YYWW
NNN
8-Lead PDIP (300 mil)
Example
25AA128
I/P e3 13F
1934
XXXXXXX
T/XXXNNN
YYWW
8-Lead SOIC (3.90 mm)
Example
XXXXXXXX
XXXYYWW
NNN
25LC128I
SN e3 1934
13F
8-Lead SOIJ (5.28 mm)
Example
25LC128
I/SM e3
193413F
XXXXXXXX
T/XXXXXXX
YYWWNNN
8-Lead TSSOP
Example
XXXX
TYYW
NNN
Part
No.
5LD
I934
13F
1st Line Marking Codes
DFN
I-Temp.
25AA128 25AA128
25LC128 25LC128
PDIP
SOIC
E-Temp.
I-Temp.
E-Temp.
I-Temp.
—
25AA128
—
25AA128T(1)
25LC128
25LC128
25LC128
25LC128T(1)
SOIJ
E-Temp.
I-Temp.
25AA128T(1) 25AA128
TSSOP
E-Temp. I-Temp. E-Temp.
—
25LC128T(1) 25AA128 25AA128
5AD
—
5ADX(2)
—
5LD
5LD
5LDX
Note 1:
2:
3:
(3)
5LDX(3)
T = Temperature grade (I, E)
For 25AA128X
For 25LC128X
2003-2019 Microchip Technology Inc.
DS20001831F-page 14
25AA128/25LC128
Legend: XX...X
T
Y
YY
WW
NNN
e3
Part number or part number code
Temperature (I, E)
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code (2 characters for small packages)
JEDEC® designator for Matte Tin (Sn)
* Standard OTP marking consists of Microchip part number, year code, week code and
traceability code.
Note:
For very small packages with no room for the JEDEC® designator
e3 , the marking will only appear on the outer carton or reel label.
Note:
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
2003-2019 Microchip Technology Inc.
DS20001831F-page 15
25AA128/25LC128
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