25LC160BT-I/MS

25AA160A/B, 25LC160A/B 16K SPI Bus Serial EEPROM Device Selection Table Part Number VCC Range Page Size Temp. Ranges Packages 25LC160A 2.5-5.5V 16 Byte I,E P, SN, ST, MS 25AA160A 1.8-5.5V 16 Byte I P, SN, ST, MS 25LC160B 2.5-5.5V 32 Byte I,E P, SN, ST, MS 25AA160B 1.8-5.5V 32 Byte I P, SN, ST, MS Features: Description: • • • • • • • • The Microchip Technology Inc. 25AA160A/B, 25LC160A/B (25XX160A/B*) are 16 Kbit Serial Electrically Erasable PROMs. The memory is accessed via a simple Serial Peripheral Interface (SPI) compatible serial bus. The bus signals required are a clock input (SCK) plus separate data in (SI) and data out (SO) lines. Access to the device is controlled through a Chip Select (CS) input. • • • • Max. Clock 10 MHz Low-Power CMOS Technology 2048 x 8-bit Organization 16-Byte Page (‘A’ version devices) 32-Byte Page (‘B’ version devices) Write Cycle Time: 5 ms max. Self-Timed Erase and Write Cycles Block Write Protection: - Protect none, 1/4, 1/2 or all of array Built-In Write Protection: - Power-on/off data protection circuitry - Write enable latch - Write-protect pin Sequential Read High Reliability: - Endurance: 1,000,000 erase/write cycles - Data retention: > 200 years - ESD protection: > 4000V Temperature Ranges Supported: - Industrial (I): -40°C to +85°C - Automotive (E): -40°C to +125°C • Pb-Free and RoHS Compliant Communication to the device can be paused via the hold pin (HOLD). While the device is paused, transitions on its inputs will be ignored, with the exception of Chip Select, allowing the host to service higher priority interrupts. The 25XX160A/B is available in standard Pb-free packages including 8-lead PDIP and SOIC, and advanced packaging including 8-lead MSOP, and 8-lead TSSOP. Package Types (not to scale) PDIP/SOIC TSSOP/MSOP (ST, MS) CS SO WP VSS 1 2 3 4 8 7 6 5 VCC HOLD SCK SI (P, SN) CS SO 1 2 8 7 VCC HOLD WP 3 6 SCK VSS 4 5 SI Pin Function Table Name Function CS Chip Select Input SO Serial Data Output WP Write-Protect VSS Ground SI Serial Data Input SCK Serial Clock Input HOLD VCC Hold Input Supply Voltage © 2007 Microchip Technology Inc. *25XX160A/B is used in this document as a generic part number for the 25AA160A/B, 25LC160A/B devices. DS21807D-page 1 25XX160A/B 1.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings(†) VCC .............................................................................................................................................................................7.0V All inputs and outputs w.r.t. VSS ......................................................................................................... -0.6V to VCC +1.0V Storage temperature .................................................................................................................................-65°C to 150°C Ambient temperature under bias ...............................................................................................................-40°C to 125°C ESD protection on all pins ..........................................................................................................................................4 kV † NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for an extended period of time may affect device reliability. TABLE 1-1: DC CHARACTERISTICS DC CHARACTERISTICS Param. No. Sym. D001 VIH1 D002 VIH2 Characteristic TAMB = -40°C to +85°C TAMB = -40°C to +125°C Industrial (I): Automotive (E): VCC = 1.8V to 5.5V VCC = 2.5V to 5.5V Min. Max. Units 2.0 VCC +1 V VCC ≥ 2.7V (Note) 0.7 VCC VCC +1 V VCC < 2.7V (Note) -0.3 0.8 V VCC ≥ 2.7V (Note) -0.3 0.2 VCC V VCC < 2.7V (Note) Low-level output voltage — 0.4 V IOL = 2.1 mA — 0.2 V IOL = 1.0 mA, VCC < 2.5V VCC -0.5 — V IOH = -400 μA High-level input voltage Low-level input voltage Test Conditions D003 VIL1 D004 VIL2 D005 VOL D006 VOL D007 VOH High-level output voltage D008 ILI Input leakage current — ±1 μA CS = VCC, VIN = VSS TO VCC D009 ILO Output leakage current — ±1 μA CS = VCC, VOUT = VSS TO VCC D010 CINT Internal Capacitance (all inputs and outputs) — 7 pF TAMB = 25°C, CLK = 1.0 MHz, VCC = 5.0V (Note) D011 ICC Read — 6 mA — 2.5 mA VCC = 5.5V; FCLK = 10.0 MHz; SO = Open VCC = 2.5V; FCLK = 5.0 MHz; SO = Open Operating Current D012 ICC Write — 3 mA VCC = 5.5V D013 ICCS — 5 μA — 1 μA CS = VCC = 5.5V, Inputs tied to VCC or VSS, TAMB = -40°C TO +125°C CS = VCC = 2.5V, Inputs tied to VCC or VSS, TAMB = -40°C TO +85°C Standby Current Note: This parameter is periodically sampled and not 100% tested. DS21807D-page 2 © 2007 Microchip Technology Inc. 25XX160A/B TABLE 1-2: AC CHARACTERISTICS AC CHARACTERISTICS Param. Sym. No. Characteristic Industrial (I): TAMB = -40°C to +85°C VCC = 1.8V to 5.5V Automotive (E): TAMB = -40°C to +125°C VCC = 2.5V to 5.5V Min. Max. Units Test Conditions — — — 10 5 3 MHz MHz MHz 4.5V ≤ VCC ≤ 5.5V 2.5V ≤ VCC < 4.5V 1.8V ≤ VCC < 2.5V 1 FCLK Clock Frequency 2 TCSS CS Setup Time 50 100 150 — — — ns ns ns 4.5V ≤ VCC ≤ 5.5V 2.5V ≤ VCC < 4.5V 1.8V ≤ VCC < 2.5V 3 TCSH CS Hold Time 100 200 250 — — — ns ns ns 4.5V ≤ VCC ≤ 5.5V 2.5V ≤ VCC < 4.5V 1.8V ≤ VCC < 2.5V 4 TCSD CS Disable Time 50 — ns — 5 Tsu Data Setup Time 10 20 30 — — — ns ns ns 4.5V ≤ VCC ≤ 5.5V 2.5V ≤ VCC < 4.5V 1.8V ≤ VCC < 2.5V 6 THD Data Hold Time 20 40 50 — — — ns ns ns 4.5V ≤ VCC ≤ 5.5V 2.5V ≤ VCC < 4.5V 1.8V ≤ VCC < 2.5V 7 TR CLK Rise Time — 500 ns (Note 1) 8 TF CLK Fall Time — 500 ns (Note 1) 9 THI Clock High Time 50 100 150 — — — ns ns ns 4.5V ≤ VCC ≤ 5.5V 2.5V ≤ VCC < 4.5V 1.8V ≤ VCC < 2.5V 10 TLO Clock Low Time 50 100 150 — — — ns ns ns 4.5V ≤ VCC ≤ 5.5V 2.5V ≤ VCC < 4.5V 1.8V ≤ VCC < 2.5V 11 TCLD Clock Delay Time 50 — ns — 12 TCLE Clock Enable Time 50 — ns — 13 TV Output Valid from Clock Low — — — 50 100 160 ns ns ns 4.5V ≤ VCC ≤ 5.5V 2.5V ≤ VCC < 4.5V 1.8V ≤ VCC < 2.5V 14 THO Output Hold Time 0 — ns (Note 1) 15 TDIS Output Disable Time — — — 40 80 160 ns ns ns 4.5V ≤ VCC ≤ 5.5V (Note 1) 2.5V ≤ VCC ≤ 4.5V (Note 1) 1.8V ≤ VCC ≤ 2.5V (Note 1) 16 THS HOLD Setup Time 20 40 80 — — — ns ns ns 4.5V ≤ VCC ≤ 5.5V 2.5V ≤ VCC < 4.5V 1.8V ≤ VCC < 2.5V Note 1: This parameter is periodically sampled and not 100% tested. 2: This parameter is not tested but ensured by characterization. For endurance estimates in a specific application, please consult the Total Endurance™ Model which can be obtained from our web site: www.microchip.com. 3: TWC begins on the rising edge of CS after a valid write sequence and ends when the internal write cycle is complete. © 2007 Microchip Technology Inc. DS21807D-page 3 25XX160A/B TABLE 1-2: AC CHARACTERISTICS (CONTINUED) Industrial (I): TAMB = -40°C to +85°C VCC = 1.8V to 5.5V Automotive (E): TAMB = -40°C to +125°C VCC = 2.5V to 5.5V AC CHARACTERISTICS Param. Sym. No. Characteristic Min. Max. Units Test Conditions 17 THH HOLD Hold Time 20 40 80 — — — ns ns ns 4.5V ≤ VCC ≤ 5.5V 2.5V ≤ VCC < 4.5V 1.8V ≤ VCC < 2.5V 18 THZ HOLD Low to Output High-Z 30 60 160 — — — ns ns ns 4.5V ≤ VCC ≤ 5.5V (Note 1) 2.5V ≤ VCC < 4.5V (Note 1) 1.8V ≤ VCC < 2.5V (Note 1) 19 THV HOLD High to Output Valid 30 60 160 — — — ns ns ns 4.5V ≤ VCC ≤ 5.5V 2.5V ≤ VCC < 4.5V 1.8V ≤ VCC < 2.5V ms (NOTE 3) 20 TWC Internal Write Cycle Time — 5 21 — Endurance 1M — E/W (NOTE 2) Cycles Note 1: This parameter is periodically sampled and not 100% tested. 2: This parameter is not tested but ensured by characterization. For endurance estimates in a specific application, please consult the Total Endurance™ Model which can be obtained from our web site: www.microchip.com. 3: TWC begins on the rising edge of CS after a valid write sequence and ends when the internal write cycle is complete. TABLE 1-3: AC TEST CONDITIONS AC Waveform: VLO = 0.2V — VHI = VCC - 0.2V (Note 1) VHI = 4.0V (Note 2) Timing Measurement Reference Level Input 0.5 VCC Output 0.5 VCC Note 1: For VCC ≤ 4.0V 2: For VCC > 4.0V DS21807D-page 4 © 2007 Microchip Technology Inc. 25XX160A/B FIGURE 1-1: HOLD TIMING CS 17 16 17 16 SCK 18 SO n+2 SI n+2 n+1 n 19 High-Impedance n 5 Don’t Care n+1 n-1 n n n-1 HOLD FIGURE 1-2: SERIAL INPUT TIMING 4 CS 2 7 Mode 1,1 8 3 12 11 SCK Mode 0,0 5 SI 6 MSB in LSB in High-Impedance SO FIGURE 1-3: SERIAL OUTPUT TIMING CS 9 3 10 Mode 1,1 SCK Mode 0,0 13 SO 14 MSB out SI © 2007 Microchip Technology Inc. 15 ISB out Don’t Care DS21807D-page 5 25XX160A/B 2.0 FUNCTIONAL DESCRIPTION 2.1 Principles of Operation The 25XX160A/B are 2048 byte Serial EEPROMs designed to interface directly with the Serial Peripheral Interface (SPI) port of many of today’s popular microcontroller families, including Microchip’s PIC® microcontrollers. It may also interface with microcontrollers that do not have a built-in SPI port by using discrete I/O lines programmed properly with the software. The 25XX160A/B contains an 8-bit instruction register. The device is accessed via the SI pin, with data being clocked in on the rising edge of SCK. The CS pin must be low and the HOLD pin must be high for the entire operation. Table 2-1 contains a list of the possible instruction bytes and format for device operation. All instructions, addresses, and data are transferred MSB first, LSB last. Data (SI) is sampled on the first rising edge of SCK after CS goes low. If the clock line is shared with other peripheral devices on the SPI bus, the user can assert the HOLD input and place the 25XX160A/B in ‘HOLD’ mode. After releasing the HOLD pin, operation will resume from the point when the HOLD was asserted. 2.2 Read Sequence The device is selected by pulling CS low. The 8-bit read instruction is transmitted to the 25XX160A/B followed by the 16-bit address, with the five MSBs of the address being "don’t care" bits. After the correct read instruction and address are sent, the data stored in the memory at the selected address is shifted out on the SO pin. The data stored in the memory at the next address can be read sequentially by continuing to provide clock pulses. The internal Address Pointer is automatically incremented to the next higher address after each byte of data is shifted out. When the highest address is reached (07FFh), the address counter rolls over to address 0000h allowing the read cycle to be continued indefinitely. The read operation is terminated by raising the CS pin (Figure 2-1). DS21807D-page 6 2.3 Write Sequence Prior to any attempt to write data to the 25XX160A/B, the write enable latch must be set by issuing the WREN instruction (Figure 2-4). This is done by setting CS low and then clocking out the proper instruction into the 25XX160A/B. After all eight bits of the instruction are transmitted, the CS must be brought high to set the write enable latch. If the write operation is initiated immediately after the WREN instruction without CS being brought high, the data will not be written to the array because the write enable latch will not have been properly set. Once the write enable latch is set, the user may proceed by setting the CS low, issuing a WRITE instruction, followed by the 16-bit address, with the five MSBs of the address being "don’t care" bits, and then the data to be written. Up to 16 bytes (25XX160A) or 32 bytes (25XX160B) of data can be sent to the device before a write cycle is necessary. The only restriction is that all of the bytes must reside in the same page. Note: Page write operations are limited to writing bytes within a single physical page, regardless of the number of bytes actually being written. Physical page boundaries start at addresses that are integer multiples of the page buffer size (or ‘page size’) and, end at addresses that are integer multiples of page size – 1. If a Page Write command attempts to write across a physical page boundary, the result is that the data wraps around to the beginning of the current page (overwriting data previously stored there), instead of being written to the next page as might be expected. It is therefore necessary for the application software to prevent page write operations that would attempt to cross a page boundary. For the data to be actually written to the array, the CS must be brought high after the Least Significant bit (D0) of the nth data byte has been clocked in. If CS is brought high at any other time, the write operation will not be completed. Refer to Figure 2-2 and Figure 2-3 for more detailed illustrations on the byte write sequence and the page write sequence, respectively. While the write is in progress, the STATUS register may be read to check the status of the WPEN, WIP, WEL, BP1 and BP0 bits (Figure 2-6). A read attempt of a memory array location will not be possible during a write cycle. When the write cycle is completed, the write enable latch is reset. © 2007 Microchip Technology Inc. 25XX160A/B Block Diagram STATUS Register HV Generator Memory Control Logic I/O Control Logic X EEPROM Array Dec Page Latches SI SO Y Decoder CS SCK Sense Amp. R/W Control HOLD WP VCC VSS TABLE 2-1: INSTRUCTION SET Instruction Name Instruction Format Description READ 0000 0011 Read data from memory array beginning at selected address WRITE 0000 0010 Write data to memory array beginning at selected address WRDI 0000 0100 Reset the write enable latch (disable write operations) WREN 0000 0110 Set the write enable latch (enable write operations) RDSR 0000 0101 Read STATUS register WRSR 0000 0001 Write STATUS register FIGURE 2-1: READ SEQUENCE CS 0 1 2 0 0 0 3 4 5 6 7 8 9 10 11 0 1 1 15 14 13 12 21 22 23 24 25 26 27 28 29 30 31 SCK Instruction SI 0 0 16-bit Address 2 1 0 Data Out High-Impedance SO © 2007 Microchip Technology Inc. 7 6 5 4 3 2 1 0 DS21807D-page 7 25XX160A/B FIGURE 2-2: BYTE WRITE SEQUENCE CS Twc 0 1 2 3 4 5 6 7 8 9 10 11 21 22 23 24 25 26 27 28 29 30 31 SCK Instruction SI 0 0 0 0 0 16-bit Address 0 2 0 15 14 13 12 1 Data Byte 1 0 7 6 5 4 3 2 1 0 High-Impedance SO FIGURE 2-3: PAGE WRITE SEQUENCE CS 0 1 2 3 4 5 6 7 8 9 10 11 21 22 23 24 25 26 27 28 29 30 31 SCK Instruction SI 0 0 0 0 0 16-bit Address 0 1 Data Byte 1 2 0 15 14 13 12 1 0 7 6 5 4 3 2 1 0 CS 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 SCK Data Byte 2 SI 7 DS21807D-page 8 6 5 4 3 2 Data Byte 3 1 0 7 6 5 4 3 2 Data Byte n (16/32 max) 1 0 7 6 5 4 3 2 1 0 © 2007 Microchip Technology Inc. 25XX160A/B 2.4 Write Enable (WREN) and Write Disable (WRDI) The following is a list of conditions under which the write enable latch will be reset: • • • • The 25XX160A/B contains a write enable latch. See Table 2-1 for the Write-Protect Functionality Matrix. This latch must be set before any write operation will be completed internally. The WREN instruction will set the latch, and the WRDI will reset the latch. FIGURE 2-4: Power-up WRDI instruction successfully executed WRSR instruction successfully executed WRITE instruction successfully executed WRITE ENABLE SEQUENCE (WREN) CS 0 1 2 3 4 5 6 7 SCK 0 SI 0 0 0 1 1 0 High-Impedance SO FIGURE 2-5: 0 WRITE DISABLE SEQUENCE (WRDI) CS 0 1 2 3 4 5 6 7 SCK SI 0 0 0 0 0 1 10 0 High-Impedance SO © 2007 Microchip Technology Inc. DS21807D-page 9 25XX160A/B 2.5 Read Status Register Instruction (RDSR) The Write Enable Latch (WEL) bit indicates the status of the write enable latch and is read-only. When set to a ‘1’, the latch allows writes to the array, when set to a ‘0’, the latch prohibits writes to the array. The state of this bit can always be updated via the WREN or WRDI commands regardless of the state of write protection on the STATUS register. These commands are shown in Figure 2-4 and Figure 2-5. The Read Status Register instruction (RDSR) provides access to the STATUS register. The STATUS register may be read at any time, even during a write cycle. The STATUS register is formatted as follows: TABLE 2-2: STATUS REGISTER 7 6 5 4 3 2 1 W/R – – – W/R W/R R WPEN X X X BP1 BP0 WEL W/R = writable/readable. R = read-only. The Block Protection (BP0 and BP1) bits indicate which blocks are currently write-protected. These bits are set by the user issuing the WRSR instruction. These bits are nonvolatile, and are shown in Table 2-3. 0 R WIP See Figure 2-6 for the RDSR timing sequence. The Write-In-Process (WIP) bit indicates whether the 25XX160A/B is busy with a write operation. When set to a ‘1’, a write is in progress, when set to a ‘0’, no write is in progress. This bit is read-only. FIGURE 2-6: READ STATUS REGISTER TIMING SEQUENCE (RDSR) CS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 1 0 SCK Instruction SI 0 0 0 0 0 High-Impedance SO DS21807D-page 10 1 0 1 Data from STATUS Register 7 6 5 4 3 2 © 2007 Microchip Technology Inc. 25XX160A/B 2.6 Write Status Register Instruction (WRSR) See Figure 2-7 for the WRSR timing sequence. TABLE 2-3: The Write Status Register instruction (WRSR) allows the user to write to the nonvolatile bits in the STATUS register as shown in Table 2-2. The user is able to select one of four levels of protection for the array by writing to the appropriate bits in the STATUS register. The array is divided up into four segments. The user has the ability to write-protect none, one, two or all four of the segments of the array. The partitioning is controlled as shown in Table 2-3. The Write-Protect Enable (WPEN) bit is a nonvolatile bit that is available as an enable bit for the WP pin. The Write-Protect (WP) pin and the Write-Protect Enable (WPEN) bit in the STATUS register control the programmable hardware write-protect feature. Hardware write protection is enabled when WP pin is low and the WPEN bit is high. Hardware write protection is disabled when either the WP pin is high or the WPEN bit is low. When the chip is hardware write-protected, only writes to nonvolatile bits in the STATUS register are disabled. See Table 2-1 for a matrix of functionality on the WPEN bit. FIGURE 2-7: ARRAY PROTECTION BP1 BP0 Array Addresses Write-Protected 0 0 none 0 1 upper 1/4 (0600h-07FFh) 1 0 upper 1/2 (0400h-07FFh) 1 1 all (0000h-07FFh) WRITE STATUS REGISTER TIMING SEQUENCE (WRSR) CS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 1 0 SCK Instruction SI 0 0 0 0 Data to STATUS Register 0 0 0 1 7 6 5 4 3 2 High-Impedance SO © 2007 Microchip Technology Inc. DS21807D-page 11 25XX160A/B 2.7 Data Protection 2.8 The following protection has been implemented to prevent inadvertent writes to the array: • The write enable latch is reset on power-up • A write enable instruction must be issued to set the write enable latch • After a byte write, page write or STATUS register write, the write enable latch is reset • CS must be set high after the proper number of clock cycles to start an internal write cycle • Access to the array during an internal write cycle is ignored and programming is continued TABLE 2-1: Power-On State The 25XX160A/B powers on in the following state: • The device is in low-power Standby mode (CS = 1) • The write enable latch is reset • SO is in high-impedance state • A high-to-low-level transition on CS is required to enter active state WRITE-PROTECT FUNCTIONALITY MATRIX WEL (SR bit 1) WPEN (SR bit 7) WP (pin 3) Protected Blocks Unprotected Blocks STATUS Register 0 x x Protected Protected Protected 1 0 x Protected Writable Writable 1 1 0 (low) Protected Writable Protected 1 1 1 (high) Protected Writable Writable x = don’t care DS21807D-page 12 © 2007 Microchip Technology Inc. 25XX160A/B 3.0 PIN DESCRIPTIONS The descriptions of the pins are listed in Table 3-1. TABLE 3-1: PIN FUNCTION TABLE Name Pin Number CS 1 Chip Select Input SO 2 Serial Data Output WP 3 Write-Protect Pin VSS 4 Ground SI 5 Serial Data Input SCK 6 Serial Clock Input HOLD 7 Hold Input VCC 8 Supply Voltage 3.1 Function Chip Select (CS) A low level on this pin selects the device. A high level deselects the device and forces it into Standby mode. However, a programming cycle which is already initiated or in progress will be completed, regardless of the CS input signal. If CS is brought high during a program cycle, the device will go into Standby mode as soon as the programming cycle is complete. When the device is deselected, SO goes to the high-impedance state, allowing multiple parts to share the same SPI bus. A low-to-high transition on CS after a valid write sequence initiates an internal write cycle. After powerup, a low level on CS is required prior to any sequence being initiated. 3.2 Serial Output (SO) The SO pin is used to transfer data out of the 25XX160A/B. During a read cycle, data is shifted out on this pin after the falling edge of the serial clock. 3.3 The WP pin function is blocked when the WPEN bit in the STATUS register is low. This allows the user to install the 25XX160A/B in a system with WP pin grounded and still be able to write to the STATUS register. The WP pin functions will be enabled when the WPEN bit is set high. 3.4 Serial Input (SI) The SI pin is used to transfer data into the device. It receives instructions, addresses and data. Data is latched on the rising edge of the serial clock. 3.5 Serial Clock (SCK) The SCK is used to synchronize the communication between a master and the 25XX160A/B. Instructions, addresses or data present on the SI pin are latched on the rising edge of the clock input, while data on the SO pin is updated after the falling edge of the clock input. 3.6 Hold (HOLD) The HOLD pin is used to suspend transmission to the 25XX160A/B while in the middle of a serial sequence without having to retransmit the entire sequence again. It must be held high any time this function is not being used. Once the device is selected and a serial sequence is underway, the HOLD pin may be pulled low to pause further serial communication without resetting the serial sequence. The HOLD pin must be brought low while SCK is low, otherwise the HOLD function will not be invoked until the next SCK high-tolow transition. The 25XX160A/B must remain selected during this sequence. The SI, SCK and SO pins are in a high-impedance state during the time the device is paused and transitions on these pins will be ignored. To resume serial communication, HOLD must be brought high while the SCK pin is low, otherwise serial communication will not resume. Lowering the HOLD line at any time will tri-state the SO line. Write-Protect (WP) This pin is used in conjunction with the WPEN bit in the STATUS register to prohibit writes to the nonvolatile bits in the STATUS register. When WP is low and WPEN is high, writing to the nonvolatile bits in the STATUS register is disabled. All other operations function normally. When WP is high, all functions, including writes to the nonvolatile bits in the STATUS register operate normally. If the WPEN bit is set, WP low during a STATUS register write sequence will disable writing to the STATUS register. If an internal write cycle has already begun, WP going low will have no effect on the write. © 2007 Microchip Technology Inc. DS21807D-page 13 25XX160A/B 4.0 PACKAGING INFORMATION 4.1 Package Marking Information 8-Lead MSOP (150 mil) Example: MSOP 1st Line Marking Codes XXXXXXT YWWNNN 8-Lead PDIP Example: XXXXXXXX T/XXXNNN YYWW 25LC160B I/P e3 1L7 0628 8-Lead SOIC Example: XXXXXXXT XXXXYYWW NNN 25L160BI SN e3 0628 1L7 8-Lead TSSOP Example: XXXX TYWW NNN Legend: XX...X Y YY WW NNN e3 * Note: DS21807D-page 14 5LABI 6281L7 5LAB I628 1L7 Device 25AA160A 25AA160B 25LC160A 25LC160B Code 5AAA 5AAB 5LAA 5LAB TSSOP 1st Line Marking Codes Device 25AA160A 25AA160B 25LC160A 25LC160B Code 5AAA 5AAB 5LAA 5LAB Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week ‘01’) Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package. 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