25LC512-I/P

25LC512 512 Kbit SPI Bus Serial EEPROM Device Selection Table Part Number VCC Range Page Size Temp. Ranges Packages 25LC512 2.5-5.5V 128 Byte I,E P, SN, SM, MF Features: Description: • 20 MHz max. Clock Speed • Byte and Page-level Write Operations: - 128-byte page - 5 ms max. - No page or sector erase required • Low-Power CMOS Technology: - Max. Write Current: 5 mA at 5.5V, 20 MHz - Read Current: 10 mA at 5.5V, 20 MHz - Standby Current: 1A at 2.5V (Deep powerdown) • Electronic Signature for Device ID • Self-Timed Erase and Write cycles: - Page Erase (5 ms, typical) - Sector Erase (10 ms/sector, typical) - Bulk Erase (10 ms, typical) • Sector Write Protection (16K byte/sector): - Protect none, 1/4, 1/2 or all of array • Built-In Write Protection: - Power-on/off data protection circuitry - Write enable latch - Write-protect pin • High Reliability: - Endurance: 1 Million erase/write cycles - Data Retention: >200 years - ESD Protection: >4000V • Temperature Ranges Supported: - Industrial (I): -40C to +85C - Automotive (E): -40°C to +125°C The Microchip Technology Inc. 25LC512 is a 512 Kbit serial EEPROM memory with byte-level and page-level serial EEPROM functions. It also features Page, Sector and Chip erase functions typically associated with Flash-based products. These functions are not required for byte or page write operations. The memory is accessed via a simple Serial Peripheral Interface (SPI) compatible serial bus. The bus signals required are a clock input (SCK) plus separate data in (SI) and data out (SO) lines. Access to the device is controlled by a Chip Select (CS) input. Pin Function Table Name The 25LC512 is available in standard packages including 8-lead PDIP, SOIC, and advanced 8-lead DFN package. All packages are Pb-free and RoHS compliant. Package Types (not to scale) DFN PDIP/SOIC/SOIJ (MF) SO 2 WP 3 VSS 4 (P, SN, SM) 8 VCC 7 HOLD 6 5 CS SO 1 2 SCK WP 3 SI VSS 4 25LC512 CS 1 25LC512 • Pb-free and RoHS Compliant Communication to the device can be paused via the hold pin (HOLD). While the device is paused, transitions on its inputs will be ignored, with the exception of Chip Select, allowing the host to service higher priority interrupts. 8 7 VCC HOLD 6 SCK 5 SI Function CS SO Chip Select Input Serial Data Output WP VSS SI SCK Write-Protect Ground Serial Data Input Serial Clock Input HOLD VCC Hold Input Supply Voltage  2010 Microchip Technology Inc. DS22065C-page 1 25LC512 1.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings (†) VCC .............................................................................................................................................................................6.5V All inputs and outputs w.r.t. VSS ......................................................................................................... -0.6V to VCC +1.0V Storage temperature .................................................................................................................................-65°C to 150°C Ambient temperature under bias ...............................................................................................................-40°C to 125°C ESD protection on all pins ..........................................................................................................................................4 kV † NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for an extended period of time may affect device reliability. TABLE 1-1: DC CHARACTERISTICS DC CHARACTERISTICS Param. No. D001 Sym. Characteristic TA = -40°C to +85°C TA = -40°C to +125°C Industrial (I): Automotive (E): Min. Max. Units VCC = 2.5V to 5.5V VCC = 2.5V to 5.5V Test Conditions VIH1 High-level input voltage .7 VCC VCC +1 V Low-level input voltage -0.3 0.3 VCC V VCC2.7V -0.3 0.2 VCC V VCC < 2.7V D002 VIL1 D003 VIL2 D004 VOL Low-level output voltage — 0.4 V IOL = 2.1 mA D005 VOH High-level output voltage VCC -0.2 — V IOH = -400 A D006 ILI Input leakage current — ±1 A CS = VCC, VIN = VSS or VCC D007 ILO Output leakage current — ±1 A CS = VCC, VOUT = VSS or VCC D008 CINT Internal capacitance (all inputs and outputs) — 7 pF TA = 25°C, CLK = 1.0 MHz, VCC = 5.0V (Note) D009 ICC Read — — 10 mA 5 mA VCC = 5.5V; FCLK = 20.0 MHz; SO = Open VCC = 2.5V; FCLK = 10.0 MHz; SO = Open — — 7 5 mA mA VCC = 5.5V VCC = 2.5V — — 20 A 10 A CS = VCC = 5.5V, Inputs tied to VCC or VSS, 125°C CS = VCC = 5.5V, Inputs tied to VCC or VSS, 85°C 2 A 1 A Operating current D010 ICC Write D011 ICCS Standby current D012 Note: ICCSPD Deep power-down current — CS = VCC = 2.5V, Inputs tied to VCC or VSS, 125°C CS = VCC = 2.5V, Inputs tied to VCC or VSS, 85°C This parameter is periodically sampled and not 100% tested. DS22065C-page 2  2010 Microchip Technology Inc. 25LC512 TABLE 1-2: AC CHARACTERISTICS Industrial (I): Automotive (E): AC CHARACTERISTICS Param. No. Sym. Characteristic TA = -40°C to +85°C TA = -40°C to +125°C Min. Max. Units VCC = 2.0V to 5.5V VCC = 2.5V to 5.5V Conditions 1 FCLK Clock frequency — — 20 10 MHz MHz 4.5V VCC 5.5V (I) 2.5V VCC 5.5V (I, E) 2 TCSS CS setup time 25 50 — — ns ns 4.5V VCC 5.5V (I) 2.5V VCC 5.5V (I, E) 3 TCSH CS hold time 50 100 — — ns ns 4.5V VCC 5.5V (I) 2.5V VCC 5.5V (I, E) 4 TCSD CS disable time 50 — ns — 5 Tsu Data setup time 5 10 — — ns ns 4.5V VCC 5.5V (I) 2.5V VCC 5.5V (I, E) 6 THD Data hold time 10 20 — — ns ns 4.5V VCC 5.5V (I) 2.5V VCC 5.5V (I, E) 7 TR CLK rise time — 20 ns (Note 1) 8 TF CLK fall time — 20 ns (Note 1) 9 THI Clock high time 25 50 — — ns ns 4.5V VCC 5.5V (I) 2.5V VCC 5.5V (I, E) 10 TLO Clock low time 25 50 — — ns ns 4.5V VCC 5.5V (I) 2.5V VCC 5.5V (I, E) 11 TCLD Clock delay time 50 — ns — 12 TCLE Clock enable time 50 — ns — 13 TV Output valid from clock low — — 25 50 ns ns 4.5V VCC 5.5V (I) 2.5V VCC 5.5V (I, E) 14 THO Output hold time 0 — ns (Note 1) 15 TDIS Output disable time — — 25 50 ns ns 4.5V VCC 5.5V (I) 2.5V VCC 5.5V (I, E) 16 THS HOLD setup time 10 20 — — ns ns 4.5V VCC 5.5V (I) 2.5V VCC 5.5V (I, E) 17 THH HOLD hold time 10 20 — — ns ns 4.5V VCC 5.5V (I) 2.5V VCC 5.5V (I, E) 18 THZ HOLD low to output High-Z 15 30 — — ns ns 4.5V VCC 5.5V (I) 2.5V VCC 5.5V (I, E) (Note 1) 19 THV HOLD high to output valid 15 30 — — ns ns 4.5V VCC 5.5V (I) 2.5V VCC 5.5V (I, E) 20 TREL CS High to Standby mode — 100 s — 21 TPD CS High to Deep powerdown — 100 s — 22 TCE Chip erase cycle time — 10 ms — 23 TSE Sector erase cycle time — 10 ms — 24 TWC Internal write cycle time — 5 ms Byte or Page mode and Page Erase Note 1: This parameter is periodically sampled and not 100% tested. 2: This parameter is not tested but established by characterization and qualification. For endurance estimates in a specific application, please consult the Total Endurance™ Model, which can be obtained from Microchip’s web site at www.microchip.com.  2010 Microchip Technology Inc. DS22065C-page 3 25LC512 TABLE 1-2: AC CHARACTERISTICS (CONTINUED) Industrial (I): Automotive (E): AC CHARACTERISTICS Param. No. 25 Sym. — Characteristic Endurance TA = -40°C to +85°C TA = -40°C to +125°C Min. Max. 1M — Units VCC = 2.0V to 5.5V VCC = 2.5V to 5.5V Conditions E/W Page mode, 25°C, 5.5V (Note 2) Cycles Note 1: This parameter is periodically sampled and not 100% tested. 2: This parameter is not tested but established by characterization and qualification. For endurance estimates in a specific application, please consult the Total Endurance™ Model, which can be obtained from Microchip’s web site at www.microchip.com. TABLE 1-3: AC TEST CONDITIONS AC Waveform: VLO = 0.2V — VHI = VCC - 0.2V (Note 1) VHI = 4.0V (Note 2) CL = 30 pF — Timing Measurement Reference Level Input 0.5 VCC Output 0.5 VCC Note 1: For VCC  4.0V 2: For VCC > 4.0V DS22065C-page 4  2010 Microchip Technology Inc. 25LC512 FIGURE 1-1: HOLD TIMING CS 16 17 16 17 16 17 16 17 SCK 18 n n+1 SO High-Impedance Don’t Care SI 19 n-1 19 High-Impedance n-2 Don’t Care 5 n n+1 18 n n-1 n n-2 HOLD FIGURE 1-2: SERIAL INPUT TIMING 4 CS 2 7 Mode 1,1 8 3 12 11 SCK Mode 0,0 5 SI 6 MSB in LSB in High-Impedance SO FIGURE 1-3: SERIAL OUTPUT TIMING CS 9 3 10 Mode 1,1 SCK Mode 0,0 13 SO 14 MSB out SI  2010 Microchip Technology Inc. 15 LSB out Don’t Care DS22065C-page 5 25LC512 2.0 FUNCTIONAL DESCRIPTION 2.1 Principles of Operation BLOCK DIAGRAM The 25LC512 is a 65,536 byte Serial EEPROM designed to interface directly with the Serial Peripheral Interface (SPI) port of many of today’s popular microcontroller families, including Microchip’s PIC® microcontrollers. It may also interface with microcontrollers that do not have a built-in SPI port by using discrete I/O lines programmed properly in firmware to match the SPI protocol. The 25LC512 contains an 8-bit instruction register. The device is accessed via the SI pin, with data being clocked in on the rising edge of SCK. The CS pin must be low and the HOLD pin must be high for the entire operation. Table 2-1 contains a list of the possible instruction bytes and format for device operation. All instructions, addresses, and data are transferred MSB first, LSB last. Data (SI) is sampled on the first rising edge of SCK after CS goes low. If the clock line is shared with other peripheral devices on the SPI bus, the user can assert the HOLD input and place the 25LC512 in ‘HOLD’ mode. After releasing the HOLD pin, operation will resume from the point when the HOLD was asserted. TABLE 2-1: STATUS Register I/O Control Logic HV Generator Memory Control Logic EEPROM Array X Dec Page Latches SI SO Y Decoder CS SCK Sense Amp. R/W Control HOLD WP VCC VSS INSTRUCTION SET Instruction Name Instruction Format Description READ 0000 0011 Read data from memory array beginning at selected address WRITE 0000 0010 Write data to memory array beginning at selected address WREN 0000 0110 Set the write enable latch (enable write operations) WRDI 0000 0100 Reset the write enable latch (disable write operations) RDSR 0000 0101 Read STATUS register WRSR 0000 0001 Write STATUS register PE 0100 0010 Page Erase – erase one page in memory array SE 1101 1000 Sector Erase – erase one sector in memory array CE 1100 0111 Chip Erase – erase all sectors in memory array RDID 1010 1011 Release from Deep power-down and read electronic signature DPD 1011 1001 Deep Power-Down mode DS22065C-page 6  2010 Microchip Technology Inc. 25LC512 Read Sequence The device is selected by pulling CS low. The 8-bit READ instruction is transmitted to the 25LC512 followed by the 16-bit address. After the correct READ instruction and address are sent, the data stored in the memory at the selected address is shifted out on the SO pin. The data stored in the memory at the next address can be read sequentially by continuing to FIGURE 2-1: provide clock pulses. The internal Address Pointer is automatically incremented to the next higher address after each byte of data is shifted out. When the highest address is reached (FFFFh), the address counter rolls over to address 0000h allowing the read cycle to be continued indefinitely. The READ instruction is terminated by raising the CS pin (Figure 2-1). READ SEQUENCE CS 0 1 2 3 4 5 6 7 8 9 10 11 21 22 23 24 25 26 27 28 29 30 31 SCK Instruction SI 0 0 0 0 0 16-bit Address 0 1 1 15 14 13 12 2 1 0 Data Out High-Impedance SO  2010 Microchip Technology Inc. 7 6 5 4 3 2 1 0 DS22065C-page 7 25LC512 2.2 Write Sequence Note: Prior to any attempt to write data to the 25LC512, the write enable latch must be set by issuing the WREN instruction (Figure 2-4). This is done by setting CS low and then clocking out the proper instruction into the 25LC512. After all eight bits of the instruction are transmitted, the CS must be brought high to set the write enable latch. If the write operation is initiated immediately after the WREN instruction without CS being brought high, the data will not be written to the array because the write enable latch will not have been properly set. A write sequence includes an automatic, self timed erase cycle. It is not required to erase any portion of the memory prior to issuing a WRITE instruction. Once the write enable latch is set, the user may proceed by setting the CS low, issuing a WRITE instruction, followed by the 16-bit address, and then the data to be written. Up to 128 bytes of data can be sent to the device before a write cycle is necessary. The only restriction is that all of the bytes must reside in the same page. Note: When doing a write of less than 128 bytes the data in the rest of the page is refreshed along with the data bytes being written. This will force the entire page to endure a write cycle, for this reason endurance is specified per page. FIGURE 2-2: Page write operations are limited to writing bytes within a single physical page, regardless of the number of bytes actually being written. Physical page boundaries start at addresses that are integer multiples of the page buffer size (or ‘page size’), and end at addresses that are integer multiples of page size – 1. If a Page Write command attempts to write across a physical page boundary, the result is that the data wraps around to the beginning of the current page (overwriting data previously stored there), instead of being written to the next page as might be expected. It is therefore necessary for the application software to prevent page write operations that would attempt to cross a page boundary. For the data to be actually written to the array, the CS must be brought high after the Least Significant bit (D0) of the nth data byte has been clocked in. If CS is brought high at any other time, the write operation will not be completed. Refer to Figure 2-2 and Figure 2-3 for more detailed illustrations on the byte write sequence and the page write sequence, respectively. While the write is in progress, the STATUS register may be read to check the status of the WPEN, WIP, WEL, BP1 and BP0 bits (Figure 2-6). A read attempt of a memory array location will not be possible during a write cycle. When the write cycle is completed, the write enable latch is reset. BYTE WRITE SEQUENCE CS Twc 0 1 2 0 0 0 3 4 8 5 6 7 9 10 11 0 1 0 15 14 13 12 21 22 23 24 25 26 27 28 29 30 31 SCK Instruction SI 0 0 16-bit Address Data Byte 2 1 0 7 6 5 4 3 2 1 0 High-Impedance SO DS22065C-page 8  2010 Microchip Technology Inc. 25LC512 FIGURE 2-3: PAGE WRITE SEQUENCE CS 0 1 2 0 0 0 3 4 5 6 7 8 9 10 11 21 22 23 24 25 26 27 28 29 30 31 SCK Instruction SI 0 0 16-bit Address 0 1 0 15 14 13 12 Data Byte 1 2 1 0 7 6 5 4 3 2 1 0 CS 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 SCK Data Byte 2 SI 7 6 5 4  2010 Microchip Technology Inc. 3 2 Data Byte n (128 max) Data Byte 3 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 DS22065C-page 9 25LC512 2.3 Write Enable (WREN) and Write Disable (WRDI) • • • • • • • The 25LC512 contains a write enable latch. See Table 2-4 for the Write-Protect Functionality Matrix. This latch must be set before any write operation will be completed internally. The WREN instruction will set the latch, and the WRDI will reset the latch. Power-up WRDI instruction successfully executed WRSR instruction successfully executed WRITE instruction successfully executed PE instruction successfully executed SE instruction successfully executed CE instruction successfully executed The following is a list of conditions under which the write enable latch will be reset: FIGURE 2-4: WRITE ENABLE SEQUENCE (WREN) CS 0 1 2 3 4 5 6 7 SCK 0 SI 0 0 0 1 1 0 High-Impedance SO FIGURE 2-5: 0 WRITE DISABLE SEQUENCE (WRDI) CS 0 1 2 3 4 5 6 7 SCK SI 0 0 0 0 0 1 10 0 High-Impedance SO DS22065C-page 10  2010 Microchip Technology Inc. 25LC512 2.4 Read Status Register Instruction (RDSR) The Write Enable Latch (WEL) bit indicates the status of the write enable latch and is read-only. When set to a ‘1’, the latch allows writes to the array, when set to a ‘0’, the latch prohibits writes to the array. The state of this bit can always be updated via the WREN or WRDI commands regardless of the state of write protection on the STATUS register. These commands are shown in Figure 2-4 and Figure 2-5. The Read Status Register instruction (RDSR) provides access to the STATUS register. The STATUS register may be read at any time, even during a write cycle. The STATUS register is formatted as follows: TABLE 2-2: STATUS REGISTER 7 6 5 4 3 2 1 W/R – – – W/R W/R R WPEN X X X BP1 BP0 WEL W/R = writable/readable. R = read-only. The Block Protection (BP0 and BP1) bits indicate which blocks are currently write-protected. These bits are set by the user issuing the WRSR instruction. These bits are nonvolatile, and are shown in Table 2-3. 0 R WIP See Figure 2-6 for the RDSR timing sequence. The Write-In-Process (WIP) bit indicates whether the 25LC512 is busy with a write operation. When set to a ‘1’, a write is in progress, when set to a ‘0’, no write is in progress. This bit is read-only. FIGURE 2-6: READ STATUS REGISTER TIMING SEQUENCE (RDSR) CS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 1 0 SCK Instruction SI 0 0 0 0 0 High-Impedance SO  2010 Microchip Technology Inc. 1 0 1 Data from STATUS Register 7 6 5 4 3 2 DS22065C-page 11 25LC512 2.5 Write Status Register Instruction (WRSR) The Write-Protect Enable (WPEN) bit is a nonvolatile bit that is available as an enable bit for the WP pin. The Write-Protect (WP) pin and the Write-Protect Enable (WPEN) bit in the STATUS register control the programmable hardware write-protect feature. Hardware write protection is enabled when WP pin is low and the WPEN bit is high. Hardware write protection is disabled when either the WP pin is high or the WPEN bit is low. When the chip is hardware write-protected, only writes to nonvolatile bits in the STATUS register are disabled. See Table 2-4 for a matrix of functionality on the WPEN bit. The Write Status Register instruction (WRSR) allows the user to write to the nonvolatile bits in the STATUS register as shown in Table 2-2. The user is able to select one of four levels of protection for the array by writing to the appropriate bits in the STATUS register. The array is divided up into four segments. The user has the ability to write-protect none, one, two or all four of the segments of the array. The partitioning is controlled as shown in Table 2-3. See Figure 2-7 for the WRSR timing sequence. TABLE 2-3: ARRAY PROTECTION BP1 BP0 Array Addresses Write-Protected Array Addresses Unprotected 0 0 none All (Sectors 0, 1, 2 & 3) (0000h-FFFFh) 0 1 Upper 1/4 (Sector 3) (C000h-FFFFh) Lower 3/4 (Sectors 0, 1 & 2) (0000h-BFFFh) 1 0 Upper 1/2 (Sectors 2 & 3) (8000h-FFFFh) Lower 1/2 (Sectors 0 & 1) (0000h-7FFFh) 1 1 All (Sectors 0, 1, 2 & 3) (0000h-FFFFh) none FIGURE 2-7: WRITE STATUS REGISTER TIMING SEQUENCE (WRSR) CS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 1 0 SCK Instruction SI 0 0 0 0 Data to STATUS Register 0 0 0 1 7 6 5 4 3 2 High-Impedance SO DS22065C-page 12  2010 Microchip Technology Inc. 25LC512 2.6 Data Protection 2.7 The following protection has been implemented to prevent inadvertent writes to the array: • The write enable latch is reset on power-up • A write enable instruction must be issued to set the write enable latch • After a byte write, page write or STATUS register write, the write enable latch is reset • CS must be set high after the proper number of clock cycles to start an internal write cycle • Access to the array during an internal write cycle is ignored and programming is continued TABLE 2-4: Power-On State The 25LC512 powers on in the following state: • The device is in low-power Standby mode (CS = 1) • The write enable latch is reset • SO is in high-impedance state • A high-to-low-level transition on CS is required to enter active state WRITE-PROTECT FUNCTIONALITY MATRIX WEL (SR bit 1) WPEN (SR bit 7) WP (pin 3) Protected Blocks Unprotected Blocks STATUS Register 0 x x Protected Protected Protected 1 0 x Protected Writable Writable 1 1 0 (low) Protected Writable Protected 1 1 1 (high) Protected Writable Writable x = don’t care  2010 Microchip Technology Inc. DS22065C-page 13 25LC512 2.8 PAGE ERASE CS must then be driven high after the last bit of the address or the PAGE ERASE will not execute. Once the CS is driven high the self-timed PAGE ERASE cycle is started. The WIP bit in the STATUS register can be read to determine when the PAGE ERASE cycle is complete. The PAGE ERASE instruction will erase all bits (FFh) inside the given page. A Write Enable (WREN) instruction must be given prior to attempting a PAGE ERASE. This is done by setting CS low and then clocking out the proper instruction into the 25LC512. After all eight bits of the instruction are transmitted, the CS must be brought high to set the write enable latch. If a PAGE ERASE instruction is given to an address that has been protected by the Block Protect bits (BP0, BP1) then the sequence will be aborted and no erase will occur. The PAGE ERASE instruction is entered by driving CS low, followed by the instruction code (Figure 2-8) and two address bytes. Any address inside the page to be erased is a valid address. FIGURE 2-8: PAGE ERASE SEQUENCE CS 0 1 2 3 4 5 6 7 8 9 10 11 21 22 23 SCK Instruction SI 0 1 0 0 0 16-bit Address 0 1 0 15 14 13 12 2 1 0 High-Impedance SO DS22065C-page 14  2010 Microchip Technology Inc. 25LC512 2.9 SECTOR ERASE CS must then be driven high after the last bit of the address or the SECTOR ERASE will not execute. Once the CS is driven high the self-timed SECTOR ERASE cycle is started. The WIP bit in the STATUS register can be read to determine when the SECTOR ERASE cycle is complete. The SECTOR ERASE instruction will erase all bits (FFh) inside the given sector. A Write Enable (WREN) instruction must be given prior to attempting a SECTOR ERASE. This is done by setting CS low and then clocking out the proper instruction into the 25LC512. After all eight bits of the instruction are transmitted, the CS must be brought high to set the write enable latch. If a SECTOR ERASE instruction is given to an address that has been protected by the Block Protect bits (BP0, BP1) then the sequence will be aborted and no erase will occur. The SECTOR ERASE instruction is entered by driving CS low, followed by the instruction code (Figure 2-9) and two address bytes. Any address inside the sector to be erased is a valid address. FIGURE 2-9: See Table 2-3 for Sector Addressing. SECTOR ERASE SEQUENCE CS 0 1 2 3 4 5 6 7 8 9 10 11 21 22 23 SCK Instruction SI 1 1 0 1 1 16-bit Address 0 0 0 15 14 13 12 2 1 0 High-Impedance SO  2010 Microchip Technology Inc. DS22065C-page 15 25LC512 2.10 CHIP ERASE The CS pin must be driven high after the eighth bit of the instruction code has been given or the CHIP ERASE instruction will not be executed. Once the CS pin is driven high the self-timed CHIP ERASE instruction begins. While the device is executing the CHIP ERASE instruction the WIP bit in the STATUS register can be read to determine when the CHIP ERASE instruction is complete. The CHIP ERASE instruction will erase all bits (FFh) in the array. A Write Enable (WREN) instruction must be given prior to executing a CHIP ERASE. This is done by setting CS low and then clocking out the proper instruction into the 25LC512. After all eight bits of the instruction are transmitted, the CS must be brought high to set the write enable latch. The CHIP ERASE instruction is entered by driving the CS low, followed by the instruction code (Figure 2-10) onto the SI line. FIGURE 2-10: The CHIP ERASE instruction is ignored if either of the Block Protect bits (BP0, BP1) are not 0, meaning ¼, ½, or all of the array is protected. CHIP ERASE SEQUENCE CS 0 1 2 3 4 5 6 7 SCK SI 1 1 0 0 0 1 1 1 High-Impedance SO DS22065C-page 16  2010 Microchip Technology Inc. 25LC512 2.11 DEEP POWER-DOWN MODE Deep Power-Down mode of the 25LC512 is its lowest power consumption state. The device will not respond to any of the Read or Write commands while in Deep Power-Down mode, and therefore it can be used as an additional software write protection feature. All instructions given during Deep Power-Down mode are ignored except the Read Electronic Signature command (RDID). The RDID command will release the device from Deep power-down and outputs the electronic signature on the SO pin, and then returns the device to Standby mode after delay (TREL) The Deep Power-Down mode is entered by driving CS low, followed by the instruction code (Figure 2-11) onto the SI line, followed by driving CS high. Deep Power-Down mode automatically releases at device power-down. Once power is restored to the device it will power-up in the Standby mode. If the CS pin is not driven high after the eighth bit of the instruction code has been given, the device will not execute Deep power-down. Once the CS line is driven high there is a delay (TDP) before the current settles to its lowest consumption. FIGURE 2-11: DEEP POWER-DOWN SEQUENCE CS 0 1 2 3 4 5 6 7 SCK SI 1 0 1 1 1 0 0 1 High-Impedance SO  2010 Microchip Technology Inc. DS22065C-page 17 25LC512 2.12 RELEASE FROM DEEP POWER-DOWN AND READ ELECTRONIC SIGNATURE Release from Deep Power-Down mode and Read Electronic Signature is entered by driving CS low, followed by the RDID instruction code (Figure 2-12) and then a dummy address of 16 bits (A15-A0). After the last bit of the dummy address is clock in, the 8-bit Electronic Signature is clocked out on the SO pin. Once the device has entered Deep Power-Down mode all instructions are ignored except the Release from Deep Power-down and Read Electronic Signature command. This command can also be used when the device is not in Deep power-down to read the electronic signature out on the SO pin unless another command is being executed such as Erase, Program or Write Status Register. FIGURE 2-12: After the signature has been read out at least once, the sequence can be terminated by driving CS high. The device will then return to Standby mode and will wait to be selected so it can be given new instructions. If additional clock cycles are sent after the electronic signature has been read once, it will continue to output the signature on the SO line until the sequence is terminated. RELEASE FROM DEEP POWER-DOWN AND READ ELECTRONIC SIGNATURE CS 0 1 1 0 2 3 4 5 6 0 1 7 8 9 10 11 21 22 23 24 25 26 27 28 29 30 31 SCK Instruction SI 1 0 16-bit Address 1 1 15 14 13 12 2 1 0 Electronic Signature Out High-Impedance SO 7 6 5 4 3 2 1 0 0 0 1 0 1 0 0 1 Manufacturer’s ID = 0x29 Driving CS high after the 8-bit RDID command but before the Electronic Signature has been transmitted will still ensure the device will be taken out of Deep Power-Down mode. However, there is a delay TREL that occurs before the device returns to Standby mode (ICCS), as shown in Figure 2-13. FIGURE 2-13: RELEASE FROM DEEP POWER-DOWN AND READ ELECTRONIC SIGNATURE CS 0 1 2 3 4 5 6 0 1 7 TREL SCK Instruction SI 1 0 1 0 1 1 High-Impedance SO DS22065C-page 18  2010 Microchip Technology Inc. 25LC512 3.0 PIN DESCRIPTIONS The descriptions of the pins are listed in Table 3-1. TABLE 3-1: PIN FUNCTION TABLE Name Pin Number CS 1 Chip Select Input SO 2 Serial Data Output WP 3 Write-Protect Pin VSS 4 Ground SI 5 Serial Data Input SCK 6 Serial Clock Input HOLD 7 Hold Input VCC 8 Supply Voltage 3.1 Function Chip Select (CS) A low level on this pin selects the device. A high level deselects the device and forces it into Standby mode. However, a programming cycle which is already initiated or in progress will be completed, regardless of the CS input signal. If CS is brought high during a program cycle, the device will go into Standby mode as soon as the programming cycle is complete. When the device is deselected, SO goes to the high-impedance state, allowing multiple parts to share the same SPI bus. A low-to-high transition on CS after a valid write sequence initiates an internal write cycle. After powerup, a low level on CS is required prior to any sequence being initiated. 3.2 Serial Output (SO) The SO pin is used to transfer data out of the 25LC512. During a read cycle, data is shifted out on this pin after the falling edge of the serial clock. 3.3 Write-Protect (WP) This pin is used in conjunction with the WPEN bit in the STATUS register to prohibit writes to the nonvolatile bits in the STATUS register. When WP is low and WPEN is high, writing to the nonvolatile bits in the STATUS register is disabled. All other operations function normally. When WP is high, all functions, including writes to the nonvolatile bits in the STATUS register, operate normally. If the WPEN bit is set, WP low during a STATUS register write sequence will disable writing to the STATUS register. If an internal write cycle has already begun, WP going low will have no effect on the write.  2010 Microchip Technology Inc. The WP pin function is blocked when the WPEN bit in the STATUS register is low. This allows the user to install the 25LC512 in a system with WP pin grounded and still be able to write to the STATUS register. The WP pin functions will be enabled when the WPEN bit is set high. 3.4 Serial Input (SI) The SI pin is used to transfer data into the device. It receives instructions, addresses and data. Data is latched on the rising edge of the serial clock. 3.5 Serial Clock (SCK) The SCK is used to synchronize the communication between a master and the 25LC512. Instructions, addresses or data present on the SI pin are latched on the rising edge of the clock input, while data on the SO pin is updated after the falling edge of the clock input. 3.6 Hold (HOLD) The HOLD pin is used to suspend transmission to the 25LC512 while in the middle of a serial sequence without having to re-transmit the entire sequence over again. It must be held high any time this function is not being used. Once the device is selected and a serial sequence is underway, the HOLD pin may be pulled low to pause further serial communication without resetting the serial sequence. The HOLD pin should be brought low while SCK is low, otherwise the HOLD function will not be invoked until the next SCK high-to-low transition. The 25LC512 must remain selected during this sequence. The SI and SCK levels are “don’t cares” during the time the device is paused and any transitions on these pins will be ignored. To resume serial communication, HOLD should be brought high while the SCK pin is low, otherwise serial communication will not be resumed until the next SCK high-to-low transition. The SO line will tri-state immediately upon a high-tolow transition of the HOLD pin, and will begin outputting again immediately upon a subsequent low-to-high transition of the HOLD pin, independent of the state of SCK. DS22065C-page 19 25LC512 4.0 PACKAGING INFORMATION 4.1 Package Marking Information 8-Lead DFN XXXXXXX T/XXXXX YYWW NNN Example: 25LC512 I/MF e3 0728 1L7 8-Lead PDIP Example: XXXXXXXX T/XXXNNN YYWW 25LC512 I/P e3 1L7 0728 8-Lead SOIC Example: XXXXXXXT XXXXYYWW NNN 25LC512I SN e3 0728 1L7 8-Lead SOIJ XXXXXXXX T/XXXXXX YYWWNNN Legend: XX...X T Y YY WW NNN e3 Note: Note: DS22065C-page 20 Example: 25LC512 I/SM e3 07281L7 Part number or part number code Temperature (I, E) Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week ‘01’) Alphanumeric traceability code (2 characters for small packages) Pb-free JEDEC designator for Matte Tin (Sn) For very small packages with no room for the Pb-free JEDEC designator e3 , the marking will only appear on the outer carton or reel label. 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