25LC640AT-E/ST16KVAO

25AA640A/25LC640A 64K SPI Bus Serial EEPROM Device Selection Table Part Number VCC Range Page Size Temp. Ranges 25AA640A 1.8V-5.5V 32 Bytes I, E MF, MS, P, SN, MNY, ST 25LC640A 2.5V-5.5V 32 Bytes I, E MF, MS, P, SN, MNY, ST Features • Maximum Clock 10 MHz • Low-Power CMOS Technology: - Maximum Write current: 5 mA at 5.5V, 10 MHz - Read current: 5 mA at 5.5V, 10 MHz - Standby current: 1 µA at 5.5V • 8192 x 8-Bit Organization • 32-Byte Page • Self-Timed Erase and Write Cycles (5 ms maximum) • Block Write Protection: - Protect none, 1/4, 1/2 or all of array • Built-In Write Protection: - Power-on/off data protection circuitry - Write enable latch - Write-protect pin • Sequential Read • High Reliability: - Endurance: 1,000,000 erase/write cycles - Data retention: > 200 years - ESD protection: > 4000V • RoHS Compliant • Temperature Ranges Supported: - Industrial (I): -40C to +85C - Extended (E): -40°C to +125°C Packages Communication to the device can be paused via the hold pin (HOLD). While the device is paused, transitions on its inputs will be ignored, with the exception of Chip Select, allowing the host to service higher priority interrupts. Note 1: 25XX640A is used in this document as a generic part number for the 25AA640A and 25LC640A devices. Packages • • • • • • 8-Lead DFN 8-Lead MSOP 8-Lead PDIP 8-Lead SOIC 8-Lead TDFN 8-Lead TSSOP Package Types (not to scale) 8-Lead DFN/TDFN CS SO WP VSS 1 2 3 4 8 VCC 7 HOLD 6 SCK 5 SI • Automotive AEC-Q100 Qualified 8-Lead MSOP/TSSOP Description CS SO WP VSS The Microchip Technology Inc. 25AA640A/25LC640A (25XX640A(1)) are 64-Kbit Serial Electrically Erasable PROMs. The memory is accessed via a simple Serial Peripheral Interface (SPI) compatible serial bus. The bus signals required are a clock input (SCK) plus separate data in (SI) and data out (SO) lines. Access to the device is controlled through a Chip Select (CS) input.  2003-2021 Microchip Technology Inc. 1 2 3 4 8 7 6 5 VCC HOLD SCK SI 8-Lead PDIP/SOIC CS SO 1 2 8 7 VCC HOLD WP 3 6 SCK VSS 4 5 SI X-Rotated TSSOP HOLD VCC CS SO 1 2 3 4 8 7 6 5 SCK SI VSS WP DS20001830G-page 1 25AA640A/25LC640A 1.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings(†) VCC .............................................................................................................................................................................6.5V All inputs and outputs w.r.t. VSS ......................................................................................................... -0.6V to VCC +1.0V Storage temperature ...............................................................................................................................-65°C to +150°C Ambient temperature under bias .............................................................................................................-40°C to +125°C ESD protection on all pins ..........................................................................................................................................4 kV † NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for an extended period of time may affect device reliability. TABLE 1-1: DC CHARACTERISTICS DC CHARACTERISTICS Param. Symbol No. D001 VIH1 D002 VIL1 D003 VIL2 D004 VOL D005 VOL D006 Characteristic Industrial (I): TA = -40°C to +85°C VCC = 1.8V to 5.5V Extended (E):TA = -40°C to +125°C VCC = 1.8V to 5.5V Min. Max. Units 0.7 VCC VCC +1 V Low-Level Input Voltage -0.3 0.3 VCC V VCC2.7V -0.3 0.2 VCC V VCC < 2.7V Low-Level OutputVoltage — 0.4 V IOL = 2.1 mA — 0.2 V IOL = 1.0 mA, VCC < 2.5V VCC -0.5 — V IOH = -400 µA High-Level Input Voltage VOH High-Level Output Voltage Test Conditions D007 ILI Input Leakage Current — ±1 µA CS = VCC, VIN = VSS or VCC D008 ILO Output Leakage Current — ±1 µA CS = VCC, VOUT = VSS or VCC D009 CINT Internal Capacitance (all inputs and outputs) — 7 pF TA = +25°C, CLK = 1.0 MHz, VCC = 5.0V (Note 1) — 5 mA VCC = 5.5V; FCLK = 10.0 MHz; SO = Open — 2.5 mA VCC = 2.5V; FCLK = 5.0 MHz; SO = Open D010 ICC Read Operating Current D011 D012 Note 1: ICC Write ICCS Standby Current — 5 mA VCC = 5.5V — 3 mA VCC = 2.5V — 5 µA CS = VCC = 5.5V, Inputs tied to VCC or VSS, +125°C — 1 µA CS = VCC = 5.5V, Inputs tied to VCC or VSS, +85°C This parameter is periodically sampled and not 100% tested. DS20001830G-page 2  2003-2021 Microchip Technology Inc. 25AA640A/25LC640A TABLE 1-2: AC CHARACTERISTICS Industrial (I): TA = -40°C to +85°C VCC = 1.8V to 5.5V Extended (E):TA = -40°C to +125°C VCC = 1.8V to 5.5V AC CHARACTERISTICS Param. Symbol No. 1 FCLK 2 TCSS 3 TCSH Characteristic Clock Frequency CS Setup Time CS Hold Time 4 TCSD CS Disable Time 5 TSU Data Setup Time 6 THD Data Hold Time Min. Max. Units Test Conditions — 10 MHz 4.5V Vcc  5.5V — 5 MHz 2.5V Vcc  4.5V — 3 MHz 1.8V Vcc  2.5V 50 — ns 4.5V Vcc  5.5V 100 — ns 2.5V Vcc  4.5V 150 — ns 1.8V Vcc  2.5V 100 — ns 4.5V Vcc  5.5V 200 — ns 2.5V Vcc  4.5V 250 — ns 1.8V Vcc  2.5V 50 — ns 10 — ns 4.5V Vcc  5.5V 20 — ns 2.5V Vcc  4.5V 30 — ns 1.8V Vcc  2.5V 20 — ns 4.5V Vcc  5.5V 40 — ns 2.5V Vcc  4.5V 50 — ns 1.8V Vcc  2.5V Note 1 7 TR CLK Rise Time — 100 ns 8 TF CLK Fall Time — 100 ns Note 1 50 — ns 4.5V Vcc  5.5V 100 — ns 2.5V Vcc  4.5V 150 — ns 1.8V Vcc  2.5V 50 — ns 4.5V Vcc  5.5V 100 — ns 2.5V Vcc  4.5V 150 — ns 1.8V Vcc  2.5V 9 THI 10 TLO Clock High Time Clock Low Time 11 TCLD Clock Delay Time 50 — ns 12 TCLE Clock Enable Time 50 — ns — 50 ns 4.5V Vcc  5.5V 13 TV Output Valid from Clock Low — 100 ns 2.5V Vcc  4.5V — 160 ns 1.8V Vcc  2.5V 14 THO Output Hold Time 0 — ns Note 1 — 40 ns 4.5V Vcc  5.5V (Note 1) — 80 ns 2.5V Vcc  4.5V (Note 1) — 160 ns 1.8V Vcc  2.5V (Note 1) 15 TDIS Note 1: 2: 3: Output Disable Time This parameter is periodically sampled and not 100% tested. TWC begins on the rising edge of CS after a valid write sequence and ends when the internal write cycle is complete. This parameter is not tested but ensured by characterization. Due to the memory array architecture, the write cycle endurance is specified for write sequences in groups of four data bytes. The beginning of any 4-byte boundaries can be determined by multiplying any integer (N) by four (i.e., 4*N). The end address can be found by adding three to the beginning value (i.e., 4*N+3).  2003-2021 Microchip Technology Inc. DS20001830G-page 3 25AA640A/25LC640A TABLE 1-2: AC CHARACTERISTICS (CONTINUED) Industrial (I): TA = -40°C to +85°C VCC = 1.8V to 5.5V Extended (E):TA = -40°C to +125°C VCC = 1.8V to 5.5V AC CHARACTERISTICS Param. Symbol No. 16 THS 17 HOLD Setup Time THH 18 Characteristic HOLD Hold Time THZ HOLD Low to Output High-Z Min. Max. Units Test Conditions 20 — ns 4.5V Vcc  5.5V 40 — ns 2.5V Vcc  4.5V 80 — ns 1.8V Vcc  2.5V 20 — ns 4.5V Vcc  5.5V 40 — ns 2.5V Vcc  4.5V 80 — ns 1.8V Vcc  2.5V — 30 ns 4.5V Vcc  5.5V (Note 1) — 60 ns 2.5V Vcc  4.5V (Note 1) — 160 ns 1.8V Vcc  2.5V (Note 1) — 30 ns 4.5V Vcc  5.5V — 60 ns 2.5V Vcc  4.5V 19 THV HOLD High to Output Valid — 160 ns 1.8V Vcc  2.5V 20 TWC Internal Write Cycle Time — 5 ms Note 2 Endurance 1M — 21 Note 1: 2: 3: E/W +25°C, VCC = 5.5V (Note 3) Cycles This parameter is periodically sampled and not 100% tested. TWC begins on the rising edge of CS after a valid write sequence and ends when the internal write cycle is complete. This parameter is not tested but ensured by characterization. Due to the memory array architecture, the write cycle endurance is specified for write sequences in groups of four data bytes. The beginning of any 4-byte boundaries can be determined by multiplying any integer (N) by four (i.e., 4*N). The end address can be found by adding three to the beginning value (i.e., 4*N+3). TABLE 1-3: AC TEST CONDITIONS AC Waveform VLO = 0.2V — VH I = VCC - 0.2V Note 1 VH I = 4.0V Note 2 CL = 100 pF — Timing Measurement Reference Level Input 0.5 VCC Output Note 1: 2: 0.5 VCC For VCC  4.0V For VCC > 4.0V DS20001830G-page 4  2003-2021 Microchip Technology Inc. 25AA640A/25LC640A FIGURE 1-1: HOLD TIMING CS 17 16 17 16 SCK 18 SO n+2 SI n+2 n+1 n 19 High-Impedance n 5 Don’t Care n+1 n-1 n n n-1 HOLD FIGURE 1-2: SERIAL INPUT TIMING 4 CS 2 7 Mode 1,1 3 8 12 11 SCK Mode 0,0 5 SI 6 MSB in LSB in High-Impedance SO FIGURE 1-3: SERIAL OUTPUT TIMING CS 9 3 10 Mode 1,1 SCK Mode 0,0 13 SO 14 MSB out SI  2003-2021 Microchip Technology Inc. 15 LSB out Don’t Care DS20001830G-page 5 25AA640A/25LC640A 2.0 PIN DESCRIPTIONS The descriptions of the pins are listed in Table 2-1. TABLE 2-1: PIN FUNCTION TABLE DFN(1) PDIP SOIC SOIJ TDFN TSSOP X-Rotated TSSOP CS 1 1 1 1 1 1 3 Chip Select Input SO 2 2 2 2 2 2 4 Serial Data Output WP 3 3 3 3 3 3 5 Write-Protect Pin Name Function VSS 4 4 4 4 4 4 6 Ground SI 5 5 5 5 5 5 7 Serial Data Input SCK 6 6 6 6 6 6 8 Serial Clock Input HOLD 7 7 7 7 7 7 1 Hold Input 8 8 8 8 8 8 2 Supply Voltage VCC Note 1: 2.1 The exposed pad on the DFN package can be connected to VSS or left floating. Chip Select (CS) A low level on this pin selects the device. A high level deselects the device and forces it into Standby mode. However, a programming cycle which is already initiated or in progress will be completed, regardless of the CS input signal. If CS is brought high during a program cycle, the device will go into Standby mode as soon as the programming cycle is complete. When the device is deselected, SO goes to the high-impedance state, allowing multiple parts to share the same SPI bus. A low-to-high transition on CS after a valid write sequence initiates an internal write cycle. After power-up, a low level on CS is required prior to any sequence being initiated. 2.2 Serial Output (SO) The SO pin is used to transfer data out of the 25XX640A. During a read cycle, data are shifted out on this pin after the falling edge of the serial clock. 2.3 Write-Protect (WP) This pin is used in conjunction with the WPEN bit in the STATUS register to prohibit writes to the nonvolatile bits in the STATUS register. When WP is low and WPEN is high, writing to the nonvolatile bits in the STATUS register is disabled. All other operations function normally. When WP is high, all functions, including writes to the nonvolatile bits in the STATUS register operate normally. If the WPEN bit is set, WP low during a STATUS register write sequence will disable writing to the STATUS register. If an internal write cycle has already begun, WP going low will have no effect on the write. DS20001830G-page 6 The WP pin function is blocked when the WPEN bit in the STATUS register is low. This allows the user to install the 25XX640A in a system with WP pin grounded and still be able to write to the STATUS register. The WP pin functions will be enabled when the WPEN bit is set high. 2.4 Serial Input (SI) The SI pin is used to transfer data into the device. It receives instructions, addresses and data. Data are latched on the rising edge of the serial clock. 2.5 Serial Clock (SCK) The SCK is used to synchronize the communication between a host and the 25XX640A. Instructions, addresses or data present on the SI pin are latched on the rising edge of the clock input, while data on the SO pin are updated after the falling edge of the clock input. 2.6 Hold (HOLD) The HOLD pin is used to suspend transmission to the 25XX640A while in the middle of a serial sequence without having to retransmit the entire sequence again. It must be held high any time this function is not being used. Once the device is selected and a serial sequence is underway, the HOLD pin may be pulled low to pause further serial communication without resetting the serial sequence. The HOLD pin must be brought low while SCK is low, otherwise the HOLD function will not be invoked until the next SCK high-to-low transition. The 25XX640A must remain selected during this sequence. The SI, SCK and SO pins are in a high-impedance state during the time the device is paused and transitions on these pins will be ignored. To resume serial communication, HOLD must be brought high while the SCK pin is low, otherwise serial communication will not resume. Lowering the HOLD line at any time will tri-state the SO line.  2003-2021 Microchip Technology Inc. 25AA640A/25LC640A 3.0 FUNCTIONAL DESCRIPTION 3.1 Principles of Operation BLOCK DIAGRAM The 25XX640A is an 8192-byte serial EEPROM designed to interface directly with the Serial Peripheral Interface (SPI) port of many of today’s popular microcontroller families, including Microchip’s PIC® microcontrollers. It may also interface with microcontrollers that do not have a built-in SPI port by using discrete I/O lines programmed properly in firmware to match the SPI protocol. The 25XX640A contains an 8-bit instruction register. The device is accessed via the SI pin, with data being clocked in on the rising edge of SCK. The CS pin must be low and the HOLD pin must be high for the entire operation. Table 3-1 contains a list of the possible instruction bytes and format for device operation. All instructions, addresses and data are transferred Most Significant Byte (MSB) first, Least Significant Byte (LSB) last. Data (SI) are sampled on the first rising edge of SCK after CS goes low. If the clock line is shared with other peripheral devices on the SPI bus, the user can assert the HOLD input and place the 25XX640A in ‘HOLD’ mode. After releasing the HOLD pin, operation will resume from the point when the HOLD was asserted. TABLE 3-1: STATUS Register I/O Control Logic HV Generator Memory Control Logic EEPROM Array X Dec Page Latches SI SO Y Decoder CS SCK Sense Amp. R/W Control HOLD WP VCC VSS INSTRUCTION SET Instruction Name Instruction Format READ 0000 0011 Read data from memory array beginning at selected address WRITE 0000 0010 Write data to memory array beginning at selected address WRDI 0000 0100 Reset the write enable latch (disable write operations) WREN 0000 0110 Set the write enable latch (enable write operations) RDSR 0000 0101 Read STATUS register WRSR 0000 0001 Write STATUS register  2003-2021 Microchip Technology Inc. Description DS20001830G-page 7 25AA640A/25LC640A 3.2 Read Sequence sent to the device before a write cycle is necessary. The only restriction is that all of the bytes must reside in the same page. The device is selected by pulling CS low. The 8-bit READ instruction is transmitted to the 25XX640A followed by the 16-bit address, with the three MSBs of the address being “don’t care” bits. After the correct READ instruction and address are sent, the data stored in the memory at the selected address are shifted out on the SO pin. The data stored in the memory at the next address can be read sequentially by continuing to provide clock pulses. The internal Address Pointer is automatically incremented to the next higher address after each byte of data is shifted out. When the highest address is reached (1FFFh), the address counter rolls over to address 0000h, allowing the read cycle to be continued indefinitely. The read operation is terminated by raising the CS pin (Figure 3-1). 3.3 Note: Page write operations are limited to writing bytes within a single physical page, regardless of the number of bytes actually being written. Physical page boundaries start at addresses that are integer multiples of the page buffer size (or ‘page size’) and, end at addresses that are integer multiples of page size – 1. If a Page Write command attempts to write across a physical page boundary, the result is that the data wraps around to the beginning of the current page (overwriting data previously stored there), instead of being written to the next page as might be expected. It is therefore necessary for the application software to prevent page write operations that would attempt to cross a page boundary. Write Sequence Prior to any attempt to write data to the 25XX640A, the write enable latch must be set by issuing the WREN instruction (Figure 3-4). This is done by setting CS low and then clocking out the proper instruction into the 25XX640A. After all eight bits of the instruction are transmitted, the CS must be brought high to set the write enable latch. If the write operation is initiated immediately after the WREN instruction without CS being brought high, the data will not be written to the array because the write enable latch will not have been properly set. For the data to be actually written to the array, the CS must be brought high after the Least Significant bit (D0) of the nth data byte has been clocked in. If CS is brought high at any other time, the write operation will not be completed. Refer to Figure 3-2 and Figure 3-3 for more detailed illustrations on the byte write sequence and the page write sequence, respectively. While the write is in progress, the STATUS register may be read to check the status of the WPEN, WIP, WEL, BP1 and BP0 bits (Figure 3-6). A read attempt of a memory array location will not be possible during a write cycle. When the write cycle is completed, the write enable latch is reset. Once the write enable latch is set, the user may proceed by setting the CS low, issuing a WRITE instruction, followed by the 16-bit address, with the three MSBs of the address being “don’t care” bits and then the data to be written. Up to 32 bytes of data can be FIGURE 3-1: READ SEQUENCE CS 0 1 2 3 4 5 6 7 8 9 10 11 21 22 23 24 25 26 27 28 29 30 31 SCK Instruction SI 0 0 0 0 0 16-bit Address 0 1 1 15 14 13 12 2 1 0 Data Out High-Impedance SO DS20001830G-page 8 7 6 5 4 3 2 1 0  2003-2021 Microchip Technology Inc. 25AA640A/25LC640A FIGURE 3-2: BYTE WRITE SEQUENCE CS Twc 0 1 2 3 4 5 6 8 7 9 10 11 21 22 23 24 25 26 27 28 29 30 31 SCK Instruction SI 0 0 0 0 0 16-bit Address 0 2 0 15 14 13 12 1 Data Byte 1 0 7 6 5 4 3 2 1 0 High-Impedance SO FIGURE 3-3: PAGE WRITE SEQUENCE CS 0 1 2 3 4 5 6 7 8 9 10 11 21 22 23 24 25 26 27 28 29 30 31 SCK Instruction SI 0 0 0 0 0 16-bit Address 0 1 Data Byte 1 2 0 15 14 13 12 1 0 7 6 5 4 3 2 1 0 CS 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 SCK Data Byte 2 SI 7 6 5 4 3 2  2003-2021 Microchip Technology Inc. Data Byte 3 1 0 7 6 5 4 3 2 Data Byte n (32 max.) 1 0 7 6 5 4 3 2 1 0 DS20001830G-page 9 25AA640A/25LC640A 3.4 Write Enable (WREN) and Write Disable (WRDI) The following is a list of conditions under which the write enable latch will be reset: • • • • The 25XX640A contains a write enable latch. See Table 5-1 for the Write-Protect Functionality Matrix. This latch must be set before any write operation will be completed internally. The WREN instruction will set the latch and the WRDI will reset the latch. FIGURE 3-4: Power-up WRDI instruction successfully executed WRSR instruction successfully executed WRITE instruction successfully executed WRITE ENABLE SEQUENCE (WREN) CS 0 1 2 3 4 5 6 7 SCK 0 SI 0 0 0 1 1 0 High-Impedance SO FIGURE 3-5: 0 WRITE DISABLE SEQUENCE (WRDI) CS 0 1 2 3 4 5 6 7 SCK SI 0 0 0 0 0 1 0 0 High-Impedance SO DS20001830G-page 10  2003-2021 Microchip Technology Inc. 25AA640A/25LC640A 3.5 Read STATUS Register Instruction (RDSR) The Write Enable Latch (WEL) bit indicates the status of the write enable latch and is read-only. When set to a ‘1’, the latch allows writes to the array, when set to a ‘0’, the latch prohibits writes to the array. The state of this bit can always be updated via the WREN or WRDI commands regardless of the state of write protection on the STATUS register. These commands are shown in Figure 3-4 and Figure 3-5. The Read STATUS Register instruction (RDSR) provides access to the STATUS register. The STATUS register may be read at any time, even during a write cycle. The STATUS register is formatted as shown in Table 3-2. TABLE 3-2: The Block Protection (BP0 and BP1) bits indicate which blocks are currently write-protected. These bits are set by the user issuing the WRSR instruction. These bits are nonvolatile and are shown in Table 3-3. STATUS REGISTER 7 6 5 4 3 2 1 0 W/R – – – W/R W/R R R WPEN X X X BP1 BP0 WEL WIP See Figure 3-6 for the RDSR timing sequence. The STATUS register can be continually read until the CS is deasserted. W/R = writable/readable. R = read-only. The Write-In-Process (WIP) bit indicates whether the 25XX640A is busy with a write operation. When set to a ‘1’, a write is in progress, when set to a ‘0’, no write is in progress. This bit is read-only. FIGURE 3-6: READ STATUS REGISTER TIMING SEQUENCE (RDSR) CS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 1 0 SCK Instruction SI 0 0 0 0 0 High-Impedance SO  2003-2021 Microchip Technology Inc. 1 0 1 Data from STATUS Register 7 6 5 4 3 2 DS20001830G-page 11 25AA640A/25LC640A 3.6 Write STATUS Register Instruction (WRSR) TABLE 3-3: The Write STATUS Register instruction (WRSR) allows the user to write to the nonvolatile bits in the STATUS register as shown in Table 3-3. The user is able to select one of four levels of protection for the array by writing to the appropriate bits in the STATUS register. The array is divided up into four segments. The user has the ability to write-protect none, one, two, or all four of the segments of the array. The partitioning is controlled as shown in Table 3-3. ARRAY PROTECTION BP1 BP0 Array Addresses Write-Protected 0 0 none 0 1 upper 1/4 (1800h-1FFFh) 1 0 upper 1/2 (1000h-1FFFh) 1 1 all (0000h-1FFFh) The Write-Protect Enable (WPEN) bit is a nonvolatile bit that is available as an enable bit for the WP pin. The Write-Protect (WP) pin and the Write-Protect Enable (WPEN) bit in the STATUS register control the programmable hardware write-protect feature. Hardware write protection is enabled when WP pin is low and the WPEN bit is high. Hardware write protection is disabled when either the WP pin is high or the WPEN bit is low. When the chip is hardware write-protected, only writes to nonvolatile bits in the STATUS register are disabled. See Table 5-1 for a matrix of functionality on the WPEN bit. See Figure 3-7 for the WRSR timing sequence. FIGURE 3-7: WRITE STATUS REGISTER TIMING SEQUENCE (WRSR) CS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 1 0 SCK Instruction SI 0 0 0 0 Data to STATUS Register 0 0 0 1 7 6 5 4 3 2 High-Impedance SO Note: An internal write cycle (TWC) is initiated on the rising edge of CS after a valid write STATUS register sequence. DS20001830G-page 12  2003-2021 Microchip Technology Inc. 25AA640A/25LC640A 4.0 DATA PROTECTION 5.0 The following protection has been implemented to prevent inadvertent writes to the array: • The write enable latch is reset on power-up • A write enable instruction must be issued to set the write enable latch • After a byte write, page write or STATUS register write, the write enable latch is reset • CS must be set high after the proper number of clock cycles to start an internal write cycle • Access to the array during an internal write cycle is ignored and programming is continued TABLE 5-1: POWER-ON STATE The 25XX640A powers on in the following state: • The device is in low-power Standby mode (CS = 1) • The write enable latch is reset • SO is in high-impedance state • A high-to-low-level transition on CS is required to enter active state WRITE-PROTECT FUNCTIONALITY MATRIX WEL (SR bit 1) WPEN (SR bit 7) WP (pin 3) Protected Blocks Unprotected Blocks STATUS Register 0 x x Protected Protected Protected 1 0 x Protected Writable Writable 1 1 0 (low) Protected Writable Protected 1 1 1 (high) Protected Writable Writable x = don’t care  2003-2021 Microchip Technology Inc. DS20001830G-page 13 25AA640A/25LC640A 6.0 PACKAGING INFORMATION 6.1 Package Marking Information 8-Lead DFN-S (5x6x1 mm) XXXXXXX XXXXXXX XXYYWW NNN 8-Lead MSOP (150 mil) XXXXXT YWWNNN Example: 5LC640A E/MF e3 2112 13F Example: 5LCAI 11213F 8-Lead PDIP Example: XXXXXXXX T/XXXNNN YYWW 25LC640A I/P e3 13F 2112 8-Lead SOIC Example: XXXXXXXT XX/XXYYWW NNN 25L640AI SN e3 2112 13F 8-Lead 2x3 TDFN Example: XXX YWW NN C81 112 13 8-Lead TSSOP XXXX TYWW NNN DS20001830G-page 14 Example: 5LCA I112 13F  2003-2021 Microchip Technology Inc. 25AA640A/25LC640A 1st Line Marking Codes Part Number TDFN MSOP I-Temp. E-Temp. TSSOP Rotated TSSOP 25AA640A 5ACAT C81 EG2 5ACA ACAX 25LC640A 5LCAT C84 C85 5LCA LCAX Legend: XX...X T Y YY WW NNN e3 Part number or part number code Temperature (I, E) Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week ‘01’) Alphanumeric traceability code (2 characters for small packages) Pb-free JEDEC designator for Matte Tin (Sn) Note: For very small packages with no room for the Pb-free JEDEC designator e3 , the marking will only appear on the outer carton or reel label. Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information.  2003-2021 Microchip Technology Inc. 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