2N7002
N-Channel Enhancement-Mode Vertical DMOS FET
Features
General Description
•
•
•
•
•
•
•
The 2N7002 is a low-threshold, Enhancement-mode
(normally-off) transistor that uses a vertical DMOS
structure and a well-proven silicon-gate manufacturing
process. This combination produces a device with the
power handling capabilities of bipolar transistors and
the high input impedance and positive temperature
coefficient inherent in MOS devices. Characteristic of
all MOS structures, this device is free from thermal
runaway and thermally induced secondary breakdown.
Free from Secondary Breakdown
Low Power Drive Requirement
Ease of Paralleling
Low CISS and Fast Switching Speeds
Excellent Thermal Stability
Integral Source-Drain Diode
High Input Impedance and High Gain
Applications
•
•
•
•
•
•
Microchip’s vertical DMOS FETs are ideally suited to a
wide range of switching and amplifying applications
where very low threshold voltage, high breakdown
voltage, high input impedance, low input capacitance
and fast switching speeds are desired.
Motor Controls
Converters
Amplifiers
Switches
Power Supply Circuits
Drivers (Relays, Hammers, Solenoids, Lamps,
Memories, Displays, Bipolar Transistors, etc.)
Package Type
3-lead SOT-23
(Top view)
DRAIN
SOURCE
GATE
See Table 3-1 for pin information.
2018 Microchip Technology Inc.
DS20005797A-page 1
2N7002
1.0
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings†
Drain-to-Source Voltage ...................................................................................................................................... BVDSS
Drain-to-Gate Voltage ......................................................................................................................................... BVDGS
Gate-to-Source Voltage ......................................................................................................................................... ±30V
Operating Ambient Temperature, TA ................................................................................................... –55°C to +150°C
Storage Temperature, TS ..................................................................................................................... –55°C to +150°C
† Notice: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only, and functional operation of the device at those or any other conditions above those
indicated in the operational sections of this specification is not intended. Exposure to maximum rating conditions for
extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
Electrical Specifications: TA = 25°C unless otherwise specified. (Note 1)
Parameter
Sym.
Min.
Typ.
Drain-to-Source Breakdown Voltage
BVDSS
60
—
—
V
VGS = 0V, ID = 10 µA
Gate Threshold Voltage
VGS(th)
1
—
2.5
V
VGS = VDS, ID = 250 µA
∆VGS(th)
—
—
–5.5
mV/°C
VGS = VDS, ID = 250 µA
(Note 2)
IGSS
—
—
±100
nA
VGS = ±20V, VDS = 0V
—
—
1
—
—
500
500
—
—
—
—
7.5
—
—
7.5
—
—
1
Change in VGS(th) with Temperature
Gate Body Leakage Current
Zero-Gate Voltage Drain Current
On-State Drain Current
IDSS
ID(ON)
Static Drain-to-Source On-State
Resistance
RDS(ON)
Change in RDS(ON) with Temperature
∆RDS(ON)
Note 1:
2:
Max.
Unit
µA
mA
Ω
%/°C
Conditions
VGS = 0V, VDS = Maximum
Rating
VGS = 0V, VDS = 0.8 Maximum
Rating, TA = 125°C (Note 2)
VGS = 10V, VDS = 25V
VGS = 5V, ID = 50 mA
VGS = 10V, ID = 500 mA
VGS = 10V, ID = 500 mA
(Note 2)
All DC parameters are 100% tested at 25°C unless otherwise stated.
(Pulse test: 300 µs pulse, 2% duty cycle)
Specification is obtained by characterization and is not 100% tested.
DS20005797A-page 2
2018 Microchip Technology Inc.
2N7002
AC ELECTRICAL CHARACTERISTICS
Electrical Specifications: TA = 25°C unless otherwise specified. (Note 2)
Parameter
Forward Transconductance
Sym.
Min.
Typ.
Max.
GFS
80
—
—
Input Capacitance
CISS
—
—
50
Common Source Output Capacitance
COSS
—
—
25
Reverse Transfer Capacitance
CRSS
—
—
5
Turn-On Time
t(ON)
—
—
20
t(OFF)
—
VSD
trr
Turn-Off Time
Unit
Conditions
mmho VDS = 25V, ID = 500 mA
pF
VGS = 0V,
VDS = 25V,
f = 1 MHz
ns
VDD = 30V,
ID = 200 mA,
RGEN = 25Ω
—
20
—
1.2
—
V
VGS = 0V, ISD = 200 mA (Note 1)
—
400
—
ns
VGS = 0V, ISD = 800 mA
DIODE PARAMETER (Note 2)
Diode Forward Voltage Drop
Reverse Recovery Time
Note 1:
2:
All DC parameters are 100% tested at 25°C unless otherwise stated.
(Pulse test: 300 µs pulse, 2% duty cycle)
Specification is obtained by characterization and is not 100% tested.
TEMPERATURE SPECIFICATIONS
Parameter
Sym.
Min.
Typ.
Max.
Unit
Operating Ambient Temperature
TA
–55
—
+150
°C
Storage Temperature
TS
–55
—
+150
°C
JA
—
203
—
°C/W
Conditions
TEMPERATURE RANGE
PACKAGE THERMAL RESISTANCE
3-lead SOT-23
THERMAL CHARACTERISTICS
Package
3-lead SOT-23
Note 1:
ID (Note 1)
(Continuous)
(mA)
115
Power Dissipation at
ID
(Pulsed)
TA = 25°C
(mA)
(W)
800
0.36
IDR (Note 1)
(mA)
IDRM
(mA)
115
800
ID (continuous) is limited by maximum TJ.
2018 Microchip Technology Inc.
DS20005797A-page 3
2N7002
2.0
TYPICAL PERFORMANCE CURVES
Note:
The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g. outside specified power supply range) and therefore outside the warranted range.
2.0
2.0
VGS = 10V
1.6
VGS = 10V
1.6
8V
0.8
7V
9V
ID (amperes)
ID (amperes)
9V
1.2
1.2
8V
0.8
7V
6V
6V
0.4
0.4
5V
4V
3V
0
0
10
20
30
40
50
5V
4V
0
0
2
4
VDS (volts)
FIGURE 2-1:
6
8
10
3V
VDS (volts)
Output Characteristics.
FIGURE 2-4:
0.5
Saturation Characteristics.
0.5
VDS = 25V
0.4
TA = -55OC
0.3
PD (watts)
GFS (seimens)
0.4
25OC
0.2
125OC
0.1
0
0.3
SOT-23
0.2
0.1
0
0.2
0.4
0.6
0.8
0
10
0
25
50
ID (amperes)
Transconductance vs. Drain
FIGURE 2-2:
Current.
75
100
125
150
TC (OC)
FIGURE 2-5:
Temperature.
1.0
Power Dissipation vs. Case
1.0
Thermal Resistance (normalized)
SOT-23 (pulsed)
ID (amperes)
SOT-23 (DC)
0.1
0.01
TA = 25OC
0.001
0.1
1.0
10
100
VDS (volts)
FIGURE 2-3:
Operating Area.
DS20005797A-page 4
Maximum Rated Safe
0.8
0.6
0.4
SOT-23
TA = 25OC
PD = 0.36W
0.2
0
0.001
0.01
0.1
1.0
10
tp (seconds)
FIGURE 2-6:
Characteristics.
Thermal Response
2018 Microchip Technology Inc.
2N7002
10
1.1
VGS = 5.0V
RDSS(ON) (ohms)
BVDSS (normalized)
8
1.0
VGS = 10V
6
4
2
0.9
-50
0
50
100
0
150
0
0.5
Tj (OC)
FIGURE 2-7:
Temperature.
1.0
1.5
2.0
2.5
ID (amperes)
BVDSS Variation with
On-Resistance vs. Drain
FIGURE 2-10:
Current.
2.0
2.0
VDS = 25V
1.4
RDS(ON) @ 10V, 0.5A
1.6
1.6
VGS(th) (normalized)
ID (amperes)
TA = -55 C
1.2
O
25 C
0.8
125OC
1.2
1.2
1.0
0.8
VGS(th) @ 1.0mA
0.8
RDS(ON) (normalized)
O
0.4
0.4
0.6
0
0
2
4
6
8
10
-50
0
0
150
100
O
Tj ( C)
VGS (volts)
FIGURE 2-8:
50
Transfer Characteristics.
FIGURE 2-11:
VGS(th) and RDS(ON)
Variation with Temperature.
10
50
f = 1.0MHz
VDS = 10V
VGS (volts)
C (picofarads)
8
CISS
25
90 pF
6
VDS = 40V
4
2
30 pF
COSS
CRSS
0
0
10
20
VDS (volts)
30
FIGURE 2-9:
Capacitance vs.
Drain-to-Source Voltage.
2018 Microchip Technology Inc.
0
0
40
0.2
0.4
0.6
0.8
1.0
QG (nanocoulombs)
FIGURE 2-12:
Characteristics.
Gate Drive Dynamic
DS20005797A-page 5
2N7002
3.0
PIN DESCRIPTION
Table 3-1 shows the description of pins in 2N7002.
Refer to Package Type for the location of pins.
TABLE 3-1:
PIN FUNCTION TABLE
Pin Number
Pin Name
1
Gate
2
Source
3
Drain
DS20005797A-page 6
Description
Gate
Source
Drain
2018 Microchip Technology Inc.
2N7002
4.0
FUNCTIONAL DESCRIPTION
Figure 4-1 illustrates the switching waveforms and test
circuit for 2N7002.
10V
VDD
90%
Pulse
Generator
INPUT
0V
10%
t(ON)
td(ON)
VDD
tr
td(OFF)
0V
tf
10%
90%
FIGURE 4-1:
OUTPUT
RGEN
10%
OUTPUT
TABLE 4-1:
t(OFF)
RL
INPUT
D.U.T.
90%
Switching Waveforms and Test Circuit.
PRODUCT SUMMARY
BVDSS/BVDGS
(V)
RDS(ON)
(Maximum)
(Ω)
ID(ON)
(Minimum)
(mA)
60
7.5
500
2018 Microchip Technology Inc.
DS20005797A-page 7
2N7002
5.0
PACKAGING INFORMATION
5.1
Package Marking Information
3-lead SOT-23
XXXNNN
Legend: XX...X
Y
YY
WW
NNN
e3
*
Note:
DS20005797A-page 8
Example
702149
Product Code or Customer-specific information
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Pb-free JEDEC® designator for Matte Tin (Sn)
This package is Pb-free. The Pb-free JEDEC designator ( e3 )
can be found on the outer packaging for this package.
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for product code or customer-specific information. Package may or
not include the corporate logo.
2018 Microchip Technology Inc.
2N7002
3-Lead TO-236AB (SOT-23) Package Outline (K1/T)
2.90x1.30mm body, 1.12mm height (max), 1.90mm pitch
D
3
E1 E
Gauge
Plane
0.25
1
Seating
Plane
L
2
e
L1
b
e1
View B
Top View
View B
A
A
A2
Seating
Plane
A1
Side View
View A - A
A
Note: For the most current package drawings, see the Microchip Packaging Specification at www.microchip.com/packaging.
Symbol
Dimension
(mm)
A
A1
A2
b
D
E
E1
MIN
0.89
0.01
0.88
0.30
2.80
2.10
1.20
NOM
-
-
0.95
-
2.90
-
1.30
MAX
1.12
0.10
1.02
0.50
3.04
2.64
1.40
e
0.95
BSC
e1
1.90
BSC
L
0.20†
0.50
0.60
L1
0.54
REF
ș
0O
8O
JEDEC Registration TO-236, Variation AB, Issue H, Jan. 1999.
† This dimension differs from the JEDEC drawing.
Drawings not to scale.
2018 Microchip Technology Inc.
DS20005797A-page 9
2N7002
NOTES:
DS20005797A-page 10
2018 Microchip Technology Inc.
2N7002
APPENDIX A:
REVISION HISTORY
Revision A (September 2018)
• Converted Supertex Doc# DSFP-2N7002 to
Microchip DS20005797A
• Changed the package marking format
• Added some sections to comply with standard
Microchip Technology documentation format
• Made minor text changes throughout the document
2018 Microchip Technology Inc.
DS20005797A-page 11
2N7002
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, contact your local Microchip representative or sales office.
XX
PART NO.
-
Package
Options
Device
X
-
Environmental
X
Media Type
Device:
2N7002
=
N-Channel Enhancement-Mode Vertical
DMOS FET
Package:
(blank)
=
3-lead SOT-23
Environmental:
G
=
Lead (Pb)-free/RoHS-compliant Package
Media Type:
(blank)
=
3000/Reel for an SOT-23 Package
DS20005797A-page 12
Example:
a) 2N7002-G:
N-Channel Enhancement-Mode
Vertical DMOS FET, 3-lead SOT-23,
3000/Reel
2018 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
•
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
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OTHERWISE, RELATED TO THE INFORMATION,
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© 2018, Microchip Technology Incorporated, All Rights Reserved.
ISBN: 978-1-5224-3477-1
== ISO/TS 16949 ==
2018 Microchip Technology Inc.
DS20005797A-page 13
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DS20005797A-page 14
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08/15/18
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