34LC02-E/MS

34AA02/34LC02 2-Kbit I2C Serial EEPROM Software Write-Protect Device Selection Table Part Number VCC Range Max. Clock Frequency Temp. Ranges Packages 34AA02 1.7V-5.5V 400 kHz(1) I, E MS, P. SN, OT, MNY, ST 34LC02 2.2V-5.5V 1 MHz I, E MS, P. SN, OT, MNY, ST Note 1: 100 kHz for VCC 4,000V • Software Write Protection for Lower 128 Bytes • Hardware Write Protection for Entire Array • More than 1 Million Erase/Write Cycles • Data Retention > 200 Years • RoHS Compliant • Available for Extended Temperature Ranges: - Industrial (I): -40°C to +85°C - Extended (E): -40°C to +125°C • Automotive AEC-Q100 Qualified • 8-Lead MSOP, 8-Lead PDIP, 8-Lead SOIC, 6-Lead SOT-23, 8-Lead TDFN and 8-Lead TSSOP Description The Microchip Technology Inc. 34XX02(1) is a 2-Kbit Electrically Erasable PROM (EEPROM). This device has two software write-protect features for the lower half of the array, as well as an external pin that can be used to write-protect the entire array. This allows the system designer to protect none, half or all of the array, depending on the application. The device is organized as one block of 256 x 8-bit memory with a two-wire serial interface. Its low-voltage design permits operation down to 1.7V, with standby and active currents of only 100 nA and 1 mA, respectively. The 34XX02 also has a page write capability for up to 16 bytes of data. Note 1: 34XX02 is used in this document as a generic part number for the 34AA02/34LC02 devices. Package Types MSOP/PDIP/SOIC/TSSOP A0 1 8 VCC A1 2 7 WP A2 3 6 SCL VSS 4 5 SDA SOT-23 TDFN VCC 1 6 SCL A0 2 5 VSS A1 3 4 SDA  2007-2022 Microchip Technology Inc. and its subsidiaries A0 1 8 VCC A1 2 7 WP A2 3 6 SCL VSS 4 5 SDA DS20002029G-page 1 34AA02/34LC02 Block Diagram A0 A1 A2 I/O Control Logic WP Memory Control Logic SDA SCL Vcc Vss HV Generator XDEC Software writeprotected area (00h-7Fh) Standard Array Write-Protect Circuitry YDEC Sense Amp. R/W Control DS20002029G-page 2  2007-2022 Microchip Technology Inc. and its subsidiaries 34AA02/34LC02 1.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings(†) VCC.............................................................................................................................................................................6.5V All inputs and outputs w.r.t. VSS ..........................................................................................................-0.3V to VCC +1.0V Storage temperature ............................................................................................................................... -65°C to +150°C Ambient temperature with power applied................................................................................................ -40°C to +125°C ESD protection on all pins  4 kV † NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions above those indicated in the operation sections of the specifications is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. TABLE 1-1: DC SPECIFICATIONS Electrical Characteristics: Industrial (I): TA = -40°C to +85°C Extended (E): TA = -40°C to +125°C DC CHARACTERISTICS Param. No. Symbol Characteristic Min. Typical Max. Units Conditions D1 VIH High-Level Input Voltage 0.7 VCC — — V D2 VIL Low-Level Input Voltage — — 0.3 VCC V 0.2 VCC for VCC < 2.5V D3 VHYS Hysteresis of Schmitt Trigger Inputs 0.05 Vcc — — V Note 1 D4 VOL Low-Level Output Voltage — — 0.40 V IOL = 3.0 mA, VCC = 2.5V 7 — 10 V A0 Pin only, VCC < 2.2V VCC + 4.8 — 10 V A0 Pin only, VCC  2.2V 10 — VCC + 4.8 V A0 Pin only, VCC  5.2V D5 VHV High-Voltage Detect D6 ILI Input Leakage Current — — ±1 µA VIN = VSS or VCC D7 ILO Output Leakage Current — — ±1 µA VOUT = VSS or VCC D8 CIN, COUT Pin Capacitance (all inputs/outputs) — — 10 pF VCC = 5.5V (Note 1) TA = +25°C, FCLK = 1 MHz D9 ICC Write D10 ICC Read D11 Note 1: ICCS Operating Current — 0.1 3 mA VCC = 5.5V, SCL = 1 MHz — 0.05 1 mA VCC = 5.5V, SCL = 1 MHz — 0.01 1 µA SDA = SCL = VCC, A0, A1, A2, WP = VSS, I-Temp. — — 5 µA SDA = SCL = VCC, A0, A1, A2, WP = VSS, E-Temp. Standby Current This parameter is periodically sampled and not 100% tested.  2007-2022 Microchip Technology Inc. and its subsidiaries DS20002029G-page 3 34AA02/34LC02 TABLE 1-2: AC SPECIFICATIONS Electrical Characteristics: Industrial (I): TA = -40°C to +85°C Extended (E): TA = -40°C to +125°C AC CHARACTERISTICS Param. Symbol No. 1 2 3 4 5 6 7 FCLK THIGH TLOW TR TF Thd:sta TSU:STA Characteristic Clock Frequency Clock High Time Clock Low Time SDA and SCL Rise Time SDA and SCL Fall Time Start Condition Hold Time Start Condition Setup Time Min. Max. Units Conditions — 100 kHz 1.7V  VCC < 1.8V — 400 kHz 1.8V  VCC  5.5V — 1000 kHz 2.5V  VCC  5.5V (34LC02) 4000 — ns 1.7V  VCC < 1.8V 600 — ns 1.8V  VCC  5.5V 500 — ns 2.5V  VCC  5.5V (34LC02) 4700 — ns 1.7V  VCC < 1.8V 1300 — ns 1.8V  VCC  5.5V 500 — ns 2.5V  VCC  5.5V (34LC02) — 1000 ns 1.7V  VCC < 1.8V (Note 1) — 300 ns 1.8V  VCC  5.5V (Note 1) — 300 ns 2.5V  VCC  5.5V (34LC02) (Note 1) — 1000 ns 1.7V  VCC < 1.8V (Note 1) — 300 ns 1.8V  VCC  5.5V (Note 1) — 300 ns 2.5V  VCC  5.5V (34LC02) (Note 1) 4000 — ns 1.7V  VCC < 1.8V 600 — ns 1.8V  VCC  5.5V 250 — ns 2.5V  VCC  5.5V (34LC02) 4700 — ns 1.7V  VCC < 1.8V 600 — ns 1.8V  VCC  5.5V 250 — ns 2.5V  VCC  5.5V (34LC02) — ns Note 2 8 THD:DAT Data Input Hold Time 0 250 — ns 1.7V  VCC < 1.8V 9 TSU:DAT Data Input Setup Time 100 — ns 1.8V  VCC  5.5V 10 11 12 TSU:STO TSU:WP THD:WP Stop Condition Setup Time WP Setup Time WP Hold Time 100 — ns 2.5V  VCC  5.5V (34LC02) 4000 — ns 1.7V  VCC < 1.8V 600 — ns 1.8V  VCC  5.5V 250 — ns 2.5V  VCC  5.5V (34LC02) 4000 — ns 1.7V  VCC < 1.8V 600 — ns 1.8V  VCC  5.5V 600 — ns 2.5V  VCC  5.5V (34LC02) 4700 — ns 1.7V  VCC < 1.8V 600 — ns 1.8V  VCC  5.5V 600 — ns 2.5V  VCC  5.5V (34LC02) Note 1: Not 100% tested. CB = total capacitance of one bus line in pF. 2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions. 3: The combined TSP and VHYS specifications are due to new Schmitt Trigger inputs, which provide improved noise spike suppression. This eliminates the need for a TI specification for standard operation. 4: This parameter is not tested but ensured by characterization. DS20002029G-page 4  2007-2022 Microchip Technology Inc. and its subsidiaries 34AA02/34LC02 TABLE 1-2: AC SPECIFICATIONS Electrical Characteristics: Industrial (I): TA = -40°C to +85°C Extended (E): TA = -40°C to +125°C AC CHARACTERISTICS Param. Symbol No. 13 14 TAA TBUF Characteristic Output Valid from cloCk Min. Max. Units — 3500 ns 1.7V  VCC < 1.8V (Note 2) — 900 ns 1.8V  VCC  5.5V (Note 2) — 400 ns 2.5V  VCC  5.5V (34LC02) (Note 2) Bus Free Time: The time the bus must be free before a new transmission can start 4700 — ns 1.7V  VCC < 1.8V 1300 — ns 1.8V  VCC  5.5V 500 — ns 2.5V  VCC  5.5V (34LC02) 34AA02 (Note 1 and Note 3) 15 TSP Input Filter Spike Suppression (SDA and SCL pins) — 50 ns 16 TWC Write Cycle Time (byte or page) — 5 ms 1,000,000 — cycles 17 Conditions Endurance +25°C, 5.5V, Page Mode (Note 4) Note 1: Not 100% tested. CB = total capacitance of one bus line in pF. 2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions. 3: The combined TSP and VHYS specifications are due to new Schmitt Trigger inputs, which provide improved noise spike suppression. This eliminates the need for a TI specification for standard operation. 4: This parameter is not tested but ensured by characterization.  2007-2022 Microchip Technology Inc. and its subsidiaries DS20002029G-page 5 34AA02/34LC02 FIGURE 1-1: BUS TIMING DATA 5 SCL 7 SDA In 3 4 D4 2 8 10 9 6 16 14 13 SDA Out WP DS20002029G-page 6 (protected) (unprotected) 11 12  2007-2022 Microchip Technology Inc. and its subsidiaries 34AA02/34LC02 2.0 PIN DESCRIPTIONS The descriptions of the pins are listed in Table 2-1. TABLE 2-1: PIN FUNCTION TABLE Name MSOP PDIP SOIC SOT-23 TDFN TSSOP A0 1 1 1 5 1 1 Chip Address Input A1 2 2 2 4 2 2 Chip Address Input A2 3 3 3 — 3 3 Chip Address Input VSS 4 4 4 2 4 4 Ground 2.1 SDA 5 5 5 3 5 5 Serial Address/Data I/O SCL 6 6 6 1 6 6 Serial Clock WP 7 7 7 — 7 7 Write-Protect Input VCC 8 8 8 6 8 8 Power Supply A0, A1, A2 Chip Address Inputs The levels on these inputs are compared with the corresponding bits in the client address. The chip is selected if the compare is true. Up to eight 34XX02 devices (four for the SOT-23 package) may be connected to the same bus by using different Chip Select bit combinations. These inputs must be connected to either VSS or VCC. The A0 pin is also used to detect VHV. 2.2 Description 2.3 Serial Clock (SCL) This input is used to synchronize the data transfer to and from the device. 2.4 Write-Protect (WP) This is the hardware write-protect pin. It can be tied to VCC or VSS. If tied to VCC, the hardware write protection is enabled. If the WP pin is tied to VSS, the hardware write protection is disabled. Serial Address/Data Input/Output (SDA) This is a bidirectional pin used to transfer addresses and data into and data out of the device. It is an open-drain terminal. Therefore, the SDA bus requires a pull-up resistor to VCC (typical 10 k for 100 kHz, 2 k for 400 kHz and 1 MHz). For normal data transfer, SDA is allowed to change only during SCL low. Changes during SCL high are reserved for indicating the Start and Stop conditions.  2007-2022 Microchip Technology Inc. and its subsidiaries DS20002029G-page 7 34AA02/34LC02 3.0 FUNCTIONAL DESCRIPTION The 34XX02 has two Software Write-Protect features that allow the user to protect half of the array from being written (Addresses 00h-7Fh). One command, Software Write-Protect (SWP) will prevent writes to half of the array and is resettable by using the Clear Software Write-Protect (CSWP) command. The other command is Permanent Software Write-Protect (PSWP), which is not resettable and will permanently lock half the array from being written to. The device still has an external pin (WP) that allows the user to protect the entire array if so desired. The 34XX02 supports a bidirectional two-wire bus and data transmission protocol. A device that sends data onto the bus is defined as a transmitter and a device receiving data, as a receiver. The bus has to be controlled by a host device, which generates the Serial Clock (SCL), controls the bus access and generates the Start and Stop conditions, while the 34XX02 works as client. Both host and client can operate as transmitter or receiver, but the host device determines which mode is activated. 4.0 BUS CHARACTERISTICS The following bus protocol has been defined: • Data transfer may be initiated only when the bus is not busy • During data transfer, the data line must remain stable whenever the clock line is high. Changes in the data line while the clock line is high will be interpreted as a Start or Stop condition Accordingly, the following bus conditions have been defined (Figure 4-1). 4.1 Bus Not Busy (A) Both data and clock lines remain high. 4.2 Start Data Transfer (B) A high-to-low transition of the SDA line while the clock (SCL) is high determines a Start condition. All commands must be preceded by a Start condition. FIGURE 4-1: SCL (A) 4.3 Stop Data Transfer (C) A low-to-high transition of the SDA line while the clock (SCL) is high determines a Stop condition. All operations must be ended with a Stop condition. 4.4 Data Valid (D) The state of the data line represents valid data when, after a Start condition, the data line is stable for the duration of the high period of the clock signal. The data on the line must be changed during the low period of clock signal. There is one clock pulse per bit of data. Each data transfer is initiated with a Start condition and terminated with a Stop condition. The number of data bytes transferred between the Start and Stop conditions is determined by the host device and is, theoretically, unlimited; although only the last 16 bytes will be stored when doing a write operation. When an overwrite does occur, it will replace data in a First-In First-Out (FIFO) principle. 4.5 Acknowledge Each receiving device, when addressed, is obliged to generate an Acknowledge after the reception of each byte. Exceptions to this rule relating to software write protection are described in Section 7.0 “Write Protection”. The host device must generate an extra clock pulse which is associated with this Acknowledge bit. Note: The 34XX02 does not generate any Acknowledge bits if an internal programming cycle is in progress. The device that acknowledges has to pull down the SDA line during the Acknowledge clock pulse in such a way that the SDA line is stable-low during the high period of the Acknowledge-related clock pulse. Moreover, setup and hold times must be taken into account. During reads, a host must signal an end-of-data to the client by not generating an Acknowledge bit on the last byte that has been clocked out of the client. In this case, the client (34XX02) will leave the data line high to enable the host to generate the Stop condition. DATA TRANSFER SEQUENCE ON THE SERIAL BUS (B) (D) Start Condition Address or Acknowledge Valid (D) (C) (A) SDA DS20002029G-page 8 Data Allowed to Change Stop Condition  2007-2022 Microchip Technology Inc. and its subsidiaries 34AA02/34LC02 5.0 DEVICE ADDRESSING A control byte is the first byte received following the Start condition from the host device. The first part of the control byte consists of a 4-bit control code which is set to ‘1010’ for normal read and write operations and ‘0110’ for writing to the write-protect register. The control byte is followed by three Chip Select bits (A2, A1, A0). The Chip Select bits allow the use of up to eight 34XX02 devices on the same bus and are used to determine which device is accessed. The Chip Select bits in the control byte must correspond to the logic levels on the corresponding A2, A1 and A0 pins for the device to respond. These bits are in effect the three Most Significant bits of the word address. The combination of the 4-bit control code and the next three bits are called the client address. Control Code Chip Select R/W Read 1010 A2 A1 A0 1 Write 1010 A2 A1 A0 0 Write-Protect Register 0110 A2 A1 A0 0 Operation FIGURE 5-1: CONTROL BYTE FORMAT Start Read/Write R/W A Client Address 1 For the SOT-23 package, the A2 pin is not connected. During device addressing, the A2 Chip Select bit should be set to ‘0’. Only four 34XX02 SOT-23 packages can be connected to the same bus. 0 1 0 A2 A1 A0 A2 A1 A0 OR 0 0 1 1 The last bit of the control byte is the Read/Write (R/W) bit and it defines the operation to be performed. When set to a ‘1’, a read operation is selected. When set to a '0', a write operation is selected. Following the Start condition, the 34XX02 monitors the SDA bus, checking the device type identifier being transmitted. Upon receiving a valid client address and the R/W bit, the client device outputs an Acknowledge signal on the SDA line. Depending on the state of the R/W bit, the 34XX02 will select a read or write operation. The next byte received defines the address of the first data byte within the selected block (Figure 5-2). The word address byte uses all eight bits. FIGURE 5-2: ADDRESS SEQUENCE BIT ASSIGNMENTS Control Byte 1 0 1 Control Code 0 x x Word Address Byte x R/W A 7 • • • • • • A 0 Chip Select bits x = “don’t care”  2007-2022 Microchip Technology Inc. and its subsidiaries DS20002029G-page 9 34AA02/34LC02 6.0 WRITE OPERATIONS 6.1 Byte Write Upon receipt of each word, the four lower order Address Pointer bits, which form the byte counter, are internally incremented by one. The higher order four bits of the word address remain constant. If the host should transmit more than 16 bytes prior to generating the Stop condition, the Address Pointer will roll over and the previously received data will be overwritten. As with the byte write operation, once the Stop condition is received, an internal write cycle will begin (Figure 6-2). Following the Start signal from the host, the device code(4 bits), the Chip Select bits (3 bits) and the R/W bit, which is a logic-low, are placed onto the bus by the host transmitter. This indicates to the addressed client receiver that a byte with a word address will follow, once it has generated an Acknowledge bit during the ninth clock cycle. Therefore, the next byte transmitted by the host is the word address and will be written into the Address Pointer of the 34XX02. After receiving another Acknowledge signal from the 34XX02, the host device will transmit the data word to be written into the addressed memory location. The 34XX02 acknowledges again and the host generates a Stop condition. This initiates the internal write cycle, which means that during this time, the 34XX02 will not generate Acknowledge signals (Figure 6-1). If an attempt is made to write to the array when the hardware write protection has been enabled, the device will acknowledge the command, but no data will be written. The write cycle time must be observed even if the write protection is enabled. Note: If an attempt is made to write to the array when the software or hardware write protection has been enabled, the device will acknowledge the command, but no data will be written. The write cycle time must be observed even if the write protection is enabled. 6.2 Page Write The write control byte, word address and the first data byte are transmitted to the 34XX02 in the same way as in a byte write. Instead of generating a Stop condition, the host transmits up to 15 additional data bytes to the 34XX02, which are temporarily stored in the on-chip page buffer and will be written into the memory after the host has transmitted a Stop condition. FIGURE 6-1: Page write operations are limited to writing bytes within a single physical page, regardless of the number of bytes actually being written. Physical page boundaries start at addresses that are integer multiples of the page buffer size (or ‘page size’) and end at addresses that are integer multiples of page size – 1. If a page write command attempts to write across a physical page boundary, the result is that the data wrap around to the beginning of the current page (overwriting data previously stored there), instead of being written to the next page, as might be expected. It is therefore necessary for the application software to prevent page write operations that would attempt to cross a page boundary. BYTE WRITE Bus Activity Host S T A R T SDA Line S Control Byte Word Address P PAGE WRITE Bus Activity Host S T A R T SDA Line S Bus Activity DS20002029G-page 10 A C K A C K A C K Bus Activity FIGURE 6-2: S T O P Data Control Byte Word Address (n) Data (n + 1) Data (n) S T O P Data (n + 15) P A C K A C K A C K A C K A C K  2007-2022 Microchip Technology Inc. and its subsidiaries 34AA02/34LC02 7.0 WRITE PROTECTION 7.2 The 34XX02 has two software write-protect features (SWP and PSWP) that allows the lower half of the array (addresses 00h-7Fh) to be write-protected, as well as a WP pin that can be used to protect the entire array. The permanent software write-protect feature is enabled by sending the device a special command. Once this feature has been enabled, it cannot be reversed. The resettable software write-protect feature is also enabled by sending the device a special command but can be reset by issuing another special command. In addition to the software protect features, there is a WP pin that can be used to write-protect the entire array, regardless of whether the software write-protect register has been written or not. In addition to hardware write-protect, the 34XX02 has an additional software write-protect feature that, when set, protects the first 128 bytes (00-7Fh) of the array from being written. Setting the software write protection is done by sending the SWP instruction. SWP can also then be cleared by issuing a CSWP instruction (see Figure 7-1). These two instructions follow the same format as the Byte Write instruction with the exception of the Device Type Identifier, (typically ‘1010’, instead changes to ‘0110’). Once this identifier is recognized by the device, the rest of the Byte Write command, address and data are “don’t cares”. In addition to the identifier, high voltage must be applied to the A0 pin of the device and specific levels must be present on A1 and A2. See Table 7-1 for the available commands. Table 7-2 and Table 7-3 describe how the 34XX02 will acknowledge specific commands under various circumstances. 7.1 Hardware Write Protection 7.3 The WP pin allows the user to write-protect the entire array (00-FF) when the pin is tied to VCC. If the pin is tied to VSS, the write protection is disabled. FIGURE 7-1: Software Write Protection (SWP) and Clear Software Write Protection (CSWP) Permanent Software Write-Protect (PSWP) The Permanent Software Write Protect (PSWP) is another instruction that may be used to permanently protect the first 128 byte of the array. Once this command is issued, the user will no longer have the ability to clear this feature regardless of instruction, power cycling or state of the WP pin. Also, once this instruction has been executed, the device will no longer acknowledge the device identifier ‘0110’. SOFTWARE WRITE PROTECTION FOR SWP, CSWP, PSWP OR CPSWP Bus Activity Host SDA Line S T A R T Control Byte Address Byte Data AA S0 110A 2 10 0 Bus Activity  2007-2022 Microchip Technology Inc. and its subsidiaries S T O P P A C K “Don’t Care” A C K A “Don’t Care” C K DS20002029G-page 11 34AA02/34LC02 TABLE 7-1: SOFTWARE WRITE PROTECTION INSTRUCTION SET WP = 0 Address Pins Instruction Device Type Identifier (1) Chip Select Bits A2 A1 A0 SWP VSS VSS VHV CSWP VSS VCC VHV 0 1 1 0 0 PSWP A2 A1 A0 0 1 1 0 A2 Read SWP VSS VSS VHV 0 1 1 0 0 Read CSWP VSS VCC VHV 0 1 1 0 0 Read PSWP A2 A1 A0 0 1 1 0 A2 Note 1: 2: B7 B6 B5 B4 0 1 1 0 B3 (2) B2 0 (2) R/W (2) B1 0 B0 1 0 1 1 0 A1 A0 0 0 1 1 1 1 1 A1 A0 1 A0 is used to detect VHV for the SWP and CSWP commands. B3, B2 and B1 are compared to the A2, A1 and A0 external pins, respectively. TABLE 7-2: ACKNOWLEDGE TABLE FOR WRITE OR WRITE PROTECTION WITH R/W = 0 Status Write- Protect Instruction ACK Permanently Protected x Page or Byte Write in lower 128 bytes 0 Not Protected 1 TABLE 7-3: Address ACK Write Cycle No ACK No Data No ACK No No ACK No CSWP ACK Don’t Care ACK Don’t Care ACK Yes PSWP ACK Don’t Care ACK Don’t Care ACK Yes Page or Byte Write in lower 128 bytes ACK Address ACK Data No ACK No No ACK No CSWP No ACK Don’t Care No ACK Don’t Care ACK Don’t Care ACK Don’t Care No ACK No PSWP ACK Don’t Care ACK Don’t Care No ACK No SWP 1 ACK ACK Data Byte No ACK Don’t Care No ACK Don’t Care SWP Protected with SWP ACK No ACK Don’t Care No ACK Don’t Care PSWP, SWP, CSWP 0 Address Page or Byte Write ACK Address ACK Data No ACK No PSWP, SWP or CSWP ACK Don’t Care ACK Don’t Care ACK Yes Page or Byte Write ACK Address ACK Data ACK Yes PSWP, SWP or CSWP ACK Don’t Care ACK Don’t Care No ACK No Page or Byte Write ACK Address ACK Address No ACK No ACKNOWLEDGE TABLE FOR WRITE OR WRITE PROTECTION WITH R/W = 1 Status Permanently Protected Protected with SWP Not protected DS20002029G-page 12 Instruction ACK PSWP, SWP, CSWP No ACK SWP No ACK CSWP ACK PSWP ACK PSWP, SWP, CSWP ACK  2007-2022 Microchip Technology Inc. and its subsidiaries 34AA02/34LC02 8.0 ACKNOWLEDGE POLLING Since the device will not acknowledge during a write cycle, this can be used to determine when the cycle is complete (this feature can be used to maximize bus throughput). Once the Stop condition for a write command has been issued from the host, the device initiates the internally timed write cycle. ACK polling can be initiated immediately. This involves the host sending a Start condition followed by the control byte for a write command (R/W = 0). If the device is still busy with the write cycle, then no ACK will be returned. If the cycle is complete, then the device will return the ACK and the host can then proceed with the next read or write operation. See Figure 8-1 for flow diagram. FIGURE 8-1: ACKNOWLEDGE POLLING FLOW Send Write Command Send Stop Condition to Initiate Write Cycle Send Start Send Control Byte with R/W = 0 Did Device Acknowledge (ACK = 0)? No Yes Next Operation  2007-2022 Microchip Technology Inc. and its subsidiaries DS20002029G-page 13 34AA02/34LC02 9.0 READ OPERATION 9.3 Read operations are initiated in the same way as write operations, with the exception that the R/W bit of the client address is set to ‘1’. There are three basic types of read operations: current address read, random read and sequential read. 9.1 Current Address Read The 34XX02 contains an Address Pointer that maintains the address of the last word accessed, internally incremented by one. Therefore, if the previous access (either a read or write operation) was to address ‘n’, the next current address read operation would access data from address n+1. Upon receipt of the client address with R/W bit set to ‘1’, the 34XX02 issues an Acknowledge and transmits the 8-bit data word. The host will not acknowledge the transfer, but does generate a Stop condition and the 34XX02 discontinues transmission (Figure 9-1). 9.2 Random Read Random read operations allow the host to access any memory location in a random manner. To perform this type of read operation, the word address must first be set. This is done by sending the word address to the 34XX02 as part of a write operation. Once the word address is sent, the host generates a Start condition following the Acknowledge. This terminates the write operation, but not before the internal Address Pointer is set. The host then issues the control byte again, but with the R/W bit set to a ‘1’. The 34XX02 then issues an Acknowledge and transmits the 8-bit data word. The host will not acknowledge the transfer, but does generate a Stop condition and the 34XX02 discontinues transmission (Figure 9-2). FIGURE 9-1: Sequential Read Sequential reads are initiated in the same way as a random read, with the exception that after the 34XX02 transmits the first data byte, the host issues an Acknowledge, as opposed to a Stop condition in a random read. This directs the 34XX02 to transmit the next sequentially addressed 8-bit word (Figure 9-3). To provide sequential reads, the 34XX02 contains an internal Address Pointer, which is incremented by one at the completion of each operation. This Address Pointer allows the entire memory contents to be serially read during one operation. 9.4 Contiguous Addressing Across Multiple Devices The Chip Select bits (A2, A1, A0) can be used to expand the contiguous address space for up to 16K bits by adding up to eight 34XX02 devices on the same bus. In this case, the software can use A0 of the control byte as address bit A8, A1 as address bit A9 and A2 as address bit A10. It is not possible to sequentially read across device boundaries. 9.5 Noise Protection and Brown-Out The 34XX02 employs a VCC threshold detector circuit which disables the internal erase/write logic if the VCC is below 1.35V at nominal conditions. The SCL and SDA inputs have Schmitt Trigger and filter circuits which suppress noise spikes to assure proper device operation, even on a noisy bus. CURRENT ADDRESS READ Bus Activity Host S T A R T Control Byte SDA Line S A 1 0 1 0 A2 A 1 0 1 Bus Activity DS20002029G-page 14 S T O P Data Byte P A C K N O A C K  2007-2022 Microchip Technology Inc. and its subsidiaries 34AA02/34LC02 FIGURE 9-2: RANDOM READ Bus Activity Host S T A R T Control Byte S 1 0 1 0 A2 A1 A0 0 SDA Line Bus Activity Host Control Byte S T O P Data (n) AAA S1010 2 101 A C K Bus Activity FIGURE 9-3: S T A R T Word Address (n) P A C K A C K N O A C K SEQUENTIAL READ Control Byte Data (n) Data (n + 1) Data (n + 2) S T O P Data (n + X) SDA Line Bus Activity P A C K  2007-2022 Microchip Technology Inc. and its subsidiaries A C K A C K A C K N O A C K DS20002029G-page 15 34AA02/34LC02 10.0 PACKAGING INFORMATION 10.1 Package Marking Information 8-Lead MSOP XXXXXXT YWWNNN 8-Lead PDIP (300 mil) XXXXXXX T/XXXNNN YYWW Example 34AA2I 20813F Example 34AA02 I/P e3 13F 2208 8-Lead SOIC Example XXXXXXXT XXXXYYWW NNN 34LC02I SN e3 2208 13F 6-Lead SOT-23 Example XXNN SK13 8-Lead 2x3 TDFN Example XXX YWW NN AJ2 208 13 8-Lead TSSOP Example XXXX TYWW NNN DS20002029G-page 16 34A2 I208 13F  2007-2022 Microchip Technology Inc. and its subsidiaries 34AA02/34LC02 1st Line Marking Codes Part Number MSOP PDIP SOIC 34AA02 34AA2T(1) 34AA02 34LC02 34LC2T(1) 34LC02 Note 1: 2: SOT-23 TDFN E-Temp. TSSOP I-Temp. E-Temp. I-Temp. 34AA02T(1) SKNN(2) SLNN(2) AJ2 AJ3 34A2 34LC02T(1) STNN(2) SUNN(2) AJ5 AJ6 34L2 T = Temperature grade (I, E) NN = Alphanumeric traceability code Legend: XX...X T Y YY WW NNN e3 Part number or part number code Temperature (I, E) Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week ‘01’) Alphanumeric traceability code (2 characters for small packages) JEDEC® designator for Matte Tin (Sn) * Standard OTP marking consists of Microchip part number, year code, week code and traceability code. Note: For very small packages with no room for the JEDEC® designator e3 , the marking will only appear on the outer carton or reel label. Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information.  2007-2022 Microchip Technology Inc. and its subsidiaries DS20002029G-page 17 34AA02/34LC02 8-Lead Plastic Micro Small Outline Package (MS) - 3x3 mm Body [MSOP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2X 0.20 H D D 2 A D N E 2 E1 2 E1 E 2X 0.20 H NOTE 1 1 2X 4 TIPS 0.25 C 2 e B TOP VIEW A 8X 0.10 C A A2 SEATING PLANE A1 8X b 0.25 C A-B D C A SIDE VIEW SEE DETAIL B H VIEW A–A Microchip Technology Drawing C04-111-MS Rev D Sheet 1 of 2 DS20002029G-page 18  2007-2022 Microchip Technology Inc. and its subsidiaries 34AA02/34LC02 8-Lead Plastic Micro Small Outline Package (MS) - 3x3 mm Body [MSOP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 4X ș1 R1 H R c SEATING PLANE C L ș (L1) 4X ș1 DETAIL B Number of Terminals Pitch Overall Height Standoff Molded Package Thickness Overall Length Overall Width Molded Package Width Terminal Width Terminal Thickness Terminal Length Footprint Lead Bend Radius Lead Bend Radius Foot Angle Mold Draft Angle Units Dimension Limits N e A A1 A2 D E E1 b c L L1 R R1 ș ș1 MIN – 0.00 0.75 0.22 0.08 0.40 0.07 0.07 0° 5° MILLIMETERS NOM 8 0.65 BSC – – 0.85 3.00 BSC 4.90 BSC 3.00 BSC – – 0.60 0.95 REF – – – – MAX 1.10 0.15 0.95 0.40 0.23 0.80 – – 8° 15° Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15mm per side. 3. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Microchip Technology Drawing C04-111-MS Rev D Sheet 2 of 2  2007-2022 Microchip Technology Inc. and its subsidiaries DS20002029G-page 19 34AA02/34LC02 8-Lead Plastic Micro Small Outline Package (MS) - 3x3 mm Body [MSOP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging GX SILK SCREEN C G1 Y X E RECOMMENDED LAND PATTERN Units Dimension Limits Contact Pitch E Contact Pad Spacing C Contact Pad Width (X8) X Contact Pad Length (X8) Y Contact Pad to Contact Pad (X4) G1 Contact Pad to Contact Pad (X6) GX MIN MILLIMETERS NOM 0.65 BSC 4.40 MAX 0.45 1.45 2.95 0.20 Notes: 1. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. Microchip Technology Drawing C04-2111-MS Rev D DS20002029G-page 20  2007-2022 Microchip Technology Inc. and its subsidiaries 34AA02/34LC02 8-Lead Plastic Dual In-Line (P) - 300 mil Body [PDIP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D A N B E1 NOTE 1 1 2 TOP VIEW E C A2 A PLANE L c A1 e eB 8X b1 8X b .010 C SIDE VIEW END VIEW Microchip Technology Drawing No. C04-018-P Rev E Sheet 1 of 2  2007-2022 Microchip Technology Inc. and its subsidiaries DS20002029G-page 21 34AA02/34LC02 8-Lead Plastic Dual In-Line (P) - 300 mil Body [PDIP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging ALTERNATE LEAD DESIGN (NOTE 5) DATUM A DATUM A b b e 2 e 2 e e Units Dimension Limits Number of Pins N e Pitch Top to Seating Plane A Molded Package Thickness A2 Base to Seating Plane A1 Shoulder to Shoulder Width E Molded Package Width E1 Overall Length D Tip to Seating Plane L c Lead Thickness b1 Upper Lead Width b Lower Lead Width eB Overall Row Spacing § MIN .115 .015 .290 .240 .348 .115 .008 .040 .014 - INCHES NOM 8 .100 BSC .130 .310 .250 .365 .130 .010 .060 .018 - MAX .210 .195 .325 .280 .400 .150 .015 .070 .022 .430 Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. § Significant Characteristic 3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" per side. 4. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. 5. Lead design above seating plane may vary, based on assembly vendor. Microchip Technology Drawing No. C04-018-P Rev E Sheet 2 of 2 DS20002029G-page 22  2007-2022 Microchip Technology Inc. and its subsidiaries 34AA02/34LC02 8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm (.150 In.) Body [SOIC] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2X 0.10 C A–B D A D NOTE 5 N E 2 E1 2 E1 E 2X 0.10 C A–B 2X 0.10 C A–B NOTE 1 2 1 e B NX b 0.25 C A–B D NOTE 5 TOP VIEW 0.10 C C A A2 SEATING PLANE 8X A1 SIDE VIEW 0.10 C h R0.13 h R0.13 H SEE VIEW C VIEW A–A 0.23 L (L1) VIEW C Microchip Technology Drawing No. C04-057-SN Rev F Sheet 1 of 2  2007-2022 Microchip Technology Inc. and its subsidiaries DS20002029G-page 23 34AA02/34LC02 8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm (.150 In.) Body [SOIC] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Units Dimension Limits Number of Pins N e Pitch Overall Height A Molded Package Thickness A2 § Standoff A1 Overall Width E Molded Package Width E1 Overall Length D Chamfer (Optional) h Foot Length L Footprint L1 Foot Angle c Lead Thickness b Lead Width Mold Draft Angle Top Mold Draft Angle Bottom MIN 1.25 0.10 0.25 0.40 0° 0.17 0.31 5° 5° MILLIMETERS NOM 8 1.27 BSC 6.00 BSC 3.90 BSC 4.90 BSC 1.04 REF - MAX 1.75 0.25 0.50 1.27 8° 0.25 0.51 15° 15° Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. § Significant Characteristic 3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15mm per side. 4. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. 5. Datums A & B to be determined at Datum H. Microchip Technology Drawing No. C04-057-SN Rev F Sheet 2 of 2 DS20002029G-page 24  2007-2022 Microchip Technology Inc. and its subsidiaries 34AA02/34LC02 8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm (.150 In.) Body [SOIC] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging SILK SCREEN C Y1 X1 E RECOMMENDED LAND PATTERN Units Dimension Limits E Contact Pitch Contact Pad Spacing C Contact Pad Width (X8) X1 Contact Pad Length (X8) Y1 MIN MILLIMETERS NOM 1.27 BSC 5.40 MAX 0.60 1.55 Notes: 1. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. Microchip Technology Drawing C04-2057-SN Rev F  2007-2022 Microchip Technology Inc. and its subsidiaries DS20002029G-page 25 34AA02/34LC02 /HDG3ODVWLF6PDOO2XWOLQH7UDQVLVWRU2727<>627@ 1RWH )RUWKHPRVWFXUUHQWSDFNDJHGUDZLQJVSOHDVHVHHWKH0LFURFKLS3DFNDJLQJ6SHFLILFDWLRQORFDWHGDW KWWSZZZPLFURFKLSFRPSDFNDJLQJ ;  & $% ' H $ ' (  ( ( (  ;  & ' ;  & $% H % ;E  & $% ' 7239,(: & $ $ 6($7,1*3/$1( $ ;  & 6,'(9,(: 5 F 5 / Ĭ / (1'9,(: 0LFURFKLS7HFKQRORJ\'UDZLQJ&'276KHHWRI DS20002029G-page 26  2007-2022 Microchip Technology Inc. and its subsidiaries 34AA02/34LC02 /HDG3ODVWLF6PDOO2XWOLQH7UDQVLVWRU2727<>627@ 1RWH )RUWKHPRVWFXUUHQWSDFNDJHGUDZLQJVSOHDVHVHHWKH0LFURFKLS3DFNDJLQJ6SHFLILFDWLRQORFDWHGDW KWWSZZZPLFURFKLSFRPSDFNDJLQJ 8QLWV 'LPHQVLRQ/LPLWV 1 1XPEHURI/HDGV H 3LWFK H 2XWVLGHOHDGSLWFK $ 2YHUDOO+HLJKW $ 0ROGHG3DFNDJH7KLFNQHVV $ 6WDQGRII 2YHUDOO:LGWK ( 0ROGHG3DFNDJH:LGWK ( 2YHUDOO/HQJWK ' )RRW/HQJWK / )RRWSULQW / I )RRW$QJOH F /HDG7KLFNQHVV /HDG:LGWK E 0,1     ƒ   0,//,0(7(56 120  %6& %6&    %6& %6& %6&  5()    0$;     ƒ   1RWHV  'LPHQVLRQV'DQG(GRQRWLQFOXGHPROGIODVKRUSURWUXVLRQV0ROGIODVKRU SURWUXVLRQVVKDOOQRWH[FHHGPPSHUVLGH  'LPHQVLRQLQJDQGWROHUDQFLQJSHU$60(627@ 1RWH )RUWKHPRVWFXUUHQWSDFNDJHGUDZLQJVSOHDVHVHHWKH0LFURFKLS3DFNDJLQJ6SHFLILFDWLRQORFDWHGDW KWWSZZZPLFURFKLSFRPSDFNDJLQJ *; < = & * * 6,/.6&5((1 ; ( 5(&200(1'('/$1'3$77(51 8QLWV 'LPHQVLRQ/LPLWV &RQWDFW3LWFK ( &RQWDFW3DG6SDFLQJ & &RQWDFW3DG:LGWK; ; < &RQWDFW3DG/HQJWK; * 'LVWDQFH%HWZHHQ3DGV 'LVWDQFH%HWZHHQ3DGV *; = 2YHUDOO:LGWK 0,1 0,//,0(7(56 120 %6&  0$;      1RWHV 'LPHQVLRQLQJDQGWROHUDQFLQJSHU$60(76623@ 1RWH )RUWKHPRVWFXUUHQWSDFNDJHGUDZLQJVSOHDVHVHHWKH0LFURFKLS3DFNDJLQJ6SHFLILFDWLRQORFDWHGDW KWWSZZZPLFURFKLSFRPSDFNDJLQJ 8QLWV 'LPHQVLRQ/LPLWV 1XPEHURI3LQV 1 H 3LWFK 2YHUDOO+HLJKW $ 0ROGHG3DFNDJH7KLFNQHVV $ 6WDQGRII $ 2YHUDOO:LGWK ( 0ROGHG3DFNDJH:LGWK ( 2YHUDOO/HQJWK ' )RRW/HQJWK / )RRWSULQW / F /HDG7KLFNQHVV )RRW$QJOH E /HDG:LGWK 0,1        ƒ  0,//,0(7(56 120  %6&    %6&    5()  ƒ  0$;        ƒ  Notes: 3LQYLVXDOLQGH[IHDWXUHPD\YDU\EXWPXVWEHORFDWHGZLWKLQWKHKDWFKHGDUHD 'LPHQVLRQV'DQG(GRQRWLQFOXGHPROGIODVKRUSURWUXVLRQV0ROGIODVKRU SURWUXVLRQVVKDOOQRWH[FHHGPPSHUVLGH 'LPHQVLRQLQJDQGWROHUDQFLQJSHU$60(