47L64
64-Kbit I2C EERAM
Serial SRAM Features
Package Types (not to scale)
• Unlimited Reads/Unlimited Writes:
- Standard serial SRAM protocol
- Symmetrical timing for reads and writes
• SRAM Array:
- 8,192 x 8 bits
• High-Speed I2C Interface:
- Industry standard: 1 MHz, 400 kHz, and
100 kHz
- Zero cycle delay writes and reads to SRAM
array
- Schmitt Trigger inputs for noise suppression
• Low-Power CMOS Technology:
- Active current: 1 mA (maximum)
- Standby current: 200 µA (maximum)
Hidden EEPROM Backup Features
• Cell-Based Nonvolatile Backup:
- Mirrors SRAM array cell-for-cell
- Transfers all data to/from SRAM cells in
parallel (all cells at same time)
• Invisible-to-User Data Transfers:
- VCC level monitored inside device
- SRAM automatically saved on power disrupt
- SRAM automatically restored on VCC return
• 100,000 Backups Minimum
• 100 Years Retention (at 55°C)
Other Features of the 47L64
8-Lead SOIC
(Top View)
VCAP
1
8
VCC
A1
2
7
WP
A2
3
6
SCL
VSS
4
5
SDA
TDFN(1)
(Top View)
VCAP 1
8 VCC
A1 2
7 WP
A2 3
VSS 4
6 SCL
5 SDA
Note 1: Includes Exposed Thermal Pad (EP)
Pin Descriptions
Pin Name
VCAP
A1, A2
VSS
SCL
SDA
WP
VCC
Description
External Capacitor
Hardware Address Pins
Ground
Serial Clock Input
Serial Data Input/Output
Write-Protect Input
Power Supply
• Operating Voltage Range: 2.7V to 3.6V
• Temperature Ranges:
- Industrial (I): -40°C to +85°C
• ESD protection: >2,000V
Packages
• 8-Lead SOIC
• 8-Lead TDFN
2019-2020 Microchip Technology Inc.
Preliminary
DS20006168B-page 1
47L64
General Description
The Microchip Technology Inc. 47L64 serial EERAM
has an SRAM memory core with hidden EEPROM
backup. The device can be treated by the user as a full
symmetrical read/write SRAM. Backup to EEPROM is
handled by the device on any power disrupt, so the
user can effectively view this device as an SRAM that
never loses its data.
The device is structured as a 64-Kbit SRAM with
EEPROM backup in each memory cell. The SRAM is
organized as 8,192 x 8 bits and uses the I2C serial
interface. The I2C bus uses two signal lines for
communication: clock input (SCL) and data (SDA).
Access to the device is controlled through a chip
address and address pins, allowing up to four devices
to share the same bus.
The SRAM is a conventional serial SRAM: it allows
symmetrical reads and writes and has no limits on cell
usage. The backup EEPROM is invisible to the user
and cannot be accessed by the user independently.
The device includes circuitry that detects VCC
dropping below a certain threshold, shuts its
connection to the outside environment, and transfers
all SRAM data to the EEPROM portion of each cell for
safe keeping. When VCC returns, the circuitry
automatically returns the data to the SRAM and the
user’s interaction with the SRAM can continue with the
same data set.
Block Diagram
VCC
VCAP
SDA
SCL
WP
A1
A2
Power
Control
Block
I2C Control Logic
and Address
Decoder
Powering the Device During SRAM to
EEPROM Backup (VCAP)
A small capacitor (typically 22 µF) is required for the
proper operation of the device. This capacitor is placed
between VCAP (pin 1) and the system VSS (see Normal
Device Operation). When power is first applied to the
device, this capacitor is charged to VCC through the
device (see Normal Device Operation). During normal
SRAM operation, the capacitor remains charged to
VCC and the level of system VCC is monitored by the
device. If system VCC drops below a set threshold, the
device interprets this as a power-off or brown-out
event. The device suspends all I/O operation, shuts off
its connection with the VCC pin, and uses the saved
energy in the capacitor to power the device through the
VCAP pin as it transfers all SRAM data to EEPROM
(see Vcc Power-Off Event). On the next power-up of
VCC, the data is transfered back to SRAM, the
capacitor is recharged, and the SRAM operation
continues.
Normal Device Operation
VCC (pin 8)
System VCC
VCC Monitor
VCAP (pin )
$
$
6&/
6'$
:3
CVCAP
Normal
SRAM
Operation
Charged to VCC
VSS (pin 4)
System VSS
Memory Address
and Data Control
Logic
VCC Power-Off Event
Automatic
Backup
EEPROM
8K x 8
SRAM
8K x 8
EEPROM
SRAM
STORE
RECALL
2019-2020 Microchip Technology Inc.
$
$
6&/
6'$
:3
Preliminary
SRAM to
EEPROM
Transfer
VCC (pin 8)
System VCC
VCAP (pin )
CVCAP
Temporary VCC
VSS (pin 4)
System VSS
DS20006168B-page 2
47L64
1.0
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings†
VCC............................................................................................................................................................................. 4.5V
All inputs and outputs w.r.t. VSS ................................................................................................................... -0.6V to 4.5V
Storage temperature ................................................................................................................................. -65°C to 150°C
Ambient temperature under bias................................................................................................................. -55°C to 85°C
ESD protection on all pins.......................................................................................................................................... 2 kV
† NOTICE: Stresses above those listed under ‘Maximum ratings’ may cause permanent damage to the device. This
is a stress rating only and functional operation of the device at those or any other conditions above those indicated in
the operational listings of this specification is not implied. Exposure to maximum rating conditions for an extended
period of time may affect device reliability.
TABLE 1-1:
DC CHARACTERISTICS
Electrical Characteristics:
Industrial (I):
TAMB = -40°C to +85°C, VCC = 2.7V to 3.6V
DC CHARACTERISTICS
Param.
No.
Symbol
D1
VIH
D2
VIL
D3
VOL
Low-Level Output Voltage
D4
VHYS
Hysteresis of Schmitt Trigger
Inputs (SDA, SCL pins)
D5
ILI
Input Leakage Current
(SDA, SCL pins)
D6
ILO
D7
RIN
D8
CINT
D9
D10
Characteristic
Min.
Typ.
Max.
Units Conditions
High-Level input Voltage
0.8 X VCC
—
VCC+0.5
V
Low-Level Input Voltage
-0.5
—
0.2*VCC
V
—
—
0.4
V
IOL = 2.0 mA
0.05 X VCC
—
—
V
Note 1
—
—
±3
A
VIN = VSS or VCC
Output Leakage Current (SDA pin)
—
—
±3
A
VOUT = VSS or VCC
Input Resistance to VSS
(A1, A2, WP pins)
50
—
—
k
VIN = VIL (max)
Internal Capacitance
(all inputs and outputs)
—
—
7
pF
TAMB = 25°C, FREQ = 1 MHz,
VCC = 3.3V (Note 1)
ICC
Active 1
Operating Current @ 1 MHz
—
—
1
mA
VCC = 3.6 V, FCLK = 1 MHz
ICC
Active 2
Operating Current @ 400 kHz
—
—
700
µA
VCC = 3.6 V, FCLK = 400 kHz
D11
ICCS
Standby Current
—
—
200
µA
SCL, SDA, VCAP, VCC = 3.6V
D12
VTRIP
AutoStore/AutoRecall Trip Voltage
2.3
—
2.65
V
Note 1
Power-on Reset Voltage
—
—
2.1
V
Bus Capacitance
—
—
400
pF
VCAP Capacitor
10
22
50
µF
D13
VPOR
D14
CB
D15
CVCAP
Note 1
Note 1: This parameter is periodically sampled and not 100% tested.
2019-2020 Microchip Technology Inc.
Preliminary
DS20006168B-page 3
47L64
1.1
AC CHARACTERISTICS
TABLE 1-1:
AC CHARACTERISTICS
Industrial (I):
AC CHARACTERISTICS
Param.
No.
Symbol
Characteristic
TAMB = -40°C to +85°C, VCC = 2.7V to 3.6V
Min.
Max.
Units
Conditions
1
FCLK
Clock Frequency
—
1000
kHz
2
THIGH
Clock High Time
400
—
ns
3
TLOW
Clock Low Time
600
—
ns
4
TR
SDA and SCL Input Rise Time
—
300
ns
Note 1
5
TF
SDA and SCL Input Fall Time
—
100
ns
Note 1
6
THD:STA
Start Condition Hold Time
250
—
ns
7
TSU:STA
Start Condition Setup Time
250
—
ns
8
THD:DAT
Data Input Hold Time
0
—
ns
9
TSU:DAT
Data Input Setup Time
100
—
ns
10
TSU:STO
Stop Condition Setup Time
250
—
ns
Output Valid from Clock
11
TAA
12
TBUF
Bus Free Time: Time the bus must
be free before a new transmission
can start
13
TOF
Output Fall Time from VIH
Minimum to VIL Maximum
CB 100pF
14
TSP
Input Filter Spike Suppression
(SDA and SCL pins)
15
TRESTORE Power-up Recall Operation
Duration
—
550
ns
500
—
ns
20+0.1CB
250
ns
—
50
ns
—
550
µs
CB 100 pF (Note 1)
16
TSTORE
Store Operation Duration
—
10
ms
17
TVRISE
VCC Rise Rate
30
—
µs/V
Note 1
18
TvFALL
VCC Fall Rate
30
—
µs/V
Note 1
19
—
Endurance
100,000
—
Store
Cycles
25°C, VCC = 3.6V
(Note 1, Note 2)
Retention
100
Years
55°C
20
Note 1: This parameter is not tested but ensured by characterization.
2: For endurance estimates in a specific application, consult the Total Endurance Model which can be obtained on
Microchip’s website at www.microchip.com.
FIGURE 1-1:
BUS TIMING DATA
5
SCL
SDA
IN
7
3
6
D4
2
8
9
4
10
14
11
12
SDA
OUT
2019-2020 Microchip Technology Inc.
Preliminary
DS20006168B-page 4
47L64
FIGURE 1-2:
AUTOSTORE/AUTORECALL TIMING DATA
18
17
D12
VCC
D13
16
16
AutoStore
15
15
AutoRecall
Device Access
Enabled
2019-2020 Microchip Technology Inc.
Preliminary
DS20006168B-page 5
47L64
2.0
PIN DESCRIPTION
The description of the pins are listed in Table 2-1.
TABLE 2-1:
Name
8-Lead SOIC
8-Lead TDFN(1)
VCAP
1
1
External Capacitor
A1
2
2
Chip Select Input
A2
3
3
Chip Select Input
Vss
4
4
Ground
5
5
Serial Data
SCL
6
6
Serial Clock
WP
7
7
Write Protect
Vcc
8
8
2.7V to 3.6V
The exposed pad on the TDFN package can be connected to VSS or left floating.
A1, A2 Chip Address Inputs
2.3
The A1, A2 inputs are used by the 47L64 for multiple
device operation. The levels on these inputs are
compared with the corresponding Chip Select bits in
the slave address. The chip is selected if the
comparison is true.
Up to four devices may be connected to the same bus
by using different Chip Select bit combinations. These
pins are not pulled up or down internally, so they must
be externally connected to VCC or VSS.
2.2
Function
SDA
Note 1:
2.1
PIN FUNCTION TABLE
Serial Data (SDA)
This is a bidirectional pin used to transfer addresses
and data into and data out of the device. It is an opendrain terminal, therefore, the SDA bus requires a pullup resistor to VCC (typical 10 k for 100 kHz, 2 kfor
400 kHz and 1 MHz).
Serial Clock (SCL)
This input is used to synchronize the data transfer from
and to the device.
2.4
Write-Protect Input
When the WP pin is set high, then writes within the
upper 1/4 of memory will not be allowed. Attempts to
write in that protected region over the I2C bus will return
an ACK (Acknowledge) for the WRITE instruction and
address byte portions of the command, and will also
return an ACK (Acknowledge) for the data portion of
the command, despite the fact that no data will be
written. See Table 4-1. The WP pin has no effect on
random or sequential read operations. If left floating,
this pin is internally pulled low.
For normal data transfer SDA is allowed to change only
during SCL low. Changes during SCL high are
reserved for indicating the Start and Stop conditions.
2019-2020 Microchip Technology Inc.
Preliminary
DS20006168B-page 6
47L64
3.0
MEMORY ORGANIZATION
3.1
Data Array Organization
3.2.3
The 47L64 is internally organized as a continuous
SRAM array for both reading and writing, along with a
nonvolatile EEPROM version that is not directly
accessible to the user, but which can be refreshed or
recalled on power cycles.
3.2
STORE/RECALL OPERATIONS
In order to provide nonvolatile storage of the SRAM
data, an EEPROM array is included on the 47L64.
During normal operation, the EEPROM array is not
directly accessible to the user. Instead, the 47L64
preserves the SRAM data by automatically performing
store and recall operations on power-down and powerup, respectively.
3.2.1
Since the device will not acknowledge during store and
recall operations, checking for the Acknowledge signal
can be used to determine when those events are
complete. Once such an event has started,
Acknowledge polling can be initiated immediately. This
involves the master sending a Start condition, followed
by the write control byte (R/W = 0) for the SRAM array.
If the device is still busy, then no Acknowledge will be
returned. In this case, the Start condition and control
byte must be resent. If the Store or Recall are
complete, then the device will return an Acknowledge,
and the master can then proceed with the next read or
write command. See Figure 3-1 for flow diagram.
FIGURE 3-1:
AUTOSTORE
To simplify device usage, the 47L64 features an
AutoStore mechanism. To enable this feature, the user
must place a capacitor on the VCAP pin. The capacitor
is charged through the VCC pin. When the 47L64
detects a power-down event, the device automatically
switches to the capacitor for power and initiates the
AutoStore operation.
To avoid extraneous store operations, the AutoStore
will only be initiated if the SRAM array has been
modified since the last Store or Recall operation.
The AutoStore is initiated when VCAP falls below
VTRIP. Even if power is restored, the 47L64 cannot be
accessed for TSTORE time and TRESTORE after the
AutoStore is initiated.
Note:
3.2.2
POLLING ROUTINE
If power is restored during an AutoStore
operation, the AutoStore will continue and
then the AutoRecall will be performed.
POLLING FLOW
Initiate SRAM
Write Event
Send Start
Send Control Byte
with R/W = 0
Did Device
Acknowledge
(ACK = 0)?
NO
YES
Next
Operation
AUTORECALL
The 47L64 devices features an AutoRecall
mechanism that is performed on power-up. This
feature ensures that the SRAM data duplicates the
EEPROM data on power-up. The AutoRecall is
initiated when VCAP rises above VTRIP, and the 47L64
cannot be accessed for TRESTORE time after the
AutoRecall is initiated.
Note 1: If power is lost during an AutoRecall
operation, the AutoRecall is aborted and
the AutoStore is not performed.
2: AutoRecall is performed every time VCAP
rises above VTRIP.
2019-2020 Microchip Technology Inc.
Preliminary
DS20006168B-page 7
47L64
FIGURE 3-2:
AUTOSTORE/AUTORECALL SCENARIOS (WITH ARRAY MODIFIED)
VCC
VCAP
VTRIP
VPOR
AutoStore
AutoRecall
TSTORE
TRESTORE
TRESTORE
Device Access
Enabled
Array Modified
CHARGE_CAP(1)
VCC
VCAP
AutoStore
VTRIP
VPOR
TSTORE
TRESTORE
AutoRecall
Device Access
Enabled
Array Modified
CHARGE_CAP(1)
VCC
VCAP
AutoStore
VTRIP
VPOR
TSTORE
AutoRecall
TRESTORE
Device Access
Enabled
Array Modified
CHARGE_CAP(1)
Note 1: When CHARGE_CAP is a ‘0’, VCC is connected to VCAP, allowing VCC to charge the external capacitor.
See Section 3.2.5 “Power Switchover” for details.
2019-2020 Microchip Technology Inc.
Preliminary
DS20006168B-page 8
47L64
FIGURE 3-3:
AUTOSTORE/AUTORECALL SCENARIOS (WITH ARRAY NOT MODIFIED)
VCC
VCAP
VTRIP
VPOR
AutoStore
AutoRecall
Device Access
Enabled
Array Modified
CHARGE_CAP(1)
VCC
VCAP
VTRIP
VPOR
AutoStore
AutoRecall
TRESTORE
Device Access
Enabled
Array Modified
CHARGE_CAP(1)
Note 1: When CHARGE_CAP is a ‘0’, VCC is connected to VCAP, allowing VCC to charge the external capacitor. See
Section 3.2.5 “Power Switchover” for details.
3.2.4
TRIP VOLTAGE
The 47L64 has an internal voltage reference that is
used to create a trip voltage threshold (VTRIP). When
VCAP rises above VTRIP, a power-up event is detected.
If this is the first power-up event after a POR, then an
AutoRecall operation is initiated. When VCAP falls
below VTRIP, a power-down event is detected and an
AutoStore operation is initiated if the array has been
modified.
Note:
3.2.5
When VCAP is below VTRIP, the 47L64
cannot be accessed and will not
acknowledge any commands.
POWER SWITCHOVER
To support the AutoStore feature, the 47L64 must be
able to charge the capacitor connected to the VCAP pin
when power is available on VCC, and also
automatically switch to being powered from the VCAP
2019-2020 Microchip Technology Inc.
pin when power is removed from VCC. Since the VCAP
pin is used as part of the internal power bus, this
means that VCC must be disconnected when power is
removed.
To accomplish this, the 47L64 has an intelligent power
switchover circuit that continuously monitors the
voltages on both VCC and VCAP.
During a power-up event, VCC is initially disconnected,
allowing it to rise above VCAP. Once VCC is above
VCAP, VCAP is connected to the VCC, charging the
external capacitor. When VCAP reaches VTRIP, the
AutoRecall operation is triggered.
During a power-down event, VCC is initially connected
to the internal power bus. As Vcc falls, it discharges
the external cap, causing VCAP to also fall. Once VCAP
falls below VTRIP, the AutoStore operation is triggered,
and VCC is disconnected to prevent discharging the
capacitor further through VCC.
Preliminary
DS20006168B-page 9
47L64
Once VCC is disconnected, it will not be reconnected
until both VCC is greater than VCAP and any internal
store cycles (AutoStore) is complete. This guards
against continuously connecting and disconnecting
VCC when VCAP falls faster than VCC.
2019-2020 Microchip Technology Inc.
Preliminary
DS20006168B-page 10
47L64
4.0
FUNCTIONAL DESCRIPTION
4.0.1
PRINCIPLES OF OPERATION
4.1.1.4
The 47L64 is a 64-Kbit serial EERAM designed to
support a bidirectional two-wire bus and data
transmission protocol (I2C). A device that sends data
onto the bus is defined as transmitter, and a device
receiving data as receiver. The bus has to be
controlled by a master device which generates the
Start and Stop conditions, while the 47L64 works as
slave. Both master and slave can operate as
transmitter or receiver but the master device
determines which mode is active.
4.1
BUS CHARACTERISTICS
4.1.1
SERIAL INTERFACE
• Data transfer may be initiated only when the bus
is not busy.
• During data transfer, the data line must remain
stable whenever the clock line is high. Changes in
the data line while the clock line is high will be
interpreted as a Start or Stop condition.
Accordingly, the following bus conditions have been
defined (Figure 4-1).
4.1.1.1
Bus Not Busy (A)
Both data and clock lines remain high.
4.1.1.2
Start Data Transfer (B)
A high-to-low transition of the SDA line while the clock
(SCL) is high determines a Start condition. All commands must be preceded by a Start condition.
4.1.1.3
Stop Data Transfer (C)
A low-to-high transition of the SDA line while the clock
(SCL) is high determines a Stop condition. All operations must end with a Stop condition.
FIGURE 4-1:
SCL
(A)
The state of the data line represents valid data when,
after a Start condition, the data line is stable for the
duration of the high period of the clock signal.
The data on the line must be changed during the low
period of the clock signal. There is one bit of data per
clock pulse.
Each data transfer is initiated with a Start condition and
terminated with a Stop condition. The number of the
data bytes transferred between the Start and Stop
conditions is determined by the master device.
4.1.1.5
The following bus protocol has been defined:
Data Valid (D)
Acknowledge
Each receiving device, when addressed, is obliged to
generate an Acknowledge signal after the reception of
each byte. The master device must generate an extra
clock pulse which is associated with this Acknowledge
bit.
A device that acknowledges must pull down the SDA
line during the Acknowledge clock pulse in such a way
that the SDA line is stable low during the high period of
the Acknowledge related clock pulse. Of course, setup
and hold times must be taken into account. During
reads, a master must signal an end of data to the slave
by NOT generating an Acknowledge bit on the last byte
that has been clocked out of the slave. In this case, the
slave (47L64) will leave the data line high to enable the
master to generate the Stop condition.
The 47L64 will generate an Acknowledge bit on
receiving a correct control byte and following address
and data bytes. Table 4-1 summarizes these situations.
The device will not generate Acknowledge bits for any
bytes following if the control byte is incorrect, such as
when the address bits do not match the A1, A2 pins,
see Section 4.2 “Device Addressing”.
DATA TRANSFER SEQUENCE ON THE SERIAL BUS
(B)
(D)
(D)
(C)
(A)
SDA
START
CONDITION
2019-2020 Microchip Technology Inc.
DATA
ADDRESS OR
ACKNOWLEDGE ALLOWED
TO CHANGE
VALID
Preliminary
STOP
CONDITION
DS20006168B-page 11
47L64
FIGURE 4-2:
ACKNOWLEDGE TIMING
Acknowledge
Bit
SCL
1
2
SDA
3
4
5
6
7
8
9
2
3
Data from transmitter
Data from transmitter
Receiver must release the SDA line at this point
so the Transmitter can continue sending data.
Transmitter must release the SDA line at this point
allowing the Receiver to pull the SDA line low to
acknowledge the previous eight bits of data.
TABLE 4-1:
1
ACKNOWLEDGE TABLE FOR SRAM WRITES
Instruction
SRAM Write in Unprotected Block
SRAM Write in Protected Block
2019-2020 Microchip Technology Inc.
ACK
Address
MSB
ACK
Address
LSB
ACK
Data
Byte
ACK
ACK
ACK
Address
Address
ACK
ACK
Address
Address
ACK
ACK
Data
Data
ACK
ACK
Preliminary
DS20006168B-page 12
47L64
4.2
DEVICE ADDRESSING
The control byte is the first byte received following the
Start condition from the master device (Figure 4-3).
The control byte begins with a 4-bit op code. The next
two bits are the user-configurable chip select bits, A2
and A1. The next bit is a non-configurable chip select
bit that must always be set to ‘1’. The chip select bits
A2 and A1 in the control byte must match the logic
levels on the corresponding A2 and A1 pins for the
device to respond.
The last bit of the control byte defines the operation to
be performed. When set to a ‘1’ a read operation is
selected, and when set to a ‘0’ a write operation is
selected.
The 47L64 is divided into two functional units: the
SRAM array and the Control registers. Section 4.3
“SRAM Array” describes the functionality for the
SRAM array.
The 4-bit op code in the control byte determines which
unit will be accessed during an operation. Table 4-2
shows the standard control bytes used by the 47L64.
TABLE 4-2:
CONTROL BYTES
Op
Code
Chip
Select
R/W
Bit
SRAM Read
1010
A2 A1 1
1
SRAM Write
1010
A2 A1 1
0
Operation
The combination of the 4-bit op code and the three
chip select bits is called the slave address. Upon
receiving a valid slave address, the slave device
outputs an Acknowledge signal on the SDA line.
Depending on the state of the R/W bit, the 47L64 will
select a read or a write operation.
Note:
When VCAP is below VTRIP, the 47L64
cannot be accessed and will not
acknowledge any commands.
FIGURE 4-3:
CONTROL BYTE FORMAT
Acknowledge Bit
Read/Write Bit
Start Bit
Chip Select
Bits
Op Code
S
1
0
1
0
A2
A1
1 R/W ACK
Slave Address
2019-2020 Microchip Technology Inc.
Preliminary
DS20006168B-page 13
47L64
4.3
SRAM ARRAY
4.3.1.2
The SRAM array is the only user-accessible memory
panel available on the 47L64. The EEPROM array,
which can only be directly accessed through test mode
operations, provides nonvolatile storage to back up
the SRAM data.
To select the SRAM array, the master device must use
the respective 4-bit op code, ‘1010’, when transmitting
the control byte.
Note: If an AutoStore is triggered during an
SRAM read or write operation, the
operation is aborted in order to execute
the Store.
4.3.1
WRITE OPERATION
When the SRAM array is selected and the R/W bit in
the control byte is set to ‘0’, a write operation is
selected and the next two bytes received are
interpreted as the array address. The Most Significant
address bits are transferred first, followed by the Least
Significant bits, and are shifted directly into the internal
Address Pointer. The Address Pointer determines
where in the SRAM array the next read or write
operation begins.
Sequential Write
To write multiple data bytes in a single operation, the
SRAM write control byte, array address, and the first
data byte are transmitted to the 47L64 in the same
way as for a byte write. However, instead of
generating a Stop condition, the master transmits
additional data bytes (Figure 4-5). Upon receipt of
each byte, the 47L64 responds with an Acknowledge,
during which the data is latched into the SRAM array
on the rising edge of SCL, and the Address Pointer is
incremented by one. Sequential write operations are
limited to the address 0x1FFF, and if the master
should transmit enough bytes further, the Address
Pointer will roll over to 0x0000 and continue writing.
There is no limit to the number of bytes that can be
written in a single command.
In the event that the WP pin is set high, writes to
addresses in the upper 1/4 portion of the array will not
be allowed. Attempts to write in that region will receive
an ACK response from the device for the address
bytes, but will receive a NACK for data bytes written
(see Table 4-1).
Data is stored into the SRAM array as soon as it is
received, specifically on the rising edge of SCL during
each Acknowledge bit. If a write operation is aborted
for any reason, all received data will already be stored
in SRAM, except for the last data byte if the rising
edge of SCL during the Acknowledge for that byte has
not yet been reached.
Note: If an attempt is made to write to a protected portion of the array, the device
will not respond with an Acknowledge
after the data byte is received, the current operation will be terminated without
incrementing the Address Pointer, and
any data transmitted on the SDA line will
be ignored until a new operation is
begun with a Start condition.
4.3.1.1
Byte Write
After the 47L64 has received the 2-byte array address,
responding with an Acknowledge after each address
byte, the master device will transmit the data byte to
be written into the addressed memory location. The
47L64 acknowledges again and the master generates
a Stop condition (Figure 4-4). The data byte is latched
into the SRAM array on the rising edge of SCL during
the Acknowledge.
After a byte write command, the internal Address
Pointer will point to the address location following the
location that was just written.
2019-2020 Microchip Technology Inc.
Preliminary
DS20006168B-page 14
47L64
FIGURE 4-4:
SRAM BYTE WRITE
BUS ACTIVITY
MASTER
S
T
A
R
T
CONTROL
BYTE
ADDRESS
HIGH BYTE
A
S1010A
2 1 10
SDA LINE
S
T
O
P
DATA
P
XXX
A
C
K
BUS ACTIVITY
ADDRESS
LOW BYTE
A
C
K
A
C
K
A
C
K
DATA LATCHED
INTO SRAM
X = Don’t Care
FIGURE 4-5:
BUS ACTIVITY
MASTER
SDA LINE
SRAM SEQUENTIAL WRITE
S
T
A
R
T
CONTROL
BYTE
ADDRESS
HIGH BYTE
AA
S10102 11 0
BUS ACTIVITY
ADDRESS
LOW BYTE
S
T
O
P
DATA BYTE N
DATA BYTE 0
P
X XX
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
DATA LATCHED
INTO SRAM
X = Don’t Care
2019-2020 Microchip Technology Inc.
Preliminary
DS20006168B-page 15
47L64
4.3.2
READ OPERATION
4.3.2.2
When the SRAM array is selected and the R/W bit is
set to ‘1’, a read operation is selected. For read
operations, the array address is not transmitted,
instead, the internal Address Pointer is used to
determine where the read starts.
Random read operations allow the master to access
any memory location in a random manner. To perform
this type of read operation, first the Address Pointer
must be set. This is done by sending the array address
to the 47L64 as part of a write operation (R/W bit set
to ‘0’). After the array address is sent, the master
generates
a
Start
condition
following
the
Acknowledge. This terminates the write operation, but
not before the Address Pointer has been set. Then,
the master issues the SRAM control byte again but
with the R/W bit set to a ‘1’. The 47L64 will then issue
an Acknowledge and transmit the 8-bit data byte. The
master will not Acknowledge the transfer but does
generate a Stop condition, which causes the 47L64 to
discontinue transmission (Figure 4-7). After a random
read operation, the Address Pointer will point to the
address location following the one that was just read.
During read operations, the master device generates
the Acknowledge bit after each data byte, and it is this
bit which determines whether the operation will
continue or end. A ‘0’ (Acknowledge) bit requests
more data and continues the read, while a ‘1’ (No
Acknowledge) bit ends the read operation.
4.3.2.1
Current Address Read
The current address read operation relies on the
current value of the Address Pointer to determine from
where to start reading. The Address Pointer is
automatically incremented after each data byte is read
or written. Therefore, if the previous access was to
address n (where n is any legal address), the next
current address read operation would access data
beginning with address n+1.
4.3.2.3
SRAM CURRENT
ADDRESS READ
BUS ACTIVITY
MASTER
S
T
A
R
T
SDA LINE
S 10 10 A A 1 1
2 1
FIGURE 4-7:
BUS ACTIVITY
MASTER
SDA LINE
P
A
C
K
BUS ACTIVITY
S
T
O
P
DATA
BYTE
CONTROL
BYTE
Sequential Read
Sequential reads are initiated in the same way as a
random read except that after the 47L64 transmits the
first data byte, the master issues an Acknowledge as
opposed to the Stop condition used in a random read.
The Acknowledge directs the 47L64 to transmit the
next sequentially addressed 8-bit byte (Figure 4-8).
Following the final byte transmitted to the master, the
master will NOT generate an Acknowledge but will
generate a Stop condition. To provide sequential
reads, the 47L64 increments the internal Address
Pointer by one after the transfer of each data byte.
This allows the entire memory contents to be serially
read during one operation. The Address Pointer will
automatically roll over at the end of the array to
address 0x0000 after the last data byte in the array
has been transferred.
Upon receipt of the control byte with the R/W bit set to
‘1’, the 47L64 issues an Acknowledge and transmits
the 8-bit data byte. The master will not acknowledge
the transfer, but does generate a Stop condition and
the 47L64 discontinues transmission (Figure 4-6).
FIGURE 4-6:
Random Read
N
O
A
C
K
SRAM RANDOM READ
S
T
A
R
T
CONTROL
BYTE
S1 0 1 0 AA10
2 1
BUS ACTIVITY
ADDRESS
HIGH BYTE
XXX
A
C
K
A
C
K
X = Don’t Care
2019-2020 Microchip Technology Inc.
S
T
A
R
T
ADDRESS
LOW BYTE
Preliminary
A
C
K
CONTROL
BYTE
S 1 0 1 0 A A1 1
2 1
S
T
O
P
DATA
BYTE
P
A
C
K
N
O
A
C
K
DS20006168B-page 16
47L64
FIGURE 4-8:
BUS ACTIVITY
MASTER
SRAM SEQUENTIAL READ
CONTROL
BYTE
DATA n
DATA n + 1
P
SDA LINE
BUS ACTIVITY
S
T
O
P
DATA n + X
DATA n + 2
A
C
K
2019-2020 Microchip Technology Inc.
A
C
K
Preliminary
A
C
K
A
C
K
N
O
A
C
K
DS20006168B-page 17
47L64
5.0
PACKAGING INFORMATION
5.1
Package Marking Information
Example
8-Lead SOIC (3.90 mm)
47L64
SN e3 1849
13F
XXXXXXXX
XXXXYYWW
NNN
8-Lead 2x3 TDFN
Example
XXX
YWW
NN
EK4
849
13
1st Line Marking
Part No.
47L64
Legend: XX...X
Y
YY
WW
NNN
e3
SOIC
TDFN
47L64
EK4
Part number or part number code
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code (2 characters for small packages)
JEDEC® designator for Matte Tin (Sn)
2019-2020 Microchip Technology Inc.
Preliminary
DS20006168B-page 18
47L64
8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm (.150 In.) Body [SOIC]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2X
0.10 C A–B
D
A
D
NOTE 5
N
E
2
E1
2
E1
E
NOTE 1
2
1
e
B
NX b
0.25
C A–B D
NOTE 5
TOP VIEW
0.10 C
C
A A2
SEATING
PLANE
8X
A1
SIDE VIEW
0.10 C
h
R0.13
h
R0.13
H
0.23
L
SEE VIEW C
(L1)
VIEW A–A
VIEW C
Microchip Technology Drawing No. C04-057-SN Rev E Sheet 1 of 2
2019-2020 Microchip Technology Inc.
Preliminary
DS20006168B-page 19
47L64
8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm (.150 In.) Body [SOIC]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Units
Dimension Limits
Number of Pins
N
e
Pitch
Overall Height
A
Molded Package Thickness
A2
§
Standoff
A1
Overall Width
E
Molded Package Width
E1
Overall Length
D
Chamfer (Optional)
h
Foot Length
L
Footprint
L1
Foot Angle
c
Lead Thickness
b
Lead Width
Mold Draft Angle Top
Mold Draft Angle Bottom
MIN
1.25
0.10
0.25
0.40
0°
0.17
0.31
5°
5°
MILLIMETERS
NOM
8
1.27 BSC
6.00 BSC
3.90 BSC
4.90 BSC
1.04 REF
-
MAX
1.75
0.25
0.50
1.27
8°
0.25
0.51
15°
15°
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. § Significant Characteristic
3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or
protrusions shall not exceed 0.15mm per side.
4. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
5. Datums A & B to be determined at Datum H.
Microchip Technology Drawing No. C04-057-SN Rev E Sheet 2 of 2
2019-2020 Microchip Technology Inc.
Preliminary
DS20006168B-page 20
47L64
8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm Body [SOIC]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
SILK SCREEN
C
Y1
X1
E
RECOMMENDED LAND PATTERN
Units
Dimension Limits
Contact Pitch
E
Contact Pad Spacing
C
Contact Pad Width (X8)
X1
Contact Pad Length (X8)
Y1
MIN
MILLIMETERS
NOM
1.27 BSC
5.40
MAX
0.60
1.55
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Microchip Technology Drawing C04-2057-SN Rev E
2019-2020 Microchip Technology Inc.
Preliminary
DS20006168B-page 21
47L64
8-Lead Plastic Dual Flat, No Lead Package (MN) – 2x3x0.8 mm Body [TDFN]
With 1.4x1.3 mm Exposed Pad (JEDEC Package type WDFN)
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
D
A
B
N
(DATUM A)
(DATUM B)
E
NOTE 1
2X
0.15 C
1
2
2X
0.15 C
TOP VIEW
0.10 C
C
(A3)
A
SEATING
PLANE
8X
0.08 C
A1
SIDE VIEW
0.10
C A B
D2
L
1
2
0.10
C A B
NOTE 1
E2
K
N
8X b
e
0.10
0.05
C A B
C
BOTTOM VIEW
Microchip Technology Drawing No. C04-129-MN Rev E Sheet 1 of 2
2019-2020 Microchip Technology Inc.
Preliminary
DS20006168B-page 22
47L64
8-Lead Plastic Dual Flat, No Lead Package (MN) – 2x3x0.8 mm Body [TDFN]
With 1.4x1.3 mm Exposed Pad (JEDEC Package type WDFN)
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Units
Dimension Limits
N
Number of Pins
e
Pitch
A
Overall Height
A1
Standoff
A3
Contact Thickness
D
Overall Length
E
Overall Width
D2
Exposed Pad Length
E2
Exposed Pad Width
b
Contact Width
L
Contact Length
Contact-to-Exposed Pad
K
MIN
0.70
0.00
1.35
1.25
0.20
0.25
0.20
MILLIMETERS
NOM
8
0.50 BSC
0.75
0.02
0.20 REF
2.00 BSC
3.00 BSC
1.40
1.30
0.25
0.30
-
MAX
0.80
0.05
1.45
1.35
0.30
0.45
-
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Package may have one or more exposed tie bars at ends.
3. Package is saw singulated
4. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing No. C04-129-MN Rev E Sheet 2 of 2
2019-2020 Microchip Technology Inc.
Preliminary
DS20006168B-page 23
47L64
8-Lead Plastic Dual Flat, No Lead Package (MN) – 2x3x0.8 mm Body [TDFN]
With 1.4x1.3 mm Exposed Pad (JEDEC Package type WDFN)
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
X2
EV
8
ØV
C
Y2
EV
Y1
1
2
SILK SCREEN
X1
E
RECOMMENDED LAND PATTERN
Units
Dimension Limits
Contact Pitch
E
Optional Center Pad Width
X2
Optional Center Pad Length
Y2
Contact Pad Spacing
C
Contact Pad Width (X8)
X1
Contact Pad Length (X8)
Y1
Thermal Via Diameter
V
Thermal Via Pitch
EV
MIN
MILLIMETERS
NOM
0.50 BSC
MAX
1.60
1.50
2.90
0.25
0.85
0.30
1.00
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
2. For best soldering results, thermal vias, if used, should be filled or tented to avoid solder loss during
reflow process
Microchip Technology Drawing No. C04-129-MN Rev. B
2019-2020 Microchip Technology Inc.
Preliminary
DS20006168B-page 24
47L64
APPENDIX A:
REVISION HISTORY
Revision B (01/2020)
Updated VCAP Capacitor values and Section 2.4
Write-Protect Input; Updated Section 4.1.1.5.
Revision A (03/2019)
Initial release of the document.
2019-2020 Microchip Technology Inc.
Preliminary
DS20006168B-page 25
47L64
THE MICROCHIP WEBSITE
CUSTOMER SUPPORT
Microchip provides online support via our website at
www.microchip.com. This website is used as a means
to make files and information easily available to
customers. Accessible by using your favorite Internet
browser, the website contains the following information:
Users of Microchip products can receive assistance
through several channels:
• Product Support – Data sheets and errata,
application notes and sample programs, design
resources, user’s guides and hardware support
documents, latest software releases and archived
software
• General Technical Support – Frequently Asked
Questions (FAQ), technical support requests,
online discussion groups, Microchip consultant
program member listing
• Business of Microchip – Product selector and
ordering guides, latest Microchip press releases,
listing of seminars and events, listings of
Microchip sales offices, distributors and factory
representatives
•
•
•
•
Distributor or Representative
Local Sales Office
Field Application Engineer (FAE)
Technical Support
Customers
should
contact
their
distributor,
representative or Field Application Engineer (FAE) for
support. Local sales offices are also available to help
customers. A listing of sales offices and locations is
included in the back of this document.
Technical support is available through the website
at: http://microchip.com/support
CUSTOMER CHANGE NOTIFICATION
SERVICE
Microchip’s customer notification service helps keep
customers current on Microchip products. Subscribers
will receive e-mail notification whenever there are
changes, updates, revisions or errata related to a
specified product family or development tool of interest.
To register, access the Microchip website at
www.microchip.com. Under “Support”, click on
“Customer Change Notification” and follow the
registration instructions.
2019-2020 Microchip Technology Inc.
Preliminary
DS20006168B-page 26
47L64
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
[X](1)
X
/XX
XXX
Tape and Reel
Option
Temperature
Range
Package
Pattern
PART NO.
Device
47L64 = 64 Kbit I2C EERAM
Tape and Reel
Option:
Blank
T
= Standard packaging (tube or tray)
= Tape and Reel(1)
Temperature
Range:
I
= -40C to
Package:
SN
=
MNY
=
47L64T-I/SN = Tape and Reel, Industrial temp.,
SOIC package,
47L64-I/SN = Industrial temp., SOIC package
47L64T-I/MNY = Tape and Reel, Industrial
temp., TDFN package
(Industrial)
Plastic Small Outline - Narrow,
3.90 mm Body, 8-lead (SOIC)
Plastic Dual Flat, No Lead Package 2x3x0.8 mm Body, 8-lead (TDFN)
2019-2020 Microchip Technology Inc.
a)
b)
c)
Device:
+85C
Examples:
Preliminary
Note
1:
Tape and Reel identifier only appears in
the catalog part number description. This
identifier is used for ordering purposes
and is not printed on the device package.
Check with your Microchip Sales Office
for package availability with the Tape and
Reel option.
DS20006168B-page 27
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
•
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights unless otherwise stated.
Trademarks
The Microchip name and logo, the Microchip logo, Adaptec,
AnyRate, AVR, AVR logo, AVR Freaks, BesTime, BitCloud, chipKIT,
chipKIT logo, CryptoMemory, CryptoRF, dsPIC, FlashFlex,
flexPWR, HELDO, IGLOO, JukeBlox, KeeLoq, Kleer, LANCheck,
LinkMD, maXStylus, maXTouch, MediaLB, megaAVR, Microsemi,
Microsemi logo, MOST, MOST logo, MPLAB, OptoLyzer,
PackeTime, PIC, picoPower, PICSTART, PIC32 logo, PolarFire,
Prochip Designer, QTouch, SAM-BA, SenGenuity, SpyNIC, SST,
SST Logo, SuperFlash, Symmetricom, SyncServer, Tachyon,
TempTrackr, TimeSource, tinyAVR, UNI/O, Vectron, and XMEGA
are registered trademarks of Microchip Technology Incorporated in
the U.S.A. and other countries.
APT, ClockWorks, The Embedded Control Solutions Company,
EtherSynch, FlashTec, Hyper Speed Control, HyperLight Load,
IntelliMOS, Libero, motorBench, mTouch, Powermite 3, Precision
Edge, ProASIC, ProASIC Plus, ProASIC Plus logo, Quiet-Wire,
SmartFusion, SyncWorld, Temux, TimeCesium, TimeHub,
TimePictra, TimeProvider, Vite, WinPath, and ZL are registered
trademarks of Microchip Technology Incorporated in the U.S.A.
Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any
Capacitor, AnyIn, AnyOut, BlueSky, BodyCom, CodeGuard,
CryptoAuthentication, CryptoAutomotive, CryptoCompanion,
CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average
Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial
Programming, ICSP, INICnet, Inter-Chip Connectivity, JitterBlocker,
KleerNet, KleerNet logo, memBrain, Mindi, MiWi, MPASM, MPF,
MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach,
Omniscient Code Generation, PICDEM, PICDEM.net, PICkit,
PICtail, PowerSmart, PureSilicon, QMatrix, REAL ICE, Ripple
Blocker, SAM-ICE, Serial Quad I/O, SMART-I.S., SQI,
SuperSwitcher, SuperSwitcher II, Total Endurance, TSHARC,
USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and
ZENA are trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated in
the U.S.A.
The Adaptec logo, Frequency on Demand, Silicon Storage
Technology, and Symmcom are registered trademarks of Microchip
Technology Inc. in other countries.
GestIC is a registered trademark of Microchip Technology Germany
II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in
other countries.
All other trademarks mentioned herein are property of their
respective companies.
© 2019-2020, Microchip Technology Incorporated, All Rights
Reserved.
For information regarding Microchip’s Quality Management Systems,
please visit www.microchip.com/quality.
2019-2020 Microchip Technology Inc.
ISBN: 978-1-5224-5518-9
Preliminary
DS20006168B-page 28
Worldwide Sales and Service
AMERICAS
ASIA/PACIFIC
ASIA/PACIFIC
EUROPE
Corporate Office
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7200
Fax: 480-792-7277
Technical Support:
http://www.microchip.com/
support
Web Address:
www.microchip.com
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Tel: 61-2-9868-6733
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Tel: 91-80-3090-4444
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Tel: 512-257-3370
Boston
Westborough, MA
Tel: 774-760-0087
Fax: 774-760-0088
Chicago
Itasca, IL
Tel: 630-285-0071
Fax: 630-285-0075
Dallas
Addison, TX
Tel: 972-818-7423
Fax: 972-818-2924
Detroit
Novi, MI
Tel: 248-848-4000
Houston, TX
Tel: 281-894-5983
Indianapolis
Noblesville, IN
Tel: 317-773-8323
Fax: 317-773-5453
Tel: 317-536-2380
China - Xiamen
Tel: 86-592-2388138
Finland - Espoo
Tel: 358-9-4520-820
France - Paris
Tel: 33-1-69-53-63-20
Fax: 33-1-69-30-90-79
Germany - Garching
Tel: 49-8931-9700
Germany - Haan
Tel: 49-2129-3766400
Germany - Heilbronn
Tel: 49-7131-72400
Germany - Karlsruhe
Tel: 49-721-625370
Germany - Munich
Tel: 49-89-627-144-0
Fax: 49-89-627-144-44
Germany - Rosenheim
Tel: 49-8031-354-560
Israel - Ra’anana
Tel: 972-9-744-7705
Italy - Milan
Tel: 39-0331-742611
Fax: 39-0331-466781
Italy - Padova
Tel: 39-049-7625286
Netherlands - Drunen
Tel: 31-416-690399
Fax: 31-416-690340
Norway - Trondheim
Tel: 47-7288-4388
China - Zhuhai
Tel: 86-756-3210040
Poland - Warsaw
Tel: 48-22-3325737
Los Angeles
Mission Viejo, CA
Tel: 949-462-9523
Fax: 949-462-9608
Tel: 951-273-7800
Romania - Bucharest
Tel: 40-21-407-87-50
Spain - Madrid
Tel: 34-91-708-08-90
Fax: 34-91-708-08-91
Raleigh, NC
Tel: 919-844-7510
Sweden - Gothenberg
Tel: 46-31-704-60-40
New York, NY
Tel: 631-435-6000
Sweden - Stockholm
Tel: 46-8-5090-4654
San Jose, CA
Tel: 408-735-9110
Tel: 408-436-4270
UK - Wokingham
Tel: 44-118-921-5800
Fax: 44-118-921-5820
Canada - Toronto
Tel: 905-695-1980
Fax: 905-695-2078
2019-2020 Microchip Technology Inc.
Denmark - Copenhagen
Tel: 45-4450-2828
Fax: 45-4485-2829
Preliminary
DS20006168B-page 29
05/14/19
