A10V10B-1PG84B

ACT™ 1 Series FPGAs F eatures • 5V and 3.3V Families fully compatible with JEDEC specifications • Up to 2000 Gate Array Gates (6000 PLD equivalent gates) • Replaces up to 50 TTL Packages • Replaces up to twenty 20-Pin PAL® Packages • Design Library with over 250 Macro Functions • Gate Array Architecture Allows Completely Automatic Place and Route • Up to 547 Programmable Logic Modules • Up to 273 Flip-Flops • Data Rates to 75 MHz • Two In-Circuit Diagnostic Probe Pins Support Speed Analysis to 25 MHz • Built-In High Speed Clock Distribution Network • I/O Drive to 10 mA (5 V), 6 mA (3.3 V) • Nonvolatile, User Programmable • Fabricated in 1.0 micron CMOS technology D escription A security fuse may be programmed to disable all further programming and to protect the design from being copied or reverse engineered. P roduct Family Profile Device Capacity Gate Array Equivalent Gates PLD Equivalent Gates TTL Equivalent Packages 20-Pin PAL Equivalent Packages Logic Modules Flip-Flops (maximum) Routing Resources Horizontal Tracks/Channel Vertical Tracks/Column PLICE Antifuse Elements User I/Os (maximum) Packages: A1010B A10V10B 1,200 3,000 30 12 295 147 22 13 112,000 57 44 PLCC 68 PLCC A1020B A10V20B 2,000 6,000 50 20 547 273 22 13 186,000 69 The ACT™ 1 Series of field programmable gate arrays (FPGAs) offers a variety of package, speed, and application combinations. Devices are implemented in silicon gate, 1-micron two-level metal CMOS, and they employ Actel’s PLICE® antifuse technology. The unique architecture offers gate array flexibility, high performance, and instant turnaround through user programming. Device utilization is typically 95 to 100 percent of available logic modules. ACT 1 devices also provide system designers with unique on-chip diagnostic probe capabilities, allowing convenient testing and debugging. Additional features include an on-chip clock driver with a hardwired distribution network. The network provides efficient clock distribution with minimum skew. The user-definable I/Os are capable of driving at both TTL and CMOS drive levels. Available packages include plastic and ceramic J-leaded chip carriers, ceramic and plastic quad flatpacks, and ceramic pin grid array. 44 PLCC 68 PLCC 84 PLCC 100 PQFP 100 PQFP 80 VQFP 80 VQFP 84 CPGA 84 CPGA 84 CQFP 75 MHz 55 MHz 75 MHz 55 MHz Performance 5 V Data Rate (maximum) 3.3 V Data Rate (maximum) Note: See Product Plan on page 1-286 for package availability. The Designer and Designer Advantage™ Systems The ACT 1 device family is supported by Actel’s Designer and Designer Advantage Systems, allowing logic design implementation with minimum effort. The systems offer Microsoft® Windows™ and X Windows™ graphical user interfaces and integrate with the resident CAE system to provide a complete gate array design environment: schematic capture, simulation, fully automatic place and route, timing verification, and device programming. The systems also include the ACTmap™ VHDL optimization and synthesis tool and the ACTgen™ Macro Builder, a powerful macro function generator for counters, adders, and other structural blocks. April 1996 1-283 © 1996 Actel Corporation The systems are available for 386/486/Pentium™ PC and for HP™ and Sun™ workstations and for running Viewlogic®, Mentor Graphics®, Cadence™, OrCAD™, and Synopsys design environments. Figure 1 • Partial View of an ACT 1 Device A CT 1 Device Structure A partial view of an ACT 1 device (Figure 1) depicts four logic modules and distributed horizontal and vertical interconnect tracks. PLICE antifuses, located at intersections of the horizontal and vertical tracks, connect logic module inputs and outputs. During programming, these antifuses are addressed and programmed to make the connections required by the circuit application. T he ACT 1 Logic Module The ACT 1 logic module is an 8-input, one-output logic circuit chosen for the wide range of functions it implements and for its efficient use of interconnect routing resources (Figure 2). The logic module can implement the four basic logic functions (NAND, AND, OR, and NOR) in gates of two, three, or four inputs. Each function may have many versions, with different combinations of active-low inputs. The logic module can also implement a variety of D-latches, exclusivity functions, AND-ORs, and OR-ANDs. No dedicated hardwired latches or flip-flops are required in the array, since latches and flip-flops may be constructed from logic modules wherever needed in the application. Figure 2 • ACT 1 Logic Module I /O Buffers Each I/O pin is available as an input, output, three-state, or bidirectional buffer. Input and output levels are compatible with standard TTL and CMOS specifications. Outputs sink or 1-284 A C T ™ 1 S eri es FP G As source 10 mA at TTL levels. See Electrical Specifications for additional I/O buffer specifications. D evice O rganization A CT 1 Array Performance T emperature and Voltage Effects ACT 1 devices consist of a matrix of logic modules arranged in rows separated by wiring channels. This array is surrounded by a ring of peripheral circuits including I/O buffers, testability circuits, and diagnostic probe circuits providing real-time diagnostic capability. Between rows of logic modules are routing channels containing sets of segmented metal tracks with PLICE antifuses. Each channel has 22 signal tracks. Vertical routing is permitted via 13 vertical tracks per logic module column. The resulting network allows arbitrary and flexible interconnections between logic modules and I/O modules. P robe Pin Worst-case delays for ACT 1 arrays are calculated in the same manner as for masked array products. A typical delay parameter is multiplied by a derating factor to account for temperature, voltage, and processing effects. However, in an ACT 1 array, temperature and voltage effects are less dramatic than with masked devices. The electrical characteristics of module interconnections on ACT 1 devices remain constant over voltage and temperature fluctuations. As a result, the total derating factor from typical to worst-case for a standard speed ACT 1 array is only 1.19 to 1, compared to 2 to 1 for a masked gate array. L ogic Module Size ACT 1 devices have two independent diagnostic probe pins. These pins allow the user to observe any two internal signals by entering the appropriate net name in the diagnostic software. Signals may be viewed on a logic analyzer using Actel’s Actionprobe® diagnostic tools. The probe pins can also be used as user-defined I/Os when debugging is finished. O rdering Information A1010 B – 2 PL 84 Logic module size also affects performance. A mask programmed gate array cell with four transistors usually implements only one logic level. In the more complex logic module (similar to the complexity of a gate array macro) of an ACT 1 array, implementation of multiple logic levels within a single module is possible. This eliminates interlevel wiring and associated RC delays. The effect is termed “net compression.” C Application (Temperature Range) C = Commercial (0 to +70°C) I = Industrial (–40 to +85°C) M = Military (–55 to +125°C) B = MIL-STD-883 Package Lead Count Package Type PL = Plastic J-Leaded Chip Carriers PQ = Plastic Quad Flatpacks CQ = Ceramic Quad Flatpack PG = Ceramic Pin Grid Array VQ = Very Thin Quad Flatpack Speed Grade Blank = Standard Speed –1 = Approximately 15% faster than Standard –2 = Approximately 25% faster than Standard –3 = Approximately 35% faster than Standard Die Revision B = 1.0 micron CMOS Process Part Number A1010 A1020 A10V10 A10V20 = = = = 1200 Gates (5 V) 2000 Gates (5 V) 1200 Gates (3.3 V) 2000 Gates (3.3 V) 1-285 P roduct Plan Speed Grade* Std A1010B Device 44-pin Plastic Leaded Chip Carrier (PL) 68-pin Plastic Leaded Chip Carrier (PL) 100-pin Plastic Quad Flatpack (PQ) 80-pin Very Thin (1.0 mm) Quad Flatpack (VQ) 84-pin Ceramic Pin Grid Array (PG) A1020B Device 44-pin Plastic Leaded Chip Carrier (PL) 68-pin Plastic Leaded Chip Carrier (PL) 84-pin Plastic Leaded Chip Carrier (PL) 100-pin Plastic Quad Flatpack (PQ) 80-pin Very Thin (1.0 mm) Quad Flatpack (VQ) 84-pin Ceramic Pin Grid Array (PG) 84-pin Ceramic Quad Flatpack (CQ) A10V10B Device 68-pin Plastic Leaded Chip Carrier (PL) 80-pin Very Thin (1.0 mm) Quad Flatpack (VQ) A10V20B Device 68-pin Plastic Leaded Chip Carrier (PL) 84-pin Plastic Leaded Chip Carrier (PL) 80-pin Very Thin (1.0 mm) Quad Flatpack (VQ) Applications: C I M B = = = = — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — –1 –2 –3 C I Application M B Commercial Availability: = Available * Speed Grade: –1 = Approx. 15% faster than Standard Industrial P = Planned –2 = Approx. 25% faster than Standard Military — = Not Planned –3 = Approx. 35% faster than Standard MIL-STD-883 D evice Resources User I/Os Device A1010B, A10V10B A1020B, A10V20B Logic Modules 295 547 Gates 1200 2000 44-pin 34 34 68-pin 57 57 80-pin 57 69 84-pin 57 69 100-pin 57 69 1-286 A C T ™ 1 S eri es FP G As P in Description C LK Clock (Input) P RA Probe A (Output) TTL Clock input for global clock distribution network. The Clock input is buffered prior to clocking the logic modules. This pin can also be used as an I/O. D CLK Diagnostic Clock (Input) TTL Clock input for diagnostic probe and device programming. DCLK is active when the MODE pin is HIGH. This pin functions as an I/O when the MODE pin is LOW. G ND Ground The Probe A pin is used to output data from any user-defined design node within the device. This independent diagnostic pin is used in conjunction with the Probe B pin to allow real-time diagnostic output of any signal path within the device. The Probe A pin can be used as a user-defined I/O when debugging has been completed. The pin’s probe capabilities can be permanently disabled to protect the programmed design’s confidentiality. PRA is active when the MODE pin is HIGH. This pin functions as an I/O when the MODE pin is LOW. P RB Probe B (Output) Input LOW supply voltage. I /O Input/Output (Input, Output) I/O pin functions as an input, output, three-state, or bidirectional buffer. Input and output levels are compatible with standard TTL and CMOS specifications. Unused I/O pins are automatically driven LOW by the ALS software. M ODE Mode (Input) The MODE pin controls the use of multifunction pins (DCLK, PRA, PRB, SDI). When the MODE pin is HIGH, the special functions are active. When the MODE pin is LOW, the pins function as I/O. To provide Actionprobe capability, the MODE pin should be terminated to GND through a 10K resistor so that the MODE pin can be pulled high when required. NC No Connection The Probe B pin is used to output data from any user-defined design node within the device. This independent diagnostic pin is used in conjunction with the Probe A pin to allow real-time diagnostic output of any signal path within the device. The Probe B pin can be used as a user-defined I/O when debugging has been completed. The pin’s probe capabilities can be permanently disabled to protect the programmed design’s confidentiality. PRB is active when the MODE pin is HIGH. This pin functions as an I/O when the MODE pin is LOW. S DI Serial Data Input (Input) Serial data input for diagnostic probe and device programming. SDI is active when the MODE pin is HIGH. This pin functions as an I/O when the MODE pin is LOW. VCC S upply Voltage This pin is not connected to circuitry within the device. Input HIGH supply voltage. A bsolute Maximum Ratings 1 F ree air temperature range Symbol VCC VI VO IIO TSTG Parameter DC Supply Voltage2 Input Voltage Output Voltage I/O Sink/Source Current3 Storage Temperature Limits –0.5 to +7.0 –0.5 to VCC +0.5 –0.5 to VCC +0.5 ± 20 –65 to +150 Units Volts Volts Volts mA °C R ecommended Operating Conditions Parameter Commercial Industrial Military Units Temperature Range1 Power Supply Tolerance 0 to +70 ±5 –40 to +85 ± 10 –55 to +125 ± 10 °C %VCC Note: 1. Ambient temperature (TA) used for commercial and industrial; case temperature (TC) used for military. Notes: 1. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. Device should not be operated outside the Recommended Operating Conditions. 2. VPP = VCC , except during device programming. 3. Device inputs are normally high impedance and draw extremely low current. However, when input voltage is greater than VCC + 0.5 V or less than GND – 0.5 V, the internal protection diode will be forward biased and can draw excessive current. 1-287 E lectrical Specifications (5V) Commercial Symbol Parameter (IOH = –10 mA)2 VOH1 (IOH = –6 mA) (IOH = –4 mA) VOL1 VIL VIH Input Transition Time tR, tF2 CIO I/O Capacitance2, 3 Standby Current, ICC4 (typical 5 (IOL = 10 mA)2 0.5 0.33 –0.3 2.0 0.8 VCC + 0.3 500 10 = 1 mA) –10 3 10 –10 –0.3 2.0 0.40 0.8 VCC + 0.3 500 10 10 10 –10 –0.3 2.0 0.40 0.8 VCC + 0.3 500 10 20 10 (IOL = 6 mA) Min. 2.4 3.84 3.7 3.7 Max. Industrial Min. Max. Min. Military Max. Units V V V V V V V ns pF mA µA Leakage Current Notes: 1. Only one output tested at a time. VCC = min. 2. Not tested, for information only. 3. Includes worst-case 84-pin PLCC package capacitance. VOUT = 0 V, f = 1 MHz. 4. Typical standby current = 1 mA. All outputs unloaded. All inputs = VCC or GND. 5. VO , VIN = VCC or GND. Electrical Specifications (3.3V) Parameter Min. VOH1 VOL1 VIL VIH Input Transition Time tR, tF2 CIO I/O Capacitance2, 3 Standby Current, ICC4 (typical 5 (IOH = –4 mA) (IOH = –3.2 mA) (IOL = 6 mA) –0.3 2.0 2.15 2.4 0.4 0.8 VCC + 0.3 500 10 = 0.3 mA) –10 0.75 10 Commercial Max. V V V V V ns pF mA µA Units Leakage Current Notes: 1. Only one output tested at a time. VCC = min. 2. Not tested, for information only. 3. Includes worst-case 84-pin PLCC package capacitance. VOUT = 0 V, f = 1 MHz. 4. Typical standby current = 0.3 mA. All outputs unloaded. All inputs = VCC or GND. 5. VO, VIN = VCC or GND 1-288 A C T ™ 1 S eri es FP G As Package Thermal Characteristics The device junction to case thermal characteristics is θjc, and the junction to ambient air characteristics is θja. The thermal characteristics for θja are shown with two different air flow rates. Maximum junction temperature is 150°C. A sample calculation of the maximum power dissipation for an 84-pin plastic leaded chip carrier at commercial temperature is as follows: Max junction temp. ( ° C ) – M ax commercial temp. ( ° C ) 150 ° C – 70 ° C ------------------------------------------------------------------------------------------------------------------------------------------------- = ---------------------------------- = 2.2 W θja(°C ⁄ W) 37 ° C ⁄ W Package Type Plastic J-Leaded Chip Carrier Plastic Quad Flatpack Very Thin (1.0 mm) Quad Flatpack Ceramic Pin Grid Array Ceramic Quad Flatpack Pin Count 44 68 84 100 80 84 84 θjc 15 13 12 13 12 8 5 θja Still Air 45 38 37 48 43 33 40 θja 300 ft/min 35 29 28 40 35 20 30 Units °C/W °C/W °C/W °C/W °C/W °C/W °C/W General Power Equation P = [ICCstandby + ICCactive] * VCC + IOL * VOL * N + IOH * (VCC – VOH) * M Where: ICCstandby is the current flowing when no inputs or outputs are changing. ICCactive is the current flowing due to CMOS switching. IOL, IOH are TTL sink/source currents. VOL, VOH are TTL level output voltages. N equals the number of outputs driving TTL loads to VOL. M equals the number of outputs driving TTL loads to VOH. An accurate determination of N and M is problematical because their values depend on the family type, design details, and on the system I/O. The power can be divided into two components: static and active. Static Power Component The power due to standby current is typically a small component of the overall power. Standby power is calculated below for commercial, worst case conditions. ICC 3 mA 1 mA 0.75 mA 0.30 mA VCC 5.25 V 5.25 V 3.60 V 3.30 V Power 15.75 mW (max) 5.25 mW (typ) 2.70 mW (max) 0.99 mW (typ) Active Power Component Power dissipation in CMOS devices is usually dominated by the active (dynamic) power dissipation. This component is frequency dependent, a function of the logic and the external I/O. Active power dissipation results from charging internal chip capacitances of the interconnect, unprogrammed antifuses, module inputs, and module outputs, plus external capacitance due to PC board traces and load device inputs. An additional component of the active power dissipation is the totem-pole current in CMOS transistor pairs. The net effect can be associated with an equivalent capacitance that can be combined with frequency and voltage to represent active power dissipation. Actel FPGAs have small static power components that result in lower power dissipation than PALs or PLDs. By integrating multiple PALs/PLDs into one FPGA, an even greater reduction in board-level power dissipation can be achieved. 1-289 E quivalent Capacitance CEQM CEQI CEQO CEQCR CL fm fn fp fq1 = Equivalent capacitance of logic modules in pF = Equivalent capacitance of input buffers in pF = Equivalent capacitance of output buffers in pF = Equivalent capacitance of routed array clock in pF = Output lead capacitance in pF = Average logic module switching rate in MHz = Average input buffer switching rate in MHz = Average output buffer switching rate in MHz = Average first routed array clock rate in MHz (All families) The power dissipated by a CMOS circuit can be expressed by the Equation 1. Power (uW) = CEQ * VCC2 * F Where: CEQ is the equivalent capacitance expressed in pF. VCC is the power supply in volts. F is the switching frequency in MHz. Equivalent capacitance is calculated by measuring ICCactive at a specified frequency and voltage for each circuit component of interest. Measurements have been made over a range of frequencies at a fixed value of VCC. Equivalent capacitance is frequency independent so that the results may be used over a wide range of operating conditions. Equivalent capacitance values are shown below. C E Q V alues for Actel FPGAs (1) F ixed Capacitance Values for Actel FPGAs (pF) Device Type A1010B A1020B 3.7 22.1 31.2 4.6 A1010B A1020B A10V10B A10V20B r1 routed_Clk1 41.4 68.6 40 65 A10V10B A10V20B Modules (CEQM) Input Buffers (CEQI) Output Buffers (CEQO) Routed Array Clock Buffer Loads (CEQCR) 3.2 10.9 11.6 4.1 Determining Average Switching Frequency To calculate the active power dissipated from the complete design, the switching frequency of each part of the logic must be known. Equation 2 shows a piece-wise linear summation over all components. Power = VCC2 * [(m * CEQM * fm)modules + (n * CEQI* fn)inputs + (p * (CEQO+ CL) * fp)outputs + 0.5 * (q1 * CEQCR * fq1)routed_Clk1 + (r1 * fq1)routed_Clk1] Where: m n p q1 r1 = Number of logic modules switching at fm = Number of input buffers switching at fn = Number of output buffers switching at fp = Number of clock loads on the first routed array clock (All families) = Fixed capacitance due to first routed array clock (All families) To determine the switching frequency for a design, you must have a detailed understanding of the data input values to the circuit. The following guidelines are meant to represent worst-case scenarios so that they can be generally used to predict the upper limits of power dissipation. These guidelines are as follows: Logic Modules (m) Inputs switching (n) Outputs switching (p) First routed array clock loads (q1) Load capacitance (CL) Average input switching rate (fn) Average output switching rate (fp) 90% of modules #inputs/4 #outputs/4 40% of modules 35 pF F/5 F/10 (2) Average logic module switching rate (fm) F/10 Average first routed array clock rate F (fq1) 1-290 A C T ™ 1 S eri es FP G As Functional Timing Tests AC timing for logic module internal delays is determined after place and route. The DirectTime Analyzer utility displays actual timing parameters for circuit delays. ACT 1 devices are AC tested to a “binning” circuit specification. The circuit consists of one input buffer + n logic modules + one output buffer (n = 16 for A1010B; n = 28 for A1020B). The logic modules are distributed along two sides of the device, as inverting or non-inverting buffers. The modules are connected through programmed antifuses with typical capacitive loading. Propagation delay [tPD = (tPLH + tPHL)/2] is tested to the following AC test specifications. Output Buffer Performance Derating (5V) Sink 12 –4 Source 10 IOH (mA) 0.3 0.4 VOL (Volts) 0.5 0.6 IOL (mA) –6 8 –8 6 –10 4 0.2 –12 4.0 3.6 3.2 2.8 2.4 2.0 VOH (Volts) Military, worst-case values at 125°C, 4.5 V. Commercial, worst-case values at 70°C, 4.75 V. Note: The above curves are based on characterizations of sample devices and are not completely tested on all devices. Output Buffer Performance Derating (3.3V) Sink 12 –4 Source 10 IOH (mA) 0.1 0.2 VOL (Volts) 0.3 0.4 IOL (mA) –6 8 –8 6 –10 4 0.0 –12 0 0.5 1.0 1.5 2.0 2.5 VOH (Volts) Commercial, worst-case values at 70°C, 4.75 V. Note: The above curves are based on characterizations of sample devices and are not completely tested on all devices. 1-291 ACT 1 Timing Module* Input Delay I/O Module tINYL = 3.1 ns tIRD2 = 1.4 ns Internal Delays Predicted Routing Delays Output Delay I/O Module Logic Module tDLH = 6.7 ns tIRD1 = 0.9 ns tIRD4 = 3.1 ns tIRD8 = 6.6 ns tPD = 2.9 ns tCO = 2.9 ns tRD1 = 0.9 ns tRD2 = 1.4 ns tRD4 = 3.1 ns tRD8 = 6.6 ns tENHZ = 11.6 ns ARRAY CLOCK tCKH = 5.6 ns FMAX = 70 MHz FO = 128 * Values shown for ACT 1 ‘–3 speed’ devices at worst-case commercial conditions. Predictable Performance: Tight Delay Distributions Timing Characteristics Propagation delay between logic modules depends on the resistive and capacitive loading of the routing tracks, the interconnect elements, and the module inputs being driven. Propagation delay increases as the length of routing tracks, the number of interconnect elements, or the number of inputs increases. From a design perspective, the propagation delay can be statistically correlated or modeled by the fanout (number of loads) driven by a module. Higher fanout usually requires some paths to have longer routing tracks. The ACT 1 family delivers a very tight fanout delay distribution. This tight distribution is achieved in two ways: by decreasing the delay of the interconnect elements and by decreasing the number of interconnect elements per path. Actel’s patented PLICE antifuse offers a very low resistive/capacitive interconnect. The ACT 1 family’s antifuses, fabricated in 1.0 micron lithography, offer nominal levels of 200 ohms resistance and 7.5 femtofarad (fF) capacitance per antifuse. The ACT 1 fanout distribution is also tight due to the low number of antifuses required for each interconnect path. The ACT 1 family’s proprietary architecture limits the number of antifuses per path to a maximum of four, with 90% of interconnects using two antifuses. Timing characteristics for ACT 1 devices fall into three categories: family dependent, device dependent, and design dependent. The input and output buffer characteristics are common to all ACT 1 family members. Internal routing delays are device dependent. Design dependency means actual delays are not determined until after placement and routing of the user design is complete. Delay values may then be determined by using the DirectTime Analyzer utility or performing simulation with post-layout delays. Critical Nets and Typical Nets Propagation delays are expressed only for typical nets, which are used for initial design performance evaluation. Critical net delays can then be applied to the most time-critical paths. Critical nets are determined by net property assignment prior to placement and routing. Up to 6% of the nets in a design may be designated as critical, while 90% of the nets in a design are typical. Long Tracks Some nets in the design use long tracks. Long tracks are special routing resources that span multiple rows, columns, or modules. Long tracks employ three and sometimes four antifuse connections. This increases capacitance and resistance, resulting in longer net delays for macros connected to long tracks. Typically, up to 6% of nets in a fully utilized device require long tracks. Long tracks contribute approximately 5 ns to 10 ns delay. This additional delay is represented statistically in higher fanout (FO=8) routing delays in the data sheet specifications section. 1-292 A C T ™ 1 S eri es FP G As Timing Derating A best case timing derating factor of 0.45 is used to reflect best case processing. Note that this factor is relative to the “standard speed” timing parameters, and must be multiplied by the appropriate voltage and temperature derating factors for a given application. T iming Derating Factor (Tem perature and Voltage) Industrial Min. (Commercial Minimum/Maximum Specification) x 0.69 Max. 1.11 Min. 0.67 Military Max. 1.23 Timing Derating Factor for Designs at Typical Temperature (T J = 2 5 ° C) and Voltage (5.0 V) (Commercial Maximum Specification) x 0.85 Temperature and Voltage Derating Factors (normalized to Worst-Case Commercial, T J = 4 .75 V, 70 ° C) –55 4.50 4.75 5.00 5.25 5.50 0.75 0.71 0.69 0.68 0.67 –40 0.79 0.75 0.72 0.69 0.69 0 0.86 0.82 0.80 0.77 0.76 25 0.92 0.87 0.85 0.82 0.81 70 1.06 1.00 0.97 0.95 0.93 85 1.11 1.05 1.02 0.98 0.97 125 1.23 1.16 1.13 1.09 1.08 Junction Temperature and Voltage Derating Curves (normalized to Worst-Case Commercial, TJ = 4.75 V, 70°C) 1.3 1.2 1.1 1.0 0.9 0.8 0.7 0.6 4.50 4.75 5.00 Voltage (V) Note: This derating factor applies to all routing and propagation delays. 5.25 5.50 25°C 0°C –40°C –55°C Derating Factor 125°C 85°C 70°C 1-293 Temperature and Voltage Deratin g Factors (normalized to Worst-Case Commercial, T J = 3 .0 V, 70 ° C) 0 2.7 3.0 3.3 3.6 1.05 0.81 0.64 0.62 25 1.09 0.84 0.67 0.64 70 1.30 1.00 0.79 0.76 Junction Temperature and Voltage Derating Curves (normalized to Worst-Case Commercial, TJ = 3.0 V, 70°C) 1.3 1.2 Derating Factor 1.1 1.0 0.9 0.8 70°C 0.7 0.6 0.5 2.7 3.0 Voltage (V) Note: This derating factor applies to all routing and propagation delays. 3.3 3.6 25°C 0°C 1-294 A C T ™ 1 S eri es FP G As Parameter Measurement Output Buffer Delays E D TRIBUFF PAD To AC test loads (shown below) VCC In PAD VOL tDLH 50% 50% VOH 1.5 V tDHL GND 1.5 V E PAD VCC 50% VCC 50% 1.5 V VOL tENZL tENLZ GND 10% E PAD GND VCC 50% 50% VOH 1.5 V tENZH tENHZ GND 90% AC Test Loads Load 1 (Used to measure propagation delay) Load 2 (Used to measure rising/falling edges) VCC GND To the output under test 35 pF To the output under test R to VCC for tPLZ/tPZL R to GND for tPHZ/tPZH R = 1 kΩ 35 pF Input Buffer Delays Module Delays PAD INBUF Y S A B VCC Y 3V PAD Y GND tINYH 1.5 V 1.5 V VCC 50% tINYL 0V 50% S, A or B Out GND Out 50% 50% VCC 50% tPLH 50% tPHL tPHL GND 50% VCC GND tPLH 50% 1-295 Sequential Ti ming Characteristics Flip-Flops and Latches D E CLK PRE CLR Q (Positive edge triggered) tHD D1 tSUD CLK tSUENA E tCO Q tRS PRE, CLR tWASYN tWCLKA tA Note: D represents all data functions involving A, B, S for multiplexed flip-flops. 1-296 A C T ™ 1 S eri es FP G As ACT 1 Timing Characteristics ( Worst-Case Commercial Conditions, V CC = 4 .75 V, T J = 7 0 ° C) 1 Logic Module Propagation Delays Parameter tPD1 tPD2 tCO tGO tRS Description Single Module Dual Module Macros Sequential Clk to Q Latch G to Q Flip-Flop (Latch) Reset to Q Delays2 ‘–3’ Speed ‘–2’ Speed ‘–1’ Speed ‘Std’ Speed 3.3 V Speed Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units 2.9 6.8 2.9 2.9 2.9 3.4 7.8 3.4 3.4 3.4 3.8 8.8 3.8 3.8 3.8 4.5 10.4 4.5 4.5 4.5 6.5 15.1 6.5 6.5 6.5 ns ns ns ns ns Predicted Routing tRD1 tRD2 tRD3 tRD4 tRD8 FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay 0.9 1.4 2.1 3.1 6.6 1.1 1.7 2.5 3.6 7.7 1.2 1.9 2.8 4.1 8.7 1.4 2.2 3.3 4.8 10.2 2.0 3.2 4.8 7.0 14.8 ns ns ns ns ns Sequential Timing Characteristics3 tSUD tHD4 tSUENA tHENA tWCLKA tWASYN tA fMAX Flip-Flop (Latch) Data Input Setup Flip-Flop (Latch) Data Input Hold Flip-Flop (Latch) Enable Setup Flip-Flop (Latch) Enable Hold Flip-Flop (Latch) Clock Active Pulse Width Flip-Flop (Latch) Asynchronous Pulse Width Flip-Flop Clock Input Period Flip-Flop (Latch) Clock Frequency (FO = 128) 5.5 0.0 5.5 0.0 6.8 6.8 14.2 70 6.4 0.0 6.4 0.0 8.0 8.0 16.7 60 7.2 0.0 7.2 0.0 9.0 9.0 18.9 53 8.5 0.0 8.5 0.0 10.5 10.5 22.3 45 10.0 0.0 10.0 0.0 9.8 9.8 20.0 50 ns ns ns ns ns ns ns MHz Notes: 1. VCC = 3.0 V for 3.3V specifications. 2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is based on actual routing delay measurements performed on the device prior to shipment. 3. Setup times assume fanout of 3. Further testing information can be obtained from the DirectTime Analyzer utility. 4. The Hold Time for the DFME1A macro may be greater than 0 ns. Use the Designer 3.0 or later Timer to check the Hold Time for this macro. 1-297 ACT 1 Timing Characteristics ( continued) (Worst-Case Commercial Conditions) Input Module Propagation Delays Parameter Description tINYH tINYL Pad to Y High Pad to Y Low ‘–3’ Speed ‘–2’ Speed ‘–1’ Speed ‘Std’ Speed 3.3 V Speed Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units 3.1 3.1 3.5 3.5 4.0 4.0 4.7 4.7 6.8 6.8 ns ns Input Module Predicted Routing Delays1 tIRD1 tIRD2 tIRD3 tIRD4 tIRD8 FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay 0.9 1.4 2.1 3.1 6.6 1.1 1.7 2.5 3.6 7.7 1.2 1.9 2.8 4.1 8.7 1.4 2.2 3.3 4.8 10.2 2.0 3.2 4.8 7.0 14.8 ns ns ns ns ns Global Clock Network tCKH tCKL tPWH tPWL tCKSW tP fMAX Input Low to High Input High to Low Minimum Pulse Width High Minimum Pulse Width Low Maximum Skew Minimum Period Maximum Frequency FO = 16 FO = 128 FO = 16 FO = 128 FO = 16 FO = 128 FO = 16 FO = 128 FO = 16 FO = 128 FO = 16 FO = 128 FO = 16 FO = 128 13.2 14.2 75 70 6.5 6.8 6.5 6.8 1.2 1.8 15.4 16.7 65 60 4.9 5.6 6.4 7.0 7.5 8.0 7.5 8.0 1.3 2.1 17.6 18.9 57 53 5.6 6.4 7.4 8.1 8.5 9.0 8.5 9.0 1.5 2.4 20.9 22.3 48 45 6.4 7.3 8.4 9.2 10.0 10.5 10.0 10.5 1.8 2.8 18.2 20 55 50 7.5 8.6 9.9 10.8 8.9 9.8 8.9 9.8 1.5 2.4 6.7 7.9 8.8 10.0 ns ns ns ns ns ns MHz Note: 1. These parameters should be used for estimating device performance. Optimization techniques may further reduce delays by 0 to 4 ns. Routing delays are for typical designs across worst-case operating conditions. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is based on actual routing delay measurements performed on the device prior to shipment. 1-298 A C T ™ 1 S eri es FP G As ACT 1 Timing Characteristics ( continued) (Worst-Case Commercial Conditions) Output Module Timing Parameter Description TTL Output Module Timing1 tDLH tDHL tENZH tENZL tENHZ tENLZ dTLH dTHL Data to Pad High Data to Pad Low Enable Pad Z to High Enable Pad Z to Low Enable Pad High to Z Enable Pad Low to Z Delta Low to High Delta High to Low Module Timing1 ‘–3’ Speed ‘–2’ Speed ‘–1’ Speed ‘Std’ Speed 3.3 V Speed Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units 6.7 7.5 6.6 7.9 10.0 9.0 0.06 0.08 7.6 8.6 7.5 9.1 11.6 10.4 0.07 0.09 8.7 9.8 8.6 10.4 13.1 11.8 0.08 0.10 10.3 11.5 10.2 12.2 15.4 13.9 0.09 0.12 15.0 16.7 14.8 17.7 22.4 20.2 ns ns ns ns ns ns 0.13 ns/pF 0.17 ns/pF CMOS Output tDLH tDHL tENZH tENZL tENHZ tENLZ dTLH dTHL Data to Pad High Data to Pad Low Enable Pad Z to High Enable Pad Z to Low Enable Pad High to Z Enable Pad Low to Z Delta Low to High Delta High to Low 7.9 6.4 6.0 8.3 10.0 9.0 0.10 0.06 9.2 7.2 6.9 9.4 11.6 10.4 0.11 0.07 10.4 8.2 7.9 10.7 13.1 11.8 0.13 0.08 12.2 9.8 9.2 12.7 15.4 13.9 0.15 0.09 17.7 14.2 13.4 18.5 22.4 20.2 ns ns ns ns ns ns 0.22 ns/pF 0.13 ns/pF Notes: 1. Delays based on 35 pF loading. 2. SSO information can be found in the “Simultaneous Switching Output Limits for Actel FPGAs” application note on page 4-125. 1-299 Package Pin Assignments 44-Pin PLCC 68-Pin PLCC 1 68 1 44 44-Pin PLCC 68-Pin PLCC Signal 3 10 14 16 21 25 32 33 34 35 36 37 38 39 43 A1010B Function VCC GND VCC VCC GND VCC GND CLK, I/O MODE VCC SDI, I/O DCLK, I/O PRA, I/O PRB, I/O GND A1020B Function VCC GND VCC VCC GND VCC GND CLK, I/O MODE VCC SDI, I/O DCLK, I/O PRA, I/O PRB, I/O GND Signal 4 14 15 21 25 32 38 49 52 54 55 56 57 58 59 66 A1010B, A10V10B Function VCC GND GND VCC VCC GND VCC GND CLK, I/O MODE VCC SDI, I/O DCLK, I/O PRA, I/O PRB, I/O GND A1020B, A10V20B Functions VCC GND GND VCC VCC GND VCC GND CLK, I/O MODE VCC SDI, I/O DCLK, I/O PRA, I/O PRB, I/O GND Notes: 1. NC: Denotes No Connection 2. All unlisted pin numbers are user I/Os. 3. MODE should be terminated to GND through a 10K resistor to enable Actionprobe usage; otherwise it can be terminated directly to GND. 1-300 A C T ™ 1 S eri es FP G As Package Pin Assignments ( continued) 84-Pin PLCC 1 84 A1020B 84-Pin PLCC Signal 4 12 18 19 25 26 33 40 46 60 61 64 66 67 68 72 73 74 75 A1020B, A10V20B Function VCC NC GND GND VCC VCC VCC GND VCC GND GND CLK, I/O MODE VCC VCC SDI, I/O DCLK, I/O PRA, I/O PRB, I/O 82 GND Notes: 1. NC: Denotes No Connection 2. All unlisted pin numbers are user I/Os. 3. MODE should be terminated to GND through a 10K resistor to enable Actionprobe usage; otherwise it can be terminated directly to GND. 1-301 Package Pin Assignments ( continued) 100-Pin PQFP 100-Pin PQFP 100 1 Pin 1 2 3 4 5 6 13 19 27 28 29 30 31 32 33 36 37 43 44 48 49 50 51 52 A1010B Function NC NC NC NC NC PRB, I/O GND VCC NC NC NC NC NC NC NC GND GND VCC VCC NC NC NC NC NC A1020B Function NC NC NC NC NC PRB, I/O GND VCC NC NC NC NC I/O I/O I/O GND GND VCC VCC I/O I/O I/O NC NC Pin 53 54 55 56 63 69 77 78 79 80 81 82 86 87 90 92 93 94 95 96 97 98 99 100 A1010B Function NC NC NC VCC GND VCC NC NC NC NC NC NC GND GND CLK, I/O MODE VCC VCC NC NC NC SDI, I/O DCLK, I/O PRA, I/O A1020B Function NC NC NC VCC GND VCC NC NC NC I/O I/O I/O GND GND CLK, I/O MODE VCC VCC I/O I/O I/O SDI, I/O DCLK, I/O PRA, I/O Notes: 1. NC: Denotes No Connection 2. All unlisted pin numbers are user I/Os. 3. MODE should be terminated to GND through a 10K resistor to enable Actionprobe usage; otherwise it can be terminated directly to GND. 1-302 A C T ™ 1 S eri es FP G As Package Pin Assignments ( continued) 80-Pin VQFP 1 80 80-Pin VQFP Pin 2 3 4 7 13 17 18 19 20 27 33 41 42 43 A1010B, A10V10B Function NC NC NC GND VCC NC NC NC VCC GND VCC NC NC NC A1020B, A10V20B Function I/O I/O I/O GND VCC I/O I/O I/O VCC GND VCC I/O I/O I/O Pin 47 50 52 53 54 55 56 57 58 59 60 61 68 74 A1010B, A10V10B Function GND CLK, I/O MODE VCC NC NC NC SDI, I/O DCLK, I/O PRA, I/O NC PRB, I/O GND VCC A1020B, A10V20B Function GND CLK, I/O MODE VCC I/O I/O I/O SDI, I/O DCLK, I/O PRA, I/O NC PRB, I/O GND VCC Notes: 1. NC: Denotes No Connection 2. All unlisted pin numbers are user I/Os. 3. MODE should be terminated to GND through a 10K resistor to enable Actionprobe usage; otherwise it can be terminated directly to GND. 1-303 Package Pin Assignments ( continued) 84-Pin CPGA 1 A B C D E F G H J K L 2 3 4 5 6 7 8 9 10 11 84-Pin CPGA Orientation Pin (C3) Pin A11 B1 B2 B5 B7 B10 B11 C1 C2 C10 C11 D10 D11 E2 E3 E9 A1010B Function PRA, I/O NC NC VCC GND PRB, I/O SDI, I/O NC NC DCLK, I/O NC NC NC GND GND VCC A1020B Function PRA, I/O I/O NC VCC GND PRB, I/O SDI,I/O I/O I/O DCLK, I/O I/O I/O I/O GND GND VCC Pin E10 E11 F1 F9 F10 G2 G10 J2 J10 K1 K2 K5 K7 K10 K11 L1 A1010B Function VCC MODE VCC CLK, I/O GND VCC GND NC NC NC VCC GND VCC NC NC NC A1020B Function VCC MODE VCC CLK, I/O GND VCC GND I/O I/O I/O VCC GND VCC I/O I/O I/O Notes: 1. NC: Denotes No Connection 2. All unlisted pin numbers are user I/Os. 3. MODE should be terminated to GND through a 10K resistor to enable Actionprobe usage; otherwise it can be terminated directly to GND. 1-304 A C T ™ 1 S eri es FP G As Package Pin Assignments ( continued) 84-Pin CQFP 84 Pin #1 Index 1 84-Pin CQFP Pin 1 7 8 14 15 22 29 35 49 50 A1020B Function NC GND GND VCC VCC VCC GND VCC GND GND Pin 53 55 56 57 61 62 63 64 71 77 A1020B Function CLK, I/O MODE VCC VCC SDI, I/O DCLK, I/O PRA, I/O PRB, I/O GND VCC Notes: 1. NC: Denotes No Connection 2. All unlisted pin numbers are user I/Os. 3. MODE should be terminated to GND through a 10K resistor to enable Actionprobe usage; otherwise it can be terminated directly to GND. 1-305 1-306