A1240A-2PL176C

v4.0.1 ACT™ 2 Family FPGAs Fe a t ur es • Up to 8000 Gate Array Gates (20,000 PLD equivalent gates) • Replaces up to 200 TTL Packages • Replaces up to eighty 20-Pin PAL ® Packages • Datapath Performance at 105 MHz • 16-Bit Accumulator Performance to 39 MHz • Two In-Circuit Diagnostic Probe Pins Support Speed Analysis to 50 MHz • Two High-Speed, Low-Skew Clock Networks • I/O Drive to 10 mA • Nonvolatile, User Programmable • Logic Fully Tested Prior to Shipment • 1.0-micron CMOS Technology • Design Library with over 500 Macro Functions • Single-Module Sequential Functions • Wide-Input Combinatorial Functions • Up to 1232 Programmable Logic Modules • Up to 998 Flip-Flops Pr od uc t F am i l y P r o f i l e Device Capacity Gate Array Equivalent Gates PLD Equivalent Gates TTL Equivalent Packages 20-Pin PAL Equivalent Packages Logic Modules S-Modules C-Modules Flip-Flops (maximum) Routing Resources Horizontal Tracks/Channel Vertical Tracks/Channel PLICE Antifuse Elements User I/Os (maximum) Packages 1 A1225A 2,500 6,250 63 25 451 231 220 382 36 15 250,000 83 100 CPGA 100 PQFP 100 VQFP 84 PLCC A1240A 4,000 10,000 100 40 684 348 336 568 36 15 400,000 104 132 CPGA 144 PQFP 176 TQFP 84 PLCC A1280A 8,000 20,000 200 80 1,232 624 608 998 36 15 750,000 140 176 CPGA 160 PQFP 176 TQFP 84 PLCC 172 CQFP 85 MHz 67 MHz 36 MHz Performance2 16-Bit Prescaled Counters 16-Bit Loadable Counters 16-Bit Accumulators 105 MHz 70 MHz 39 MHz 100 MHz 69 MHz 38 MHz Notes: 1. See the “Product Plan” on page 3 for package availability. 2. Performance is based on ‘–2’ speed devices at commercial worst-case operating conditions using PREP Benchmarks, Suite #1, Version 1.2, dated 3-28-93, any analysis is not endorsed by PREP. D e ce m b e r 2 0 0 0 1 © 2000 Actel Corporation A C T ™ 2 F a m il y F P GA s D es cr i p t i o n The ACT™ 2 family represents Actel’s second generation of field programmable gate arrays (FPGAs). The ACT 2 family presents a two-module architecture, consisting of C-modules and S-modules. These modules are optimized for both combinatorial and sequential designs. Based on Actel’s patented channeled array architecture, the ACT 2 family provides significant enhancements to gate density and performance while maintaining downward compatibility with the ACT 1 design environment and upward compatibility with the ACT 3 design environment. The devices are implemented in silicon gate, 1.0-µm, two-level metal CMOS, and employ Actel’s PLICE® antifuse O r d e r i n g I nf o r m a t i o n technology. This revolutionary architecture offers gate array design flexibility, high performance, and fast time-to-production with user programming. The ACT 2 family is supported by the Designer and Designer Advantage Systems, which offers automatic pin assignment, validation of electrical and design rules, automatic placement and routing, timing analysis, user programming, and diagnostic probe capabilities. The systems are supported on the following platforms: 386/486™ PC, Sun™, and HP™ workstations. The systems provide CAE interfaces to the following design environments: Cadence, Viewlogic®, Mentor Graphics®, and OrCAD™. A1280 A – 1 PG 176 C Application (Temperature Range) C = Commercial (0 to +70°C) I = Industrial (–40 to +85°C) M = Military (–55 to +125°C) B = MIL-STD-883 Package Lead Count Package Type PL = Plastic J-Leaded Chip Carrier PQ = Plastic Quad Flat Pack CQ = Ceramic Quad Flat Pack PG = Ceramic Pin Grid Array TQ = Thin (1.4 mm) Quad Flat Pack VQ = Very Thin (1.0 mm) Quad Flat Pack Speed Grade Blank = Standard Speed –1 = Approximately 15% faster than Standard –2 = Approximately 25% faster than Standard Die Revision A = 1.0-µm CMOS process Part Number A1225 = 2500 Gates A1240 = 4000 Gates A1280 = 8000 Gates 2 v4.0 A C T ™ 2 F a m il y F PG A s Pr od uc t P l a n Speed Grade* Std A1225A Device 100-pin Ceramic Pin Grid Array (PG) ✔ ✔ ✔ ✔ ✔ ✔ ✔ ✔ ✔ ✔ ✔ ✔ ✔ — ✔ — ✔ — — — — — — — — 100-pin Plastic Quad Flat Pack (PQ) ✔ 100-pin Very Thin (1.0 mm) Quad Flat Pack (VQ) ✔ 84-pin Plastic Leaded Chip Carrier (PL) A1240A Device 132-pin Ceramic Pin Grid Array (PG) 176-pin Thin (1.4 mm) Quad Flat Pack (TQ) 144-pin Plastic Quad Flat Pack (PQ) 84-pin Plastic Leaded Chip Carrier (PL) A1280A Device 176-pin Ceramic Pin Grid Array (PG) 176-pin Thin (1.4 mm) Quad Flat Pack (TQ) 160-pin Plastic Quad Flat Pack (PQ) 172-pin Ceramic Quad Flat Pack (CQ) ✔ ✔ ✔ ✔ ✔ ✔ ✔ ✔ ✔ ✔ ✔ ✔ ✔ ✔ ✔ ✔ — — ✔ — ✔ — — ✔ ✔ — — ✔ ✔ ✔ ✔ ✔ ✔ ✔ ✔ ✔ ✔ ✔ ✔ ✔ ✔ ✔ ✔ ✔ — — ✔ ✔ ✔ — — — ✔ — — — ✔ –1 –2 Application C I M B Contact your Actel sales representatives for product availability. Applications: C = Commercial Availability: ✔ = Available *Speed Grade: I = Industrial P = Planned M = Military — = Not Planned B = MIL-STD-883 –1 = Approx. 15% faster than Standard –2 = Approx. 25% faster than Standard D ev i ce R es ou r c es User I/Os Device Series A1225A A1240A A1280A CPGA PQFP PLCC CQFP TQFP VQFP Logic Modules Gates 176-pin 132-pin 100-pin 160-pin 144-pin 100-pin 84-pin 172-pin 176-pin 100-pin 451 684 1232 2500 4000 8000 — — 140 — 104 — 83 — — — — 125 — 104 — 83 — — 72 72 72 — — 140 — 104 140 83 — — . v4.0 3 A C T ™ 2 F a m il y F P GA s O pe r a t i ng C on d i t i on s Abs ol ut e M axim u m Ra ti ngs 1 R ecom m en ded Oper at ing C ondi ti ons Free air temperature range Symbol VCC VI VO IIO TSTG Parameter DC Supply Voltage Input Voltage Output Voltage I/O Source/Sink Current2 Storage Temperature Limits –0.5 to +7.0 –0.5 to VCC +0.5 –0.5 to VCC +0.5 ±20 –65 to +150 Units V V V mA °C Parameter Temperature Range1 Power Supply Tolerance Commercia Industria l l 0 to +70 –40 to +85 ±10 Military –55 to +125 ±10 Units °C ±5 %VCC Notes: 1. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. Device should not be operated outside the Recommended Operating Conditions. 2. Device inputs are normally high impedance and draw extremely low current. However, when input voltage is greater than VCC + 0.5 V or less than GND – 0.5 V, the internal protection diode will be forward biased and can draw excessive current. E lect r ica l Sp eci ficat i ons Note: 1. Ambient temperature (TA) is used for commercial and industrial; case temperature (TC) is used for military. Commercial Symbol VOH1 Parameter (IOH = –10 mA) 2 (IOH = –6 mA) (IOH = –4 mA) VOL1 VIL VIH Input Transition Time tR, tF CIO I/O Capacitance Leakage Current 5 2, 3 4 2 Industrial Min. Max. Military Min. Max. Units V V Min. 2.4 3.84 Max. 3.7 2 3.7 V V (IOL = 10 mA) (IOL = 6 mA) 0.5 0.33 –0.3 2.0 0.8 VCC + 0.3 500 10 2 –10 10 –10 –0.3 2.0 0.40 0.8 VCC + 0.3 500 10 10 10 –10 –0.3 2.0 0.40 0.8 VCC + 0.3 500 10 20 10 V V V ns pF mA µA Standby Current, ICC (typical = 1 mA) Notes: 1. Only one output tested at a time. VCC = min. 2. Not tested, for information only. 3. Includes worst-case 176 CPGA package capacitance. VOUT = 0 V, f = 1 MHz. 4. All outputs unloaded. All inputs = VCC or GND, typical ICC = 1 mA. ICC limit includes IPP and ISV during normal operation. 5. VOUT , VIN = VCC or GND. 4 v4.0 A C T ™ 2 F a m il y F PG A s Pa c ka ge T he r m a l C ha r a ct e r i s t i c s Maximum junction temperature is 150°C. A sample calculation of the absolute maximum power dissipation allowed for a PQFP 160-pin package at commercial temperature is as follows: The device junction to case thermal characteristic is θjc, and the junction to ambient air characteristic is θja. The thermal characteristics for θja are shown with two different air flow rates. Max. junction temp. (°C) – Max. commercial temp. ---------------------------------------------------------------------------------------------------------------------------- = 150°C – 70°C = 2.4 W --------------------------------θ ja (°C/W) 33°C/W θja Still Air 35 30 23 25 48 40 38 37 43 32 θja 300 ft/min 17 15 12 15 40 32 30 28 35 25 Package Type Ceramic Pin Grid Array Pin Count 100 132 176 172 100 144 160 84 100 176 3 θjc 5 5 8 8 13 15 15 12 12 15 Units °C/W °C/W °C/W °C/W °C/W °C/W °C/W °C/W °C/W °C/W Ceramic Quad Flat Pack Plastic Quad Flat Pack 1 Plastic Leaded Chip Carrier2 Very Thin Quad Flat Pack Thin Quad Flat Pack 4 Notes:(Maximum Power in Still Air) 1. Maximum Power Dissipation for PQFP packages are 1.9 Watts (100-pin), 2.3 Watts (144-pin), and 2.4 Watts (160-pin). 2. Maximum Power Dissipation for PLCC packages is 2.7 Watts. 3. Maximum Power Dissipation for VQFP packages is 2.3 Watts. 4. Maximum Power Dissipation for TQFP packages is 3.1 Watts. Po w e r D i ss i pa t i o n P = [ICCstandby + ICCactive] * VCC + IOL * VOL * N + IOH * (VCC – VOH) * M Where: ICC standby is the current flowing when no inputs or outputs are changing. ICC active is the current flowing due to CMOS switching. IOL, IOH are TTL sink/source currents. VOL, VOH are TTL level output voltages. N equals the number of outputs driving TTL loads to VOL. M equals the number of outputs driving TTL loads to VOH. An accurate determination of N and M is problematical because their values depend on the family type, design details, and on the system I/O. The power can be divided into two components: static and active. S tat i c P ow er Co m ponen t greater reduction in board-level power dissipation can be achieved. The power due to standby current is typically a small component of the overall power. Standby power is calculated below for commercial, worst case conditions. ICC 2 mA VCC 5.25V Power 10.5 mW The static power dissipated by TTL loads depends on the number of outputs driving high or low and the DC load current. Again, this value is typically small. For instance, a 32-bit bus sinking 4 mA at 0.33 V will generate 42 mW with all outputs driving low, and 140 mW with all outputs driving high. The actual dissipation will average somewhere between as I/Os switch states with time. Ac ti ve P ower Com po nent Actel FPGAs have small static power components that result in lower power dissipation than PALs or PLDs. By integrating multiple PALs/PLDs into one FPGA, an even Power dissipation in CMOS devices is usually dominated by the active (dynamic) power dissipation. This component is frequency dependent, a function of the logic and the external I/O. Active power dissipation results from charging internal chip capacitances of the interconnect, unprogrammed antifuses, module inputs, and module outputs, plus external capacitance due to PC board traces v4.0 5 A C T ™ 2 F a m il y F P GA s and load device inputs. An additional component of the active power dissipation is the totem-pole current in CMOS transistor pairs. The net effect can be associated with an equivalent capacitance that can be combined with frequency and voltage to represent active power dissipation. E quiv al ent C apac it ance r2 CEQM CEQI CEQO = Fixed capacitance due to second routed array clock = Equivalent capacitance of logic modules in pF = Equivalent capacitance of input buffers in pF = Equivalent capacitance of output buffers in pF The power dissipated by a CMOS circuit can be expressed by the Equation 1. Power (µW) = CEQ * VCC2 * F Where: CEQ is the equivalent capacitance expressed in pF. VCC is the power supply in volts. F is the switching frequency in MHz. Equivalent capacitance is calculated by measuring ICC active at a specified frequency and voltage for each circuit component of interest. Measurements have been made over a range of frequencies at a fixed value of VCC. Equivalent capacitance is frequency independent so that the results may be used over a wide range of operating conditions. Equivalent capacitance values are shown below. C E Q V a lues f or Ac tel F PG A s CEQCR = Equivalent capacitance of routed array clock in pF CL fm fn fp fq1 fq2 = Output lead capacitance in pF = Average logic module switching rate in MHz = Average input buffer switching rate in MHz = Average output buffer switching rate in MHz = Average first routed array clock rate in MHz = Average second routed array clock rate in MHz (1) F i xed Ca paci ta nce Val ues fo r Act el FP GA s (pF ) Device Type A1225A A1240A A1280A r1 routed_Clk1 106 134 168 r2 routed_Clk2 106.0 134.2 167.8 Modules (CEQM) Input Buffers (CEQI) Output Buffers (CEQO) Routed Array Clock Buffer Loads (CEQCR) 5.8 12.9 23.8 3.9 D et erm i nin g A ve ra ge S wi t chi ng F re quenc y To calculate the active power dissipated from the complete design, the switching frequency of each part of the logic must be known. Equation 2 shows a piece-wise linear summation over all components. Power = VCC2 * [(m * CEQM* fm)modules +(n * CEQI* fn)inputs + (p * (CEQO+ CL) * fp)outputs + 0.5 * (q1 * CEQCR * fq1)routed_Clk1 + (r1 * fq1)routed_Clk1 + 0.5 * (q2 * CEQCR * fq2)routed_Clk2 (2) + (r2 * fq2)routed_Clk2] Where: m n p q1 q2 r1 = Number of logic modules switching at fm = Number of input buffers switching at fn = Number of output buffers switching at fp = Number of clock loads on the first routed array clock = Number of clock loads on the second routed array clock = Fixed capacitance due to first routed array clock To determine the switching frequency for a design, you must have a detailed understanding of the data input values to the circuit. The following guidelines are meant to represent worst-case scenarios so that they can be generally used to predict the upper limits of power dissipation. These guidelines are as follows: Logic Modules (m) Inputs switching (n) Outputs switching (p) First routed array clock loads (q1) 80% of modules # inputs/4 # outputs/4 40%of sequential modules 40%of sequential modules 35 pF F/10 F/5 F/10 F Second routed array clock loads (q2) Load capacitance (CL) Average logic module switching rate (fm) Average input switching rate (fn) Average output switching rate (fp) Average first routed array clock rate (fq1) Average second routed array clock rate F/2 (fq2) 6 v4.0 A C T ™ 2 F a m il y F PG A s A CT 2 Ti m i n g M od el * Input Delays Internal Delays Combinatorial I/O Module Logic Module tINYL = 2.6 ns t IRD2 = 4.8 ns† Predicted Routing Delays Output Delays I/O Module tDLH = 8.0 ns D Q tPD = 3.8 ns tRD1 = 1.4 ns tRD2 = 1.7 ns tRD4 = 3.1 ns tRD8 = 4.7 ns G tINH = 2.0 ns tINSU = 4.0 ns tINGL = 4.7 ns Sequential Logic Module Combinatorial Logic included in tSUD ARRAY CLOCKS tSUD = 0.4 ns tHD = 0.0 ns I/O Module tDLH = 8.0 ns D Q tRD1 = 1.4 ns D Q tENHZ = 7.1 ns G tOUTH = 0.0 ns tOUTSU = 0.4 ns tGLH = 9.0 ns tCO = 3.8 ns tCKH = 11.8 ns FMAX = 100 MHz FO = 256 *Values shown for A1240A-2 at worst-case commercial conditions. † Input Module Predicted Routing Delay v4.0 7 A C T ™ 2 F a m il y F P GA s P ar am e t e r M ea s ur e m e nt O ut put Buf f e r De lay s E D TRIBUFF PAD To AC test loads (shown below) VCC In PAD VOL tDLH 50% 50% VOH 1.5 V tDHL GND 1.5 V E PAD VCC 50% VCC 50% 1.5 V VOL tENZL tENLZ GND 10% E PAD GND VCC 50% 50% VOH 1.5 V tENZH tENHZ GND 90% A C T es t Lo ads Load 1 (Used to measure propagation delay) Load 2 (Used to measure rising/falling edges) VCC GND To the output under test 50 pF To the output under test R to VCC for tPLZ/tPZL R to GND for tPHZ/tPZH R = 1 kΩ 50 pF Inp ut Bu ffer D ela ys Modu le Del ay s PAD INBUF Y VCC S, A or B S A B Y 3V PAD Y GND tINYH 1.5 V 1.5 V VCC 50% tINYL 0V 50% Y GND Y 50% 50% VCC 50% tPLH 50% tPHL GND 50% tPHL VCC GND tPLH 50% 8 v4.0 A C T ™ 2 F a m il y F PG A s S eq u en t i a l M od ul e T i m i ng C ha r a ct er i st i c s Fl ip- Fl ops and La tch es D E CLK PRE CLR Y (Positive edge triggered) tHD D1 tSUD G, CLK tSUENA tHENA E tCO Q tRS PRE, CLR tWASYN tWCLKI tWCLKA tA Note: D represents all data functions involving A, B, and S for multiplexed flip-flops. v4.0 9 A C T ™ 2 F a m il y F P GA s Se q ue nt i al T i m i n g C h ar ac t er i st i c s ( continued) Inpu t Buffe r Lat che s DATA PAD G IBDL CLK PAD CLKBUF DATA tINH G tINSU tHEXT CLK tSUEXT Out put B uffer L at ches D OBDLHS G PAD D tOUTSU G tOUTH 10 v4.0 A C T ™ 2 F a m il y F PG A s Ti m i n g D er a t i n g F a ct o r ( T e m p e r a t u r e a n d V o l t a g e ) Industrial Min. (Commercial Minimum/Maximum Specification) x 0.69 Max. 1.11 Min. 0.67 Military Max. 1.23 Ti m i ng D er a t i n g F a ct o r f o r D e si g ns at Ty pi c a l Te m p er a t u r e ( T J = 2 5 ° C ) an d V ol t a g e ( 5 . 0 V) (Commercial Maximum Specification) x 0.85 Te m p er a t u r e an d Vo l t a ge D er at i n g Fa ct or s ( n or m a l i z ed t o W or s t - C a se Co m m e r c i al , T J = 4 . 7 5 V , 7 0 ° C ) –55 4.50 4.75 5.00 5.25 5.50 0.75 0.71 0.69 0.68 0.67 –40 0.79 0.75 0.72 0.69 0.69 0 0.86 0.82 0.80 0.77 0.76 25 0.92 0.87 0.85 0.82 0.81 70 1.06 1.00 0.97 0.95 0.93 85 1.11 1.05 1.02 0.98 0.97 125 1.23 1.16 1.13 1.09 1.08 Junction Temperature and Voltage Derating Curves (normalized to Worst-Case Commercial, T J = 4 .75V, 70 ° C) 1.3 1.2 1.1 1.0 0.9 0.8 0.7 0.6 4.50 4.75 5.00 Voltage (V) Note: This derating factor applies to all routing and propagation delays. Derating Factor 125˚C 85˚C 70˚C 25˚C 0˚C –40˚C –55˚C 5.25 5.50 v4.0 11 A C T ™ 2 F a m il y F P GA s A 12 25 A Ti m i ng Ch a r ac t e r i s t i cs (Worst-Case Commercial Conditions, V CC = 4 .75 V, T J = 7 0 ° C) Logic Module Propagation Delays1 Parameter Description Single Module Sequential Clk to Q Latch G to Q Flip-Flop (Latch) Reset to Q 2 ‘–2’ Speed Min. Max. 3.8 3.8 3.8 3.8 ‘–1’ Speed Min. Max. 4.3 4.3 4.3 4.3 ‘Std’ Speed Min. Max. 5.0 5.0 5.0 5.0 Units ns ns ns ns tPD1 tCO tGO tRS tRD1 tRD2 tRD3 tRD4 tRD8 tSUD tHD tSUENA tHENA tWCLKA tWASYN tA tINH tINSU tOUTH tOUTSU fMAX Predicted Routing Delays FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay 3,4 1.1 1.7 2.3 2.8 4.4 1.2 1.9 2.6 3.1 4.9 1.4 2.2 3.0 3.7 5.8 ns ns ns ns ns Sequential Timing Characteristics Flip-Flop (Latch) Data Input Setup Flip-Flop (Latch) Data Input Hold Flip-Flop (Latch) Enable Setup Flip-Flop (Latch) Enable Hold Flip-Flop (Latch) Clock Active Pulse Width Flip-Flop (Latch) Asynchronous Pulse Width Flip-Flop Clock Input Period Input Buffer Latch Hold Input Buffer Latch Setup Output Buffer Latch Hold Output Buffer Latch Setup Flip-Flop (Latch) Clock Frequency 0.4 0.0 0.8 0.0 4.5 4.5 9.4 0.0 0.4 0.0 0.4 105.0 0.4 0.0 0.9 0.0 5.0 5.0 11.0 0.0 0.4 0.0 0.4 90.0 0.5 0.0 1.0 0.0 6.0 6.0 13.0 0.0 0.5 0.0 0.5 75.0 ns ns ns ns ns ns ns ns ns ns ns MHz Notes: 1. For dual-module macros, use tPD1 + tRD1 + tPDn , tCO + tRD1 + tPDn or tPD1 + tRD1 + tSUD, whichever is appropriate. 2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is based on actual routing delay measurements performed on the device prior to shipment. 3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be obtained from the DirectTime Analyzer utility. 4. Setup and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input. External setup/hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to the G input subtracts (adds) to the internal setup (hold) time. 12 v4.0 A C T ™ 2 F a m il y F PG A s A 12 25 A Ti m i ng Ch a r ac t e r i s t i cs ( continued) ( W or st -C as e C om m er cia l Cond it ion s) Input Module Propagation Delays Parameter tINYH tINYL tINGH tINGL tIRD1 tIRD2 tIRD3 tIRD4 tIRD8 Description Pad to Y High Pad to Y Low G to Y High G to Y Low 1 ‘–2’ Speed Min. Max. 2.9 2.6 5.0 4.7 ‘–1’ Speed Min. Max. 3.3 3.0 5.7 5.4 ‘Std’ Speed Min. Max. 3.8 3.5 6.6 6.3 Unit s ns ns ns ns Input Module Predicted Routing Delays FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay 4.1 4.6 5.3 5.7 7.4 4.6 5.2 6.0 6.4 8.3 5.4 6.1 7.1 7.6 9.8 ns ns ns ns ns Global Clock Network tCKH tCKL tPWH tPWL tCKSW tSUEXT tHEXT tP fMAX Input Low to High Input High to Low Minimum Pulse Width High Minimum Pulse Width Low Maximum Skew Input Latch External Setup Input Latch External Hold Minimum Period Maximum Frequency FO = 32 FO = 256 FO = 32 FO = 256 FO = 32 FO = 256 FO = 32 FO = 256 FO = 32 FO = 256 FO = 32 FO = 256 FO = 32 FO = 256 FO = 32 FO = 256 FO = 32 FO = 256 0.0 0.0 7.0 11.2 7.7 8.1 130.0 125.0 3.4 3.8 3.4 3.8 0.7 3.5 0.0 0.0 7.0 11.2 8.3 8.8 120.0 115.0 10.2 11.8 10.2 12.0 4.1 4.5 4.1 4.5 0.7 3.5 0.0 0.0 7.0 11.2 9.1 10.0 110.0 100.0 11.0 13.0 11.0 13.2 4.5 5.0 4.5 5.0 0.7 3.5 12.8 15.7 12.8 15.9 ns ns ns ns ns ns ns ns MHz Note: 1. These parameters should be used for estimating device performance. Optimization techniques may further reduce delays by 0 to 4 ns. Routing delays are for typical designs across worst-case operating conditions. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is based on actual routing delay measurements performed on the device prior to shipment. v4.0 13 A C T ™ 2 F a m il y F P GA s A 12 25 A Ti m i ng Ch a r ac t e r i s t i cs ( continued) ( W or st -C as e C om m er cia l Cond it ion s) Output Module Timing Parameter Description ‘–2’ Speed Min. Max. ‘–1’ Speed Min. Max. ‘Std’ Speed Min. Max. Units TTL Output Module Timing1 tDLH tDHL tENZH tENZL tENHZ tENLZ tGLH tGHL dTLH dTHL tDLH tDHL tENZH tENZL tENHZ tENLZ tGLH tGHL dTLH dTHL Data to Pad High Data to Pad Low Enable Pad Z to High Enable Pad Z to Low Enable Pad High to Z Enable Pad Low to Z G to Pad High G to Pad Low Delta Low to High Delta High to Low 1 8.0 10.1 8.9 11.6 7.1 8.3 8.9 11.2 0.07 0.12 9.0 11.4 10.0 13.2 8.0 9.5 10.2 12.7 0.08 0.13 10.6 13.4 11.8 15.5 9.4 11.1 11.9 14.9 0.09 0.16 ns ns ns ns ns ns ns ns ns/pF ns/pF CMOS Output Module Timing Data to Pad High Data to Pad Low Enable Pad Z to High Enable Pad Z to Low Enable Pad High to Z Enable Pad Low to Z G to Pad High G to Pad Low Delta Low to High Delta High to Low 10.1 8.4 8.9 11.6 7.1 8.3 8.9 11.2 0.12 0.09 11.5 9.6 10.0 13.2 8.0 9.5 10.2 12.7 0.13 0.10 13.5 11.2 11.8 15.5 9.4 11.1 11.9 14.9 0.16 0.12 ns ns ns ns ns ns ns ns ns/pF ns/pF Note: 1. Delays based on 50 pF loading. 2. SSO information can be found at http://www.actel.com/support/appnotes/appnotes_design.html#board. 14 v4.0 A C T ™ 2 F a m il y F PG A s A 12 40 A Ti m i ng Ch a r ac t e r i s t i cs (Worst-Case Commercial Conditions, V CC = 4 .75 V, T J = 7 0 ° C) Logic Module Propagation Delays1 Parameter tPD1 tCO tGO tRS tRD1 tRD2 tRD3 tRD4 tRD8 Description Single Module Sequential Clk to Q Latch G to Q Flip-Flop (Latch) Reset to Q 2 ‘–2’ Speed Min. Max. 3.8 3.8 3.8 3.8 ‘–1’ Speed Min. Max. 4.3 4.3 4.3 4.3 ‘Std’ Speed Min. Max. 5.0 5.0 5.0 5.0 Units ns ns ns ns Predicted Routing Delays FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay 3, 4 1.4 1.7 2.3 3.1 4.7 1.5 2.0 2.6 3.5 5.4 1.8 2.3 3.0 4.1 6.3 ns ns ns ns ns Sequential Timing Characteristics tSUD tHD tSUENA tHENA tWCLKA tWASYN tA tINH tINSU tOUTH tOUTSU fMAX Flip-Flop (Latch) Data Input Setup Flip-Flop (Latch) Data Input Hold Flip-Flop (Latch) Enable Setup Flip-Flop (Latch) Enable Hold Flip-Flop (Latch) Clock Active Pulse Width Flip-Flop (Latch) Asynchronous Pulse Width Flip-Flop Clock Input Period Input Buffer Latch Hold Input Buffer Latch Setup Output Buffer Latch Hold Output Buffer Latch Setup Flip-Flop (Latch) Clock Frequency 0.4 0.0 0.8 0.0 4.5 4.5 9.8 0.0 0.4 0.0 0.4 100.0 0.4 0.0 0.9 0.0 6.0 6.0 12.0 0.0 0.4 0.0 0.4 80.0 0.5 0.0 1.0 0.0 6.5 6.5 15.0 0.0 0.5 0.0 0.5 66.0 ns ns ns ns ns ns ns ns ns ns ns MHz Notes: 1. For dual-module macros, use tPD1 + tRD1 + tPDn , tCO + tRD1 + tPDn or tPD1 + tRD1 + tSUD, whichever is appropriate. 2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is based on actual routing delay measurements performed on the device prior to shipment. 3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be obtained from the DirectTime Analyzer utility. 4. Setup and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input. External setup/hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to the G input subtracts (adds) to the internal setup (hold) time. v4.0 15 A C T ™ 2 F a m il y F P GA s A 12 40 A Ti m i ng Ch a r ac t e r i s t i cs ( continued) ( W or st -C as e C om m er cia l Cond it ion s) Input Module Propagation Delays Parameter tINYH tINYL tINGH tINGL tIRD1 tIRD2 tIRD3 tIRD4 tIRD8 Description Pad to Y High Pad to Y Low G to Y High G to Y Low 1 ‘–2’ Speed Min. Max. 2.9 2.6 5.0 4.7 ‘–1’ Speed Min. Max. 3.3 3.0 5.7 5.4 ‘Std’ Speed Min. Max. 3.8 3.5 6.6 6.3 Units ns ns ns ns Input Module Predicted Routing Delays FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay 4.2 4.8 5.4 5.9 7.9 4.8 5.4 6.1 6.7 8.9 5.6 6.4 7.2 7.9 10.5 ns ns ns ns ns Global Clock Network tCKH tCKL tPWH tPWL tCKSW tSUEXT tHEXT tP fMAX Input Low to High Input High to Low Minimum Pulse Width High Minimum Pulse Width Low Maximum Skew Input Latch External Setup Input Latch External Hold Minimum Period Maximum Frequency FO = 32 FO = 256 FO = 32 FO = 256 FO = 32 FO = 256 FO = 32 FO = 256 FO = 32 FO = 256 FO = 32 FO = 256 FO = 32 FO = 256 FO = 32 FO = 256 FO = 32 FO = 256 0.0 0.0 7.0 11.2 8.1 8.8 125.0 115.0 3.8 4.1 3.8 4.1 0.5 2.5 0.0 0.0 7.0 11.2 9.1 10.0 110.0 100.0 10.2 11.8 10.2 12.0 4.5 5.0 4.5 5.0 0.5 2.5 0.0 0.0 7.0 11.2 11.1 11.7 90.0 85.0 11.0 13.0 11.0 13.2 5.5 5.8 5.5 5.8 0.5 2.5 12.8 15.7 12.8 15.9 ns ns ns ns ns ns ns ns MHz Note: These parameters should be used for estimating device performance. Optimization techniques may further reduce delays by 0 to 4 ns. Routing delays are for typical designs across worst-case operating conditions. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is based on actual routing delay measurements performed on the device prior to shipment. 16 v4.0 A C T ™ 2 F a m il y F PG A s A 12 4 0A T i m i ng C ha r a ct er i s t i c s ( continued) ( W or st -C as e C om m er cia l Cond it ion s) Output Module Timing Parameter Description ‘–2’ Speed Min. Max. ‘–1’ Speed Min. Max. ‘Std’ Speed Min. Max. Units TTL Output Module Timing1 tDLH tDHL tENZH tENZL tENHZ tENLZ tGLH tGHL dTLH dTHL tDLH tDHL tENZH tENZL tENHZ tENLZ tGLH tGHL dTLH dTHL Data to Pad High Data to Pad Low Enable Pad Z to High Enable Pad Z to Low Enable Pad High to Z Enable Pad Low to Z G to Pad High G to Pad Low Delta Low to High Delta High to Low 1 8.0 10.1 8.9 11.7 7.1 8.4 9.0 11.2 0.07 0.12 9.0 11.4 10.0 13.2 8.0 9.5 10.2 12.7 0.08 0.13 10.6 13.4 11.8 15.5 9.4 11.1 11.9 14.9 0.09 0.16 ns ns ns ns ns ns ns ns ns/pF ns/pF CMOS Output Module Timing Data to Pad High Data to Pad Low Enable Pad Z to High Enable Pad Z to Low Enable Pad High to Z Enable Pad Low to Z G to Pad High G to Pad Low Delta Low to High Delta High to Low 10.2 8.4 8.9 11.7 7.1 8.4 9.0 11.2 0.12 0.09 11.5 9.6 10.0 13.2 8.0 9.5 10.2 12.7 0.13 0.10 13.5 11.2 11.8 15.5 9.4 11.1 11.9 14.9 0.16 0.12 ns ns ns ns ns ns ns ns ns/pF ns/pF Note: 1. Delays based on 50 pF loading. 2. SSO information can be found at http://www.actel.com/support/appnotes/appnotes_design.html#board. v4.0 17 A C T ™ 2 F a m il y F P GA s A 12 80 A Ti m i ng Ch a r ac t e r i s t i cs (Worst-Case Commercial Conditions, V CC = 4 .75 V, T J = 7 0 ° C) Logic Module Propagation Delays1 Parameter tPD1 tCO tGO tRS tRD1 tRD2 tRD3 tRD4 tRD8 tSUD tHD tSUENA tHENA tWCLKA tWASYN tA tINH tINSU tOUTH tOUTSU fMAX Description Single Module Sequential Clk to Q Latch G to Q Flip-Flop (Latch) Reset to Q 2 ‘–2’ Speed Min. Max. 3.8 3.8 3.8 3.8 ‘–1’ Speed Min. Max. 4.3 4.3 4.3 4.3 ‘Std’ Speed Min. Max. 5.0 5.0 5.0 5.0 Units ns ns ns ns Predicted Routing Delays FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay 3,4 1.7 2.5 3.0 3.7 6.7 2.0 2.8 3.4 4.2 7.5 2.3 3.3 4.0 4.9 8.8 ns ns ns ns ns Sequential Timing Characteristics Flip-Flop (Latch) Data Input Setup Flip-Flop (Latch) Data Input Hold Flip-Flop (Latch) Enable Setup Flip-Flop (Latch) Enable Hold Flip-Flop (Latch) Clock Active Pulse Width Flip-Flop (Latch) Asynchronous Pulse Width Flip-Flop Clock Input Period Input Buffer Latch Hold Input Buffer Latch Setup Output Buffer Latch Hold Output Buffer Latch Setup Flip-Flop (Latch) Clock Frequency 0.4 0.0 0.8 0.0 5.5 5.5 11.7 0.0 0.4 0.0 0.4 85.0 0.4 0.0 0.9 0.0 6.0 6.0 13.3 0.0 0.4 0.0 0.4 75.0 0.5 0.0 1.0 0.0 7.0 7.0 18.0 0.0 0.5 0.0 0.5 50.0 ns ns ns ns ns ns ns ns ns ns ns MHz Notes: 1. For dual-module macros, use tPD1 + tRD1 + tPDn , tCO + tRD1 + tPDn , or tPD1 + tRD1 + tSUD , whichever is appropriate. 2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is based on actual routing delay measurements performed on the device prior to shipment. 3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be obtained from the DirectTime Analyzer utility. 4. Setup and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input. External setup/hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to the G input subtracts (adds) to the internal setup (hold) time. 18 v4.0 A C T ™ 2 F a m il y F PG A s A 12 8 0A T i m i ng C ha r a ct er i s t i c s ( continued) ( W or st -C as e C om m er cia l Cond it ion s) Input Module Propagation Delays Parameter tINYH tINYL tINGH tINGL tIRD1 tIRD2 tIRD3 tIRD4 tIRD8 Description Pad to Y High Pad to Y Low G to Y High G to Y Low 1 ‘–2’ Speed Min. Max. 2.9 2.7 5.0 4.8 ‘–1’ Speed Min. Max. 3.3 3.0 5.7 5.4 ‘Std’ Speed Min. Max. 3.8 3.5 6.6 6.3 Units ns ns ns ns Input Module Predicted Routing Delays FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay 4.6 5.2 5.6 6.5 9.4 5.1 5.9 6.3 7.3 10.5 6.0 6.9 7.4 8.6 12.4 ns ns ns ns ns Global Clock Network tCKH tCKL tPWH tPWL tCKSW tSUEXT tHEXT tP fMAX Input Low to High Input High to Low Minimum Pulse Width High Minimum Pulse Width Low Maximum Skew Input Latch External Setup Input Latch External Hold Minimum Period Maximum Frequency FO = 32 FO = 384 FO = 32 FO = 384 FO = 32 FO = 384 FO = 32 FO = 384 FO = 32 FO = 384 FO = 32 FO = 384 FO = 32 FO = 384 FO = 32 FO = 384 FO = 32 FO = 384 0.0 0.0 7.0 11.2 9.6 10.6 105.0 95.0 5.0 5.8 5.0 5.8 0.5 2.5 0.0 0.0 7.0 11.2 11.2 12.6 90.0 80.0 10.2 13.1 10.2 13.3 5.5 6.4 5.5 6.4 0.5 2.5 0.0 0.0 7.0 11.2 13.3 15.3 75.0 65.0 11.0 14.6 11.0 14.9 6.6 7.6 6.6 7.6 0.5 2.5 12.8 17.2 12.8 17.5 ns ns ns ns ns ns ns ns MHz Note: These parameters should be used for estimating device performance. Optimization techniques may further reduce delays by 0 to 4 ns. Routing delays are for typical designs across worst-case operating conditions. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is based on actual routing delay measurements performed on the device prior to shipment. v4.0 19 A C T ™ 2 F a m il y F P GA s A 12 80 A Ti m i ng Ch a r ac t e r i s t i cs ( continued) ( W or st -C as e C om m er cia l Cond it ion s) Output Module Timing Parameter Description ‘–2’ Speed Min. Max. ‘–1’ Speed Min. Max. ‘Std’ Speed Min. Max. Units TTL Output Module Timing1 tDLH tDHL tENZH tENZL tENHZ tENLZ tGLH tGHL dTLH dTHL Data to Pad High Data to Pad Low Enable Pad Z to High Enable Pad Z to Low Enable Pad High to Z Enable Pad Low to Z G to Pad High G to Pad Low Delta Low to High Delta High to Low 1 8.1 10.2 9.0 11.8 7.1 8.4 9.0 11.3 0.07 0.12 9.0 11.4 10.0 13.2 8.0 9.5 10.2 12.7 0.08 0.13 10.6 13.4 11.8 15.5 9.4 11.1 11.9 14.9 0.09 0.16 ns ns ns ns ns ns ns ns ns/pF ns/pF CMOS Output Module Timing tDLH tDHL tENZH tENZL tENHZ tENLZ tGLH tGHL dTLH dTHL Data to Pad High Data to Pad Low Enable Pad Z to High Enable Pad Z to Low Enable Pad High to Z Enable Pad Low to Z G to Pad High G to Pad Low Delta Low to High Delta High to Low 10.3 8.5 9.0 11.8 7.1 8.4 9.0 11.3 0.12 0.09 11.5 9.6 10.0 13.2 8.0 9.5 10.2 12.7 0.13 0.10 13.5 11.2 11.8 15.5 9.4 11.1 11.9 14.9 0.16 0.12 ns ns ns ns ns ns ns ns ns/pF ns/pF Note: 1. Delays based on 50 pF loading. 2. SSO information can be found at http://www.actel.com/support/appnotes/appnotes_design.html#board. 20 v4.0 A C T ™ 2 F a m il y F PG A s Pi n D es c r i pt i on CLKA Clock A (Input) P RA Probe A (Output) TTL Clock input for clock distribution networks. The Clock input is buffered prior to clocking the logic modules. This pin can also be used as an I/O. CLKB Clock B (Input) TTL Clock input for clock distribution networks. The Clock input is buffered prior to clocking the logic modules. This pin can also be used as an I/O. DCLK Diagnostic Clock (Input) TTL Clock input for diagnostic probe and device programming. DCLK is active when the MODE pin is HIGH. This pin functions as an I/O when the MODE pin is LOW. GND Ground The Probe A pin is used to output data from any user-defined design node within the device. This independent diagnostic pin is used in conjunction with the Probe B pin to allow real-time diagnostic output of any signal path within the device. The Probe A pin can be used as a user-defined I/O when debugging has been completed. The pin’s probe capabilities can be permanently disabled to protect programmed design confidentiality. PRA is active when the MODE pin is HIGH. This pin functions as an I/O when the MODE pin is LOW. PRB Probe B (Output) LOW supply voltage. I/O Input/Output (Input, Output) The I/O pin functions as an input, output, three-state, or bidirectional buffer. Input and output levels are compatible with standard TTL and CMOS specifications. Unused I/O pins are automatically driven LOW by the ALS software. MODE Mode (Input) The Probe B pin is used to output data from any user-defined design node within the device. This independent diagnostic pin is used in conjunction with the Probe A pin to allow real-time diagnostic output of any signal path within the device. The Probe B pin can be used as a user-defined I/O when debugging has been completed. The pin’s probe capabilities can be permanently disabled to protect programmed design confidentiality. PRB is active when the MODE pin is HIGH. This pin functions as an I/O when the MODE pin is LOW. SDI Serial Data Input (Input) The MODE pin controls the use of multifunction pins (DCLK, PRA, PRB, SDI). When the MODE pin is HIGH, the special functions are active. When the MODE pin is LOW, the pins function as I/Os. To provide Actionprobe capability, the MODE pin should be terminated to GND through a 10K resistor so that the MODE pin can be pulled high when required. NC No Connection Serial data input for diagnostic probe and device programming. SDI is active when the MODE pin is HIGH. This pin functions as an I/O when the MODE pin is LOW. V CC 5.0V Supply Voltage HIGH supply voltage. This pin is not connected to circuitry within the device. v4.0 21 A C T ™ 2 F a m il y F P GA s Pa c ka ge P i n A s si g nm e n t s 84- Pi n PL CC 1 84 84-Pin PLCC Signal 2 4 6 10 12 22 23 28 A1225A Function CLKB, I/O PRB, I/O GND DCLK, I/O MODE VCC VCC GND A1240A Function CLKB, I/O PRB, I/O GND DCLK, I/O MODE VCC VCC GND A1280A Function CLKB, I/O PRB, I/O GND DCLK, I/O MODE VCC VCC GND Notes: 1. All unlisted pin numbers are user I/Os. 2. MODE pin should be terminated to GND through a 10K resistor to enable Actionprobe usage, otherwise it can be terminated directly to GND. 22 v4.0 A C T ™ 2 F a m il y F PG A s Pa c ka ge P i n A s si g nm e n t s 84- Pi n PL CC 1 84 84-Pin PLCC Signal 43 49 63 64 65 70 76 81 83 84 A1225A Function VCC GND GND VCC VCC GND SDI, I/O PRA, I/O CLKA, I/O VCC A1240A Function VCC GND GND VCC VCC GND SDI, I/O PRA, I/O CLKA, I/O VCC A1280A Function VCC GND GND VCC VCC GND SDI, I/O PRA, I/O CLKA, I/O VCC Notes: 1. All unlisted pin numbers are user I/Os. 2. MODE pin should be terminated to GND through a 10K resistor to enable Actionprobe usage, otherwise it can be terminated directly to GND. v4.0 23 A C T ™ 2 F a m il y F P GA s Pa c ka ge P i n A s si g nm e n t s ( cont i nued) 100- P in P Q FP 100-Pin PQFP 100 1 Pin Number 2 4 9 16 17 22 34 40 46 57 64 65 A1225A Function DCLK, I/O MODE GND VCC VCC GND GND VCC GND GND GND VCC Pin Number 66 67 72 79 84 87 89 90 92 94 96 A1225A Function VCC VCC GND SDI, I/O GND PRA, I/O CLKA, I/O VCC CLKB, I/O PRB, I/O GND Notes: 1. All unlisted pin numbers are user I/Os. 2. MODE pin should be terminated to GND through a 10K resistor to enable Actionprobe usage, otherwise it can be terminated directly to GND. 24 v4.0 A C T ™ 2 F a m il y F PG A s Pa c ka ge P i n A s si g nm e n t s ( cont i nued) 144- P in P Q FP 1 144 144-Pin PQFP v4.0 25 A C T ™ 2 F a m il y F P GA s 144- P in P Q FP Pin Number 2 9 10 11 18 19 20 21 28 29 30 44 45 46 54 55 56 64 65 79 80 81 88 A1240A Function MODE GND GND GND VCC VCC VCC VCC GND GND GND GND GND GND VCC VCC VCC GND GND GND GND GND GND Pin Number 89 90 91 92 93 100 101 102 110 116 117 118 123 125 126 127 128 130 132 136 137 138 144 A1240A Function VCC VCC VCC VCC VCC GND GND GND SDI, I/O GND GND GND PRA, I/O CLKA, I/O VCC VCC VCC CLKB, I/O PRB, I/O GND GND GND DCLK, I/O Notes: 1. All unlisted pin numbers are user I/Os. 2. MODE pin should be terminated to GND through a 10K resistor to enable Actionprobe usage, otherwise it can be terminated directly to GND. 26 v4.0 A C T ™ 2 F a m il y F PG A s Pa c ka ge P i n A s si g nm e n t s ( cont i nued) 160- P in P Q FP 160 1 160-Pin PQFP v4.0 27 A C T ™ 2 F a m il y F P GA s 160- P in P Q FP Pin Number 2 6 11 16 18 20 21 23 30 35 38 40 44 49 54 57 58 59 60 61 64 A1280A Function DCLK, I/O VCC GND PRB, I/O CLKB, I/O VCC CLKA, I/O PRA, I/O GND VCC SDI, I/O GND GND GND VCC VCC VCC GND VCC GND GND Pin Number 69 80 86 89 98 99 109 114 120 125 130 135 138 139 140 145 150 155 159 160 A1280A Function GND GND VCC GND VCC GND GND VCC GND GND GND VCC VCC VCC GND GND VCC GND MODE GND Notes: 1. All unlisted pin numbers are user I/Os. 2. MODE pin should be terminated to GND through a 10K resistor to enable Actionprobe usage, otherwise it can be terminated directly to GND. 28 v4.0 A C T ™ 2 F a m il y F PG A s Pa c ka ge P i n A s si g nm e n t s ( cont i nued) 100- P in VQF P 100 1 100-Pin VQFP 100- P in VQF P Pin Number 2 7 14 15 20 32 38 44 55 62 63 64 A1225A Function MODE GND VCC VCC GND GND VCC GND GND GND VCC VCC Pin Number 65 70 77 82 85 87 88 90 92 94 100 A1225A Function VCC GND SDI, I/O GND PRA, I/O CLKA, I/O VCC CLKB, I/O PRB, I/O GND DCLK, I/O Notes: 1. All unlisted pin numbers are user I/Os. 2. MODE pin should be terminated to GND through a 10K resistor to enable Actionprobe usage, otherwise it can be terminated directly to GND. v4.0 29 A C T ™ 2 F a m il y F P GA s Pa c ka ge P i n A s si g nm e n t s ( cont i nued) 176- P in T Q FP 176 1 176-Pin TQFP 30 v4.0 A C T ™ 2 F a m il y F PG A s 176- P in T Q FP Pin Number 1 2 8 10 11 13 18 19 20 22 23 24 25 26 27 28 29 33 37 38 45 52 54 55 57 61 64 66 67 68 74 77 78 80 82 86 89 96 A1240A Function GND MODE NC NC NC NC GND NC NC NC GND NC VCC NC NC VCC NC NC NC NC GND NC NC NC NC NC NC NC GND VCC NC NC NC NC NC NC GND NC A1280A Function GND MODE NC I/O I/O VCC GND I/O I/O I/O GND VCC VCC I/O I/O VCC I/O NC I/O NC GND VCC I/O I/O NC I/O I/O I/O GND VCC I/O NC I/O I/O VCC I/O GND I/O Pin Number 101 103 106 107 108 109 110 111 112 113 114 115 116 121 124 125 126 133 135 136 140 143 144 145 147 151 152 154 155 156 158 160 161 165 166 168 170 173 A1240A Function NC NC GND NC NC GND VCC GND VCC VCC NC NC NC NC NC NC NC GND SDI, I/O NC NC NC NC NC NC NC PRA, I/O CLKA, I/O VCC GND CLKB, I/O PRB, I/O NC NC NC NC NC NC A1280A Function NC I/O GND I/O I/O GND VCC GND VCC VCC I/O I/O VCC NC I/O I/O NC GND SDI, I/O I/O VCC I/O I/O NC I/O I/O PRA, I/O CLKA, I/O VCC GND CLKB, I/O PRB, I/O I/O NC I/O I/O VCC I/O 97 NC I/O 175 DCLK, I/O DCLK, I/O Notes: 1. NC: Denotes No Connection 2. All unlisted pin numbers are user I/Os. 3. MODE pin should be terminated to GND through a 10K resistor to enable Actionprobe usage, otherwise it can be terminated directly to GND. v4.0 31 A C T ™ 2 F a m il y F P GA s Pa c ka ge P i n A s si g nm e n t s ( cont i nued) 172- P in CQF P 172 Pin #1 Index 1 172-Pin CQFP 172-Pin CQFP Pin Number 1 7 12 17 22 23 24 27 32 37 50 55 65 66 75 80 98 103 106 A1280A Function MODE GND VCC GND GND VCC VCC VCC GND GND VCC GND GND VCC GND VCC GND GND GND Pin Number 107 108 109 110 113 118 123 131 136 141 148 150 151 152 154 156 161 166 171 A1280A Function VCC GND VCC VCC VCC GND GND SDI, I/O VCC GND PRA, I/O CLKA, I/O VCC GND CLKB, I/O PRB, I/O GND VCC DCLK, I/O Notes: 1. All unlisted pin numbers are user I/Os. 2. MODE pin should be terminated to GND through a 10K resistor to enable Actionprobe usage, otherwise it can be terminated directly to GND. 32 v4.0 A C T ™ 2 F a m il y F PG A s Pa c ka ge P i n A s si g nm e n t s ( cont i nued) 100- P in CP GA 1 A B C D E F G H J K L 1 2 3 4 5 6 7 8 9 10 11 A B C D E 100-Pin CPGA F G H J K L 2 3 4 5 6 7 8 9 10 11 Orientation Pin Pin Number A4 A7 B6 C2 C3 C5 C6 C7 C8 D6 D10 E3 A1225A Function PRB, I/O PRA, I/O VCC MODE DCLK, I/O GND CLKA, I/O GND SDI, I/O CLKB, I/O GND GND Pin Number E11 F3 F9 F10 F11 G1 G3 G9 J5 J7 K6 A1225A Function VCC VCC VCC VCC GND VCC GND GND GND GND VCC Note: 1. All unlisted pin numbers are user I/Os. 2. MODE pin should be terminated to GND through a 10K resistor to enable Actionprobe usage, otherwise it can be terminated directly to GND. v4.0 33 A C T ™ 2 F a m il y F P GA s Pa c ka ge P i n A s si g nm e n t s ( cont i nued) 132- P in CP GA 1 A B C D E F G H J K L M N 1 2 3 4 5 6 7 8 9 10 11 12 13 A B C D E F 132-Pin CPGA G H J K L M N 2 3 4 5 6 7 8 9 10 11 12 13 Orientation Pin Pin Number A1 B5 B6 B7 B8 B9 B12 C3 C5 C6 C7 C9 D7 E3 E11 E12 A1240A Function MODE GND CLKB, I/O CLKA, I/O PRA, I/O GND SDI, I/O DCLK, I/O GND PRB, I/O VCC GND VCC GND GND GND Pin Number G2 G3 G4 G10 G11 G12 G13 H13 J2 J3 J11 K7 K12 L5 L7 L9 A1240A Function VCC VCC VCC VCC VCC VCC VCC GND GND GND GND VCC GND GND VCC GND F4 GND M9 GND Notes: 1. All unlisted pin numbers are user I/Os. 2. MODE pin should be terminated to GND through a 10K resistor to enable Actionprobe usage, otherwise it can be terminated directly to GND. 34 v4.0 A C T ™ 2 F a m il y F PG A s Pa c ka ge P i n A s si g nm e n t s ( cont i nued ) 176- P in CP GA 1 A B C D E F G H J K L M N P R 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 A B C D E F G 176-Pin CPGA H J K L M N P R 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Pin Number A9 B3 B8 B14 C3 C8 C9 D4 D5 D6 D7 D8 D10 D11 D12 E4 E12 F4 F12 G4 G12 A1280A Function CLKA, I/O DCLK, I/O CLKB, I/O SDI, I/O MODE GND PRA, I/O GND VCC GND PRB, I/O VCC GND VCC GND GND GND VCC GND GND VCC Pin Number H2 H3 H4 H12 H13 H14 J4 J12 J13 J14 K4 K12 L4 M4 M5 M6 M8 M10 M11 M12 N8 A1280A Function VCC VCC GND GND VCC VCC VCC GND GND VCC GND GND GND GND VCC GND GND GND VCC GND VCC Notes: 1. All unlisted pin numbers are user I/Os. 2. MODE pin should be terminated to GND through a 10K resistor to enable Actionprobe usage, otherwise it can be terminated directly to GND. v4.0 35 A C T ™ 2 F a m il y F P GA s Li s t o f C ha ng e s The following table lists critical changes that were made in the current version of the document. Previous version unspecified Changes in current version (production (unmarked) v4.0.1–web-only) Page In the 176-Pin CPGA package, pin A3 was incorrectly assigned as CLKA, I/O. A3 is a 35 user I/O. Pin A9 is CLKA, I/O D at a S he et Ca t e g o r i e s In order to provide the latest information to designers, some data sheets are published before data has been fully characterized. These data sheets are marked as “Advanced” or Preliminary” data sheets. The definition of these categories are as follows: Adv anc ed The data sheet contains initial estimated information based on simulation, other products, devices, or speed grades. This information can be used as estimates, but not for production. P rel im i nar y The data sheet contains information based on simulation and/or initial characterization. The information is believed to be correct, but changes are possible. Unm ar ked (pr odu ct ion) The data sheet contains information that is considered to be final. 36 v4.0 A C T ™ 2 F a m il y F PG A s v4.0 37 Actel and the Actel logo are registered trademarks of Actel Corporation. All other trademarks are the property of their owners. http://www.actel.com Actel Europe Ltd. Daneshill House, Lutyens Close Basingstoke, Hampshire RG24 8AG United Kingdom Tel: +44 (0)1256 305600 Fax: +44 (0)1256 355420 Actel Corporation 955 East Arques Avenue Sunnyvale, California 94086 USA Tel: (408) 739-1010 Fax: (408) 739-1540 Actel Asia-Pacific EXOS Ebisu Bldg. 4F 1-24-14 Ebisu Shibuya-ku Tokyo 150 Japan Tel: +81 03-3445-7671 Fax: +81 03-3445-7668 5172104-6/12.00