A14V60AA-1CQ208B

Accelerator Series FPGAs – ACT™ 3 Family F eatures • Replaces up to twenty 32 macro-cell CPLDs • Replaces up to one hundred 20-pin PAL® Packages • Up to 1153 Dedicated Flip-Flops • VQFP, TQFP, BGA, and PQFP Packages • Nonvolatile, User Programmable • Fully Tested Prior to Shipment • 5.0V and 3.3V Versions • Optimized for Logic Synthesis Methodologies • Low-power CMOS Technology A1415 1,500 3,750 40 15 200 104 96 264 80 100 84 100 — 100 — — — 108 MHz 63 MHz 110 MHz 250 MHz 250 MHz 7.5 ns A1425 2,500 6,250 60 25 310 160 150 360 100 133 84 100, 160 — 100 — — 132 108 MHz 63 MHz 110 MHz 250 MHz 250 MHz 7.5 ns A1440 4,000 10,000 100 40 564 288 276 568 140 175 84 160 — 100 176 — — 100 MHz 63 MHz 110 MHz 250 MHz 250 MHz 8.5 ns A1460 6,000 15,000 150 60 848 432 416 768 168 207 — 160, 208 — — 176 225 196 97 MHz 63 MHz 110 MHz 200 MHz 200 MHz 9.0 ns A14100 10,000 25,000 250 100 1,377 697 680 1,153 228 257 — — 208 — — 313 256 93 MHz 63 MHz 105 MHz 200 MHz 200 MHz 9.5 ns • Up to 10,000 Gate Array Equivalent Gates (up to 25,000 equivalent PLD Gates) • Highly Predictable Performance with 100% Automatic Placement and Routing • 7.5 ns Clock-to-Output Times • Up to 250 MHz On-Chip Performance • Up to 228 User-Programmable I/O Pins • Four Fast, Low-Skew Clock Networks • More than 500 Macro Functions Device Capacity Gate Array Equivalent Gates PLD Equivalent Gates TTL Equivalent Packages (40 gates) 20-Pin PAL Equivalent Packages (100 gates) Logic Modules S-Module C-Module Dedicated Flip-Flops1 User I/Os (maximum) Packages2 CPGA PLCC PQFP RQFP VQFP TQFP BGA CQFP Performance3 (maximum, worst-case commercial) Chip-to-Chip4 Accumulators (16-bit) Loadable Counter (16-bit) Prescaled Loadable Counters (16-bit) Datapath, Shift Registers Clock-to-Output (pad-to-pad) (by pin count) Notes: 1. One flip-flop per S-Module, two flip-flops per I/O-Module. 2. See product plan on page 1-178 for package availability. 3. Based on A1415A-3, A1425A-3, A1440B-3, A1460B-3, and A14100B-3. 4. Clock-to-Output + Setup S e p t e m b e r 1997 1-175 © 1997 Actel Corporation D escription Actel’s ACT 3 Accelerator Series of FPGAs offers the industry’s fastest high-capacity programmable logic device. ACT 3 FPGAs offer a high perfomance, PCI compliant programmable solution capable of 250 MHz on-chip performance and 7.5 nanosecond clock-to-output, with capacities spanning from 1,500 to 10,000 gate array equivalent gates. For further information regarding PCI compliance of ACT 3 devices, see “Accelerator Series FPGAs—ACT 3 PCI Compliant Family.” The ACT 3 family builds on the proven two-module architecture consisting of combinatorial and sequential logic modules used in Actel’s 3200DX and 1200XL families. In addition, the ACT 3 I/O modules contain registers which deliver 7.5 nanosecond clock-to-out times. The devices contain four clock distribution networks, including dedicated array and I/O clocks, supporting very fast synchronous and asynchronous designs. In addition, routed clocks can be used to drive high fanout signals such as flip-flop resets and output enables. The ACT 3 family is supported by Actel’s Designer Series Development System which offers automatic placement and routing (with automatic or fixed pin assignments), static timing anlaysis, user programming, and debug and diagnostic probe capabilities. The Designer Series is supported on the following platforms: 486/Pentium class PC’s, Sun®‚ and HP®‚ workstations. The software provides CAE interfaces to Cadence, Mentor Graphics®, OrCAD™ and Viewlogic®‚ design environments. Additional platforms are supported through Actel’s Industry Alliance Program, including DATA I/O (ABEL FPGA) and MINC. Predictable Performance* (Worst-Case Commercial) Accumulators (16-bit) 63 MHz 110 MHz 250 MHz 250 MHz Loadable Counters (16-bit) Prescaled Loadable Counters (16-bit) Shift Registers S ystem Performance Model Chip #1 I/O Module Chip #2 I/O Module 35 pF I/O CLK I/O CLK tCKHS tTRACE tINSU Chip-to-Chip Performance (Worst-Case Commercial) tCKHS A1425A-3 A1460A-3 7.5 9.0 tTRACE 1.0 1.0 tINSU 1.8 1.3 Total 10.3 ns 11.3 ns MHz 97 88 1-176 A c c e l e ra to r S e ri e s F P G A s – A C T ™ 3 F ami l y O rdering Information A14100 A – RQ 208 C Application (Temperature Range) C = Commercial (0 to +70°C) I = Industrial (–40 to +85°C) M = Military (–55 to +125°C) B = MIL-STD-883 Package Lead Count Package Type PG = Ceramic Pin Grid Array PL = Plastic Leaded Chip Carrier PQ = Plastic Quad Flatpack RQ = Plastic Power Quad Flatpack VQ = Very Thin (1.0 mm) Quad Flatpack TQ = Thin (1.4 mm) Quad Flatpack CQ = Ceramic Quad Flatpack BG = Plastic Ball Grid Array Speed Grade Std = Standard Speed –1 = Approximately 15% faster than Standard –2 = Approximately 25% faster than Standard –3 = Approximately 35% faster than Standard Die Revision Part Number A1415A = A14V15A = A1425A = A14V25A = A1440A = A14V40A = A1460A = A14V60A = A14100A = A14V100A = 1500 Gates 1500 Gates (3.3V) 2500 Gates 2500 Gates (3.3V) 4000 Gates 4000 Gates (3.3V) 6000 Gates 6000 Gates (3.3V) 10000 Gates 10000 Gates (3.3V) 1-177 P roduct Plan Speed Grade* Std A1415A Device 84-pin Plastic Leaded Chip Carrier (PLCC) 100-pin Plastic Quad Flatpack (PQFP) 100-pin Very Thin Quad Flatpack (VQFP) 100-pin Ceramic Pin Grid Array (CPGA) A14V15A Device 84-pin Plastic Leaded Chip Carrier (PLCC) 100-pin Very Thin Quad Flatpack (VQFP) A1425A Device 84-pin Plastic Leaded Chip Carrier (PLCC) 100-pin Plastic Quad Flatpack (PQFP) 100-pin Very Thin Quad Flatpack (VQFP) 132-pin Ceramic Quad Flatpack (CQFP) 133-pin Ceramic Pin Grid Array (CPGA) 160-pin Plastic Quad Flatpack (PQFP) A14V25A Device 84-pin Plastic Leaded Chip Carrier (PLCC) 100-pin Very Thin Quad Flatpack (VQFP) 160-pin Plastic Quad Flatpack (PQFP) A1440A Device 84-pin Plastic Leaded Chip Carrier (PLCC) 100-pin Very Thin Quad Flatpack (VQFP) 160-pin Plastic Quad Flatpack (PQFP) 175-pin Ceramic Pin Grid Array (CPGA) 176-pin Thin Quad Flatpack (TQFP) A14V40A Device 84-pin Plastic Leaded Chip Carrier (PLCC) 100-pin Very Thin Quad Flatpack (VQFP) 160-pin Plastic Quad Flatpack (PQFP) 176-pin Thin Quad Flatpack (TQFP) A1460A Device 160-pin Plastic Quad Flatpack (PQFP) 176-pin Thin Quad Flatpack (TQFP) 196-pin Ceramic Quad Flatpack (CQFP) 207-pin Ceramic Pin Grid Array (CPGA) 208-pin Plastic Quad Flatpack (PQFP) 225-pin Platic Ball Grid Array (BGA) Applications: C I M B † = Commercial = Industrial = Military = MIL-STD-883 Commercial Only Availability: = Available P = Planned — = Not Planned P P — P† P P — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — † — † — — — — — — — — — — — — — — — — — — — — — — — — — — — –1 –2 –3 C I Application M B — — † * Speed Grade: –1 = Approx. 15% faster than Standard –2 = Approx. 25% faster than Standard –3 = Approx. 35 % faster than Standard. 1-178 A c c e l e ra to r S e ri e s F P G A s – A C T ™ 3 F ami l y P roduct Plan ( continued) Speed Grade* Std A14V60A Device 160-pin Plastic Quad Flatpack (PQFP) 176-pin Thin Quad Flatpack (TQFP) 208-pin Plastic Quad Flatpack (PQFP) A14100A Device 208-pin Power Quad Flatpack (RQFP) 257-pin Ceramic Pin Grid Array (CPGA) 313-pin Plastic Ball Grid Array (BGA) 256-pin Ceramic Quad Flatpack (CQFP) A14V100A Device 208-pin Power Quad Flatpack (RQFP) 313-pin Plastic Ball Grid Array (BGA) Applications: C I M B † = Commercial = Industrial = Military = MIL-STD-883 Commercial Only Availability: — — = Available P = Planned — = Not Planned — — — — — — — — — — — † — † — — — — — — — — — — — — — — — — — — — — — — — — — –1 –2 –3 C I Application M B * Speed Grade: –1 = Approx. 15% faster than Standard –2 = Approx. 25% faster than Standard –3 = Approx. 35 % faster than Standard. P lastic Device Resources User I/Os PLCC Device Series A1415 A1425 A1440 A1460 A14100 Logic Modules 200 310 564 848 1377 Gates 1500 2500 4000 6000 10000 84-pin 70 70 70 — — 100-pin 80 80 — — — PQFP, RQFP 160-pin — 100 131 131 — 208-pin — — — 167 175 VQFP 100-pin 80 83 83 — — TQFP 176-pin — — 140 151 — BGA 225-pin — — — 168 — 313-pin — — — — 228 1-179 H ermetic Device Resources User I/Os CPGA Device Series A1415 A1425 A1440 A1460 A14100 Logic Modules 200 310 564 848 1377 Gates 1500 2500 4000 6000 10000 100-pin 80 — — — — 133-pin — 100 — — — 175-pin — — 140 — — 207-pin — — — 168 — 257-pin — — — — 228 132-pin — 100 — — — CQFP 196-pin — — — 168 — 256-pin — — — — 228 Pin Description C LKA Clock A (Input) Clock input for clock distribution networks. The Clock input is buffered prior to clocking the logic modules. This pin can also be used as an I/O. C LKB Clock B (Input) function as I/Os. To provide Actionprobe capability, the MODE pin should be terminated to GND through a 10K resistor so that the MODE pin can be pulled high when required. NC No Connection This pin is not connected to circuitry within the device. P RA Probe A (Output) Clock input for clock distribution networks. The Clock input is buffered prior to clocking the logic modules. This pin can also be used as an I/O. G ND Ground LOW supply voltage. H CLK Dedicated (Hard-wired) Array Clock (Input) Clock input for sequential modules. This input is directly wired to each S-Module and offers clock speeds independent of the number of S-Modules being driven. This pin can also be used as an I/O. I /O Input/Output (Input, Output) The Probe A pin is used to output data from any user-defined design node within the device. This independent diagnostic pin can be used in conjunction with the Probe B pin to allow real-time diagnostic output of any signal path within the device. The Probe A pin can be used as a user-defined I/O when debugging has been completed. The pin’s probe capabilities can be permanently disabled to protect programmed design confidentiality. PRA is accessible when the MODE pin is HIGH. This pin functions as an I/O when the MODE pin is LOW. P RB Probe B (Output) The I/O pin functions as an input, output, three-state, or bidirectional buffer. Input and output levels are compatible with standard TTL and CMOS specifications. Unused I/O pins are tristated by the Designer Series software. I OCLK Dedicated (Hard-wired) I/O Clock (Input) Clock input for I/O modules. This input is directly wired to each I/O module and offers clock speeds independent of the number of I/O modules being driven. This pin can also be used as an I/O. I OPCL Dedicated (Hard-wired) I/O Preset/Clear (Input) The Probe B pin is used to output data from any user-defined design node within the device. This independent diagnostic pin can be used in conjunction with the Probe A pin to allow real-time diagnostic output of any signal path within the device. The Probe B pin can be used as a user-defined I/O when debugging has been completed. The pin’s probe capabilities can be permanently disabled to protect programmed design confidentiality. PRB is accessible when the MODE pin is HIGH. This pin functions as an I/O when the MODE pin is LOW. S DI Serial Data Input (Input) Input for I/O preset or clear. This global input is directly wired to the preset and clear inputs of all I/O registers. This pin functions as an I/O when no I/O preset or clear macros are used. M ODE Mode (Input) Serial data input for diagnostic probe and device programming. SDI is active when the MODE pin is HIGH. This pin functions as an I/O when the MODE pin is LOW. D CLK Diagnostic Clock (Input) Clock input for diagnostic probe and device programming. DCLK is active when the MODE pin is HIGH. This pin functions as an I/O when the MODE pin is LOW. VCC 5 V S upply Voltage The MODE pin controls the use of diagnostic pins (DCLK, PRA, PRB, SDI). When the MODE pin is HIGH, the special functions are active. When the MODE pin is LOW, the pins HIGH supply voltage. 1-180 A c c e l e ra to r S e ri e s F P G A s – A C T ™ 3 F ami l y A rchitecture Logic Modules This section of the data sheet is meant to familiarize the user with the architecture of the ACT 3 family of FPGA devices. A generic description of the family will be presented first, followed by a detailed description of the logic blocks, the routing structure, the antifuses, and the special function circuits. The on-chip circuitry required to program the devices is not covered. T opology The ACT 3 family architecture is composed of six key elements: Logic modules, I/O modules, I/O Pad Drivers, Routing Tracks, Clock Networks, and Programming and Test Circuits. The basic structure is similar for all devices in the family, differing only in the number of rows, columns, and I/Os. The array itself consists of alternating rows of modules and channels. The logic modules and channels are in the center of the array; the I/O modules are located along the array periphery. A simplified floor plan is depicted in Figure 1. ACT 3 logic modules are enhanced versions of the 1200XL family logic modules. As in the 1200XL family, there are two types of modules: C-modules and S-modules. The C-module is functionally equivalent to the 1200XL C-module and implements high fanin combinatorial macros, such as 5-input AND, 5-input OR, and so on. It is available for use as the CM8 hard macro. The S-module is designed to implement high-speed sequential functions within a single module. S-modules consist of a full C-module driving a flip-flop, which allows an additional level of logic to be implemented without additional propagation delay. It is available for use as the DFM8A/B and DLM8A/B hard macros. C-modules and S-modules are arranged in pairs called module-pairs. Module-pairs are arranged in alternating patterns and make up the bulk of the array. This arrangement allows the placement software to support two-module macros of four types (CC, CS, SC, and SS). The C-module implements the following function: Y = !S1 * !S0 * D00 + !S1 * S0 * D01 + S1 * !S0 * D10 + S1 * S0 * D11 where: S0 = A0 * B0 and S1 = A1 + B1 An Array with n rows and m columns 0 Rows Channels n+2 n+1 n+1 n n n–1 • • • 2 n–1 • • • 2 1 1 Left I/Os 0 0 BIO IO IO IO IO IO IO IO IO IO IO IO Right I/Os Bottom I/Os IO IO BIN S S C C S S C C S C S IO IO IO IO BIN S S C C S S C C S C S IO IO IO IO BIN S S C C S S C C S C S IO IO IO IO BIN S S C C S S C C S C S IO IO IO IO IO CLKM IO IO IO IO IO IO Top I/Os 1 2 3 4 5 c–1 c c+1 m m+1 m+2 m+3 Columns Figure 1 • Generalized Floor Plan of ACT 3 Device 1-181 The S-module contains a full implementation of the C-module plus a clearable sequential element that can either implement a latch or flip-flop function. The S-module can therefore implement any function implemented by the C-module. This allows complex combinatorial-sequential functions to be implemented with no delay penalty. The Designer Series Development System will automatically combine any C-module macro driving an S-module macro into the S-module, thereby freeing up a logic module and eliminating a module delay. The clear input CLR is accessible from the routing channel. In addition, the clock input may be connected to one of three clock networks: CLKA, CLKB, or HCLK. The C-module and S-module functional descriptions are shown in Figures 2 and 3. The clock selection is determined by a multiplexor select at the clock input to the S-module. I/Os D00 D01 D10 D11 S1 S0 Y OUT A1 B1 A0 B0 I/O Modules Figure 2 • C-Module Diagram preset/clear network (IOPCL). Either preset or clear can be selected individually on an I/O module by I/O module basis. The I/O module output Y is used to bring Pad signals into the array or to feed the output register back into the array. This allows the output register to be used in high-speed state machine applications. Side I/O modules have a dedicated output segment for Y extending into the routing channels above and below (similar to logic modules). Top/Bottom I/O modules have no dedicated output segment. Signals coming into the chip from the top or bottom are routed using F-fuses and LVTs (F-fuses and LVTs are explained in detail in the routing section). I/O modules provide an interface between the array and the I/O Pad Drivers. I/O modules are located in the array and access the routing channels in a similar fashion to logic modules. The I/O module schematic is shown in Figure 4. The signals DataIn and DataOut connect to the I/O pad driver. Each I/O module contains two D-type flip-flops. Each flip-flop is connected to the dedicated I/O clock (IOCLK). Each flip-flop can be bypassed by nonsequential I/Os. In addition, each flip-flop contains a data enable input that can be accessed from the routing channels (ODE and IDE). The asynchronous preset/clear input is driven by the dedicated D00 D01 D10 D11 S1 S0 Y D Q OUT CLK A1 B1 A0 B0 CLR Figure 3 • S-Module Diagram 1-182 A c c e l e ra to r S e ri e s F P G A s – A C T ™ 3 F ami l y D 0 MUX 1 D Q 0 MUX 1 DATAOUT ODE CLR/PRE S0 Y 0 S1 1 MUX 2 3 Q D 1 MUX 0 DATAIN CLR/PRE IOPCL IOCLK Figure 4 • Functional Diagram for I/O Module I/O Pad Drivers All pad drivers are capable of being tristate. Each buffer connects to an associated I/O module with four signals: OE (Output Enable), IE (Input Enable), DataOut, and DataIn. Certain special signals used only during programming and test also connect to the pad drivers: OUTEN (global output enable), INEN (global input enable), and SLEW (individual slew selection). See Figure 5. Special I/Os buffer (IOPCL). Their function is determined by the I/O macros selected. Clock Networks The ACT 3 architecture contains four clock networks: two high-performance dedicated clock networks and two general purpose routed networks. The high-performance networks function up to 200 MHz, while the general purpose routed networks function up to 150 MHz. Dedicated Clocks The special I/Os are of two types: temporary and permanent. Temporary special I/Os are used during programming and testing. They function as normal I/Os when the MODE pin is inactive. Permanent special I/Os are user programmed as either normal I/Os or special I/Os. Their function does not change once the device has been programmed. The permanent special I/Os consist of the array clock input buffers (CLKA and CLKB), the hard-wired array clock input buffer (HCLK), the hard-wired I/O clock input buffer (IOCLK), and the hard-wired I/O register preset/clear input Dedicated clock networks support high performance by providing sub-nanosecond skew and guaranteed performance. Dedicated clock networks contain no programming elements in the path from the I/O Pad Driver to the input of S-modules or I/O modules. There are two dedicated clock networks: one for the array registers (HCLK), and one for the I/O registers (IOCLK). The clock networks are accessed by special I/Os. 1-183 CLKB OE CLKA SLEW FROM PADS CLKMOD CLKINB CLKINA S0 S1 INTERNAL SIGNAL CLKO(17) DATAOUT CLOCK DRIVERS PAD CLKO(16) CLKO(15) DATAIN CLKO(2) CLKO(1) IEN INEN OUTEN CLOCK TRACKS Figure 6 • Clock Networks Routing Structure Figure 5 • Function Diagram for I/O Pad Driver Routed Clocks The routed clock networks are referred to as CLK0 and CLK1. Each network is connected to a clock module (CLKMOD) that selects the source of the clock signal and may be driven as follows (see Figure 6): • externally from the CLKA pad • externally from the CLKB pad • internally from the CLKINA input • internally from the CLKINB input The clock modules are located in the top row of I/O modules. Clock drivers and a dedicated horizontal clock track are located in each horizontal routing channel. The function of the clock module is determined by the selection of clock macros from the macro library. The macro CLKBUF is used to connect one of the two external clock pins to a clock network, and the macro CLKINT is used to connect an internally generated clock signal to a clock network. Since both clock networks are identical, the user does not care whether CLK0 or CLK1 is being used. Routed clocks can also be used to drive high fanout nets like resets, output enables, or data enables. This saves logic modules and results in performance increases in some cases. The ACT 3 architecture uses vertical and horizontal routing tracks to connect the various logic and I/O modules. These routing tracks are metal interconnects that may either be of continuous length or broken into segments. Segments can be joined together at the ends using antifuses to increase their lengths up to the full length of the track. Horizontal Routing Horizontal channels are located between the rows of modules and are composed of several routing tracks. The horizontal routing tracks within the channel are divided into one or more segments. The minimum horizontal segment length is the width of a module-pair, and the maximum horizontal segment length is the full length of the channel. Any segment that spans more than one-third the row length is considered a long horizontal segment. A typical channel is shown in Figure 7. Undedicated horizontal routing tracks are used to route signal nets. Dedicated routing tracks are used for the global clock networks and for power and ground tie-off tracks. Vertical Routing Other tracks run vertically through the modules. Vertical tracks are of three types: input, output, and long. Vertical tracks are also divided into one or more segments. Each segment in an input track is dedicated to the input of a particular module. Each segment in an output track is dedicated to the output of a particular module. Long segments are uncommitted and can be assigned during 1-184 A c c e l e ra to r S e ri e s F P G A s – A C T ™ 3 F ami l y routing. Each output segment spans four channels (two above and two below), except near the top and bottom of the array where edge effects occur. LVTs contain either one or two segments. An example of vertical routing tracks and segments is shown in Figure 8. MODULE ROW HCLK CLK0 NVCC SIGNAL TRACK SEGMENT SIGNAL (LHT) | | | | | | | SIGNAL NVSS CLK1 MODULE ROW HF Figure 7 • Horizontal Routing Tracks and Segments LVTS S-MODULE C-MODULE MODULE ROW VF CHANNEL VERTICLE INPUT SEGMENT XF FF S-MODULE C-MODULE Figure 8 • Vertical Routing Tracks and Segments 1-185 Antifuse Connections An antifuse is a “normally open” structure as opposed to the normally closed fuse structure used in PROMs or PALs. The use of antifuses to implement a programmable logic device results in highly testable structures as well as an efficient programming architecture. The structure is highly testable because there are no preexisting connections; temporary connections can be made using pass transistors. These temporary connections can isolate individual antifuses to be programmed as well as isolate individual circuit structures to be tested. This can be done both before and after programming. For example, all metal tracks can be tested for continuity and shorts between adjacent tracks, and the functionality of all logic modules can be verified. Four types of antifuse connections are used in the routing structure of the ACT 3 array. (The physical structure of the antifuse is identical in each case; only the usage differs.) Table 1 shows four types of antifuses. Table 1 • Antifuse Types XF HF VF FF Horizontal-to-Vertical Connection Horizontal-to-Horizontal Connection Vertical-to-Vertical Connection “Fast” Vertical Connection or the channel below. The logic modules are arranged such that half of the inputs are connected to the channel above and half of the inputs to segments in the channel below as shown in Figure 9. Module Output Connections Module outputs have dedicated output segments. Output segments extend vertically two channels above and two channels below, except at the top or bottom of the array. Output segments twist, as shown in Figure 10, so that only four vertical tracks are required. LVT Connections Outputs may also connect to nondedicated segments called Long Vertical Tracks (LVTs). Each module pair in the array shares four LVTs that span the length of the column. Any module in the column pair can connect to one of the LVTs in the column using an FF connection. The FF connection uses antifuses connected directly to the driver stage of the module output, bypassing the isolation transistor. FF antifuses are programmed at a higher current level than HF, VF, or XF antifuses to produce a lower resistance value. Antifuse Connections In general every intersection of a vertical segment and a horizontal segment contains an unprogrammed antifuse (XF-type). One exception is in the case of the clock networks. Clock Connections Examples of all four types of connections are shown in Figures 7 and 8. Module Interface Connections to Logic and I/O modules are made through vertical segments that connect to the module inputs and outputs. These vertical segments lie on vertical tracks that span the entire height of the array. Module Input Connections To minimize loading on the clock networks, a subset of inputs has antifuses on the clock tracks. Only a few of the C-module and S-module inputs can be connected to the clock networks. To further reduce loading on the clock network, only a subset of the horizontal routing tracks can connect to the clock inputs of the S-module. Programming and Test Circuits The tracks dedicated to module inputs are segmented by pass transistors in each module row. During normal user operation, the pass transistors are inactive, which isolates the inputs of a module from the inputs of the module directly above or below it. During certain test modes, the pass transistors are active to verify the continuity of the metal tracks. Vertical input segments span only the channel above The array of logic and I/O modules is surrounded by test and programming circuits controlled by the temporary special I/O pins MODE, SDI, and DCLK. The function of these pins is similar to all ACT family devices. The ACT 3 family also includes support for two Actionprobe® circuits allowing complete observability of any logic or I/O module in the array using the temporary special I/O pins, PRA and PRB. 1-186 A c c e l e ra to r S e ri e s F P G A s – A C T ™ 3 F ami l y Y+2 Y+2 Y+1 Y+1 B1 B0 D01 D00 A1 D10 D11 A0 Y Y B0 D10 A0 D11 A1 B1 D01 Y-1 Y-1 Y-2 LVTs S-MODULES Y-2 C-MODULES Figure 9 • Logic Module Routing Interface 1-187 5V Operating Conditions Absolute Maximum Ratings 1 Free air temperature range Recommended Operating Conditions Parameter Temperature Range1 Limits Units V V V mA °C 5V Power Supply Tolerance Commercial Industrial Military 0 to +70 ±5 –40 to +85 ± 10 –55 to +125 ± 10 Units °C %VCC Symbol VCC VI VO IIO TSTG Parameter DC Supply Voltage Input Voltage Output Voltage I/O Source Sink Current2 Storage Temperature –0.5 to +7.0 –0.5 to VCC +0.5 –0.5 to VCC +0.5 ± 20 –65 to +150 Note: 1. Ambient temperature (TA) is used for commercial and industrial; case temperature (TC) is used for military. Notes: 1. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. Device should not be operated outside the Recommended Operating Conditions. 2. Device inputs are normally high impedance and draw extremely low current. However, when input voltage is greater than VCC + 0.5 V or less than GND – 0.5 V, the internal protection diodes will forward bias and can draw excessive current. Electrical Specifications Commercial Symbol Parameter VOH1,2 HIGH Level Output Test Condition IOH = –4 mA (CMOS) IOH = –6 mA (CMOS) 3.84 IOH = –10 mA VOL1,2 VIH VIL IIN IOZ CIO ICC(S) ICC(D) LOW Level Output IOL = +12 mA HIGH Level Input LOW Level Input Input Leakage 3-state Output Leakage I/O Capacitance3,4 TTL Inputs TTL Inputs VI = VCC or GND VO = VCC or GND (TTL)3 (TTL)3 2.0 –0.3 –10 –10 2.40 0.33 0.50 VCC + 0.3 0.8 +10 +10 10 2 2.0 –0.3 –10 –10 VCC + 0.3 0.8 +10 +10 10 10 2.0 –0.3 –10 –10 VCC + 0.3 0.8 +10 +10 10 20 0.4 0.4 IOL = +6 mA (CMOS) Min. Max. Industrial Min. 3.7 Max. Military Min. 3.7 Max. Units V V V V V V V µA µA pF mA Standby VCC Supply Current (typical = 0.7 mA) Dynamic VCC Supply Current See “Power Dissipation” Section Notes: 1. Actel devices can drive and receive either CMOS or TTL signal levels. No assignment of I/Os as TTL or CMOS is required. 2. Tested one output at a time, VCC = min. 3. Not tested, for information only. 4. VOUT = 0V, f = 1 MHz. 5. Typical standby current = 0.7 mA. All outputs unloaded. All inputs = VCC or GND. 1-188 A c c e l e ra to r S e ri e s F P G A s – A C T ™ 3 F ami l y 3.3V Operating Conditions Absolute Maximum Ratings 1 Free air temperature range Recommended Operating Conditions Parameter Temperature Range1 Power Supply Tolerance Commercial 0 to +70 3.0 to 3.6 Units °C V Symbol VCC VI VO IIO TSTG Parameter DC Supply Voltage Input Voltage Output Voltage I/O Source Sink Current2 Storage Temperature Limits –0.5 to +7.0 –0.5 to VCC +0.5 –0.5 to VCC +0.5 ± 20 –65 to +150 Units V V V mA °C Note: 1. Ambient temperature (TA) is used for commercial. Notes: 1. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. Device should not be operated outside the Recommended Operating Conditions. 2. Device inputs are normally high impedance and draw extremely low current. However, when input voltage is greater than VCC + 0.5 V or less than GND – 0.5 V, the internal protection diodes will forward bias and can draw excessive current. Electrical Specifications Commercial Parameter Min. VOH1 VOL1 VIL VIH Input Transition Time tR, tF2 CIO I/O Capacitance2, 3 Standby Current, ICC4 (typical 5 (IOH = –4 mA) (IOH = –3.2 mA) (IOL = 6 mA) –0.3 2.0 2.15 2.4 0.4 0.8 VCC + 0.3 500 10 = 0.3 mA) –10 0.75 10 Max. V V V V V ns pF mA µA Units Leakage Current Notes: 1. Only one output tested at a time. VCC = min. 2. Not tested, for information only. 3. Includes worst-case 84-pin PLCC package capacitance. VOUT = 0 V, f = 1 MHz. 4. Typical standby current = 0.3 mA. All outputs unloaded. All inputs = VCC or GND. 5. VO, VIN = VCC or GND. 1-189 Package Thermal Characteristics The device junction to case thermal characteristic is θjc, and the junction to ambient air characteristic is θja. The thermal characteristics for θja are shown with two different air flow rates. Maximum junction temperature is 150°C. A sample calculation of the absolute maximum power dissipation allowed for a CPGA 175-pin package at commercial temperature and still air is as follows: 150°C – 70°C Max. junction temp. (°C) – Max. ambient temp. (°C) Absolute Maximum Power Allowed = ------------------------------------------------------------------------------------------------------------------------------ = --------------------------------- = 3.2 W θ j a (°C/W) 25 °C/W θja Still Air 35 30 25 22 15 55 36 30 51 33 33 43 32 17 37 25 23 θja 300 ft/min 17 15 14 13 8 30 24 18 40 26 26 35 25 13 28 19 17 Package Type1 Ceramic Pin Grid Array Pin Count 100 133 175 207 257 132 196 256 100 160 208 100 176 208 84 225 313 θjc 20 20 20 20 20 13 13 13 13 10 10 12 11 0.4 12 10 10 Units °C/W °C/W °C/W °C/W °C/W °C/W °C/W °C/W °C/W °C/W °C/W °C/W °C/W °C/W °C/W °C/W °C/W Ceramic Quad Flatpack Plastic Quad Flatpack Very Thin Quad Flatpack Thin Quad Flatpack Power Quad Flatpack Plastic Leaded Chip Carrier Plastic Ball Grid Array Note: 1. Maximum Power Dissipation in Still Air for 160-pin PQFP package is 2.4 Watts, 208-pin PQFP package is 2.4 Watts, 100-pin PQFP package is 1.6 Watts, 100-pin VQFP package is 1.9 Watts, 176-pin TQFP package is 2.5 Watts, 84-pin PLCC package is 2.2 Watts, 208-pin RQFP package is 4.7 Watts, 225-pin BGA package is 3.2 Watts, 313-pin BGA package is 3.5 Watts. Power Dissipation Static Power Component P = [ICC standby+ Iactive] * VCC + IOL * VOL * N + IOH * (VCC – VOH) * M Where: (1) Actel FPGAs have small static power components that result in lower power dissipation than PALs or PLDs. By integrating multiple PALs/PLDs into one FPGA, an even greater reduction in board-level power dissipation can be achieved. The power due to standby current is typically a small component of the overall power. Standby power is calculated below for commercial, worst case conditions. ICC 2mA VCC 5.25 V Power 10.5 mW ICC standby is the current flowing when no inputs or outputs are changing. Iactive is the current flowing due to CMOS switching. IOL, IOH are TTL sink/source currents. VOL, VOH are TTL level output voltages. N equals the number of outputs driving TTL loads to VOL. M equals the number of outputs driving TTL loads to VOH. An accurate determination of N and M is problematical because their values depend on the design and on the system I/O. The power can be divided into two components: static and active. The static power dissipated by TTL loads depends on the number of outputs driving high or low and the DC load current. Again, this value is typically small. For instance, a 32-bit bus sinking 4 mA at 0.33 V will generate 42 mW with all outputs driving low, and 140 mW with all outputs driving high. The actual dissipation will average somewhere between as I/Os switch states with time. 1-190 A c c e l e ra to r S e ri e s F P G A s – A C T ™ 3 F ami l y A ctive Power Component Where: m n p q1 q2 r1 r2 s1 s2 CEQM CEQI CEQO CEQCR CEQCD CEQCI CL fm fn fp fq1 fq2 fs1 fs2 = = = = = = = = = = = = = = = = = = = = = = = Number of logic modules switching at fm Number of input buffers switching at fn Number of output buffers switching at fp Number of clock loads on the first routed array clock Number of clock loads on the second routed array clock Fixed capacitance due to first routed array clock Fixed capacitance due to second routed array clock Fixed number of clock loads on the dedicated array clock Fixed number of clock loads on the dedicated I/O clock Equivalent capacitance of logic modules in pF Equivalent capacitance of input buffers in pF Equivalent capacitance of output buffers in pF Equivalent capacitance of routed array clock in pF Equivalent capacitance of dedicated array clock in pF Equivalent capacitance of dedicated I/O clock in pF Output lead capacitance in pF Average logic module switching rate in MHz Average input buffer switching rate in MHz Average output buffer switching rate in MHz Average first routed array clock rate in MHz Average second routed array clock rate in MHz Average dedicated array clock rate in MHz Average dedicated I/O clock rate in MHz Power dissipation in CMOS devices is usually dominated by the active (dynamic) power dissipation. This component is frequency dependent, a function of the logic and the external I/O. Active power dissipation results from charging internal chip capacitances of the interconnect, unprogrammed antifuses, module inputs, and module outputs, plus external capacitance due to PC board traces and load device inputs. An additional component of the active power dissipation is the totem-pole current in CMOS transistor pairs. The net effect can be associated with an equivalent capacitance that can be combined with frequency and voltage to represent active power dissipation. E quivalent Capacitance The power dissipated by a CMOS circuit can be expressed by the Equation 2. Power (uW) = CEQ * VCC2 * F Where: CEQ is the equivalent capacitance expressed in pF. VCC is the power supply in volts. F is the switching frequency in MHz. Equivalent capacitance is calculated by measuring ICCactive at a specified frequency and voltage for each circuit component of interest. Measurements have been made over a range of frequencies at a fixed value of VCC. Equivalent capacitance is frequency independent so that the results may be used over a wide range of operating conditions. Equivalent capacitance values are shown below. C E Q V alues for Actel FPGAs (2) Modules (CEQM) Input Buffers (CEQI) Output Buffers (CEQO) Routed Array Clock Buffer Loads (CEQCR) Dedicated Clock Buffer Loads (CEQCD) I/O Clock Buffer Loads (CEQCI) 6.7 7.2 10.4 1.6 0.7 0.9 To calculate the active power dissipated from the complete design, the switching frequency of each part of the logic must be known. Equation 3 shows a piece-wise linear summation over all components. Power =VCC2 * [(m * CEQM* fm)modules + (n * CEQI* fn)inputs + (p * (CEQO+ CL) * fp)outputs + 0.5 * (q1 * CEQCR * fq1)routed_Clk1 + (r1 * fq1)routed_Clk1 + 0.5 * (q2 * CEQCR * fq2)routed_Clk2 + (r2 * fq2)routed_Clk2 + 0.5 * (s1 * CEQCD * fs1)dedicated_Clk + (s2 * CEQCI * fs2)IO_Clk] (3) 1-191 Fixed Capacitance Values for Actel FPGAs (pF) Determining Average Switching Frequency Device Type A1415A A14V15A A1425A A14V25A A1440A A14V40A A1440B A1460A A14V60A A1460B A14100A A14V100A A14100B r1 routed_Clk1 60 57 75 72 105 100 105 165 157 165 195 185 195 r2 routed_Clk2 60 57 75 72 105 100 105 165 157 165 195 185 195 To determine the switching frequency for a design, you must have a detailed understanding of the data input values to the circuit. The following guidelines are meant to represent worst-case scenarios so that they can be generally used to predict the upper limits of power dissipation. These guidelines are as follows: Logic Modules (m) Inputs switching (n) Outputs switching (p) First routed array clock loads (q1) 80% of modules # inputs/4 # output/4 40% of sequential modules Second routed array clock loads (q2) = 40% of sequential modules Load capacitance (CL) = 35 pF Average logic module switching rate = F/10 (fm) Average input switching rate (fn) = F/5 Average output switching rate (fp) = F/10 Average first routed array clock rate = F/2 (fq1) Average second routed array clock rate = F/2 (fq2) Average dedicated array clock rate = F (fs1) Average dedicated I/O clock rate (fs2) = F = = = = Fixed Clock Loads (s 1 /s 2 ) Device Type A1415A A14V15A A1425A A14V25A A1440A A14V40A A1440B A1460A A14V60A A1460B A14100A A14V100A A14100B s1 Clock Loads on dedicated array clock 104 104 160 160 288 288 288 432 432 432 697 697 697 s2 Clock Loads on dedicated I/O clock 80 80 100 100 140 140 140 168 168 168 228 228 228 1-192 A c c e l e ra to r S e ri e s F P G A s – A C T ™ 3 F ami l y ACT 3 Timing Model* Input Delays I/O Module tINY = 2.8 ns Internal Delays Combinatorial Logic Module tIRD2 = 1.2 ns Predicted Routing Delays Output Delays I/O Module tDHS = 5.0 ns D Q tPD = 2.0 ns tRD1 = 0.9 ns tRD4 = 1.7 ns tRD8 = 2.8 ns I/O Module tDHS = 5.0 ns tINH = 0.0 ns tINSU = 1.8 ns tICKY = 4.7 ns Sequential Logic Module Combinatorial Logic included in tSUD D Q tRD1 = 0.9 ns D Q tENZHS = 4.0 ns ARRAY CLOCK tHCKH = 3.0 ns FHMAX = 250 MHz tSUD = 0.5 ns tHD = 0.0 ns tCO = 2.0 ns tOUTH = 0.7 ns tOUTSU = 0.7 ns I/O CLOCK tCKHS = 7.5 ns (pad-pad) FIOMAX = 250 MHz *Values shown for A1425A-3. 1-193 Output Buffer Delays E D TRIBUFF PAD To AC test loads (shown below) VCC In Out VOL tDHS, 50% 50% VOH 1.5 V tDHS, GND 1.5 V En Out VCC 50% VCC 50% 1.5 V VOL tENZHS, tENHSZ, GND 10% En Out GND VCC 50% 50% VOH 1.5 V tENZHS, GND 90% tENHSZ, AC Test Loads Load 1 (Used to measure propagation delay) To the output under test Load 2 (Used to measure rising/falling edges) VCC GND 35 pF To the output under test R to VCC for tPLZ/tPZL R to GND for tPHZ/tPZH R = 1 kΩ 35 pF Input Buffer Delays Module Delays PAD INBUF Y S A B VCC Y 3V In Out GND tINY 1.5 V 1.5 V VCC 50% tINY 0V 50% S, A or B Out GND Out 50% 50% VCC 50% tPD 50% tPD tPD GND 50% VCC GND tPD 50% 1-194 A c c e l e ra to r S e ri e s F P G A s – A C T ™ 3 F ami l y Sequential Module Timing Characteristics Flip-Flops D CLK CLR Q (Positive edge triggered) tHD D tSUD CLK tWCLKA tCO Q tCLR CLR tWASYN tWCLKA tA I /O Module: Sequential Input Timing Characteristics D E IOCLK PRE CLR Y (Positive edge triggered) tINH D tINSU IOCLK tIDESU E tICKY Y tICLRY PRE, CLR tIOASPW tIOPWL tIDEH tIOPWH tIOP 1-195 I/O Module: Sequential Output Timing Characteristics D E IOCLK Y PRE CLR Q (Positive edge triggered) tOUTH D tOUTSU IOCLK tODESU E tOCKY Y tCKHS, tCKLS tIOPWH tIOP tIOPWL tODEH Q tOCLRY PRE, CLR tIOASPW 1-196 A c c e l e ra to r S e ri e s F P G A s – A C T ™ 3 F ami l y Predictable Performance: Tightest Delay Distributions Timing Characteristics Propagation delay between logic modules depends on the resistive and capacitive loading of the routing tracks, the interconnect elements, and the module inputs being driven. Propagation delay increases as the length of routing tracks, the number of interconnect elements, or the number of inputs increases. From a design perspective, the propagation delay can be statistically correlated or modeled by the fanout (number of loads) driven by a module. Higher fanout usually requires some paths to have longer lengths of routing track. The ACT 3 family delivers the tightest fanout delay distribution of any FPGA. This tight distribution is achieved in two ways: by decreasing the delay of the interconnect elements and by decreasing the number of interconnect elements per path. Actel’s patented PLICE antifuse offers a very low resistive/capacitive interconnect. The ACT 3 family’s antifuses, fabricated in 0.8 micron m lithography, offer nominal levels of 200Ω resistance and 6 femtofarad (fF) capacitance per antifuse. The ACT 3 fanout distribution is also tighter than alternative devices due to the low number of antifuses required per interconnect path. The ACT 3 family’s proprietary architecture limits the number of antifuses per path to only four, with 90% of interconnects using only two antifuses. The ACT 3 family’s tight fanout delay distribution offers an FPGA design environment in which fanout can be traded for the increased performance of reduced logic level designs. This also simplifies performance estimates when designing with ACT 3 devices. Table 2 • Logic Module and Routing Delay by Fanout (ns) (Worst-Case Commercial Conditions) Speed ACT 3 –3 FO=1 2.9 FO=2 3.2 FO=3 3.4 FO=4 3.7 FO=8 4.8 Timing characteristics for ACT 3 devices fall into three categories: family dependent, device dependent, and design dependent. The input and output buffer characteristics are common to all ACT 3 family members. Internal routing delays are device dependent. Design dependency means actual delays are not determined until after placement and routing of the user’s design is complete. Delay values may then be determined by using the ALS Timer utility or performing simulation with post-layout delays. Critical Nets and Typical Nets Propagation delays are expressed only for typical nets, which are used for initial design performance evaluation. Critical net delays can then be applied to the most time-critical paths. Critical nets are determined by net property assignment prior to placement and routing. Up to 6% of the nets in a design may be designated as critical, while 90% of the nets in a design are typical. Long Tracks Some nets in the design use long tracks. Long tracks are special routing resources that span multiple rows, columns, or modules. Long tracks employ three and sometimes four antifuse connections. This increases capacitance and resistance, resulting in longer net delays for macros connected to long tracks. Typically up to 6% of nets in a fully utilized device require long tracks. Long tracks contribute approximatley 4 ns to 14 ns delay. This additional delay is represented statistically in higher fanout (FO=8) routing delays in the data sheet specifications section. Timing Derating ACT 3 devices are manufactured in a CMOS process. Therefore, device performance varies according to temperature, voltage, and process variations. Minimum timing parameters reflect maximum operating voltage, minimum operating temperature, and best-case processing. Maximum timing parameters reflect minimum operating voltage, maximum operating temperature, and worst-case processing. 1-197 Timing Derating Factor (Temperature and Voltage) Industrial Min. (Commercial Minimum/Maximum Specification) x 0.66 Max. 1.07 Min. 0.63 Military Max. 1.17 Timing Derating Factor for Designs at Typical Temperature (T J = 2 5 ° C) and Voltage (5.0 V) (Commercial Maximum Specification) x 0.85 Temperature and Voltage Deratin g Factors (normalized to Worst-Case Commercial, T J = 4 .75 V, 70 ° C) –55 4.50 4.75 5.00 5.25 5.50 0.72 0.70 0.68 0.66 0.63 –40 0.76 0.73 0.71 0.69 0.66 0 0.85 0.82 0.79 0.77 0.74 25 0.90 0.87 0.84 0.82 0.79 70 1.04 1.00 0.97 0.94 0.90 85 1.07 1.03 1.00 0.97 0.93 125 1.17 1.12 1.09 1.06 1.01 Junction Temperature and Voltage Derating Curves (normalized to Worst-Case Commercial, T J = 4 .75 V, 70 ° C) 1.20 1.10 Derating Factor 1.00 0.90 0.80 0.70 0.60 4.50 4.75 5.00 Voltage (V) Note: This derating factor applies to all routing and propagation dealys. 5.25 5.50 1-198 A c c e l e ra to r S e ri e s F P G A s – A C T ™ 3 F ami l y A1415A, A14V15A Timing Characteristics (Worst-Case Commercial Conditions, V CC = 4 .75 V, T J = 7 0 ° C) 1 Logic Module Propagation Delays2 Parameter tPD tCO tCLR tRD1 tRD2 tRD3 tRD4 tRD8 tSUD tHD tSUD tHD tWASYN tWCLKA tA fMAX Description Internal Array Module Sequential Clock to Q Asynchronous Clear to Q 3 ‘–3’ Speed Min. Max. 2.0 2.0 2.0 ‘–2’ Speed Min. Max. 2.3 2.3 2.3 ‘–1’ Speed Min. Max. 2.6 2.6 2.6 ‘Std’ Speed 3.3V Speed1 Min. Max. 3.0 3.0 3.0 Min. Max. Units 3.9 3.9 3.9 ns ns ns Predicted Routing Delays FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay 0.9 1.2 1.4 1.7 2.8 1.0 1.4 1.6 1.9 3.2 1.1 1.6 1.8 2.2 3.6 1.3 1.8 2.1 2.5 4.2 1.7 2.4 2.8 3.3 5.5 ns ns ns ns ns Logic Module Sequential Timing Flip-Flop Data Input Setup Flip-Flop Data Input Hold Latch Data Input Setup Latch Data Input Hold Asynchronous Pulse Width Flip-Flop Clock Pulse Width Flip-Flop Clock Input Period Flip-Flop Clock Frequency 0.5 0.0 0.5 0.0 1.9 1.9 4.0 250 0.6 0.0 0.6 0.0 2.4 2.4 5.0 200 0.7 0.0 0.7 0.0 3.2 3.2 6.8 150 0.8 0.0 0.8 0.0 3.8 3.8 8.0 125 0.8 0.0 0.8 0.0 4.8 4.8 10.0 100 ns ns ns ns ns ns ns MHz Notes: 1. VCC = 3.0 V for 3.3V specifications. 2. For dual-module macros, use tPD + tRD1 + tPDn , tCO + tRD1 + tPDn or tPD1 + tRD1 + tSUD , whichever is appropriate. 3. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is based on actual routing delay measurements performed on the device prior to shipment. 1-199 A1415A, A14V15A Timing Characteristics ( continued) (Worst-Case Commercial Conditions) I/O Module Input Propagation Delays Parameter tINY tICKY tOCKY tICLRY tOCLRY Description Input Data Pad to Y Input Reg IOCLK Pad to Y Output Reg IOCLK Pad to Y Input Asynchronous Clear to Y Output Asynchronous Clear to Y Delays1 ‘–3’ Speed Min. Max. 2.8 4.7 4.7 4.7 4.7 ‘–2’ Speed Min. Max. 3.2 5.3 5.3 5.3 5.3 ‘–1’ Speed Min. Max. 3.6 6.0 6.0 6.0 6.0 ‘Std’ Speed Min. Max. 4.2 7.0 7.0 7.0 7.0 3.3V Speed Min. Max. Units 5.5 9.2 9.2 9.2 9.2 ns ns ns ns ns Predicted Input Routing tIRD1 tIRD2 tIRD3 tIRD4 tIRD8 FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay 0.9 1.2 1.4 1.7 2.8 1.0 1.4 1.6 1.9 3.2 1.1 1.6 1.8 2.2 3.6 1.3 1.8 2.1 2.5 4.2 1.7 2.4 2.8 3.3 5.5 ns ns ns ns ns I/O Module Sequential Timing tINH tINSU tIDEH tIDESU tOUTH tOUTSU tODEH tODESU Input F-F Data Hold (w.r.t. IOCLK Pad) Input F-F Data Setup (w.r.t. IOCLK Pad) Input Data Enable Hold (w.r.t. IOCLK Pad) Input Data Enable Setup (w.r.t. IOCLK Pad) Output F-F Data Hold (w.r.t. IOCLK Pad) Output F-F Data Setup (w.r.t. IOCLK Pad) Output Data Enable Hold (w.r.t. IOCLK Pad) Output Data Enable Setup (w.r.t. IOCLK Pad) 0.0 2.0 0.0 5.8 0.7 0.7 0.3 1.3 0.0 2.3 0.0 6.5 0.8 0.8 0.4 1.5 0.0 2.5 0.0 7.5 0.9 0.9 0.4 1.7 0.0 3.0 0.0 8.6 1.0 1.0 0.5 2.0 0.0 3.0 0.0 8.6 1.0 1.0 0.5 2.0 ns ns ns ns ns ns ns ns Note: 1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is based on actual routing delay measurements performed on the device prior to shipment. 1-200 A c c e l e ra to r S e ri e s F P G A s – A C T ™ 3 F ami l y A1415A, A14V15A Timing Characteristics ( continued) (Worst-Case Commercial Conditions) I/O Module – TTL Output Timing1 Parameter tDHS tDLS tENZHS tENZLS tENHSZ tENLSZ tCKHS tCKLS dTLHHS dTLHLS dTHLHS dTHLLS tDHS tDLS tENZHS tENZLS tENHSZ tENLSZ tCKHS tCKLS dTLHHS dTLHLS dTHLHS dTHLLS Description Data to Pad, High Slew Data to Pad, Low Slew Enable to Pad, Z to H/L, Hi Slew Enable to Pad, Z to H/L, Lo Slew Enable to Pad, H/L to Z, Hi Slew Enable to Pad, H/L to Z, Lo Slew IOCLK Pad to Pad H/L, Hi Slew IOCLK Pad to Pad H/L, Lo Slew Delta Low to High, Hi Slew Delta Low to High, Lo Slew Delta High to Low, Hi Slew Delta High to Low, Lo Slew 1 ‘–3’ Speed Min. Max. 5.0 8.0 4.0 7.4 6.5 6.5 7.5 11.3 0.02 0.05 0.04 0.05 ‘–2’ Speed Min. Max. 5.6 9.0 4.5 8.3 7.5 7.5 7.5 11.3 0.02 0.05 0.04 0.05 ‘–1’ Speed Min. Max. 6.4 10.2 5.1 9.4 8.5 8.5 9.0 13.5 0.03 0.06 0.04 0.06 ‘Std’ Speed Min. Max. 7.5 12.0 6.0 11.0 10.0 10.0 10.0 15.0 0.03 0.07 0.05 0.07 3.3V Speed Min. Max. Units 9.8 15.6 7.8 14.3 13.0 13.0 13.0 19.5 0.04 0.09 0.07 0.09 ns ns ns ns ns ns ns ns ns/pF ns/pF ns/pF ns/pF I/O Module – CMOS Output Timing Data to Pad, High Slew Data to Pad, Low Slew Enable to Pad, Z to H/L, Hi Slew Enable to Pad, Z to H/L, Lo Slew Enable to Pad, H/L to Z, Hi Slew Enable to Pad, H/L to Z, Lo Slew IOCLK Pad to Pad H/L, Hi Slew IOCLK Pad to Pad H/L, Lo Slew Delta Low to High, Hi Slew Delta Low to High, Lo Slew Delta High to Low, Hi Slew Delta High to Low, Lo Slew 6.2 11.7 5.2 8.9 6.7 6.7 8.9 13.0 0.04 0.07 0.03 0.04 7.0 13.1 5.9 10.0 7.5 7.5 8.9 13.0 0.04 0.08 0.03 0.04 7.9 14.9 6.6 11.3 8.5 9.0 10.7 15.6 0.05 0.09 0.03 0.04 9.3 17.5 7.8 13.3 10.0 10.0 11.8 17.3 0.06 0.11 0.04 0.05 12.1 22.8 10.1 17.3 13.0 13.0 15.3 22.5 0.08 0.14 0.05 0.07 ns ns ns ns ns ns ns ns ns/pF ns/pF ns/pF ns/pF Note: 1. Delays based on 35pF loading. 1-201 A1415A, A14V15A Timing Characteristics ( continued) (Worst-Case Commercial Conditions) Dedicated (Hard-Wired) I/O Clock Network Parameter tIOCKH tIOPWH tIOPWL tIOSAPW tIOCKSW tIOP fIOMAX Description Input Low to High (Pad to I/O Module Input) Minimum Pulse Width High Minimum Pulse Width Low Minimum Asynchronous Pulse Width Maximum Skew Minimum Period Maximum Frequency ‘–3’ Speed Min. Max. 2.0 1.9 1.9 1.9 0.4 4.0 250 ‘–2’ Speed Min. Max. 2.3 2.4 2.4 2.4 0.4 5.0 200 ‘–1’ Speed Min. Max. 2.6 3.3 3.3 3.3 0.4 6.8 150 ‘Std’ Speed Min. Max. 3.0 3.8 3.8 3.8 0.4 8.0 125 3.3V Speed Min. Max. Units 3.5 4.8 4.8 4.8 0.4 10.0 100 ns ns ns ns ns ns MHz Dedicated (Hard-Wired) Array Clock Network tHCKH tHCKL tHPWH tHPWL tHCKSW tHP fHMAX Input Low to High (Pad to S-Module Input) Input High to Low (Pad to S-Module Input) Minimum Pulse Width High Minimum Pulse Width Low Maximum Skew Minimum Period Maximum Frequency 4.0 250 1.9 1.9 0.3 5.0 200 3.0 3.0 2.4 2.4 0.3 6.8 150 3.4 3.4 3.3 3.3 0.3 8.0 125 3.9 3.9 3.8 3.8 0.3 10.0 100 4.5 4.5 4.8 4.8 0.3 5.5 5.5 ns ns ns ns ns ns MHz Routed Array Clock Networks tRCKH tRCKL tRPWH tRPWL tRCKSW tRP fRMAX Input Low to High (FO=64) Input High to Low (FO=64) Min. Pulse Width High (FO=64) Min. Pulse Width Low (FO=64) Maximum Skew (FO=128) Minimum Period (FO=64) Maximum Frequency (FO=64) 6.8 150 3.3 3.3 0.7 8.0 125 3.7 4.0 3.8 3.8 0.8 8.7 115 4.1 4.5 4.2 4.2 0.9 10.0 100 4.7 5.1 4.9 4.9 1.0 13.4 75 5.5 6.0 6.5 6.5 1.0 9.0 9.0 ns ns ns ns ns ns MHz Clock-to-Clock Skews tIOHCKSW tIORCKSW tHRCKSW I/O Clock to H-Clock Skew I/O Clock to R-Clock Skew (FO = 64) H-Clock to R-Clock Skew (FO = 64) (FO = 50% max.) 0.0 0.0 0.0 1.7 1.0 1.0 0.0 0.0 0.0 1.8 1.0 1.0 0.0 0.0 0.0 2.0 1.0 1.0 0.0 0.0 0.0 2.2 1.0 1.0 0.0 0.0 0.0 0.0 3.0 3.0 1.0 3.0 ns ns ns Note: 1. Delays based on 35pF loading. 1-202 A c c e l e ra to r S e ri e s F P G A s – A C T ™ 3 F ami l y A1425A, A14V25A Timing Characteristics ( Worst-Case Commercial Conditions, V CC = 4 .75 V, T J = 7 0 ° C) 1 Logic Module Propagation Delays2 Parameter tPD tCO tCLR Description Internal Array Module Sequential Clock to Q Asynchronous Clear to Q Delays3 ‘–3’ Speed Min. Max. 2.0 2.0 2.0 ‘–2’ Speed Min. Max. 2.3 2.3 2.3 ‘–1’ Speed Min. Max. 2.6 2.6 2.6 ‘Std’ Speed 3.3V Speed1 Min. Max. 3.0 3.0 3.0 Min. Max. Units 3.9 3.9 3.9 ns ns ns Predicted Routing tRD1 tRD2 tRD3 tRD4 tRD8 FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay 0.9 1.2 1.4 1.7 2.8 1.0 1.4 1.6 1.9 3.2 1.1 1.6 1.8 2.2 3.6 1.3 1.8 2.1 2.5 4.2 1.7 2.4 2.8 3.3 5.5 ns ns ns ns ns Logic Module Sequential Timing tSUD tHD tSUD tHD tWASYN tWCLKA tA fMAX Flip-Flop Data Input Setup Flip-Flop Data Input Hold Latch Data Input Setup Latch Data Input Hold Asynchronous Pulse Width Flip-Flop Clock Pulse Width Flip-Flop Clock Input Period Flip-Flop Clock Frequency 0.5 0.0 0.5 0.0 1.9 1.9 4.0 250 0.6 0.0 0.6 0.0 2.4 2.4 5.0 200 0.7 0.0 0.7 0.0 3.2 3.2 6.8 150 0.8 0.0 0.8 0.0 3.8 3.8 8.0 125 0.8 0.0 0.8 0.0 4.8 4.8 10.0 100 ns ns ns ns ns ns ns MHz Notes: 1. VCC = 3.0 V for 3.3V specifications. 2. For dual-module macros, use tPD + tRD1 + tPDn , tCO + tRD1 + tPDn or tPD1 + tRD1 + tSUD , whichever is appropriate. 3. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is based on actual routing delay measurements performed on the device prior to shipment. 1-203 A1425A, A14V25A Timing Characteristics ( continued) (Worst-Case Commercial Conditions) I/O Module Input Propagation Delays Parameter tINY tICKY tOCKY tICLRY tOCLRY Description Input Data Pad to Y Input Reg IOCLK Pad to Y Output Reg IOCLK Pad to Y Input Asynchronous Clear to Y Output Asynchronous Clear to Y Delays1 ‘–3’ Speed Min. Max. 2.8 4.7 4.7 4.7 4.7 ‘–2’ Speed Min. Max. 3.2 5.3 5.3 5.3 5.3 ‘–1’ Speed Min. Max. 3.6 6.0 6.0 6.0 6.0 ‘Std’ Speed Min. Max. 4.2 7.0 7.0 7.0 7.0 3.3V Speed Min. Max. Units 5.5 9.2 9.2 9.2 9.2 ns ns ns ns ns Predicted Input Routing tIRD1 tIRD2 tIRD3 tIRD4 tIRD8 FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay 0.9 1.2 1.4 1.7 2.8 1.0 1.4 1.6 1.9 3.2 1.1 1.6 1.8 2.2 3.6 1.3 1.8 2.1 2.5 4.2 1.7 2.4 2.8 3.3 5.5 ns ns ns ns ns I/O Module Sequential Timing tINH tINSU tIDEH tIDESU tOUTH tOUTSU tODEH tODESU Input F-F Data Hold (w.r.t. IOCLK Pad) Input F-F Data Setup (w.r.t. IOCLK Pad) Input Data Enable Hold (w.r.t. IOCLK Pad) Input Data Enable Setup (w.r.t. IOCLK Pad) Output F-F Data Hold (w.r.t. IOCLK Pad) Output F-F Data Setup (w.r.t. IOCLK Pad) Output Data Enable Hold (w.r.t. IOCLK Pad) Output Data Enable Setup (w.r.t. IOCLK Pad) 0.0 1.8 0.0 5.8 0.7 0.7 0.3 1.3 0.0 2.0 0.0 6.5 0.8 0.8 0.4 1.5 0.0 2.3 0.0 7.5 0.9 0.9 0.4 1.7 0.0 2.7 0.0 8.6 1.0 1.0 0.5 2.0 0.0 3.0 0.0 8.6 1.0 1.0 0.5 2.0 ns ns ns ns ns ns ns ns Note: 1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is based on actual routing delay measurements performed on the device prior to shipment. 1-204 A c c e l e ra to r S e ri e s F P G A s – A C T ™ 3 F ami l y A1425A, A14V25A Timing Characteristics ( continued) (Worst-Case Commercial Conditions) I/O Module – TTL Output Timing1 Parameter tDHS tDLS tENZHS tENZLS tENHSZ tENLSZ tCKHS tCKLS dTLHHS dTLHLS dTHLHS dTHLLS Description Data to Pad, High Slew Data to Pad, Low Slew Enable to Pad, Z to H/L, Hi Slew Enable to Pad, Z to H/L, Lo Slew Enable to Pad, H/L to Z, Hi Slew Enable to Pad, H/L to Z, Lo Slew IOCLK Pad to Pad H/L, Hi Slew IOCLK Pad to Pad H/L, Lo Slew Delta Low to High, Hi Slew Delta Low to High, Lo Slew Delta High to Low, Hi Slew Delta High to Low, Lo Slew Output Timing1 ‘–3’ Speed Min. Max. 5.0 8.0 4.0 7.4 6.5 6.5 7.5 11.3 0.02 0.05 0.04 0.05 ‘–2’ Speed Min. Max. 5.6 9.0 4.5 8.3 7.5 7.5 7.5 11.3 0.02 0.05 0.04 0.05 ‘–1’ Speed Min. Max. 6.4 10.2 5.1 9.4 8.5 8.5 9.0 13.5 0.03 0.06 0.04 0.06 ‘Std’ Speed Min. Max. 7.5 12.0 6.0 11.0 10.0 10.0 10.0 15.0 0.03 0.07 0.05 0.07 3.3V Speed Min. Max. Units 9.8 15.6 7.8 14.3 13.0 13.0 13.0 19.5 0.04 0.09 0.07 0.09 ns ns ns ns ns ns ns ns ns/pF ns/pF ns/pF ns/pF I/O Module – CMOS tDHS tDLS tENZHS tENZLS tENHSZ tENLSZ tCKHS tCKLS dTLHHS dTLHLS dTHLHS dTHLLS Data to Pad, High Slew Data to Pad, Low Slew Enable to Pad, Z to H/L, Hi Slew Enable to Pad, Z to H/L, Lo Slew Enable to Pad, H/L to Z, Hi Slew Enable to Pad, H/L to Z, Lo Slew IOCLK Pad to Pad H/L, Hi Slew IOCLK Pad to Pad H/L, Lo Slew Delta Low to High, Hi Slew Delta Low to High, Lo Slew Delta High to Low, Hi Slew Delta High to Low, Lo Slew 6.2 11.7 5.2 8.9 6.7 6.7 8.9 13.0 0.04 0.07 0.03 0.04 7.0 13.1 5.9 10.0 7.5 7.5 8.9 13.0 0.04 0.08 0.03 0.04 7.9 14.9 6.6 11.3 8.5 9.0 10.7 15.6 0.05 0.09 0.03 0.04 9.3 17.5 7.8 13.3 10.0 10.0 11.8 17.3 0.06 0.11 0.04 0.05 12.1 22.8 10.1 17.3 13.0 13.0 15.3 22.5 0.08 0.14 0.05 0.07 ns ns ns ns ns ns ns ns ns/pF ns/pF ns/pF ns/pF Note: 1. Delays based on 35pF loading. 1-205 A1425A, A14V25A Timing Characteristics ( continued) (Worst-Case Commercial Conditions) Dedicated (Hard-Wired) I/O Clock Network Parameter tIOCKH tIOPWH tIOPWL tIOSAPW tIOCKSW tIOP fIOMAX Description Input Low to High (Pad to I/O Module Input) Minimum Pulse Width High Minimum Pulse Width Low Minimum Asynchronous Pulse Width Maximum Skew Minimum Period Maximum Frequency ‘–3’ Speed Min. Max. 2.0 1.9 1.9 1.9 0.4 4.0 250 ‘–2’ Speed Min. Max. 2.3 2.4 2.4 2.4 0.4 5.0 200 ‘–1’ Speed Min. Max. 2.6 3.3 3.3 3.3 0.4 6.8 150 ‘Std’ Speed Min. Max. 3.0 3.8 3.8 3.8 0.4 8.0 125 3.3V Speed Min. Max. Units 3.5 4.8 4.8 4.8 0.4 10.0 100 ns ns ns ns ns ns MHz Dedicated (Hard-Wired) Array Clock Network tHCKH tHCKL tHPWH tHPWL tHCKSW tHP fHMAX Input Low to High (Pad to S-Module Input) Input High to Low (Pad to S-Module Input) Minimum Pulse Width High Minimum Pulse Width Low Maximum Skew Minimum Period Maximum Frequency 4.0 250 1.9 1.9 0.3 5.0 200 3.0 3.0 2.4 2.4 0.3 6.8 150 3.4 3.4 3.3 3.3 0.3 8.0 125 3.9 3.9 3.8 3.8 0.3 10.0 100 4.5 4.5 4.8 4.8 0.3 5.5 5.5 ns ns ns ns ns ns MHz Routed Array Clock Networks tRCKH tRCKL tRPWH tRPWL tRCKSW tRP fRMAX Input Low to High (FO=64) Input High to Low (FO=64) Min. Pulse Width High (FO=64) Min. Pulse Width Low (FO=64) Maximum Skew (FO=128) Minimum Period (FO=64) Maximum Frequency (FO=64) 6.8 150 3.3 3.3 0.7 8.0 125 3.7 4.0 3.8 3.8 0.8 8.7 115 4.1 4.5 4.2 4.2 0.9 10.0 100 4.7 5.1 4.9 4.9 1.0 13.4 75 5.5 6.0 6.5 6.5 1.0 9.0 9.0 ns ns ns ns ns ns MHz Clock-to-Clock Skews tIOHCKSW tIORCKSW I/O Clock to H-Clock Skew I/O Clock to R-Clock Skew (FO = 64) (FO = 80) H-Clock to R-Clock Skew (FO = 64) (FO = 80) 0.0 0.0 0.0 0.0 0.0 1.7 1.0 3.0 1.0 3.0 0.0 0.0 0.0 0.0 0.0 1.8 1.0 3.0 1.0 3.0 0.0 0.0 0.0 0.0 0.0 2.0 1.0 3.0 1.0 3.0 0.0 0.0 0.0 0.0 0.0 2.2 1.0 3.0 1.0 3.0 0.0 0.0 0.0 0.0 0.0 3.0 3.0 3.0 1.0 3.0 ns ns ns ns ns tHRCKSW Note: 1. Delays based on 35pF loading. 1-206 A c c e l e ra to r S e ri e s F P G A s – A C T ™ 3 F ami l y A1440A, A14V40A Timing Characteristics (Worst-Case Commercial Conditions, V CC = 4 .75 V, T J = 7 0 ° C) 1 Logic Module Propagation Delays2 Parameter tPD tCO tCLR Description Internal Array Module Sequential Clock to Q Asynchronous Clear to Q Delays3 ‘–3’ Speed Min. Max. 2.0 2.0 2.0 ‘–2’ Speed Min. Max. 2.3 2.3 2.3 ‘–1’ Speed Min. Max. 2.6 2.6 2.6 ‘Std’ Speed 3.3V Speed1 Min. Max. 3.0 3.0 3.0 Min. Max. Units 3.9 3.9 3.9 ns ns ns Predicted Routing tRD1 tRD2 tRD3 tRD4 tRD8 FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay 0.9 1.2 1.4 1.7 2.8 1.0 1.4 1.6 1.9 3.2 1.1 1.6 1.8 2.2 3.6 1.3 1.8 2.1 2.5 4.2 1.7 2.4 2.8 3.3 5.5 ns ns ns ns ns Logic Module Sequential Timing tSUD tHD tSUD tHD tWASYN tWCLKA tA fMAX Flip-Flop Data Input Setup Flip-Flop Data Input Hold Latch Data Input Setup Latch Data Input Hold Asynchronous Pulse Width Flip-Flop Clock Pulse Width Flip-Flop Clock Input Period Flip-Flop Clock Frequency 0.5 0.0 0.5 0.0 1.9 1.9 4.0 250 0.6 0.0 0.6 0.0 2.4 2.4 5.0 200 0.7 0.0 0.7 0.0 3.2 3.2 6.8 150 0.8 0.0 0.8 0.0 3.8 3.8 8.0 125 0.8 0.0 0.8 0.0 4.8 4.8 10.0 100 ns ns ns ns ns ns ns MHz Notes: 1. VCC = 3.0 V for 3.3V specifications. 2. For dual-module macros, use tPD + tRD1 + tPDn , tCO + tRD1 + tPDn or tPD1 + tRD1 + tSUD , whichever is appropriate. 3. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is based on actual routing delay measurements performed on the device prior to shipment. 1-207 A1440A, A14V40A Timing Characteristics ( continued) (Worst-Case Commercial Conditions) I/O Module Input Propagation Delays Parameter tINY tICKY tOCKY tICLRY tOCLRY Description Input Data Pad to Y Input Reg IOCLK Pad to Y Output Reg IOCLK Pad to Y Input Asynchronous Clear to Y Output Asynchronous Clear to Y Delays1 ‘–3’ Speed Min. Max. 2.8 4.7 4.7 4.7 4.7 ‘–2’ Speed Min. Max. 3.2 5.3 5.3 5.3 5.3 ‘–1’ Speed Min. Max. 3.6 6.0 6.0 6.0 6.0 ‘Std’ Speed Min. Max. 4.2 7.0 7.0 7.0 7.0 3.3V Speed Min. Max. Units 5.5 9.2 9.2 9.2 9.2 ns ns ns ns ns Predicted Input Routing tIRD1 tIRD2 tIRD3 tIRD4 tIRD8 FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay 0.9 1.2 1.4 1.7 2.8 1.0 1.4 1.6 1.9 3.2 1.1 1.6 1.8 2.2 3.6 1.3 1.8 2.1 2.5 4.2 1.7 2.4 2.8 3.3 5.5 ns ns ns ns ns I/O Module Sequential Timing tINH tINSU tIDEH tIDESU tOUTH tOUTSU tODEH tODESU Input F-F Data Hold (w.r.t. IOCLK Pad) Input F-F Data Setup (w.r.t. IOCLK Pad) Input Data Enable Hold (w.r.t. IOCLK Pad) Input Data Enable Setup (w.r.t. IOCLK Pad) Output F-F Data Hold (w.r.t. IOCLK Pad) Output F-F Data Setup (w.r.t. IOCLK Pad) Output Data Enable Hold (w.r.t. IOCLK Pad) Output Data Enable Setup (w.r.t. IOCLK Pad) 0.0 1.5 0.0 5.8 0.7 0.7 0.3 1.3 0.0 1.7 0.0 6.5 0.8 0.8 0.4 1.5 0.0 2.0 0.0 7.5 0.9 0.9 0.4 1.7 0.0 2.3 0.0 8.6 1.0 1.0 0.5 2.0 0.0 2.3 0.0 8.6 1.0 1.0 0.5 2.0 ns ns ns ns ns ns ns ns Note: 1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is based on actual routing delay measurements performed on the device prior to shipment. 1-208 A c c e l e ra to r S e ri e s F P G A s – A C T ™ 3 F ami l y A1440A, A14V40A Timing Characteristics ( continued) (Worst-Case Commercial Conditions) I/O Module – TTL Output Timing1 Parameter tDHS tDLS tENZHS tENZLS tENHSZ tENLSZ tCKHS tCKLS dTLHHS dTLHLS dTHLHS dTHLLS Description Data to Pad, High Slew Data to Pad, Low Slew Enable to Pad, Z to H/L, Hi Slew Enable to Pad, Z to H/L, Lo Slew Enable to Pad, H/L to Z, Hi Slew Enable to Pad, H/L to Z, Lo Slew IOCLK Pad to Pad H/L, Hi Slew IOCLK Pad to Pad H/L, Lo Slew Delta Low to High, Hi Slew Delta Low to High, Lo Slew Delta High to Low, Hi Slew Delta High to Low, Lo Slew Output Timing1 ‘–3’ Speed Min. Max. 5.0 8.0 4.0 7.4 7.4 7.4 8.5 11.3 0.02 0.05 0.04 0.05 ‘–2’ Speed Min. Max. 5.6 9.0 4.5 8.3 8.3 8.3 8.5 11.3 0.02 0.05 0.04 0.05 ‘–1’ Speed Min. Max. 6.4 10.2 5.1 9.4 9.4 9.4 9.5 13.5 0.03 0.06 0.04 0.06 ‘Std’ Speed Min. Max. 7.5 12.0 6.0 11.0 11.0 11.0 11.0 15.0 0.03 0.07 0.05 0.07 3.3V Speed Min. Max. Units 9.8 15.6 7.8 14.3 14.3 14.3 14.3 19.5 0.04 0.09 0.07 0.09 ns ns ns ns ns ns ns ns ns/pF ns/pF ns/pF ns/pF I/O Module – CMOS tDHS tDLS tENZHS tENZLS tENHSZ tENLSZ tCKHS tCKLS dTLHHS dTLHLS dTHLHS dTHLLS Data to Pad, High Slew Data to Pad, Low Slew Enable to Pad, Z to H/L, Hi Slew Enable to Pad, Z to H/L, Lo Slew Enable to Pad, H/L to Z, Hi Slew Enable to Pad, H/L to Z, Lo Slew IOCLK Pad to Pad H/L, Hi Slew IOCLK Pad to Pad H/L, Lo Slew Delta Low to High, Hi Slew Delta Low to High, Lo Slew Delta High to Low, Hi Slew Delta High to Low, Lo Slew 6.2 11.7 5.2 8.9 7.4 7.4 9.0 13.0 0.04 0.07 0.03 0.04 7.0 13.1 5.9 10.0 8.3 8.3 9.0 13.0 0.04 0.08 0.03 0.04 7.9 14.9 6.6 11.3 9.4 9.4 10.1 15.6 0.05 0.09 0.03 0.04 9.3 17.5 7.8 13.3 11.0 11.0 11.8 17.3 0.06 0.11 0.04 0.05 12.1 22.8 10.1 17.3 14.3 14.3 14.3 22.5 0.08 0.14 0.05 0.07 ns ns ns ns ns ns ns ns ns/pF ns/pF ns/pF ns/pF Note: 1. Delays based on 35pF loading. 1-209 A1440A, A14V40A Timing Characteristics ( continued) (Worst-Case Commercial Conditions) Dedicated (Hard-Wired) I/O Clock Network Parameter tIOCKH tIOPWH tIOPWL tIOSAPW tIOCKSW tIOP fIOMAX Description Input Low to High (Pad to I/O Module Input) Minimum Pulse Width High Minimum Pulse Width Low Minimum Asynchronous Pulse Width Maximum Skew Minimum Period Maximum Frequency ‘–3’ Speed Min. Max. 2.0 1.9 1.9 1.9 0.4 4.0 250 ‘–2’ Speed Min. Max. 2.3 2.4 2.4 2.4 0.4 5.0 200 ‘–1’ Speed Min. Max. 2.6 3.3 3.3 3.3 0.4 6.8 150 ‘Std’ Speed Min. Max. 3.0 3.8 3.8 3.8 0.4 8.0 125 3.3V Speed Min. Max. Units 3.5 4.8 4.8 4.8 0.4 10.0 100 ns ns ns ns ns ns MHz Dedicated (Hard-Wired) Array Clock Network tHCKH tHCKL tHPWH tHPWL tHCKSW tHP fHMAX Input Low to High (Pad to S-Module Input) Input High to Low (Pad to S-Module Input) Minimum Pulse Width High Minimum Pulse Width Low Maximum Skew Minimum Period Maximum Frequency 4.0 250 1.9 1.9 0.3 5.0 200 3.0 3.0 2.4 2.4 0.3 6.8 150 3.4 3.4 3.3 3.3 0.3 8.0 125 3.9 3.9 3.8 3.8 0.3 10.0 100 4.5 4.5 4.8 4.8 0.3 5.5 5.5 ns ns ns ns ns ns MHz Routed Array Clock Networks tRCKH tRCKL tRPWH tRPWL tRCKSW tRP fRMAX Input Low to High (FO=64) Input High to Low (FO=64) Min. Pulse Width High (FO=64) Min. Pulse Width Low (FO=64) Maximum Skew (FO=128) Minimum Period (FO=64) Maximum Frequency (FO=64) 6.8 150 3.3 3.3 0.7 8.0 125 3.7 4.0 3.8 3.8 0.8 8.7 115 4.1 4.5 4.2 4.2 0.9 10.0 100 4.7 5.1 4.9 4.9 1.0 13.4 75 5.5 6.0 6.5 6.5 1.0 9.0 9.0 ns ns ns ns ns ns MHz Clock-to-Clock Skews tIOHCKSW tIORCKSW I/O Clock to H-Clock Skew I/O Clock to R-Clock Skew (FO = 64) (FO = 144) H-Clock to R-Clock Skew (FO = 64) (FO = 144) 0.0 0.0 0.0 0.0 0.0 1.7 1.0 3.0 1.0 3.0 0.0 0.0 0.0 0.0 0.0 1.8 1.0 3.0 1.0 3.0 0.0 0.0 0.0 0.0 0.0 2.0 1.0 3.0 1.0 3.0 0.0 0.0 0.0 0.0 0.0 2.2 1.0 3.0 1.0 3.0 0.0 0.0 0.0 0.0 0.0 3.0 3.0 3.0 1.0 3.0 ns ns ns ns ns tHRCKSW Note: 1. Delays based on 35pF loading. 1-210 A c c e l e ra to r S e ri e s F P G A s – A C T ™ 3 F ami l y A1460A, A14V60A Timing Characteristics (Worst-Case Commercial Conditions, V CC = 4 .75 V, T J = 7 0 ° C) 1 Logic Module Propagation Delays2 Parameter tPD tCO tCLR Description Internal Array Module Sequential Clock to Q Asynchronous Clear to Q Delays3 ‘–3’ Speed Min. Max. 2.0 2.0 2.0 ‘–2’ Speed Min. Max. 2.3 2.3 2.3 ‘–1’ Speed Min. Max. 2.6 2.6 2.6 ‘Std’ Speed 3.3V Speed1 Min. Max. 3.0 3.0 3.0 Min. Max. Units 3.9 3.9 3.9 ns ns ns Predicted Routing tRD1 tRD2 tRD3 tRD4 tRD8 FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay 0.9 1.2 1.4 1.7 2.8 1.0 1.4 1.6 1.9 3.2 1.1 1.6 1.8 2.2 3.6 1.3 1.8 2.1 2.5 4.2 1.7 2.4 2.8 3.3 5.5 ns ns ns ns ns Logic Module Sequential Timing tSUD tHD tSUD tHD tWASYN tWCLKA tA fMAX Flip-Flop Data Input Setup Flip-Flop Data Input Hold Latch Data Input Setup Latch Data Input Hold Asynchronous Pulse Width Flip-Flop Clock Pulse Width Flip-Flop Clock Input Period Flip-Flop Clock Frequency 0.5 0.0 0.5 0.0 2.4 2.4 5.0 200 0.6 0.0 0.6 0.0 3.2 3.2 6.8 150 0.7 0.0 0.7 0.0 3.8 3.8 8.0 125 0.8 0.0 0.8 0.0 4.8 4.8 10.0 100 0.8 0.0 0.8 0.0 6.5 6.5 13.4 75 ns ns ns ns ns ns ns MHz Notes: 1. VCC = 3.0 V for 3.3V specifications. 2. For dual-module macros, use tPD + tRD1 + tPDn , tCO + tRD1 + tPDn or tPD1 + tRD1 + tSUD , whichever is appropriate. 3. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is based on actual routing delay measurements performed on the device prior to shipment. 1-211 A1460A, A14V60A Timing Characteristics ( continued) (Worst-Case Commercial Conditions) I/O Module Input Propagation Delays Parameter tINY tICKY tOCKY tICLRY tOCLRY Description Input Data Pad to Y Input Reg IOCLK Pad to Y Output Reg IOCLK Pad to Y Input Asynchronous Clear to Y Output Asynchronous Clear to Y Delays1 ‘–3’ Speed Min. Max. 2.8 4.7 4.7 4.7 4.7 ‘–2’ Speed Min. Max. 3.2 5.3 5.3 5.3 5.3 ‘–1’ Speed Min. Max. 3.6 6.0 6.0 6.0 6.0 ‘Std’ Speed Min. Max. 4.2 7.0 7.0 7.0 7.0 3.3V Speed Min. Max. Units 5.5 9.2 9.2 9.2 9.2 ns ns ns ns ns Predicted Input Routing tIRD1 tIRD2 tIRD3 tIRD4 tIRD8 FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay 0.9 1.2 1.4 1.7 2.8 1.0 1.4 1.6 1.9 3.2 1.1 1.6 1.8 2.2 3.6 1.3 1.8 2.1 2.5 4.2 1.7 2.4 2.8 3.3 5.5 ns ns ns ns ns I/O Module Sequential Timing tINH tINSU tIDEH tIDESU tOUTH tOUTSU tODEH tODESU Input F-F Data Hold (w.r.t. IOCLK Pad) Input F-F Data Setup (w.r.t. IOCLK Pad) Input Data Enable Hold (w.r.t. IOCLK Pad) Input Data Enable Setup (w.r.t. IOCLK Pad) Output F-F Data Hold (w.r.t. IOCLK Pad) Output F-F Data Setup (w.r.t. IOCLK Pad) Output Data Enable Hold (w.r.t. IOCLK Pad) Output Data Enable Setup (w.r.t. IOCLK Pad) 0.0 1.3 0.0 5.8 0.7 0.7 0.3 1.3 0.0 1.5 0.0 6.5 0.8 0.8 0.4 1.5 0.0 1.8 0.0 7.5 0.9 0.9 0.4 1.7 0.0 2.0 0.0 8.6 1.0 1.0 0.5 2.0 0.0 2.0 0.0 8.6 1.0 1.0 0.5 2.0 ns ns ns ns ns ns ns ns Note: 1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is based on actual routing delay measurements performed on the device prior to shipment. 1-212 A c c e l e ra to r S e ri e s F P G A s – A C T ™ 3 F ami l y A1460A, A14V60A Timing Characteristics ( continued) (Worst-Case Commercial Conditions) I/O Module – TTL Output Timing1 Parameter tDHS tDLS tENZHS tENZLS tENHSZ tENLSZ tCKHS tCKLS dTLHHS dTLHLS dTHLHS dTHLLS Description Data to Pad, High Slew Data to Pad, Low Slew Enable to Pad, Z to H/L, Hi Slew Enable to Pad, Z to H/L, Lo Slew Enable to Pad, H/L to Z, Hi Slew Enable to Pad, H/L to Z, Lo Slew IOCLK Pad to Pad H/L, Hi Slew IOCLK Pad to Pad H/L, Lo Slew Delta Low to High, Hi Slew Delta Low to High, Lo Slew Delta High to Low, Hi Slew Delta High to Low, Lo Slew Output Timing1 ‘–3’ Speed Min. Max. 5.0 8.0 4.0 7.4 7.8 7.4 9.0 12.8 0.02 0.05 0.04 0.05 ‘–2’ Speed Min. Max. 5.6 9.0 4.5 8.3 8.7 8.3 9.0 12.8 0.02 0.05 0.04 0.05 ‘–1’ Speed Min. Max. 6.4 10.2 5.1 9.4 9.9 9.4 10.0 15.3 0.03 0.06 0.04 0.06 ‘Std’ Speed Min. Max. 7.5 12.0 6.0 11.0 11.6 11.0 11.5 17.0 0.03 0.07 0.05 0.07 3.3V Speed Min. Max. Units 9.8 15.6 7.8 14.3 15.1 14.3 15.0 22.1 0.04 0.09 0.07 0.09 ns ns ns ns ns ns ns ns ns/pF ns/pF ns/pF ns/pF I/O Module – CMOS tDHS tDLS tENZHS tENZLS tENHSZ tENLSZ tCKHS tCKLS dTLHHS dTLHLS dTHLHS dTHLLS Data to Pad, High Slew Data to Pad, Low Slew Enable to Pad, Z to H/L, Hi Slew Enable to Pad, Z to H/L, Lo Slew Enable to Pad, H/L to Z, Hi Slew Enable to Pad, H/L to Z, Lo Slew IOCLK Pad to Pad H/L, Hi Slew IOCLK Pad to Pad H/L, Lo Slew Delta Low to High, Hi Slew Delta Low to High, Lo Slew Delta High to Low, Hi Slew Delta High to Low, Lo Slew 6.2 11.7 5.2 8.9 7.4 7.4 10.4 14.5 0.04 0.07 0.03 0.04 7.0 13.1 5.9 10.0 8.3 8.3 10.4 14.5 0.04 0.08 0.03 0.04 7.9 14.9 6.6 11.3 9.4 9.4 12.1 17.4 0.05 0.09 0.03 0.04 9.3 17.5 7.8 13.3 11.0 11.0 13.8 19.3 0.06 0.11 0.04 0.05 12.1 22.8 10.1 17.3 14.3 14.3 17.9 25.1 0.08 0.14 0.05 0.07 ns ns ns ns ns ns ns ns ns/pF ns/pF ns/pF ns/pF Note: 1. Delays based on 35pF loading. 1-213 A1460A, A14V60A Timing Characteristics ( continued) (Worst-Case Commercial Conditions) Dedicated (Hard-Wired) I/O Clock Network Parameter tIOCKH tIOPWH tIOPWL tIOSAPW tIOCKSW tIOP fIOMAX Description Input Low to High (Pad to I/O Module Input) Minimum Pulse Width High Minimum Pulse Width Low Minimum Asynchronous Pulse Width Maximum Skew Minimum Period Maximum Frequency ‘–3’ Speed Min. Max. 2.3 2.4 2.4 2.4 0.6 5.0 200 ‘–2’ Speed Min. Max. 2.6 3.2 3.2 3.2 0.6 6.8 150 ‘–1’ Speed Min. Max. 3.0 3.8 3.8 3.8 0.6 8.0 125 ‘Std’ Speed Min. Max. 3.5 4.8 4.8 4.8 0.6 10.0 100 3.3V Speed Min. Max. Units 4.5 6.5 6.5 6.5 0.6 13.4 75 ns ns ns ns ns ns MHz Dedicated (Hard-Wired) Array Clock Network tHCKH tHCKL tHPWH tHPWL tHCKSW tHP fHMAX Input Low to High (Pad to S-Module Input) Input High to Low (Pad to S-Module Input) Minimum Pulse Width High Minimum Pulse Width Low Maximum Skew Minimum Period Maximum Frequency 5.0 200 2.4 2.4 0.6 6.8 150 3.7 3.7 3.2 3.2 0.6 8.0 125 4.1 4.1 3.8 3.8 0.6 10.0 100 4.7 4.7 4.8 4.8 0.6 13.4 75 5.5 5.5 6.5 6.5 0.6 7.0 7.0 ns ns ns ns ns ns MHz Routed Array Clock Networks tRCKH tRCKL tRPWH tRPWL tRCKSW tRP fRMAX Input Low to High (FO=256) Input High to Low (FO=256) Min. Pulse Width High (FO=256) Min. Pulse Width Low (FO=256) Maximum Skew (FO=128) Minimum Period (FO=256) Maximum Frequency (FO=256) 8.3 120 4.1 4.1 1.2 9.3 105 6.0 6.0 4.5 4.5 1.4 11.1 90 6.8 6.8 5.4 5.4 1.6 12.5 80 7.7 7.7 6.1 6.1 1.8 16.7 60 9.0 9.0 8.2 8.2 1.8 11.8 11.8 ns ns ns ns ns ns MHz Clock-to-Clock Skews tIOHCKSW tIORCKSW I/O Clock to H-Clock Skew I/O Clock to R-Clock Skew (FO = 64) (FO = 216) H-Clock to R-Clock Skew (FO = 64) (FO = 216) 0.0 0.0 0.0 0.0 0.0 2.6 1.7 5.0 1.3 3.0 0.0 0.0 0.0 0.0 0.0 2.7 1.7 5.0 1.0 3.0 0.0 0.0 0.0 0.0 0.0 2.9 1.7 5.0 1.0 3.0 0.0 0.0 0.0 0.0 0.0 3.0 1.7 5.0 1.0 3.0 0.0 0.0 0.0 0.0 0.0 3.0 5.0 5.0 1.0 3.0 ns ns ns ns ns tHRCKSW Note: 1. Delays based on 35pF loading. 1-214 A c c e l e ra to r S e ri e s F P G A s – A C T ™ 3 F ami l y A14100A, A14V100A Timing Characteristics (Worst-Case Commercial Conditions, V CC = 4 .75 V, T J = 7 0 ° C) 1 Logic Module Propagation Delays2 Parameter tPD tCO tCLR Description Internal Array Module Sequential Clock to Q Asynchronous Clear to Q Delays3 ‘–3’ Speed Min. Max. 2.0 2.0 2.0 ‘–2’ Speed Min. Max. 2.3 2.3 2.3 ‘–1’ Speed Min. Max. 2.6 2.6 2.6 ‘Std’ Speed 3.3V Speed1 Min. Max. 3.0 3.0 3.0 Min. Max. Units 3.9 3.9 3.9 ns ns ns Predicted Routing tRD1 tRD2 tRD3 tRD4 tRD8 FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay 0.9 1.2 1.4 1.7 2.8 1.0 1.4 1.6 1.9 3.2 1.1 1.6 1.8 2.2 3.6 1.3 1.8 2.1 2.5 4.2 1.7 2.4 2.8 3.3 5.5 ns ns ns ns ns Logic Module Sequential Timing tSUD tHD tSUD tHD tWASYN tWCLKA tA fMAX Flip-Flop Data Input Setup Flip-Flop Data Input Hold Latch Data Input Setup Latch Data Input Hold Asynchronous Pulse Width Flip-Flop Clock Pulse Width Flip-Flop Clock Input Period Flip-Flop Clock Frequency 0.5 0.0 0.5 0.0 2.4 2.4 5.0 200 0.6 0.0 0.6 0.0 3.2 3.2 6.8 150 0.8 0.5 0.8 0.5 3.8 3.8 8.0 125 0.8 0.5 0.8 0.5 4.8 4.8 10.0 100 0.8 0.5 0.8 0.5 6.5 6.5 13.4 75 ns ns ns ns ns ns ns MHz Notes: 1. VCC = 3.0 V for 3.3V specifications. 2. For dual-module macros, use tPD + tRD1 + tPDn , tCO + tRD1 + tPDn or tPD1 + tRD1 + tSUD , whichever is appropriate. 3. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is based on actual routing delay measurements performed on the device prior to shipment. 1-215 A14100A, A14V100A Timing Characteristics ( continued) (Worst-Case Commercial Conditions) I/O Module Input Propagation Delays Parameter tINY tICKY tOCKY tICLRY tOCLRY Description Input Data Pad to Y Input Reg IOCLK Pad to Y Output Reg IOCLK Pad to Y Input Asynchronous Clear to Y Output Asynchronous Clear to Y Delays1 ‘–3’ Speed Min. Max. 2.8 4.7 4.7 4.7 4.7 ‘–2’ Speed Min. Max. 3.2 5.3 5.3 5.3 5.3 ‘–1’ Speed Min. Max. 3.6 6.0 6.0 6.0 6.0 ‘Std’ Speed Min. Max. 4.2 7.0 7.0 7.0 7.0 3.3V Speed Min. Max. Units 5.5 9.2 9.2 9.2 9.2 ns ns ns ns ns Predicted Input Routing tIRD1 tIRD2 tIRD3 tIRD4 tIRD8 FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay 0.9 1.2 1.4 1.7 2.8 1.0 1.4 1.6 1.9 3.2 1.1 1.6 1.8 2.2 3.6 1.3 1.8 2.1 2.5 4.2 1.7 2.4 2.8 3.3 5.5 ns ns ns ns ns I/O Module Sequential Timing tINH tINSU tIDEH tIDESU tOUTH tOUTSU tODEH tODESU Input F-F Data Hold (w.r.t. IOCLK Pad) Input F-F Data Setup (w.r.t. IOCLK Pad) Input Data Enable Hold (w.r.t. IOCLK Pad) Input Data Enable Setup (w.r.t. IOCLK Pad) Output F-F Data Hold (w.r.t. IOCLK Pad) Output F-F Data Setup (w.r.t. IOCLK Pad) Output Data Enable Hold (w.r.t. IOCLK Pad) Output Data Enable Setup (w.r.t. IOCLK Pad) 0.0 1.2 0.0 5.8 0.7 0.7 0.3 1.3 0.0 1.4 0.0 6.5 0.8 0.8 0.4 1.5 0.0 1.5 0.0 7.5 1.0 1.0 0.5 2.0 0.0 1.8 0.0 8.6 1.0 1.0 0.5 2.0 0.0 1.8 0.0 8.6 1.0 1.0 0.5 2.0 ns ns ns ns ns ns ns ns Note: 1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is based on actual routing delay measurements performed on the device prior to shipment. 1-216 A c c e l e ra to r S e ri e s F P G A s – A C T ™ 3 F ami l y A14100A, A14V100A Timing Characteristics ( continued) (Worst-Case Commercial Conditions ) I/O Module – TTL Output Timing1 Parameter tDHS tDLS tENZHS tENZLS tENHSZ tENLSZ tCKHS tCKLS dTLHHS dTLHLS dTHLHS dTHLLS Description Data to Pad, High Slew Data to Pad, Low Slew Enable to Pad, Z to H/L, Hi Slew Enable to Pad, Z to H/L, Lo Slew Enable to Pad, H/L to Z, Hi Slew Enable to Pad, H/L to Z, Lo Slew IOCLK Pad to Pad H/L, Hi Slew IOCLK Pad to Pad H/L, Lo Slew Delta Low to High, Hi Slew Delta Low to High, Lo Slew Delta High to Low, Hi Slew Delta High to Low, Lo Slew Output Timing1 ‘–3’ Speed Min. Max. 5.0 8.0 4.0 7.4 8.0 7.4 9.5 12.8 0.02 0.05 0.04 0.05 ‘–2’ Speed Min. Max. 5.6 9.0 4.5 8.3 9.0 8.3 9.5 12.8 0.02 0.05 0.04 0.05 ‘–1’ Speed Min. Max. 6.4 10.2 5.1 9.4 10.2 9.4 10.5 15.3 0.03 0.06 0.04 0.06 ‘Std’ Speed Min. Max. 7.5 12.0 6.0 11.0 12.0 11.0 12.0 17.0 0.03 0.07 0.05 0.07 3.3V Speed Min. Max. Units 9.8 15.6 7.8 14.3 15.6 14.3 15.6 22.1 0.04 0.09 0.07 0.09 ns ns ns ns ns ns ns ns ns/pF ns/pF ns/pF ns/pF I/O Module – CMOS tDHS tDLS tENZHS tENZLS tENHSZ tENLSZ tCKHS tCKLS dTLHHS dTLHLS dTHLHS dTHLLS Data to Pad, High Slew Data to Pad, Low Slew Enable to Pad, Z to H/L, Hi Slew Enable to Pad, Z to H/L, Lo Slew Enable to Pad, H/L to Z, Hi Slew Enable to Pad, H/L to Z, Lo Slew IOCLK Pad to Pad H/L, Hi Slew IOCLK Pad to Pad H/L, Lo Slew Delta Low to High, Hi Slew Delta Low to High, Lo Slew Delta High to Low, Hi Slew Delta High to Low, Lo Slew 6.2 11.7 5.2 8.9 8.0 7.4 10.4 14.5 0.04 0.07 0.03 0.04 7.0 13.1 5.9 10.0 9.0 8.3 10.4 14.5 0.04 0.08 0.03 0.04 7.9 14.9 6.6 11.3 10.0 9.4 12.4 17.4 0.05 0.09 0.03 0.04 9.3 17.5 7.8 13.3 12.0 11.0 13.8 19.3 0.06 0.11 0.04 0.05 12.1 22.8 10.1 17.3 15.6 14.3 17.9 25.1 0.08 0.14 0.05 0.07 ns ns ns ns ns ns ns ns ns/pF ns/pF ns/pF ns/pF Note: 1. Delays based on 35pF loading. 1-217 A14100A, A14V100A Timing Characteristics ( continued) (Worst-Case Commercial Conditions) Dedicated (Hard-Wired) I/O Clock Network Parameter tIOCKH tIOPWH tIOPWL tIOSAPW tIOCKSW tIOP fIOMAX Description Input Low to High (Pad to I/O Module Input) Minimum Pulse Width High Minimum Pulse Width Low Minimum Asynchronous Pulse Width Maximum Skew Minimum Period Maximum Frequency ‘–3’ Speed Min. Max. 2.3 2.4 2.4 2.4 0.6 5.0 200 ‘–2’ Speed Min. Max. 2.6 3.3 3.3 3.3 0.6 6.8 150 ‘–1’ Speed Min. Max. 3.0 3.8 3.8 3.8 0.7 8.0 125 ‘Std’ Speed Min. Max. 3.5 4.8 4.8 4.8 0.8 10.0 100 3.3V Speed Min. Max. Units 4.5 6.5 6.5 6.5 0.6 13.4 75 ns ns ns ns ns ns MHz Dedicated (Hard-Wired) Array Clock Network tHCKH tHCKL tHPWH tHPWL tHCKSW tHP fHMAX Input Low to High (Pad to S-Module Input) Input High to Low (Pad to S-Module Input) Minimum Pulse Width High Minimum Pulse Width Low Maximum Skew Minimum Period Maximum Frequency 5.0 200 2.4 2.4 0.6 6.8 150 3.7 3.7 3.3 3.3 0.6 8.0 125 4.1 4.1 3.8 3.8 0.7 10.0 100 4.7 4.7 4.8 4.8 0.8 13.4 75 5.5 5.5 6.5 6.5 0.6 7.0 7.0 ns ns ns ns ns ns MHz Routed Array Clock Networks tRCKH tRCKL tRPWH tRPWL tRCKSW tRP fRMAX Input Low to High (FO=256) Input High to Low (FO=256) Min. Pulse Width High (FO=256) Min. Pulse Width Low (FO=256) Maximum Skew (FO=128) Minimum Period (FO=256) Maximum Frequency (FO=256) 8.3 120 4.1 4.1 1..2 9.3 105 6.0 6.0 4.5 4.5 1.4 11.1 90 6.8 6.8 5.4 5.4 1.6 12.5 80 7.7 7.7 6.1 6.1 1.8 16.7 60 9.0 9.0 8.2 8.2 1.8 11.8 11.8 ns ns ns ns ns ns MHz Clock-to-Clock Skews tIOHCKSW tIORCKSW I/O Clock to H-Clock Skew I/O Clock to R-Clock Skew (FO = 64) (FO = 350) H-Clock to R-Clock Skew (FO = 64) (FO = 350) 0.0 0.0 0.0 0.0 0.0 2.6 1.7 5.0 1.3 3.0 0.0 0.0 0.0 0.0 0.0 2.7 17 5.0 1.0 3.0 0.0 0.0 0.0 0.0 0.0 2.9 1.7 5.0 1.0 3.0 0.0 0.0 0.0 0.0 0.0 3.0 1.7 5.0 1.0 3.0 0.0 0.0 0.0 0.0 0.0 3.0 5.0 5.0 1.0 3.0 ns ns tHRCKSW ns Note: 1. Delays based on 35pF loading. 1-218 A c c e l e ra to r S e ri e s F P G A s – A C T ™ 3 F ami l y Package Pin Assignments 100-Pin PQFP (Top View) 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 81 50 82 49 83 48 84 47 85 46 86 45 87 44 88 43 89 42 100-Pin 90 41 PQFP 91 40 92 39 93 38 94 37 95 36 96 35 97 34 98 33 99 32 100 31 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Pin Number 2 14 15 16 17 18 19 20 27 28 29 34 35 36 47 A1415 Function IOCLK, I/O CLKA, I/O CLKB, I/O VCC GND VCC GND PRA, I/O DCLK, I/O GND SDI, I/O MODE VCC GND GND A1425 Function IOCLK, I/O CLKA, I/O CLKB, I/O VCC GND VCC GND PRA, I/O DCLK, I/O GND SDI, I/O MODE VCC GND GND Pin Number 48 61 62 63 64 65 67 78 79 85 86 87 96 97 A1415 Function VCC PRB, I/O GND VCC GND VCC HCLK, I/O IOPCL, I/O GND VCC VCC GND VCC GND A1425 Function VCC PRB, I/O GND VCC GND VCC HCLK, I/O IOPCL, I/O GND VCC VCC GND VCC GND Notes: 1. All unlisted pin numbers are user I/Os. 2. NC : Denotes No Connection 3. MODE should be terminated to GND through a 10K resistor to enable Actionprobe usage; otherwise it can be terminated directly to GND. 1-219 Package Pin Assignments ( continued) 8 4-Pin PLCC (Top View) 11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 74 73 72 71 70 69 68 67 66 84-Pin PLCC 65 64 63 62 61 60 59 58 57 56 55 54 1-220 A c c e l e ra to r S e ri e s F P G A s – A C T ™ 3 F ami l y 84-Pin PLCC Pin Number 1 2 3 4 11 12 16 27 28 40 41 42 43 45 53 59 60 61 68 69 74 83 84 A1415 A14V15 Function VCC GND VCC PRA, I/O DCLK, I/O SDI, I/O MODE GND VCC PRB, I/O VCC GND VCC HCLK, I/O IOPCL, I/O VCC VCC GND VCC GND IOCLK, I/O CLKA, I/O CLKB, I/O A1425 A14V25 Function VCC GND VCC PRA, I/O DCLK, I/O SDI, I/O MODE GND VCC PRB, I/O VCC GND VCC HCLK, I/O IOPCL, I/O VCC VCC GND VCC GND IOCLK, I/O CLKA, I/O CLKB, I/O A1440 A14V40 Function VCC GND VCC PRA, I/O DCLK, I/O SDI, I/O MODE GND VCC PRB, I/O VCC GND VCC HCLK, I/O IOPCL, I/O VCC VCC GND VCC GND IOCLK, I/O CLKA, I/O CLKB, I/O Notes: 1. All unlisted pin numbers are user I/Os. 2. NC : Denotes No Connection 3. MODE should be terminated to GND through a 10K resistor to enable Actionprobe usage; otherwise it can be terminated directly to GND. 1-221 Package Pin Assignments ( continued) 160-Pin PQFP (Top View) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 160-Pin PQFP 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1-222 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 A c c e l e ra to r S e ri e s F P G A s – A C T ™ 3 F ami l y 160-Pin PQFP Pin Number 1 2 5 9 10 14 15 18 19 20 24 27 28 29 40 41 43 45 46 47 49 51 53 58 59 60 62 63 74 75 76 77 78 80 81 A1425 A14V25 Function GND SDI, I/O NC MODE VCC NC GND VCC GND NC NC NC VCC VCC GND NC NC NC VCC NC NC NC NC PRB, I/O GND VCC HCLK, I/O GND NC VCC NC NC NC IOPCL, I/O GND A1440 A14V40 Function GND SDI, I/O I/O MODE VCC I/O GND VCC GND I/O I/O I/O VCC VCC GND I/O I/O I/O VCC I/O I/O I/O I/O PRB, I/O GND VCC HCLK, I/O GND I/O VCC I/O I/O I/O IOPCL, I/O GND A1460 A14V60 Function GND SDI, I/O I/O MODE VCC I/O GND VCC GND I/O I/O I/O VCC VCC GND I/O I/O I/O VCC I/O I/O I/O I/O PRB, I/O GND VCC HCLK, I/O GND I/O VCC I/O I/O I/O IOPCL, I/O GND Pin Number 90 91 92 93 98 99 100 103 107 109 110 111 112 113 119 120 121 124 127 136 137 138 139 140 141 142 143 145 147 149 151 153 154 160 A1425 A14V25 Function VCC VCC NC NC GND VCC NC GND NC NC VCC GND VCC NC NC IOCLK, I/O GND NC NC CLKA, I/O CLKB, I/O VCC GND VCC GND PRA, I/O NC NC NC NC NC NC VCC DCLK, I/O A1440 A14V40 Function VCC VCC I/O I/O GND VCC I/O GND I/O I/O VCC GND VCC I/O I/O IOCLK, I/O GND I/O I/O CLKA, I/O CLKB, I/O VCC GND VCC GND PRA, I/O I/O I/O I/O I/O I/O I/O VCC DCLK, I/O A1460 A14V60 Function VCC VCC I/O I/O GND VCC I/O GND I/O I/O VCC GND VCC I/O I/O IOCLK, I/O GND I/O I/O CLKA, I/O CLKB, I/O VCC GND VCC GND PRA, I/O I/O I/O I/O I/O I/O I/O VCC DCLK, I/O Notes: 1. All unlisted pin numbers are user I/Os. 2. NC : Denotes No Connection 3. MODE should be terminated to GND through a 10K resistor to enable Actionprobe usage; otherwise it can be terminated directly to GND. 1-223 Package Pin Assignments ( continued) 208-Pin PQFP, RQFP (Top View) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 208-Pin PQFP, RQFP 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 1-224 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 A c c e l e ra to r S e ri e s F P G A s – A C T ™ 3 F ami l y 208-Pin PQFP, RQFP Pin Number 1 2 11 12 25 26 27 28 40 41 52 53 60 65 76 77 78 79 80 82 98 102 104 105 114 A1460 A14V60 Function GND SDI, I/O MODE VCC VCC GND VCC GND VCC VCC GND NC VCC NC PRB, I/O GND VCC GND VCC HCLK, I/O VCC NC IOPCL, I/O GND VCC A14100 A14V100 Function GND SDI, I/O MODE VCC VCC GND VCC GND VCC VCC GND I/O VCC I/O PRB, I/O GND VCC GND VCC HCLK, I/O VCC I/O IOPCL, I/O GND VCC Pin Number 115 116 129 130 131 132 145 146 147 148 156 157 158 164 180 181 182 183 184 185 186 195 201 205 208 A1460 A14V60 Function VCC NC GND VCC GND VCC VCC GND NC VCC IOCLK, I/O GND NC VCC CLKA, I/O CLKB, I/O VCC GND VCC GND PRA, I/O NC VCC NC DCLK, I/O A14100 A14V100 Function VCC I/O GND VCC GND VCC VCC GND I/O VCC IOCLK, I/O GND I/O VCC CLKA, I/O CLKB, I/O VCC GND VCC GND PRA, I/O I/O VCC I/O DCLK, I/O Notes: 1. All unlisted pin numbers are user I/Os. 2. NC : Denotes No Connection 3. MODE should be terminated to GND through a 10K resistor to enable Actionprobe usage; otherwise it can be terminated directly to GND. 1-225 Package Pin Assignments ( continued) 176-Pin TQFP (Top View) 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 176-Pin TQFP 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 1-226 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 A c c e l e ra to r S e ri e s F P G A s – A C T ™ 3 F ami l y 176-Pin TQFP Pin Number 1 2 10 11 20 21 22 23 32 33 44 49 51 63 64 65 66 67 69 82 83 88 89 A1440 A14V40 Function GND SDI, I/O MODE VCC NC GND VCC GND VCC VCC GND NC NC NC PRB, I/O GND VCC VCC HCLK, I/O NC NC IOPCL, I/O GND A1460 A14V60 Function GND SDI, I/O MODE VCC I/O GND VCC GND VCC VCC GND I/O I/O I/O PRB, I/O GND VCC VCC HCLK, I/O I/O I/O IOPCL, I/O GND Pin Number 98 99 108 109 110 119 121 122 123 124 132 133 138 152 153 154 155 156 157 158 170 176 A1440 A14V40 Function VCC VCC GND VCC GND NC NC VCC GND VCC IOCLK, I/O GND NC CLKA, I/O CLKB, I/O VCC GND VCC PRA, I/O NC NC DCLK, I/O A1460 A14V60 Function VCC VCC GND VCC GND I/O I/O VCC GND VCC IOCLK, I/O GND I/O CLKA, I/O CLKB, I/O VCC GND VCC PRA, I/O I/O I/O DCLK, I/O Notes: 1. All unlisted pin numbers are user I/Os. 2. NC : Denotes No Connection 3. MODE should be terminated to GND through a 10K resistor to enable Actionprobe usage; otherwise it can be terminated directly to GND. 1-227 Package Pin Assignments ( continued) 100-Pin VQFP (Top View) 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 76 75 74 73 72 71 70 69 68 67 66 65 100-Pin VQFP 64 63 62 61 60 59 58 57 56 55 54 53 52 51 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 1-228 50 A c c e l e ra to r S e ri e s F P G A s – A C T ™ 3 F ami l y 100-Pin VQFP Pin Number 1 2 7 8 9 20 21 34 35 36 37 39 50 51 57 58 67 68 69 74 75 87 88 89 90 91 92 93 100 A1415 A14V15 Function GND SDI, I/O MODE VCC GND VCC NC PRB, I/O VCC GND VCC HCLK, I/O IOPCL, I/O GND VCC VCC VCC GND GND NC IOCLK, I/O CLKA, I/O CLKB, I/O VCC VCC GND PRA, I/O NC DCLK, I/O A1425 A14V25 Function GND SDI, I/O MODE VCC GND VCC I/O PRB, I/O VCC GND VCC HCLK, I/O IOPCL, I/O GND VCC VCC VCC GND GND I/O IOCLK, I/O CLKA, I/O CLKB, I/O VCC VCC GND PRA, I/O I/O DCLK, I/O A1440 A14V40 Function GND SDI, I/O MODE VCC GND VCC I/O PRB, I/O VCC GND VCC HCLK, I/O IOPCL, I/O GND VCC VCC VCC GND GND I/O IOCLK, I/O CLKA, I/O CLKB, I/O VCC VCC GND PRA, I/O I/O DCLK, I/O Notes: 1. All unlisted pin numbers are user I/Os. 2. NC : Denotes No Connection 3. MODE should be terminated to GND through a 10K resistor to enable Actionprobe usage; otherwise it can be terminated directly to GND. 1-229 Package Pin Assigments ( continued) 132-Pin CQFP (Top View) 132 131 130 129 128 127 126 125 124 107 106 105 104 103 102 101 100 Pin #1 Index 1 2 3 4 5 6 7 8 99 98 97 96 95 94 93 92 132-Pin CQFP 25 26 27 28 29 30 31 32 33 75 74 73 72 71 70 69 68 67 34 35 36 37 38 39 40 41 42 59 60 61 62 63 64 65 66 1-230 A c c e l e ra to r S e ri e s F P G A s – A C T ™ 3 F ami l y 132-Pin CQFP Pin Number 1 2 3 9 10 11 22 26 27 34 36 42 43 48 50 58 59 64 65 66 67 A1425 Function NC GND SDI, I/O MODE GND VCC VCC GND VCC NC GND GND VCC PRB, I/O HCLK, I/O GND VCC IOPCL, I/O GND NC NC Pin Number 74 75 78 89 90 91 92 98 99 100 101 106 107 116 117 118 122 123 131 132 A1425 Function GND VCC VCC VCC GND VCC GND IOCLK, I/O NC NC GND GND VCC CLKA, I/O CLKB, I/O PRA, I/O GND VCC DCLK, I/O NC Notes: 1. All unlisted pin numbers are user I/Os. 2. NC : Denotes No Connection 3. MODE should be terminated to GND through a 10K resistor to enable Actionprobe usage; otherwise it can be terminated directly to GND. 1-231 Package Pin Assigments ( continued) 196-Pin CQFP (Top View) 196 195 194 193 192 191 190 189 188 155 154 153 152 151 150 149 148 Pin #1 Index 1 2 3 4 5 6 7 8 147 146 145 144 143 142 141 140 196-Pin CQFP 41 42 43 44 45 46 47 48 49 107 106 105 104 103 102 101 100 99 50 51 52 53 54 55 56 57 58 91 92 93 94 95 96 97 98 1-232 A c c e l e ra to r S e ri e s F P G A s – A C T ™ 3 F ami l y 196-Pin CQFP Pin Number 1 2 11 12 13 37 38 39 51 52 59 64 77 79 86 94 98 100 101 A1460 Function GND SDI, I/O MODE VCC GND GND VCC VCC GND GND VCC GND HCLK, I/O PRB, I/O GND VCC GND IOPCL, I/O GND Pin Number 110 111 112 137 138 139 140 148 149 155 162 172 173 174 183 189 193 196 A1460 Function VCC VCC GND VCC GND GND VCC IOCLK, I/O GND VCC GND CLKA, I/O CLKB, I/O PRA, I/O GND VCC GND DCLK, I/O Notes: 1. All unlisted pin numbers are user I/Os. 2. NC : Denotes No Connection 3. MODE should be terminated to GND through a 10K resistor to enable Actionprobe usage; otherwise it can be terminated directly to GND. 1-233 Package Pin Assigments ( continued) 256-Pin CQFP (Top View) 256 255 254 253 252 251 250 249 248 200 199 198 197 196 195 194 193 Pin #1 Index 1 2 3 4 5 6 7 8 192 191 190 189 188 187 186 185 256-Pin CQFP 56 57 58 59 60 61 62 63 64 137 136 135 134 133 132 131 130 129 65 66 67 68 69 70 71 72 73 121 122 123 124 125 126 127 128 1-234 A c c e l e ra to r S e ri e s F P G A s – A C T ™ 3 F ami l y 256-Pin CQFP Pin Number 1 2 11 28 29 30 31 46 59 90 91 92 93 94 96 110 127 128 141 A14100 Function GND SDI, I/O MODE VCC GND VCC GND VCC GND PRB, I/O GND VCC GND VCC HCLK, I/O GND IOPCL, I/O GND VCC Pin Number 158 159 160 161 174 175 176 188 189 219 220 221 222 223 224 225 240 256 A14100 Function GND VCC GND VCC VCC GND GND IOCLK, I/O GND CLKA, I/O CLKB, I/O VCC GND VCC GND PRA, I/O GND DCLK, I/O Notes: 1. All unlisted pin numbers are user I/Os. 2. NC: Denotes No Connection 3. MODE should be terminated to GND through a 10K resistor to enable Actionprobe usage; otherwise it can be terminated directly to GND. 1-235 Package Pin Assignments ( continued) 225-Pin BGA (Top View) 1 A B C D E F G H J K L M N P R 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 A B C D E F G H J K L M N P R 2 3 4 5 6 7 8 9 10 11 12 13 14 15 A1460 Function CLKA or I/O CLKB or I/O DCLK or I/O GND HCLK or I/O IOCLK or I/O IOPCL or I/O MODE NC PRA OR I/O PRB or I/O SDI or I/O VCC Location C8 B8 B2 A1, A15, D15, F8, G7, G8, G9, H6, H7, H8, H9, H10, J7, J8, J9, K8, P2, R15 P9 B14 P14 D1 A11, B5, B7, D8, D12, F6, F11, H1, H12, H14, K11, L1, L13, N8, P5, R1, R8, R11, R14 A7 L7 D4 A8, B12, D5, D14, E3, E8, E13, H2, H3, H11, H15, K4, L2, L12, M8, M15, P4, P8, R13 Notes: 1. Unused I/O pins are designated as outputs by ALS and are driven low. 2. All unassigned pins are available for use as I/Os. 3. MODE should be terminated to GND through a 10K resistor to enable Actionprobe usage; otherwise it can be terminated directly to GND. 1-236 A c c e l e ra to r S e ri e s F P G A s – A C T ™ 3 F ami l y Package Pin Assignments ( continued) 313-Pin BGA (Top View) 1 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE 1 2 3 4 5 6 78 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 2 3 4 5 6 78 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE A14100 A14V100 Function CLKA or I/O CLKB or I/O DCLK or I/O GND HCLK or I/O IOCLK or I/O IOPCL or I/O MODE NC Location J13 G13 B2 A1, A25, AD2, AE25, J21, L13, M12, M14, N11, N13, N15, P12, P14, R13 T14 B24 AD24 G3 A3, A13, A23, AA5, AA9, AA23, AB2, AB4, AB20, AC13, AC25, AD22, AE1, AE21, B14, C5, C25, D4, D24, E3, E21, F6, F10, F16, G1, G25, H18, H24, J1, J7, J25, K12, L15, L17, M6, N1, N5, N7, N21, N23, P20, R11, T6, T8, U9, U13, U21, V16, W7, Y20, Y24 H12 AD12 C1 AB18, AD6, AE13, C13, C19, E13, G9, H22, K8, K20, M16, N3, N9, N25, U5, W13, V2, V22, V24 PRA OR I/O PRB or I/O SDI or I/O VCC Notes: 1. 2. 3. Unused I/O pins are designated as outputs by ALS and are driven low. All unassigned pins are available for use as I/Os. MODE should be terminated to GND through a 10K resistor to enable Actionprobe usage; otherwise it can be terminated directly to GND. 1-237 Package Pin Assignments ( continued) 100-Pin CPGA (Top View) 1 A B C D E F G H J K L 1 2 3 4 5 6 7 8 9 10 11 A B C D E 100-Pin CPGA F G H J K L 2 3 4 5 6 7 8 9 10 11 Orientation Pin A1415 Function CLKA or I/O CLKB or I/O DCLK or I/O GND HCLK or I/O IOCLK or I/O IOPCL or I/O MODE PRA OR I/O PRB or I/O SDI or I/O VCC Location C7 D6 C4 C3, C6, C9, E9, F3, F9, J3, J6, J8, J9 H6 C10 K9 C2 A6 L3 B3 B6, B10, E11, F2, F10, G2, K2, K6, K10 Notes: 1. 2. 3. Unused I/O pins are designated as outputs by ALS and are driven low. All unassigned pins are available for use as I/Os. MODE should be terminated to GND through a 10K resistor to enable Actionprobe usage; otherwise it can be terminated directly to GND. 1-238 A c c e l e ra to r S e ri e s F P G A s – A C T ™ 3 F ami l y Package Pin Assignments ( continued) 133-Pin CPGA (Top View) 1 A B C D E F G H J K L M N 1 2 3 4 5 6 7 8 9 10 11 12 13 A B C D E F 133-Pin CPGA G H J K L M N 2 3 4 5 6 7 8 9 10 11 12 13 A1425 Function CLKA or I/O CLKB or I/O DCLK or I/O GND HCLK or I/O IOCLK or I/O IOPCL or I/O MODE NC PRA OR I/O PRB or I/O SDI or I/O VCC Location D7 B6 D4 A2, C3, C7, C11, C12, F10, G3, G11, L3, L7, L11, M3, N12 K7 C10 L10 E3 A1, A7, A13, G1, G13, N1, N7, N13 A6 L6 C2 B2, B7, B12, E11, G2, G12, J2, J12, M2, M7, M12 Notes: 1. 2. 3. Unused I/O pins are designated as outputs by ALS and are driven low. All unassigned pins are available for use as I/Os. MODE should be terminated to GND through a 10K resistor to enable Actionprobe usage; otherwise it can be terminated directly to GND. 1-239 Package Pin Assignments ( continued) 175-Pin CPGA (Top View) A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 A B C D E F G H J K L M N P R 1 2 3 4 5 6 7 175-Pin CPGA 8 9 10 11 12 13 14 15 B C D E F G H J K L M N P R A1440 Function CLKA or I/O CLKB or I/O DCLK or I/O GND HCLK or I/O IOCLK or I/O IOPCL or I/O MODE NC PRA OR I/O PRB or I/O SDI or I/O VCC Location C9 A9 D5 D4, D8, D11, D12, E4, E14, H4, H12, L4, L12, M4, M8, M12 R8 E12 P13 F3 A1, A2, A15, B2, B3, P2, P14, R1, R2, R14, R15 B8 R7 D3 C3, C8, C13, E15, H3, H13, L1, L14, N3, N8, N13 Notes: 1. 2. 3. Unused I/O pins are designated as outputs by ALS and are driven low. All unassigned pins are available for use as I/Os. MODE should be terminated to GND through a 10K resistor to enable Actionprobe usage; otherwise it can be terminated directly to GND. 1-240 A c c e l e ra to r S e ri e s F P G A s – A C T ™ 3 F ami l y Package Pin Assignments ( continued) 207-Pin CPGA (Top View) 1 A B C D E F G H J K L M N P R S T 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 A B C D E F G H 207-Pin CPGA J K L M N P R S T 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 A1460 Function CLKA or I/O CLKB or I/O DCLK or I/O GND HCKL or I/O IOCLK or I/O IOPCL or I/O MODE NC PRA OR I/O PRB or I/O SDI or I/O VCC Location K1 J3 E4 C15, D4, D5, D9, D14, J4, J14, P3, P4, P7, P9, P14, R15 J15 P5 N14 D7 A1, A2, A16, A17, B1, B17, C1, C2, S1, S3, S17, T1, T2, T16, T17 H1 K16 C3 B2, B9, B16, D11, J2, J16, P12, S2, S9, S16, T5 Notes: 1. 2. 3. Unused I/O pins are designated as outputs by ALS and are driven low. All unassigned pins are available for use as I/Os. MODE should be terminated to GND through a 10K resistor to enable Actionprobe usage; otherwise it can be terminated directly to GND. 1-241 Package Pin Assignments ( continued) 257-Pin CPGA (Top View) 1 A B C D E F G H J K L M N P R T V X Y 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 A B C D E F G H J 257-Pin CPGA K L M N P R T V X Y 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 A14100 Function CLKA or I/O CLKB or I/O DCLK or I/O GND HCLK or I/O IOCLK or I/O IOPCL or I/O MODE NC PRA OR I/O PRB or I/O SDI or I/O VCC Location L4 L5 E4 B16, C4, D4, D10, D16, E11, J5, K4, K16, L15, R4, T4, T10, T16, T17, X7 J16 T5 R16 A5 E5 J1 J17 B4 C3, C10, C13, C17, K3, K17, V3, V7, V10, V17, X14 Notes: 1. 2. 3. Unused I/O pins are designated as outputs by ALS and are driven low. All unassigned pins are available for use as I/Os. MODE should be terminated to GND through a 10K resistor to enable Actionprobe usage; otherwise it can be terminated directly to GND. 1-242