0
登录后你可以
  • 下载海量资料
  • 学习在线课程
  • 观看技术视频
  • 写文章/发帖/加入社区
会员中心
创作中心
发布
  • 发文章

  • 发资料

  • 发帖

  • 提问

  • 发视频

创作活动
A3P400-1FGG144

A3P400-1FGG144

  • 厂商:

    ACTEL(微芯科技)

  • 封装:

    LBGA144

  • 描述:

    IC FPGA 97 I/O 144FBGA

  • 详情介绍
  • 数据手册
  • 价格&库存
A3P400-1FGG144 数据手册
Revision 18 DS0097 ProASIC3 Flash Family FPGAs with Optional Soft ARM Support Features and Benefits Advanced I/O High Capacity • 15 K to 1 M System Gates • Up to 144 Kbits of True Dual-Port SRAM • Up to 300 User I/Os Reprogrammable Flash Technology • 130-nm, 7-Layer Metal (6 Copper), Flash-Based CMOS Process • Instant On Level 0 Support • Single-Chip Solution • Retains Programmed Design when Powered Off High Performance • 350 MHz System Performance • 3.3 V, 66 MHz 64-Bit PCI† In-System Programming (ISP) and Security • ISP Using On-Chip 128-Bit Advanced Encryption Standard (AES) Decryption (except ARM®-enabled ProASIC®3 devices) via JTAG (IEEE 1532–compliant)† • FlashLock® to Secure FPGA Contents Low Power • Core Voltage for Low Power • Support for 1.5 V-Only Systems • Low-Impedance Flash Switches High-Performance Routing Hierarchy • Segmented, Hierarchical Routing and Clock Structure • 700 Mbps DDR, LVDS-Capable I/Os (A3P250 and above) • 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation • Wide Range Power Supply Voltage Support per JESD8-B, Allowing I/Os to Operate from 2.7 V to 3.6 V • Bank-Selectable I/O Voltages—up to 4 Banks per Chip • Single-Ended I/O Standards: LVTTL, LVCMOS 3.3 V / 2.5 V / 1.8 V / 1.5 V, 3.3 V PCI / 3.3 V PCI-X† and LVCMOS 2.5 V / 5.0 V Input • Differential I/O Standards: LVPECL, LVDS, B-LVDS, and M-LVDS (A3P250 and above) • I/O Registers on Input, Output, and Enable Paths • Hot-Swappable and Cold Sparing I/Os‡ • Programmable Output Slew Rate† and Drive Strength • Weak Pull-Up/-Down • IEEE 1149.1 (JTAG) Boundary Scan Test • Pin-Compatible Packages across the ProASIC3 Family Clock Conditioning Circuit (CCC) and PLL† • Six CCC Blocks, One with an Integrated PLL • Configurable Phase-Shift, Multiply/Divide, Delay Capabilities and External Feedback • Wide Input Frequency Range (1.5 MHz to 350 MHz) Embedded Memory† • 1 Kbit of FlashROM User Nonvolatile Memory • SRAMs and FIFOs with Variable-Aspect-Ratio 4,608-Bit RAM Blocks (×1, ×2, ×4, ×9, and ×18 organizations)† • True Dual-Port SRAM (except ×18) ARM Processor Support in ProASIC3 FPGAs • M1 ProASIC3 Devices—ARM®Cortex®-M1 Soft Processor Available with or without Debug ProASIC3 Devices A3P0151 A3P030 A3P060 A3P125 A3P250 A3P400 A3P600 2 Cortex-M1 Devices M1A3P250 M1A3P400 M1A3P600 System Gates 15,000 30,000 60,000 125,000 250,000 400,000 600,000 Typical Equivalent Macrocells 128 256 512 1,024 2,048 – – VersaTiles (D-flip-flops) 384 768 1,536 3,072 6,144 9,216 13,824 RAM Kbits (1,024 bits) – – 18 36 36 54 108 4,608-Bit Blocks – – 4 8 8 12 24 FlashROM Kbits 1 1 1 1 1 1 1 Secure (AES) ISP 3 – – Yes Yes Yes Yes Yes Integrated PLL in CCCs – – 1 1 1 1 1 VersaNet Globals 4 6 6 18 18 18 18 18 I/O Banks 2 2 2 2 4 4 4 Maximum User I/Os 49 81 96 133 157 194 235 Notes: 1. A3P015 is not recommended for new designs. 2. Refer to the Cortex-M1 product brief for more information. 3. AES is not available for Cortex-M1 ProASIC3 devices. 4. Six chip (main) and three quadrant global networks are available for A3P060 and above. 5. The M1A3P250 device does not support this package. 6. For higher densities and support of additional features, refer to the ProASIC3E Flash Family FPGAs datasheet. 7. Package not available. † A3P015 and A3P030 devices do not support this feature. March 2016 © 2016 Microsemi Corporation A3P1000 M1A3P1000 1,000,000 – 24,576 144 32 1 Yes 1 18 4 300 ‡ Supported only by A3P015 and A3P030 devices. I ProASIC3 Flash Family FPGAs ProASIC3 Devices Cortex-M1 Devices 2 Package Pins QFN CS VQFP TQFP PQFP FBGA A3P0151 A3P030 A3P060 A3P125 A3P250 M1A3P250 QN68 QN48, QN68, QN1327 QN1327 QN1327 QN1327 VQ100 TQ144 PQ208 FG144 VQ100 VQ100 CS121 VQ100 TQ144 FG144 A3P400 M1A3P400 A3P600 M1A3P600 A3P1000 M1A3P1000 PQ208 PQ208 FG144/256 5 FG144/256/ 484 PQ208 FG144/256/ 484 PQ208 FG144/256/ 484 Notes: 1. A3P015 is not recommended for new designs. 2. Refer to the Cortex-M1 product brief for more information. 3. AES is not available for Cortex-M1 ProASIC3 devices. 4. Six chip (main) and three quadrant global networks are available for A3P060 and above. 5. The M1A3P250 device does not support this package. 6. For higher densities and support of additional features, refer to the ProASIC3E Flash Family FPGAs datasheet. 7. Package not available. II R evis i o n 18 ProASIC3 Flash Family FPGAs I/Os Per Package 1 ProASIC3 Devices A3P0152 A3P030 A3P060 A3P125 Cortex-M1 Devices A3P250 3 A3P400 3 A3P600 A3P1000 M1A3P250 3,5 M1A3P400 3 M1A3P600 M1A3P1000 – 49 49 – – – – – QN132 – 81 80 84 87 19 CS121 – – 96 – – VQ100 – 77 71 71 TQ144 – – 91 PQ208 – – FG144 – FG2565,6 FG4846 QN68 7 Differential I/O Pairs Differential I/O Pairs – Single-Ended I/O4 Single-Ended I/O4 – Differential I/O Pairs Single-Ended I/O – Single-Ended I/O4 Single-Ended I/O 34 QN48 Differential I/O Pairs Single-Ended I/O – Package Single-Ended I/O4 Single-Ended I/O I/O Type – – – – – – – – – – – – – – – – – – – – 68 13 – – – – – 100 – – – – – – – – – 133 151 34 151 34 154 35 154 35 – 96 97 97 24 97 25 97 25 97 25 – – – – 157 38 178 38 177 43 177 44 – – – – – – 194 38 235 60 300 74 – Notes: 1. When considering migrating your design to a lower- or higher-density device, refer to the ProASIC3 FPGA Fabric User Guide to ensure complying with design and board migration requirements. 2. A3P015 is not recommended for new designs. 3. For A3P250 and A3P400 devices, the maximum number of LVPECL pairs in east and west banks cannot exceed 15. Refer to the ProASIC3 FPGA Fabric Users Guide for position assignments of the 15 LVPECL pairs. 4. Each used differential I/O pair reduces the number of single-ended I/Os available by two. 5. The M1A3P250 device does not support FG256 package. 6. FG256 and FG484 are footprint-compatible packages. 7. Package not available. Table 1 • ProASIC3 FPGAs Package Sizes Dimensions CS121 QN48 QN68 QN132 * VQ100 TQ144 PQ208 FG144 FG256 FG484 6×6 6×6 8×8 8×8 14 × 14 20 × 20 28 × 28 13 × 13 17 × 17 23 × 23 Nominal Area (mm2) 36 36 64 64 196 400 784 169 289 529 Pitch (mm) 0.5 0.4 0.4 0.5 0.5 0.5 0.5 1.0 1.0 1.0 Height (mm) 0.99 0.90 0.90 0.75 1.00 1.40 3.40 1.45 1.60 2.23 Package Length × Width (mm × mm) Note: * Package not available R ev i si o n 1 8 III ProASIC3 Flash Family FPGAs ProASIC3 Ordering Information A3P1000 _ 1 FG G 144 I Y Security Feature Y = Device Includes License to Implement IP Based on the Cryptography Research, Inc. (CRI) Patent Portfolio Blank = Device Does Not Include License to Implement IP Based on the Cryptography Research, Inc. (CRI) Patent Portfolio Note: Only devices with packages greater than or equal to 5x5 are supported Application (Temperature Range) Blank = Commercial (0°C to +85°C Junction Temperature) I = Industrial (–40°C to +100°C Junction Temperature) PP = Pre-Production ES = Engineering Sample (Room Temperature Only) Package Lead Count Lead-Free Packaging Blank = Standard Packaging G= RoHS-Compliant (Green) Packaging (some packages also halogen-free) Package Type QN = Quad Flat Pack No Leads (0.4 mm and 0.5 mm pitches) VQ = Very Thin Quad Flat Pack (0.5 mm pitch) TQ = Thin Quad Flat Pack (0.5 mm pitch) PQ = Plastic Quad Flat Pack (0.5 mm pitch) FG = Fine Pitch Ball Grid Array (1.0 mm pitch) Speed Grade CS = Chip Scale Package (0.5 mm pitch) Blank = Standard 1 = 15% Faster than Standard 2 = 25% Faster than Standard Part Number ProASIC3 Devices A3P015 = A3P030 = A3P060 = A3P125 = A3P250 = A3P400 = A3P600 = A3P1000 = 15,000 System Gates (A3P015 is not recommended for new designs.) 30,000 System Gates 60,000 System Gates 125,000 System Gates 250,000 System Gates 400,000 System Gates 600,000 System Gates 1,000,000 System Gates ProASIC3 Devices with Cortex-M1 M1A3P250 M1A3P400 M1A3P600 M1A3P1000 = = = = 250,000 System Gates 400,000 System Gates 600,000 System Gates 1,000,000 System Gates ProASIC3 Device Status ProASIC3 Devices Status Cortex-M1 Devices Status A3P015 Not recommended for new designs. A3P030 Production A3P060 Production A3P125 Production A3P250 Production M1A3P250 Production A3P400 Production M1A3P400 Production A3P600 Production M1A3P600 Production A3P1000 Production M1A3P1000 Production IV R evis i o n 18 ProASIC3 Flash Family FPGAs ProASIC3 Device Family Overview General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 ProASIC3 DC and Switching Characteristics General Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 Calculating Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 User I/O Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15 VersaTile Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-81 Global Resource Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-85 Clock Conditioning Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-90 Embedded SRAM and FIFO Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-92 Embedded FlashROM Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-107 JTAG 1532 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-108 Pin Descriptions Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . User Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . JTAG Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Special Function Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 3-2 3-3 3-4 3-4 Package Pin Assignments QN48 – Bottom View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 QN68 – Bottom View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3 QN132 – Bottom View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6 CS121 – Bottom View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-15 VQ100 – Top View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-18 TQ144 – Top View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-23 PQ208 – Top View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-28 FG144 – Bottom View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-39 FG256 – Bottom View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-52 FG484 – Bottom View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-65 Datasheet Information List of Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 Datasheet Categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-15 Safety Critical, Life Support, and High-Reliability Applications Policy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-15 R ev i si o n 1 8 V 1 – ProASIC3 Device Family Overview General Description ProASIC3, the third-generation family of Microsemi flash FPGAs, offers performance, density, and features beyond those of the ProASICPLUS® family. Nonvolatile flash technology gives ProASIC3 devices the advantage of being a secure, low power, single-chip solution that is Instant On. ProASIC3 is reprogrammable and offers time-to-market benefits at an ASIC-level unit cost. These features enable designers to create high-density systems using existing ASIC or FPGA design flows and tools. ProASIC3 devices offer 1 kbit of on-chip, reprogrammable, nonvolatile FlashROM storage as well as clock conditioning circuitry based on an integrated phase-locked loop (PLL). The A3P015 and A3P030 devices have no PLL or RAM support. ProASIC3 devices have up to 1 million system gates, supported with up to 144 kbits of true dual-port SRAM and up to 300 user I/Os. ProASIC3 devices support the ARM Cortex-M1 processor. The ARM-enabled devices have Microsemi ordering numbers that begin with M1A3P (Cortex-M1) and do not support AES decryption. Flash Advantages Reduced Cost of Ownership Advantages to the designer extend beyond low unit cost, performance, and ease of use. Unlike SRAMbased FPGAs, flash-based ProASIC3 devices allow all functionality to be Instant On; no external boot PROM is required. On-board security mechanisms prevent access to all the programming information and enable secure remote updates of the FPGA logic. Designers can perform secure remote in-system reprogramming to support future design iterations and field upgrades with confidence that valuable intellectual property (IP) cannot be compromised or copied. Secure ISP can be performed using the industry-standard AES algorithm. The ProASIC3 family device architecture mitigates the need for ASIC migration at higher user volumes. This makes the ProASIC3 family a cost-effective ASIC replacement solution, especially for applications in the consumer, networking/ communications, computing, and avionics markets. Security The nonvolatile, flash-based ProASIC3 devices do not require a boot PROM, so there is no vulnerable external bitstream that can be easily copied. ProASIC3 devices incorporate FlashLock, which provides a unique combination of reprogrammability and design security without external overhead, advantages that only an FPGA with nonvolatile flash programming can offer. ProASIC3 devices utilize a 128-bit flash-based lock and a separate AES key to provide the highest level of protection in the FPGA industry for intellectual property and configuration data. In addition, all FlashROM data in ProASIC3 devices can be encrypted prior to loading, using the industry-leading AES-128 (FIPS192) bit block cipher encryption standard. The AES standard was adopted by the National Institute of Standards and Technology (NIST) in 2000 and replaces the 1977 DES standard. ProASIC3 devices have a built-in AES decryption engine and a flash-based AES key that make them the most comprehensive programmable logic device security solution available today. ProASIC3 devices with AES-based security provide a high level of protection for remote field updates over public networks such as the Internet, and are designed to ensure that valuable IP remains out of the hands of system overbuilders, system cloners, and IP thieves. ARM-enabled ProASIC3 devices do not support user-controlled AES security mechanisms. Since the ARM core must be protected at all times, AES encryption is always on for the core logic, so bitstreams are always encrypted. There is no user access to encryption for the FlashROM programming data. Security, built into the FPGA fabric, is an inherent component of the ProASIC3 family. The flash cells are located beneath seven metal layers, and many device design and layout techniques have been used to make invasive attacks extremely difficult. The ProASIC3 family, with FlashLock and AES security, is unique in being highly resistant to both invasive and noninvasive attacks. R ev i si o n 1 8 1-1 ProASIC3 Flash Family FPGAs Your valuable IP is protected with industry-standard security, making remote ISP possible. A ProASIC3 device provides the best available security for programmable logic designs. Single Chip Flash-based FPGAs store their configuration information in on-chip flash cells. Once programmed, the configuration data is an inherent part of the FPGA structure, and no external configuration data needs to be loaded at system powerup (unlike SRAM-based FPGAs). Therefore, flash-based ProASIC3 FPGAs do not require system configuration components such as EEPROMs or microcontrollers to load device configuration data. This reduces bill-of-materials costs and PCB area, and increases security and system reliability. Instant On Flash-based ProASIC3 devices support Level 0 of the Instant On classification standard. This feature helps in system component initialization, execution of critical tasks before the processor wakes up, setup and configuration of memory blocks, clock generation, and bus activity management. The Instant On feature of flash-based ProASIC3 devices greatly simplifies total system design and reduces total system cost, often eliminating the need for CPLDs and clock generation PLLs that are used for these purposes in a system. In addition, glitches and brownouts in system power will not corrupt the ProASIC3 device's flash configuration, and unlike SRAM-based FPGAs, the device will not have to be reloaded when system power is restored. This enables the reduction or complete removal of the configuration PROM, expensive voltage monitor, brownout detection, and clock generator devices from the PCB design. Flash-based ProASIC3 devices simplify total system design and reduce cost and design risk while increasing system reliability and improving system initialization time. Firm Errors Firm errors occur most commonly when high-energy neutrons, generated in the upper atmosphere, strike a configuration cell of an SRAM FPGA. The energy of the collision can change the state of the configuration cell and thus change the logic, routing, or I/O behavior in an unpredictable way. These errors are impossible to prevent in SRAM FPGAs. The consequence of this type of error can be a complete system failure. Firm errors do not exist in the configuration memory of ProASIC3 flash-based FPGAs. Once it is programmed, the flash cell configuration element of ProASIC3 FPGAs cannot be altered by high-energy neutrons and is therefore immune to them. Recoverable (or soft) errors occur in the user data SRAM of all FPGA devices. These can easily be mitigated by using error detection and correction (EDAC) circuitry built into the FPGA fabric. Low Power Flash-based ProASIC3 devices exhibit power characteristics similar to an ASIC, making them an ideal choice for power-sensitive applications. ProASIC3 devices have only a very limited power-on current surge and no high-current transition period, both of which occur on many FPGAs. ProASIC3 devices also have low dynamic power consumption to further maximize power savings. R ev i si o n 1 8 1-2 ProASIC3 Device Family Overview Advanced Flash Technology The ProASIC3 family offers many benefits, including nonvolatility and reprogrammability through an advanced flashbased, 130-nm LVCMOS process with seven layers of metal. Standard CMOS design techniques are used to implement logic and control functions. The combination of fine granularity, enhanced flexible routing resources, and abundant flash switches allows for very high logic utilization without compromising device routability or performance. Logic functions within the device are interconnected through a four-level routing hierarchy. Advanced Architecture The proprietary ProASIC3 architecture provides granularity comparable to standard-cell ASICs. The ProASIC3 device consists of five distinct and programmable architectural features (Figure 1-1 and Figure 1-2 on page 1-4): • FPGA VersaTiles • Dedicated FlashROM • Dedicated SRAM/FIFO memory† • Extensive CCCs and PLLs† • Advanced I/O structure Bank 0 Bank 0 Bank 1 CCC RAM Block 4,608-Bit Dual-Port SRAM or FIFO Block* I/Os ISP AES Decryption* User Nonvolatile FlashROM Bank 0 Bank 1 VersaTile Charge Pumps Bank 1 Note: *Not supported by A3P015 and A3P030 devices Figure 1-1 • ProASIC3 Device Architecture Overview with Two I/O Banks (A3P015, A3P030, A3P060, and A3P125) † The A3P015 and A3P030 do not support PLL or SRAM. 1 -3 R evis i o n 18 ProASIC3 Flash Family FPGAs Bank 0 Bank 1 Bank 3 CCC RAM Block 4,608-Bit Dual-Port SRAM or FIFO Block I/Os Bank 1 Bank 3 VersaTile ISP AES Decryption User Nonvolatile FlashROM RAM Block 4,608-Bit Dual-Port SRAM or FIFO Block (A3P600 and A3P1000) Charge Pumps Bank 2 Figure 1-2 • ProASIC3 Device Architecture Overview with Four I/O Banks (A3P250, A3P600, and A3P1000) The FPGA core consists of a sea of VersaTiles. Each VersaTile can be configured as a three-input logic function, a Dflip-flop (with or without enable), or a latch by programming the appropriate flash switch interconnections. The versatility of the ProASIC3 core tile as either a three-input lookup table (LUT) equivalent or as a D-flip-flop/latch with enable allows for efficient use of the FPGA fabric. The VersaTile capability is unique to the Microsemi ProASIC family of third-generation architecture flash FPGAs. VersaTiles are connected with any of the four levels of routing hierarchy. Flash switches are distributed throughout the device to provide nonvolatile, reconfigurable interconnect programming. Maximum core utilization is possible for virtually any design. VersaTiles The ProASIC3 core consists of VersaTiles, which have been enhanced beyond the ProASICPLUS® core tiles. The ProASIC3 VersaTile supports the following: • All 3-input logic functions—LUT-3 equivalent • Latch with clear or set • D-flip-flop with clear or set • Enable D-flip-flop with clear or set Refer to Figure 1-3 for VersaTile configurations. LUT-3 Equivalent X1 X2 X3 LUT-3 Y D-Flip-Flop with Clear or Set Data CLK CLR Y D-FF Enable D-Flip-Flop with Clear or Set Data CLK Y D-FF Enable CLR Figure 1-3 • VersaTile Configurations R ev i si o n 1 8 1-4 ProASIC3 Device Family Overview User Nonvolatile FlashROM ProASIC3 devices have 1 kbit of on-chip, user-accessible, nonvolatile FlashROM. The FlashROM can be used in diverse system applications: • Internet protocol addressing (wireless or fixed) • System calibration settings • Device serialization and/or inventory control • Subscription-based business models (for example, set-top boxes) • Secure key storage for secure communications algorithms • Asset management/tracking • Date stamping • Version management The FlashROM is written using the standard ProASIC3 IEEE 1532 JTAG programming interface. The core can be individually programmed (erased and written), and on-chip AES decryption can be used selectively to securely load data over public networks (except in the A3P015 and A3P030 devices), as in security keys stored in the FlashROM for a user design. The FlashROM can be programmed via the JTAG programming interface, and its contents can be read back either through the JTAG programming interface or via direct FPGA core addressing. Note that the FlashROM can only be programmed from the JTAG interface and cannot be programmed from the internal logic array. The FlashROM is programmed as 8 banks of 128 bits; however, reading is performed on a byte-by-byte basis using a synchronous interface. A 7-bit address from the FPGA core defines which of the 8 banks and which of the 16 bytes within that bank are being read. The three most significant bits (MSBs) of the FlashROM address determine the bank, and the four least significant bits (LSBs) of the FlashROM address define the byte. The ProASIC3 development software solutions, Libero® System-on-Chip (SoC) and Designer, have extensive support for the FlashROM. One such feature is auto-generation of sequential programming files for applications requiring a unique serial number in each part. Another feature allows the inclusion of static data for system version control. Data for the FlashROM can be generated quickly and easily using Libero SoC and Designer software tools. Comprehensive programming file support is also included to allow for easy programming of large numbers of parts with differing FlashROM contents. SRAM and FIFO ProASIC3 devices (except the A3P015 and A3P030 devices) have embedded SRAM blocks along their north and south sides. Each variable-aspect-ratio SRAM block is 4,608 bits in size. Available memory configurations are 256×18, 512×9, 1k×4, 2k×2, and 4k×1 bits. The individual blocks have independent read and write ports that can be configured with different bit widths on each port. For example, data can be sent through a 4-bit port and read as a single bitstream. The embedded SRAM blocks can be initialized via the device JTAG port (ROM emulation mode) using the UJTAG macro (except in A3P015 and A3P030 devices). In addition, every SRAM block has an embedded FIFO control unit. The control unit allows the SRAM block to be configured as a synchronous FIFO without using additional core VersaTiles. The FIFO width and depth are programmable. The FIFO also features programmable Almost Empty (AEMPTY) and Almost Full (AFULL) flags in addition to the normal Empty and Full flags. The embedded FIFO control unit contains the counters necessary for generation of the read and write address pointers. The embedded SRAM/FIFO blocks can be cascaded to create larger configurations. PLL and CCC ProASIC3 devices provide designers with very flexible clock conditioning capabilities. Each member of the ProASIC3 family contains six CCCs. One CCC (center west side) has a PLL. The A3P015 and A3P030 devices do not have a PLL. The six CCC blocks are located at the four corners and the centers of the east and west sides. All six CCC blocks are usable; the four corner CCCs and the east CCC allow simple clock delay operations as well as clock spine access. The inputs of the six CCC blocks are accessible from the FPGA core or from one of several inputs located near the CCC that have dedicated connections to the CCC block. 1 -5 R evis i o n 18 ProASIC3 Flash Family FPGAs The CCC block has these key features: • Wide input frequency range (fIN_CCC) = 1.5 MHz to 350 MHz • Output frequency range (fOUT_CCC) = 0.75 MHz to 350 MHz • Clock delay adjustment via programmable and fixed delays from –7.56 ns to +11.12 ns • 2 programmable delay types for clock skew minimization • Clock frequency synthesis (for PLL only) Additional CCC specifications: • Internal phase shift = 0°, 90°, 180°, and 270°. Output phase shift depends on the output divider configuration (for PLL only). • Output duty cycle = 50% ± 1.5% or better (for PLL only) • Low output jitter: worst case < 2.5% × clock period peak-to-peak period jitter when single global network used (for PLL only) • Maximum acquisition time = 300 µs (for PLL only) • Low power consumption of 5 mW • Exceptional tolerance to input period jitter— allowable input jitter is up to 1.5 ns (for PLL only) • Four precise phases; maximum misalignment between adjacent phases of 40 ps × (350 MHz / fOUT_CCC) (for PLL only) Global Clocking ProASIC3 devices have extensive support for multiple clocking domains. In addition to the CCC and PLL support described above, there is a comprehensive global clock distribution network. Each VersaTile input and output port has access to nine VersaNets: six chip (main) and three quadrant global networks. The VersaNets can be driven by the CCC or directly accessed from the core via multiplexers (MUXes). The VersaNets can be used to distribute low-skew clock signals or for rapid distribution of high fanout nets. R ev i si o n 1 8 1-6 ProASIC3 Device Family Overview I/Os with Advanced I/O Standards The ProASIC3 family of FPGAs features a flexible I/O structure, supporting a range of voltages (1.5 V, 1.8 V, 2.5 V, and 3.3 V). ProASIC3 FPGAs support many different I/O standards—single-ended and differential. The I/Os are organized into banks, with two or four banks per device. The configuration of these banks determines the I/O standards supported (Table 1-1). Table 1-1 • I/O Standards Supported I/O Standards Supported I/O Bank Type Device and Bank Location LVTTL/ LVCMOS PCI/PCI-X LVPECL, LVDS, B-LVDS, M-LVDS Advanced East and west Banks of A3P250 and larger devices    Standard Plus North and south banks of A3P250 and larger devices   Not supported  Not supported Not supported All banks of A3P060 and A3P125 Standard All banks of A3P015 and A3P030 Each I/O module contains several input, output, and enable registers. These registers allow the implementation of the following: • Single-Data-Rate applications • Double-Data-Rate applications—DDR LVDS, B-LVDS, and M-LVDS I/Os for point-to-point communications ProASIC3 banks for the A3P250 device and above support LVPECL, LVDS, B-LVDS and M-LVDS. B-LVDS and MLVDS can support up to 20 loads. Hot-swap (also called hot-plug, or hot-insertion) is the operation of hot-insertion or hot-removal of a card in a poweredup system. Cold-sparing (also called cold-swap) refers to the ability of a device to leave system data undisturbed when the system is powered up, while the component itself is powered down, or when power supplies are floating. Wide Range I/O Support ProASIC3 devices support JEDEC-defined wide range I/O operation. ProASIC3 supports the JESD8-B specification, covering both 3 V and 3.3 V supplies, for an effective operating range of 2.7 V to 3.6 V. Wider I/O range means designers can eliminate power supplies or power conditioning components from the board or move to less costly components with greater tolerances. Wide range eases I/O bank management and provides enhanced protection from system voltage spikes, while providing the flexibility to easily run custom voltage applications. Specifying I/O States During Programming You can modify the I/O states during programming in FlashPro. In FlashPro, this feature is supported for PDB files generated from Designer v8.5 or greater. See the FlashPro User’s Guide for more information. Note: PDB files generated from Designer v8.1 to Designer v8.4 (including all service packs) have limited display of Pin Numbers only. 1. Load a PDB from the FlashPro GUI. You must have a PDB loaded to modify the I/O states during programming. 2. From the FlashPro GUI, click PDB Configuration. A FlashPoint – Programming File Generator window appears. 3. Click the Specify I/O States During Programming button to display the Specify I/O States During Programming dialog box. 4. Sort the pins as desired by clicking any of the column headers to sort the entries by that header. Select the I/Os you wish to modify (Figure 1-4 on page 1-8). 5. Set the I/O Output State. You can set Basic I/O settings if you want to use the default I/O settings for your pins, or use Custom I/O settings to customize the settings for each pin. Basic I/O state settings: 1 – I/O is set to drive out logic High 1 -7 R evis i o n 18 ProASIC3 Flash Family FPGAs 0 – I/O is set to drive out logic Low Last Known State – I/O is set to the last value that was driven out prior to entering the programming mode, and then held at that value during programming Z -Tristate: I/O is tristated Figure 1-4 • I/O States During Programming Window 6. Click OK to return to the FlashPoint – Programming File Generator window. Note: I/O States During programming are saved to the ADB and resulting programming files after completing programming file generation. R ev i si o n 1 8 1-8 2 – ProASIC3 DC and Switching Characteristics General Specifications Operating Conditions Stresses beyond those listed in Table 2-1 may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Absolute Maximum Ratings are stress ratings only; functional operation of the device at these or any other conditions beyond those listed under the Recommended Operating Conditions specified in Table 2-2 on page 2-2 is not implied. Table 2-1 • Symbol Absolute Maximum Ratings Parameter Limits Units VCC DC core supply voltage –0.3 to 1.65 V VJTAG JTAG DC voltage –0.3 to 3.75 V VPUMP Programming voltage –0.3 to 3.75 V VCCPLL Analog power supply (PLL) –0.3 to 1.65 V VCCI DC I/O output buffer supply voltage –0.3 to 3.75 V VMV DC I/O input buffer supply voltage –0.3 to 3.75 V VI I/O input voltage –0.3 V to 3.6 V V (when I/O hot insertion mode is enabled) –0.3 V to (VCCI + 1 V) or 3.6 V, whichever voltage is lower (when I/O hot-insertion mode is disabled) TSTG 2 Storage temperature –65 to +150 °C TJ 2 Junction temperature +125 °C Notes: 1. The device should be operated within the limits specified by the datasheet. During transitions, the input signal may undershoot or overshoot according to the limits shown in Table 2-4 on page 2-3. 2. VMV pins must be connected to the corresponding VCCI pins. See the "VMVx I/O Supply Voltage (quiet)" section on page 3-1 for further information. 3. For flash programming and retention maximum limits, refer to Table 2-3 on page 2-3, and for recommended operating limits, refer to Table 2-2 on page 2-2. R ev i si o n 1 8 2-1 ProASIC3 Flash Family FPGAs Table 2-2 • Recommended Operating Conditions 1 Parameters 1 Symbol TJ Commercial Junction temperature 3 0 to 85 VCC 1.5 V DC core supply voltage VJTAG JTAG DC voltage VPUMP Programming voltage VCCI and VMV 5 Industrial -40 to 100 2 Units °C 1.425 to 1.575 1.425 to 1.575 V 1.4 to 3.6 1.4 to 3.6 V 3.15 to 3.45 3.15 to 3.45 V 0 to 3.6 0 to 3.6 V Analog power supply (PLL) 1.425 to 1.575 1.425 to 1.575 V 1.5 V DC supply voltage 1.425 to 1.575 1.425 to 1.575 V 1.8 V DC supply voltage 1.7 to 1.9 1.7 to 1.9 V 2.5 V DC supply voltage 2.3 to 2.7 2.3 to 2.7 V 3.0 to 3.6 3.0 to 3.6 V 2.7 to 3.6 2.7 to 3.6 V 2.375 to 2.625 2.375 to 2.625 V 3.0 to 3.6 3.0 to 3.6 V Programming Mode Operation 4 VCCPLL 2 3.3 V DC supply voltage 3.3 V wide range DC supply voltage 6 LVDS/B-LVDS/M-LVDS differential I/O LVPECL differential I/O Notes: 1. All parameters representing voltages are measured with respect to GND unless otherwise specified. 2. Software Default Junction Temperature Range in the Libero® System-on-Chip (SoC) software is set to 0°C to +70°C for commercial, and -40°C to +85°C for industrial. To ensure targeted reliability standards are met across the full range of junction temperatures, Microsemi recommends using custom settings for temperature range before running timing and power analysis tools. For more information regarding custom settings, refer to the New Project Dialog Box in the Libero SoC Online Help. 3. The ranges given here are for power supplies only. The recommended input voltage ranges specific to each I/O standard are given in Table 2-18 on page 2-19. 4. VPUMP can be left floating during operation (not programming mode). 5. VMV and VCCI should be at the same voltage within a given I/O bank. VMV pins must be connected to the corresponding VCCI pins. See the "VMVx I/O Supply Voltage (quiet)" section on page 3-1 for further information. 6. 3.3 V wide range is compliant to the JESD8-B specification and supports 3.0 V VCCI operation. R ev i si o n 1 8 2-2 ProASIC3 DC and Switching Characteristics 70 102.7 85 100 43.8 20.0 105 15.6 110 12.3 115 9.7 120 125 7.7 6.2 130 5.0 135 140 4.0 3.3 145 150 2.7 2.2 Years Tj (°C) 110 100 90 80 70 60 50 40 30 20 10 0 HTR Lifetime (yrs) 70 85 100 105 110 115 120 125 130 135 140 145 150 Temperature (ºC) Note: HTR time is the period during which you would not expect a verify failure due to flash cell leakage. Figure 2-1 • High-Temperature Data Retention (HTR) Table 2-3 • Product Grade Flash Programming Limits – Retention, Storage and Operating Temperature1 Programming Program Retention Cycles (biased/unbiased) Maximum Storage Temperature TSTG (°C) Maximum Operating Junction Temperature TJ (°C)2 Commercial 500 20 years 110 100 Industrial 500 20 years 110 100 1. 2. This is a stress rating only; functional operation at any condition other than those indicated is not implied. These limits apply for program/data retention only. Refer to Table 2-1 on page 2-1 and Table 2-2 for device operating conditions and absolute limits. Table 2-4 • Overshoot and Undershoot Limits 1 VCCI and VMV 2.7 V or less 3V Average VCCI–GND Overshoot or Undershoot Duration as a Percentage of Clock Cycle2 Maximum Overshoot/ Undershoot2 10% 1.4 V 5% 1.49 V 10% 1.1 V 5% 1.19 V 3.3 V 10% 0.79 V 5% 0.88 V 3.6 V 10% 0.45 V 5% 0.54 V Notes: 1. Based on reliability requirements at 85°C. 2. The duration is allowed at one out of six clock cycles. If the overshoot/undershoot occurs at one out of two cycles, the maximum overshoot/undershoot has to be reduced by 0.15 V. 3. This table does not provide PCI overshoot/undershoot limits. 2 -3 R evis i o n 18 ProASIC3 Flash Family FPGAs I/O Power-Up and Supply Voltage Thresholds for Power-On Reset (Commercial and Industrial) Sophisticated power-up management circuitry is designed into every ProASIC®3 device. These circuits ensure easy transition from the powered-off state to the powered-up state of the device. The many different supplies can power up in any sequence with minimized current spikes or surges. In addition, the I/O will be in a known state through the power-up sequence. The basic principle is shown in Figure 2-2 on page 2-5. There are five regions to consider during power-up. ProASIC3 I/Os are activated only if ALL of the following three conditions are met: 1. VCC and VCCI are above the minimum specified trip points (Figure 2-2 on page 2-5). 2. VCCI > VCC – 0.75 V (typical) 3. Chip is in the operating mode. VCCI Trip Point: Ramping up: 0.6 V < trip_point_up < 1.2 V Ramping down: 0.5 V < trip_point_down < 1.1 V VCC Trip Point: Ramping up: 0.6 V < trip_point_up < 1.1 V Ramping down: 0.5 V < trip_point_down < 1 V VCC and VCCI ramp-up trip points are about 100 mV higher than ramp-down trip points. This specifically built-in hysteresis prevents undesirable power-up oscillations and current surges. Note the following: • During programming, I/Os become tristated and weakly pulled up to VCCI. • JTAG supply, PLL power supplies, and charge pump VPUMP supply have no influence on I/O behavior. PLL Behavior at Brownout Condition Microsemi recommends using monotonic power supplies or voltage regulators to ensure proper power-up behavior. Power ramp-up should be monotonic at least until VCC and VCCPLLX exceed brownout activation levels. The VCC activation level is specified as 1.1 V worst-case (see Figure 2-2 on page 2-5 for more details). When PLL power supply voltage and/or VCC levels drop below the VCC brownout levels (0.75 V ± 0.25 V), the PLL output lock signal goes low and/or the output clock is lost. Refer to the "Power-Up/Down Behavior of Low Power Flash Devices" chapter of the ProASIC3 FPGA Fabric User’s Guide for information on clock and lock recovery. Internal Power-Up Activation Sequence 1. Core 2. Input buffers Output buffers, after 200 ns delay from input buffer activation. Thermal Characteristics Introduction The temperature variable in the Microsemi Designer software refers to the junction temperature, not the ambient temperature. This is an important distinction because dynamic and static power consumption cause the chip junction to be higher than the ambient temperature. EQ can be used to calculate junction temperature. TJ = Junction Temperature = T + TA where: TA = Ambient Temperature T = Temperature gradient between junction (silicon) and ambient T = ja * P ja = Junction-to-ambient of the package. ja numbers are located in Table 2-5 on page 2-6. P = Power dissipation R ev i si o n 1 8 2-4 ProASIC3 DC and Switching Characteristics VCC = VCCI + VT where VT can be from 0.58 V to 0.9 V (typically 0.75 V) VCC VCC = 1.575 V Region 4: I/O buffers are ON. I/Os are functional (except differential but slower because VCCI is below specification. For the same reason, input buffers do not meet VIH / VIL levels, and output buffers do not meet VOH / VOL levels. Region 1: I/O Buffers are OFF Region 5: I/O buffers are ON and power supplies are within specification. I/Os meet the entire datasheet and timer specifications for speed, VIH / VIL, VOH / VOL, etc. VCC = 1.425 V Region 2: I/O buffers are ON. I/Os are functional (except differential inputs) but slower because VCCI / VCC are below specification. For the same reason, input buffers do not meet VIH / VIL levels, and output buffers do not meet VOH / VOL levels. Activation trip point: Va = 0.85 V ± 0.25 V Deactivation trip point: Vd = 0.75 V ± 0.25 V Region 1: I/O buffers are OFF Activation trip point: Va = 0.9 V ± 0.3 V Deactivation trip point: Vd = 0.8 V ± 0.3 V Figure 2-2 • Region 3: I/O buffers are ON. I/Os are functional; I/O DC specifications are met, but I/Os are slower because the VCC is below specification. Min VCCI datasheet specification voltage at a selected I/O standard; i.e., 1.425 V or 1.7 V or 2.3 V or 3.0 V VCCI I/O State as a Function of VCCI and VCC Voltage Levels Package Thermal Characteristics The device junction-to-case thermal resistivity is jc and the junction-to-ambient air thermal resistivity is ja. The thermal characteristics for ja are shown for two air flow rates. 2 -5 R evis i o n 18 ProASIC3 Flash Family FPGAs The absolute maximum junction temperature is 100°C. EQ 1 shows a sample calculation of the absolute maximum power dissipation allowed for a 484-pin FBGA package at commercial temperature and in still air. Max. junction temp. (C) – Max. ambient temp. (C) 100C – 70C · Maximum Power Allowed = ------------------------------------------------------------------------------------------------------------------------------------------ = ------------------------------------- = 1.463 W  ja (C/W) 20.5C/W EQ 1 Table 2-5 • Package Thermal Resistivities ja Package Type Device Pin Count jc Still Air 200 ft/min 500 ft/min Units Quad Flat No Lead A3P030 132 0.4 21.4 16.8 15.3 °C/W A3P060 132 0.3 21.2 16.6 15.0 °C/W A3P125 132 0.2 21.1 16.5 14.9 °C/W A3P250 132 0.1 21.0 16.4 14.8 °C/W Very Thin Quad Flat Pack (VQFP) All devices 100 10.0 35.3 29.4 27.1 °C/W Thin Quad Flat Pack (TQFP) All devices 144 11.0 33.5 28.0 25.7 °C/W Plastic Quad Flat Pack (PQFP) All devices 208 8.0 26.1 22.5 20.8 °C/W * 144 3.8 26.9 22.9 21.5 °C/W See note* 256 3.8 26.6 22.8 21.5 °C/W See note* 484 3.2 20.5 17.0 15.9 °C/W A3P1000 144 6.3 31.6 26.2 24.2 °C/W A3P1000 256 6.6 28.1 24.4 22.7 °C/W A3P1000 484 8.0 23.3 19.0 16.7 °C/W Fine Pitch Ball Grid Array (FBGA) See note Note: *This information applies to all ProASIC3 devices except the A3P1000. Detailed device/package thermal information will be available in future revisions of the datasheet. Temperature and Voltage Derating Factors Table 2-6 • Temperature and Voltage Derating Factors for Timing Delays (normalized to TJ = 70°C, VCC = 1.425 V) Array Voltage VCC (V) Junction Temperature (°C) –40°C 0°C 25°C 70°C 85°C 100°C 1.425 0.88 0.93 0.95 1.00 1.02 1.04 1.500 0.83 0.88 0.90 0.95 0.96 0.98 1.575 0.80 0.84 0.87 0.91 0.93 0.94 R ev i si o n 1 8 2-6 ProASIC3 DC and Switching Characteristics Calculating Power Dissipation Quiescent Supply Current Table 2-7 • Quiescent Supply Current Characteristics A3P015 A3P030 A3P060 A3P125 A3P250 A3P400 A3P600 A3P1000 Typical (25°C) 2 mA 2 mA 2 mA 2 mA 3 mA 3 mA 5 mA 8 mA Max. (Commercial) 10 mA 10 mA 10 mA 10 mA 20 mA 20 mA 30 mA 50 mA Max. (Industrial) 15 mA 15 mA 15 mA 15 mA 30 mA 30 mA 45 mA 75 mA Note: IDD Includes VCC, VPUMP, VCCI, and VMV currents. Values do not include I/O static contribution, which is shown in Table 2-11 and Table 2-12 on page 2-9. Power per I/O Pin Table 2-8 • Summary of I/O Input Buffer Power (Per Pin) – Default I/O Software Settings Applicable to Advanced I/O Banks VMV (V) Static Power PDC2 (mW) 1 Dynamic Power PAC9 (µW/MHz) 2 3.3 V LVTTL / 3.3 V LVCMOS 3.3 – 16.22 3 Single-Ended 3.3 V LVCMOS Wide Range 3.3 – 16.22 2.5 V LVCMOS 2.5 – 5.12 1.8 V LVCMOS 1.8 – 2.13 1.5 V LVCMOS (JESD8-11) 1.5 – 1.45 3.3 V PCI 3.3 – 18.11 3.3 V PCI-X 3.3 – 18.11 LVDS 2.5 2.26 1.20 LVPECL 3.3 5.72 1.87 Differential Notes: 1. PDC2 is the static power (where applicable) measured on VMV. 2. PAC9 is the total dynamic power measured on VCC and VMV. 3. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8-B specification. Table 2-9 • Summary of I/O Input Buffer Power (Per Pin) – Default I/O Software Settings Applicable to Standard Plus I/O Banks VMV (V) Static Power PDC2 (mW) 1 Dynamic Power PAC9 (µW/MHz) 2 3.3 V LVTTL / 3.3 V LVCMOS 3.3 – 16.23 3.3 V LVCMOS Wide Range3 3.3 – 16.23 Single-Ended Notes: 1. PDC2 is the static power (where applicable) measured on VMV. 2. PAC9 is the total dynamic power measured on VCC and VMV. 3. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8-B specification. 2 -7 R evis i o n 18 ProASIC3 Flash Family FPGAs Table 2-9 • Summary of I/O Input Buffer Power (Per Pin) – Default I/O Software Settings Applicable to Standard Plus I/O Banks VMV (V) Static Power PDC2 (mW) 1 Dynamic Power PAC9 (µW/MHz) 2 2.5 V LVCMOS 2.5 – 5.14 1.8 V LVCMOS 1.8 – 2.13 1.5 V LVCMOS (JESD8-11) 1.5 – 1.48 3.3 V PCI 3.3 – 18.13 3.3 V PCI-X 3.3 – 18.13 Notes: 1. PDC2 is the static power (where applicable) measured on VMV. 2. PAC9 is the total dynamic power measured on VCC and VMV. 3. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8-B specification. Table 2-10 • Summary of I/O Input Buffer Power (Per Pin) – Default I/O Software Settings Applicable to Standard I/O Banks VMV (V) Static Power PDC2 (mW) 1 Dynamic Power PAC9 (µW/MHz) 2 3.3 V LVTTL / 3.3 V LVCMOS 3.3 – 17.24 3 3.3 V LVCMOS Wide Range 3.3 – 17.24 2.5 V LVCMOS 2.5 – 5.19 1.8 V LVCMOS 1.8 – 2.18 1.5 V LVCMOS (JESD8-11) 1.5 – 1.52 Single-Ended Notes: 1. PDC2 is the static power (where applicable) measured on VMV. 2. PAC9 is the total dynamic power measured on VCC and VMV. 3. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8-B specification. R ev i si o n 1 8 2-8 ProASIC3 DC and Switching Characteristics Table 2-11 • Summary of I/O Output Buffer Power (per pin) – Default I/O Software Settings1 Applicable to Advanced I/O Banks CLOAD (pF) VCCI (V) Static Power PDC3 (mW)2 Dynamic Power PAC10 (µW/MHz)3 3.3 V LVTTL / 3.3 V LVCMOS 35 3.3 – 468.67 4 35 3.3 – 468.67 2.5 V LVCMOS 35 2.5 – 267.48 1.8 V LVCMOS 35 1.8 – 149.46 1.5 V LVCMOS (JESD8-11) 35 1.5 – 103.12 3.3 V PCI 10 3.3 – 201.02 3.3 V PCI-X 10 3.3 – 201.02 LVDS – 2.5 7.74 88.92 LVPECL – 3.3 19.54 166.52 Single-Ended 3.3 V LVCMOS Wide Range Differential Notes: 1. 2. 3. 4. Dynamic power consumption is given for standard load and software default drive strength and output slew. PDC3 is the static power (where applicable) measured on VCCI. PAC10 is the total dynamic power measured on VCC and VCCI. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8-B specification. Table 2-12 • Summary of I/O Output Buffer Power (Per Pin) – Default I/O Software Settings1 Applicable to Standard Plus I/O Banks CLOAD (pF) VCCI (V) Static Power PDC3 (mW)2 Dynamic Power PAC10 (µW/MHz)3 3.3 V LVTTL / 3.3 V LVCMOS 35 3.3 – 452.67 3.3 V LVCMOS Wide Range4 35 3.3 – 452.67 2.5 V LVCMOS 35 2.5 – 258.32 1.8 V LVCMOS 35 1.8 – 133.59 1.5 V LVCMOS (JESD8-11) 35 1.5 – 92.84 3.3 V PCI 10 3.3 – 184.92 3.3 V PCI-X 10 3.3 – 184.92 Single-Ended Notes: 1. 2. 3. 4. 2 -9 Dynamic power consumption is given for standard load and software default drive strength and output slew. PDC3 is the static power (where applicable) measured on VMV. PAC10 is the total dynamic power measured on VCC and VMV. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8-B specification. R evis i o n 18 ProASIC3 Flash Family FPGAs Table 2-13 • Summary of I/O Output Buffer Power (Per Pin) – Default I/O Software Settings 1 Applicable to Standard I/O Banks CLOAD (pF) VCCI (V) Static Power PDC3 (mW) 2 Dynamic Power PAC10 (µW/MHz) 3 3.3 V LVTTL / 3.3 V LVCMOS 35 3.3 – 431.08 4 35 3.3 – 431.08 2.5 V LVCMOS 35 2.5 – 247.36 1.8 V LVCMOS 35 1.8 – 128.46 1.5 V LVCMOS (JESD8-11) 35 1.5 – 89.46 Single-Ended 3.3 V LVCMOS Wide Range Notes: 1. 2. 3. 4. Dynamic power consumption is given for standard load and software default drive strength and output slew. PDC3 is the static power (where applicable) measured on VCCI. PAC10 is the total dynamic power measured on VCC and VCCI. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8-B specification. R ev i si o n 1 8 2-10 ProASIC3 DC and Switching Characteristics Power Consumption of Various Internal Resources Table 2-14 • Different Components Contributing to Dynamic Power Consumption in ProASIC3 Devices A3P015 A3P030 A3P060 A3P125 A3P250 A3P400 Definition A3P600 Parameter A3P1000 Device Specific Dynamic Contributions (µW/MHz) PAC1 Clock contribution of a Global Rib 14.50 12.80 12.80 11.00 11.00 9.30 9.30 9.30 PAC2 Clock contribution of a Global Spine 2.48 0.41 0.41 PAC3 Clock contribution of a VersaTile row 0.81 PAC4 Clock contribution of a VersaTile used as a sequential module 0.12 PAC5 First contribution of a VersaTile used as a sequential module 0.07 PAC6 Second contribution of a VersaTile used as a sequential module 0.29 PAC7 Contribution of a VersaTile used as a combinatorial Module 0.29 PAC8 Average contribution of a routing net 0.70 PAC9 Contribution of an I/O input pin (standard dependent) See Table 2-8 on page 2-7 through Table 2-10 on page 2-8. PAC10 Contribution of an I/O output pin (standard dependent) See Table 2-11 on page 2-9 through Table 2-13 on page 2-10. PAC11 Average contribution of a RAM block during a read operation 25.00 PAC12 Average contribution of a RAM block during a write operation 30.00 PAC13 Dynamic contribution for PLL 2.60 1.85 1.35 1.58 0.81 0.81 Note: *For a different output load, drive strength, or slew rate, Microsemi recommends using the Microsemi Power spreadsheet calculator or SmartPower tool in Libero SoC software. 2 -1 1 R evi s i o n 18 ProASIC3 Flash Family FPGAs Table 2-15 • Different Components Contributing to the Static Power Consumption in ProASIC3 Devices PDC1 Array static power in Active mode PDC2 I/O input pin static power (standard-dependent) See Table 2-8 on page 2-7 through Table 2-10 on page 2-8. PDC3 I/O output pin static power (standard-dependent) See Table 2-11 on page 2-9 through Table 2-13 on page 2-10. PDC4 Static PLL contribution PDC5 Bank quiescent power (VCCI-dependent) A3P015 A3P030 A3P060 A3P125 A3P250 A3P600 Parameter A3P400 Device Specific Static Power (mW) A3P1000 Definition See Table 2-7 on page 2-7. 2.55 mW See Table 2-7 on page 2-7. Note: *For a different output load, drive strength, or slew rate, Microsemi recommends using the Microsemi Power spreadsheet calculator or SmartPower tool in Libero SoC software. Power Calculation Methodology This section describes a simplified method to estimate power consumption of an application. For more accurate and detailed power estimations, use the SmartPower tool in Libero SoC software. The power calculation methodology described below uses the following variables: • The number of PLLs as well as the number and the frequency of each output clock generated • The number of combinatorial and sequential cells used in the design • The internal clock frequencies • The number and the standard of I/O pins used in the design • The number of RAM blocks used in the design • Toggle rates of I/O pins as well as VersaTiles—guidelines are provided in Table 2-16 on page 2-14. • Enable rates of output buffers—guidelines are provided for typical applications in Table 2-17 on page 2-14. • Read rate and write rate to the memory—guidelines are provided for typical applications in Table 2-17 on page 2-14. The calculation should be repeated for each clock domain defined in the design. Methodology Total Power Consumption—PTOTAL PTOTAL = PSTAT + PDYN PSTAT is the total static power consumption. PDYN is the total dynamic power consumption. Total Static Power Consumption—PSTAT PSTAT = PDC1 + NINPUTS* PDC2 + NOUTPUTS* PDC3 NINPUTS is the number of I/O input buffers used in the design. NOUTPUTS is the number of I/O output buffers used in the design. Total Dynamic Power Consumption—PDYN PDYN = PCLOCK + PS-CELL + PC-CELL + PNET + PINPUTS + POUTPUTS + PMEMORY + PPLL Global Clock Contribution—PCLOCK PCLOCK = (PAC1 + NSPINE*PAC2 + NROW*PAC3 + NS-CELL* PAC4) * FCLK NSPINE is the number of global spines used in the user design—guidelines are provided in the "Spine Architecture" section of the Global Resources chapter in the ProASIC3 FPGA Fabric User's Guide. NROW is the number of VersaTile rows used in the design—guidelines are provided in the "Spine Architecture" section of the Global Resources chapter in the ProASIC3 FPGA Fabric User's Guide. R ev i si o n 1 8 2-12 ProASIC3 DC and Switching Characteristics FCLK is the global clock signal frequency. NS-CELL is the number of VersaTiles used as sequential modules in the design. PAC1, PAC2, PAC3, and PAC4 are device-dependent. Sequential Cells Contribution—PS-CELL PS-CELL = NS-CELL * (PAC5 + 1 / 2 * PAC6) * FCLK NS-CELL is the number of VersaTiles used as sequential modules in the design. When a multi-tile sequential cell is used, it should be accounted for as 1. 1 is the toggle rate of VersaTile outputs—guidelines are provided in Table 2-16 on page 2-14. FCLK is the global clock signal frequency. Combinatorial Cells Contribution—PC-CELL PC-CELL = NC-CELL* 1 / 2 * PAC7 * FCLK NC-CELL is the number of VersaTiles used as combinatorial modules in the design. 1 is the toggle rate of VersaTile outputs—guidelines are provided in Table 2-16 on page 2-14. FCLK is the global clock signal frequency. Routing Net Contribution—PNET PNET = (NS-CELL + NC-CELL) * 1 / 2 * PAC8 * FCLK NS-CELL is the number of VersaTiles used as sequential modules in the design. NC-CELL is the number of VersaTiles used as combinatorial modules in the design. 1 is the toggle rate of VersaTile outputs—guidelines are provided in Table 2-16 on page 2-14. FCLK is the global clock signal frequency. I/O Input Buffer Contribution—PINPUTS PINPUTS = NINPUTS * 2 / 2 * PAC9 * FCLK NINPUTS is the number of I/O input buffers used in the design. 2 is the I/O buffer toggle rate—guidelines are provided in Table 2-16 on page 2-14. FCLK is the global clock signal frequency. I/O Output Buffer Contribution—POUTPUTS POUTPUTS = NOUTPUTS * 2 / 2 * 1 * PAC10 * FCLK NOUTPUTS is the number of I/O output buffers used in the design. 2 is the I/O buffer toggle rate—guidelines are provided in Table 2-16 on page 2-14. 1 is the I/O buffer enable rate—guidelines are provided in Table 2-17 on page 2-14. FCLK is the global clock signal frequency. 2 -1 3 R evi s i o n 18 ProASIC3 Flash Family FPGAs RAM Contribution—PMEMORY PMEMORY = PAC11 * NBLOCKS * FREAD-CLOCK * 2 + PAC12 * NBLOCK * FWRITE-CLOCK * 3 NBLOCKS is the number of RAM blocks used in the design. FREAD-CLOCK is the memory read clock frequency. 2 is the RAM enable rate for read operations. FWRITE-CLOCK is the memory write clock frequency. 3 is the RAM enable rate for write operations—guidelines are provided in Table 2-17 on page 2-14. PLL Contribution—PPLL PPLL = PDC4 + PAC13 *FCLKOUT FCLKOUT is the output clock frequency.1 Guidelines Toggle Rate Definition A toggle rate defines the frequency of a net or logic element relative to a clock. It is a percentage. If the toggle rate of a net is 100%, this means that this net switches at half the clock frequency. Below are some examples: • The average toggle rate of a shift register is 100% because all flip-flop outputs toggle at half of the clock frequency. • The average toggle rate of an 8-bit counter is 25%: – Bit 0 (LSB) = 100% – Bit 1 = 50% – Bit 2 = 25% – … – Bit 7 (MSB) = 0.78125% – Average toggle rate = (100% + 50% + 25% + 12.5% + . . . + 0.78125%) / 8 Enable Rate Definition Output enable rate is the average percentage of time during which tristate outputs are enabled. When nontristate output buffers are used, the enable rate should be 100%. Table 2-16 • Toggle Rate Guidelines Recommended for Power Calculation Component 1 2 Definition Guideline Toggle rate of VersaTile outputs 10% I/O buffer toggle rate 10% Table 2-17 • Enable Rate Guidelines Recommended for Power Calculation Component 1 2 3 1. Definition Guideline I/O output buffer enable rate 100% RAM enable rate for read operations 12.5% RAM enable rate for write operations 12.5% The PLL dynamic contribution depends on the input clock frequency, the number of output clock signals generated by the PLL, and the frequency of each output clock. If a PLL is used to generate more than one output clock, include each output clock in the formula by adding its corresponding contribution (PAC14 * FCLKOUT product) to the total PLL contribution. R ev i si o n 1 8 2-14 ProASIC3 DC and Switching Characteristics User I/O Characteristics Timing Model I/O Module (Non-Registered) Combinational Cell Combinational Cell Y LVPECL (Applicable to Advanced I/O Banks Only)L Y tPD = 0.56 ns tPD = 0.49 ns tDP = 1.34 ns I/O Module (Non-Registered) Combinational Cell Y LVTTL Output drive strength = 12 mA High slew rate tDP = 2.64 ns (Advanced I/O Banks) tPD = 0.87 ns I/O Module (Non-Registered) Combinational Cell I/O Module (Registered) Y LVTTL Output drive strength = 8 mA High slew rate tDP = 3.66 ns (Advanced I/O Banks) tPY = 1.05 ns LVPECL (Applicable to Advanced I/O Banks only) D tPD = 0.47 ns Q I/O Module (Non-Registered) Combinational Cell Y tICLKQ = 0.24 ns tISUD = 0.26 ns LVCMOS 1.5 V Output drive strength = 4 mA High slew rate tDP = 3.97 ns (Advanced I/O Banks) tPD = 0.47 ns Input LVTTL Clock Register Cell tPY = 0.76 ns (Advanced I/O Banks) D Y Q I/O Module (Non-Registered) LVDS, BLVDS, M-LVDS (Applicable for Advanced I/O Banks only) Figure 2-3 • 2 -1 5 D Q D tPD = 0.47 ns tCLKQ = 0.55 ns tSUD = 0.43 ns tPY = 1.20 ns I/O Module (Registered) Combinational Cell Register Cell Q LVTTL 3.3 V Output drive strength = 12 mA High slew rate tDP = 2.64 ns (Advanced I/O Banks) tCLKQ = 0.55 ns tSUD = 0.43 ns tOCLKQ = 0.59 ns tOSUD = 0.31 ns Input LVTTL Clock Input LVTTL Clock tPY = 0.76 ns (Advanced I/O Banks) tPY = 0.76 ns (Advanced I/O Banks) Timing Model Operating Conditions: –2 Speed, Commercial Temperature Range (TJ = 70°C), Worst Case VCC = 1.425 V R evi s i o n 18 ProASIC3 Flash Family FPGAs tPY tDIN D PAD Q DIN Y CLK tPY = MAX(tPY(R), tPY(F)) tDIN = MAX(tDIN(R), tDIN(F)) To Array I/O Interface VIH PAD Vtrip Vtrip VIL VCC 50% 50% Y GND tPY (F) tPY (R) VCC 50% DIN GND tDIN (R) Figure 2-4 • 50% tDIN (F) Input Buffer Timing Model and Delays (Example) R ev i si o n 1 8 2-16 ProASIC3 DC and Switching Characteristics tDOUT tDP D Q D PAD DOUT Std Load CLK From Array tDP = MAX(tDP(R), tDP(F)) tDOUT = MAX(tDOUT(R), tDOUT(F)) I/O Interface tDOUT (R) D 50% tDOUT VCC (F) 50% 0V VCC DOUT 50% 50% 0V VOH Vtrip Vtrip VOL PAD tDP (R) Figure 2-5 • 2 -1 7 Output Buffer Model and Delays (Example) R evi s i o n 18 tDP (F) ProASIC3 Flash Family FPGAs tEOUT D Q CLK E tZL, tZH, tHZ, tLZ, tZLS, tZHS EOUT D Q PAD DOUT CLK D tEOUT = MAX(tEOUT(r), tEOUT(f)) I/O Interface VCC D VCC 50% tEOUT (F) 50% E tEOUT (R) VCC 50% EOUT tZL PAD 50% 50% tHZ Vtrip tZH 50% tLZ VCCI 90% VCCI Vtrip VOL 10% VCCI VCC D VCC E 50% tEOUT (R) 50% tEOUT (F) VCC EOUT PAD 50% 50% tZLS VOH Vtrip Figure 2-6 • 50% tZHS Vtrip VOL Tristate Output Buffer Timing Model and Delays (Example) R ev i si o n 1 8 2-18 ProASIC3 DC and Switching Characteristics Overview of I/O Performance Summary of I/O DC Input and Output Levels – Default I/O Software Settings Table 2-18 • Summary of Maximum and Minimum DC Input and Output Levels Applicable to Commercial and Industrial Conditions—Software Default Settings Applicable to Advanced I/O Banks Equiv. Software Default Drive Drive Strength Slew Min I/O Standard Strength Option2 Rate V VIL VIH VOL VOH Max V Min V Max V Max V Min V IOL1 IOH1 mA mA 3.3 V LVTTL / 3.3 V LVCMOS 12 mA 12 mA High –0.3 0.8 2 3.6 0.4 2.4 12 12 3.3 V LVCMOS Wide Range3 100 µA 12 mA High –0.3 0.8 2 3.6 0.2 VCCI – 0.2 0.1 0.1 2.5 V LVCMOS 12 mA 12 mA High –0.3 0.7 1.7 2.7 0.7 1.7 12 12 1.8 V LVCMOS 12 mA 12 mA High –0.3 0.35 * VCCI 0.65 * VCCI 1.9 0.45 VCCI – 0.45 12 12 1.5 V LVCMOS 12 mA 12 mA High –0.3 0.35 * VCCI 0.65 * VCCI 1.6 0.25 * VCCI 0.75 * VCCI 12 12 3.3 V PCI 3.3 V PCI-X Per PCI specifications Per PCI-X specifications Notes: 1. Currents are measured at 85°C junction temperature. 2. 3.3 V LVCMOS wide range is applicable to 100 µA drive strength only. The configuration will NOT operate at the equivalent software default drive strength. These values are for Normal Ranges ONLY. 3. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD-8B specification. 2 -1 9 R evi s i o n 18 ProASIC3 Flash Family FPGAs Table 2-19 • Summary of Maximum and Minimum DC Input and Output Levels Applicable to Commercial and Industrial Conditions—Software Default Settings Applicable to Standard Plus I/O Banks Equiv. Software Default Drive Drive Strength Slew Min I/O Standard Strength Option2 Rate V VIL VIH VOL VOH Max V Min V Max V Max V Min V 2.4 IOL1 IOH1 mA mA 3.3 V LVTTL / 12 mA 3.3 V LVCMOS 12 mA High –0.3 0.8 2 3.6 0.4 100 µA 3.3 V LVCMOS Wide Range3 12 mA High –0.3 0.8 2 3.6 0.2 2.5 V LVCMOS 12 mA 12 mA High –0.3 0.7 1.7 2.7 0.7 1.7 12 12 1.8 V LVCMOS 8 mA 8 mA High –0.3 0.35 * VCCI 0.65 * VCCI 1.9 0.45 VCCI – 0.45 8 8 1.5 V LVCMOS 4 mA 4 mA High –0.3 0.35 * VCCI 0.65 * VCCI 1.6 0.25 * VCCI 0.75 * VCCI 4 4 3.3 V PCI 3.3 V PCI-X 12 12 VCCI – 0.2 0.1 0.1 Per PCI specifications Per PCI-X specifications Notes: 1. Currents are measured at 85°C junction temperature. 2. 3.3 V LVCMOS wide range is applicable to 100 µA drive strength only. The configuration will NOT operate at the equivalent software default drive strength. These values are for Normal Ranges ONLY. 3. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8-B specification. R ev i si o n 1 8 2-20 ProASIC3 DC and Switching Characteristics Table 2-20 • Summary of Maximum and Minimum DC Input and Output Levels Applicable to Commercial and Industrial Conditions—Software Default Settings Applicable to Standard I/O Banks Equiv. Software Default Drive Drive Strength Slew Min I/O Standard Strength Option2 Rate V 3.3 V LVTTL / 3.3 V LVCMOS 8 mA VIL VIH VOL VOH Max V Min V Max V Max V Min V IOL1 IOH1 mA mA 8 mA High –0.3 0.8 2 3.6 0.4 2.4 8 8 100 µA 3.3 V LVCMOS Wide Range3 8 mA High –0.3 0.8 2 3.6 0.2 VCCI – 0.2 0.1 0.1 2.5 V LVCMOS 8 mA 8 mA High –0.3 0.7 1.7 2.7 0.7 1.7 8 8 1.8 V LVCMOS 4 mA 4 mA High –0.3 0.35 * VCCI 0.65 * VCCI 3.6 0.45 VCCI – 0.45 4 4 1.5 V LVCMOS 2 mA 2 mA High –0.3 0.35 * VCCI 0.65 * VCCI 3.6 0.25 * VCCI 0.75 * VCCI 2 2 Notes: 1. Currents are measured at 85°C junction temperature. 2. 3.3 V LVCMOS wide range is applicable to 100 µA drive strength only. The configuration will NOT operate at the equivalent software default drive strength. These values are for Normal Ranges ONLY. 3. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD-8B specification. Table 2-21 • Summary of Maximum and Minimum DC Input Levels Applicable to Commercial and Industrial Conditions Commercial1 Industrial2 IIL3 IIH4 IIL3 IIH4 DC I/O Standards µA µA µA µA 3.3 V LVTTL / 3.3 V LVCMOS 10 10 15 15 3.3 V LVCMOS Wide Range 10 10 15 15 2.5 V LVCMOS 10 10 15 15 1.8 V LVCMOS 10 10 15 15 1.5 V LVCMOS 10 10 15 15 3.3 V PCI 10 10 15 15 3.3 V PCI-X 10 10 15 15 Notes: 1. Commercial range (0°C < TA < 70°C) 2. Industrial range (–40°C < TA < 85°C) 3. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3V < VIN 20 years 0°C > 20 years 25°C > 20 years 70°C 5 years 85°C 2 years 100°C 0.5 years Table 2-36 • I/O Input Rise Time, Fall Time, and Related I/O Reliability Input Buffer Input Rise/Fall Time (min) Input Rise/Fall Time (max) Reliability LVTTL/LVCMOS No requirement 10 ns * 20 years (110°C) LVDS/B-LVDS/ M-LVDS/LVPECL No requirement 10 ns * 10 years (100°C) Note: *The maximum input rise/fall time is related to the noise induced into the input buffer trace. If the noise is low, then the rise time and fall time of input buffers can be increased beyond the maximum value. The longer the rise/fall times, the more susceptible the input signal is to the board noise. Microsemi recommends signal integrity evaluation/characterization of the system to ensure that there is no excessive noise coupling into input signals. 2 -3 1 R evi s i o n 18 ProASIC3 Flash Family FPGAs Single-Ended I/O Characteristics 3.3 V LVTTL / 3.3 V LVCMOS Low-Voltage Transistor–Transistor Logic (LVTTL) is a general-purpose standard (EIA/JESD) for 3.3 V applications. It uses an LVTTL input buffer and push-pull output buffer. Table 2-37 • Minimum and Maximum DC Input and Output Levels Applicable to Advanced I/O Banks 3.3 V LVTTL / 3.3 V LVCMOS VIL VIH VOL VOH IOL IOH IOSL IOSH IIL1 IIH2 mA mA Max mA3 Max mA3 µA4 µA4 Drive Strength Min V Max V Min V Max V Max V Min V 2 mA –0.3 0.8 2 3.6 0.4 2.4 2 2 27 25 10 10 4 mA –0.3 0.8 2 3.6 0.4 2.4 4 4 27 25 10 10 6 mA –0.3 0.8 2 3.6 0.4 2.4 6 6 54 51 10 10 8 mA –0.3 0.8 2 3.6 0.4 2.4 8 8 54 51 10 10 12 mA –0.3 0.8 2 3.6 0.4 2.4 12 12 109 103 10 10 16 mA –0.3 0.8 2 3.6 0.4 2.4 16 16 127 132 10 10 24 mA –0.3 0.8 2 3.6 0.4 2.4 24 24 181 268 10 10 Notes: 1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL. 2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is larger when operating outside recommended ranges 3. Currents are measured at 100°C junction temperature and maximum voltage. 4. Currents are measured at 85°C junction temperature. 5. Software default selection highlighted in gray. Table 2-38 • Minimum and Maximum DC Input and Output Levels Applicable to Standard Plus I/O Banks 3.3 V LVTTL / 3.3 V LVCMOS VIL VIH VOL VOH IOL IOH IOSL IOSH IIL1 IIH2 µA4 µA4 Drive Strength Min V Max V Min V Max V Max V Min V mA mA Max mA3 Max mA3 2 mA –0.3 0.8 2 3.6 0.4 2.4 2 2 27 25 10 10 4 mA –0.3 0.8 2 3.6 0.4 2.4 4 4 27 25 10 10 6 mA –0.3 0.8 2 3.6 0.4 2.4 6 6 54 51 10 10 8 mA –0.3 0.8 2 3.6 0.4 2.4 8 8 54 51 10 10 12 mA –0.3 0.8 2 3.6 0.4 2.4 12 12 109 103 10 10 16 mA –0.3 0.8 2 3.6 0.4 2.4 16 16 109 103 10 10 Notes: 1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL. 2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is larger when operating outside recommended ranges 3. Currents are measured at 100°C junction temperature and maximum voltage. 4. Currents are measured at 85°C junction temperature. 5. Software default selection highlighted in gray. R ev i si o n 1 8 2-32 ProASIC3 DC and Switching Characteristics Table 2-39 • Minimum and Maximum DC Input and Output Levels Applicable to Standard I/O Banks 3.3 V LVTTL / 3.3 V LVCMOS VIL VIH Max V Min V Max V VOL VOH IOL IOH IOSL IOSH IIL1 IIH2 Max V Min V mA mA Max mA3 Max mA3 µA4 µA4 Drive Strength Min V 2 mA –0.3 0.8 2 3.6 0.4 2.4 2 2 25 27 10 10 4 mA –0.3 0.8 2 3.6 0.4 2.4 4 4 25 27 10 10 6 mA –0.3 0.8 2 3.6 0.4 2.4 6 6 51 54 10 10 8 mA –0.3 0.8 2 3.6 0.4 2.4 8 8 51 54 10 10 Notes: 1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL. 2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is larger when operating outside recommended ranges 3. Currents are measured at 100°C junction temperature and maximum voltage. 4. Currents are measured at 85°C junction temperature. 5. Software default selection highlighted in gray. R = 1 kΩ Test Point Enable Path Test Point Datapath Figure 2-7 • 35 pF R to VCCI for tLZ / tZL / tZLS R to GND for tHZ / tZH / tZHS 35 pF for tZH / tZHS / tZL / tZLS 35 pF for tHZ / tLZ AC Loading Table 2-40 • AC Waveforms, Measuring Points, and Capacitive Loads Input Low (V) 0 Input High (V) Measuring Point* (V) CLOAD (pF) 3.3 1.4 35 Note: *Measuring point = Vtrip. See Table 2-22 on page 2-22 for a complete table of trip points. 2 -3 3 R evi s i o n 18 ProASIC3 Flash Family FPGAs Timing Characteristics Table 2-41 • 3.3 V LVTTL / 3.3 V LVCMOS High Slew Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V Applicable to Advanced I/O Banks Drive Strength 2 mA 4 mA 6 mA 8 mA 12 mA 16 mA 24 mA Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Std. 0.66 7.66 0.04 1.02 0.43 7.80 6.59 2.65 2.61 10.03 8.82 ns –1 0.56 6.51 0.04 0.86 0.36 6.63 5.60 2.25 2.22 8.54 7.51 ns –2 0.49 5.72 0.03 0.76 0.32 5.82 4.92 1.98 1.95 7.49 6.59 ns Std. 0.66 7.66 0.04 1.02 0.43 7.80 6.59 2.65 2.61 10.03 8.82 ns –1 0.56 6.51 0.04 0.86 0.36 6.63 5.60 2.25 2.22 8.54 7.51 ns –2 0.49 5.72 0.03 0.76 0.32 5.82 4.92 1.98 1.95 7.49 6.59 ns Std. 0.66 4.91 0.04 1.02 0.43 5.00 4.07 2.99 3.20 7.23 6.31 ns –1 0.56 4.17 0.04 0.86 0.36 4.25 3.46 2.54 2.73 6.15 5.36 ns –2 0.49 3.66 0.03 0.76 0.32 3.73 3.04 2.23 2.39 5.40 4.71 ns Std. 0.66 4.91 0.04 1.02 0.43 5.00 4.07 2.99 3.20 7.23 6.31 ns –1 0.56 4.17 0.04 0.86 0.36 4.25 3.46 2.54 2.73 6.15 5.36 ns –2 0.49 3.66 0.03 0.76 0.32 3.73 3.04 2.23 2.39 5.40 4.71 ns Std. 0.66 3.53 0.04 1.02 0.43 3.60 2.82 3.21 3.58 5.83 5.06 ns –1 0.56 3.00 0.04 0.86 0.36 3.06 2.40 2.73 3.05 4.96 4.30 ns –2 0.49 2.64 0.03 0.76 0.32 2.69 2.11 2.40 2.68 4.36 3.78 ns Std. 0.66 3.33 0.04 1.02 0.43 3.39 2.56 3.26 3.68 5.63 4.80 ns –1 0.56 2.83 0.04 0.86 0.36 2.89 2.18 2.77 3.13 4.79 4.08 ns –2 0.49 2.49 0.03 0.76 0.32 2.53 1.91 2.44 2.75 4.20 3.58 ns Std. 0.66 3.08 0.04 1.02 0.43 3.13 2.12 3.32 4.06 5.37 4.35 ns –1 0.56 2.62 0.04 0.86 0.36 2.66 1.80 2.83 3.45 4.57 3.70 ns –2 0.49 2.30 0.03 0.76 0.32 2.34 1.58 2.48 3.03 4.01 3.25 ns Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. R ev i si o n 1 8 2-34 ProASIC3 DC and Switching Characteristics Table 2-42 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V Applicable to Advanced I/O Banks Drive Strength 2 mA 4 mA 6 mA 8 mA 12 mA 16 mA 24 mA Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Std. 0.66 10.26 0.04 1.02 0.43 10.45 8.90 2.64 2.46 12.68 11.13 ns –1 0.56 8.72 0.04 0.86 0.36 8.89 7.57 2.25 2.09 10.79 9.47 ns –2 0.49 7.66 0.03 0.76 0.32 7.80 6.64 1.98 1.83 9.47 8.31 ns Std. 0.66 10.26 0.04 1.02 0.43 10.45 8.90 2.64 2.46 12.68 11.13 ns –1 0.56 8.72 0.04 0.86 0.36 8.89 7.57 2.25 2.09 10.79 9.47 ns –2 0.49 7.66 0.03 0.76 0.32 7.80 6.64 1.98 1.83 9.47 8.31 ns Std. 0.66 7.27 0.04 1.02 0.43 7.41 6.28 2.98 3.04 9.65 8.52 ns –1 0.56 6.19 0.04 0.86 0.36 6.30 5.35 2.54 2.59 8.20 7.25 ns –2 0.49 5.43 0.03 0.76 0.32 5.53 4.69 2.23 2.27 7.20 6.36 ns Std. 0.66 7.27 0.04 1.02 0.43 7.41 6.28 2.98 3.04 9.65 8.52 ns –1 0.56 6.19 0.04 0.86 0.36 6.30 5.35 2.54 2.59 8.20 7.25 ns –2 0.49 5.43 0.03 0.76 0.32 5.53 4.69 2.23 2.27 7.20 6.36 ns Std. 0.66 5.58 0.04 1.02 0.43 5.68 4.87 3.21 3.42 7.92 7.11 ns –1 0.56 4.75 0.04 0.86 0.36 4.84 4.14 2.73 2.91 6.74 6.05 ns –2 0.49 4.17 0.03 0.76 0.32 4.24 3.64 2.39 2.55 5.91 5.31 ns Std. 0.66 5.21 0.04 1.02 0.43 5.30 4.56 3.26 3.51 7.54 6.80 ns –1 0.56 4.43 0.04 0.86 0.36 4.51 3.88 2.77 2.99 6.41 5.79 ns –2 0.49 3.89 0.03 0.76 0.32 3.96 3.41 2.43 2.62 5.63 5.08 ns Std. 0.66 4.85 0.04 1.02 0.43 4.94 4.54 3.32 3.88 7.18 6.78 ns –1 0.56 4.13 0.04 0.86 0.36 4.20 3.87 2.82 3.30 6.10 5.77 ns –2 0.49 3.62 0.03 0.76 0.32 3.69 3.39 2.48 2.90 5.36 5.06 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. 2 -3 5 R evi s i o n 18 ProASIC3 Flash Family FPGAs Table 2-43 • 3.3 V LVTTL / 3.3 V LVCMOS High Slew Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V Applicable to Standard Plus I/O Banks Drive Strength 2 mA 4 mA 6 mA 8 mA 12 mA 16 mA Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Std. 0.66 7.20 0.04 1.00 0.43 7.34 6.29 2.27 2.34 9.57 8.52 ns –1 0.56 6.13 0.04 0.85 0.36 6.24 5.35 1.93 1.99 8.14 7.25 ns –2 0.49 5.38 0.03 0.75 0.32 5.48 4.69 1.70 1.75 7.15 6.36 ns Std. 0.66 7.20 0.04 1.00 0.43 7.34 6.29 2.27 2.34 9.57 8.52 ns –1 0.56 6.13 0.04 0.85 0.36 6.24 5.35 1.93 1.99 8.14 7.25 ns –2 0.49 5.38 0.03 0.75 0.32 5.48 4.69 1.70 1.75 7.15 6.36 ns Std. 0.66 4.50 0.04 1.00 0.43 4.58 3.82 2.58 2.88 6.82 6.05 ns –1 0.56 3.83 0.04 0.85 0.36 3.90 3.25 2.19 2.45 5.80 5.15 ns –2 0.49 3.36 0.03 0.75 0.32 3.42 2.85 1.92 2.15 5.09 4.52 ns Std. 0.66 4.50 0.04 1.00 0.43 4.58 3.82 2.58 2.88 6.82 6.05 ns –1 0.56 3.83 0.04 0.85 0.36 3.90 3.25 2.19 2.45 5.80 5.15 ns –2 0.49 3.36 0.03 0.75 0.32 3.42 2.85 1.92 2.15 5.09 4.52 ns Std. 0.66 3.16 0.04 1.00 0.43 3.22 2.58 2.79 3.22 5.45 4.82 ns –1 0.56 2.69 0.04 0.85 0.36 2.74 2.20 2.37 2.74 4.64 4.10 ns –2 0.49 2.36 0.03 0.75 0.32 2.40 1.93 2.08 2.41 4.07 3.60 ns Std. 0.66 3.16 0.04 1.00 0.43 3.22 2.58 2.79 3.22 5.45 4.82 ns –1 0.56 2.69 0.04 0.85 0.36 2.74 2.20 2.37 2.74 4.64 4.10 ns –2 0.49 2.36 0.03 0.75 0.32 2.40 1.93 2.08 2.41 4.07 3.60 ns Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. R ev i si o n 1 8 2-36 ProASIC3 DC and Switching Characteristics Table 2-44 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V Applicable to Standard Plus I/O Banks Drive Strength 2 mA 4 mA 6 mA 8 mA 12 mA 16 mA Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Std. 0.66 9.68 0.04 1.00 0.43 9.86 8.42 2.28 2.21 12.09 10.66 ns –1 0.56 8.23 0.04 0.85 0.36 8.39 7.17 1.94 1.88 10.29 9.07 ns –2 0.49 7.23 0.03 0.75 0.32 7.36 6.29 1.70 1.65 9.03 7.96 ns Std. 0.66 9.68 0.04 1.00 0.43 9.86 8.42 2.28 2.21 12.09 10.66 ns –1 0.56 8.23 0.04 0.85 0.36 8.39 7.17 1.94 1.88 10.29 9.07 ns –2 0.49 7.23 0.03 0.75 0.32 7.36 6.29 1.70 1.65 9.03 7.96 ns Std. 0.66 6.70 0.04 1.00 0.43 6.82 5.89 2.58 2.74 9.06 8.12 ns –1 0.56 5.70 0.04 0.85 0.36 5.80 5.01 2.20 2.33 7.71 6.91 ns –2 0.49 5.00 0.03 0.75 0.32 5.10 4.40 1.93 2.05 6.76 6.06 ns Std. 0.66 6.70 0.04 1.00 0.43 6.82 5.89 2.58 2.74 9.06 8.12 ns –1 0.56 5.70 0.04 0.85 0.36 5.80 5.01 2.20 2.33 7.71 6.91 ns –2 0.49 5.00 0.03 0.75 0.32 5.10 4.40 1.93 2.05 6.76 6.06 ns Std. 0.66 5.05 0.04 1.00 0.43 5.14 4.51 2.79 3.08 7.38 6.75 ns –1 0.56 4.29 0.04 0.85 0.36 4.37 3.84 2.38 2.62 6.28 5.74 ns –2 0.49 3.77 0.03 0.75 0.32 3.84 3.37 2.09 2.30 5.51 5.04 ns Std. 0.66 5.05 0.04 1.00 0.43 5.14 4.51 2.79 3.08 7.38 6.75 ns –1 0.56 4.29 0.04 0.85 0.36 4.37 3.84 2.38 2.62 6.28 5.74 ns –2 0.49 3.77 0.03 0.75 0.32 3.84 3.37 2.09 2.30 5.51 5.04 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. Table 2-45 • 3.3 V LVTTL / 3.3 V LVCMOS High Slew Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V Applicable to Standard I/O Banks Drive Strength 2 mA 4 mA 6 mA 8 mA 2 -3 7 Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ Units Std. 0.66 7.07 0.04 1.00 0.43 7.20 6.23 2.07 2.15 ns –1 0.56 6.01 0.04 0.85 0.36 6.12 5.30 1.76 1.83 ns –2 0.49 5.28 0.03 0.75 0.32 5.37 4.65 1.55 1.60 ns Std. 0.66 7.07 0.04 1.00 0.43 7.20 6.23 2.07 2.15 ns –1 0.56 6.01 0.04 0.85 0.36 6.12 5.30 1.76 1.83 ns –2 0.49 5.28 0.03 0.75 0.32 5.37 4.65 1.55 1.60 ns Std. 0.66 4.41 0.04 1.00 0.43 4.49 3.75 2.39 2.69 ns –1 0.56 3.75 0.04 0.85 0.36 3.82 3.19 2.04 2.29 ns –2 0.49 3.29 0.03 0.75 0.32 3.36 2.80 1.79 2.01 ns Std. 0.66 4.41 0.04 1.00 0.43 4.49 3.75 2.39 2.69 ns –1 0.56 3.75 0.04 0.85 0.36 3.82 3.19 2.04 2.29 ns R evi s i o n 18 ProASIC3 Flash Family FPGAs Table 2-45 • 3.3 V LVTTL / 3.3 V LVCMOS High Slew Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V Applicable to Standard I/O Banks Drive Strength Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ Units –2 0.49 3.29 0.03 0.75 0.32 3.36 2.80 1.79 2.01 ns Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. Table 2-46 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V Applicable to Standard I/O Banks Drive Strength 2 mA 4 mA 6 mA 8 mA Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ Units Std. 0.66 9.46 0.04 1.00 0.43 9.64 8.54 2.07 2.04 ns –1 0.56 8.05 0.04 0.85 0.36 8.20 7.27 1.76 1.73 ns –2 0.49 7.07 0.03 0.75 0.32 7.20 6.38 1.55 1.52 ns Std. 0.66 9.46 0.04 1.00 0.43 9.64 8.54 2.07 2.04 ns –1 0.56 8.05 0.04 0.85 0.36 8.20 7.27 1.76 1.73 ns –2 0.49 7.07 0.03 0.75 0.32 7.20 6.38 1.55 1.52 ns Std. 0.66 6.57 0.04 1.00 0.43 6.69 5.98 2.40 2.57 ns –1 0.56 5.59 0.04 0.85 0.36 5.69 5.09 2.04 2.19 ns –2 0.49 4.91 0.03 0.75 0.32 5.00 4.47 1.79 1.92 ns Std. 0.66 6.57 0.04 1.00 0.43 6.69 5.98 2.40 2.57 ns –1 0.56 5.59 0.04 0.85 0.36 5.69 5.09 2.04 2.19 ns –2 0.49 4.91 0.03 0.75 0.32 5.00 4.47 1.79 1.92 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. R ev i si o n 1 8 2-38 ProASIC3 DC and Switching Characteristics 3.3 V LVCMOS Wide Range Table 2-47 • Minimum and Maximum DC Input and Output Levels Applicable to Advanced I/O Banks 3.3 V Equiv. LVCMOS Software Wide Range Default Drive Drive Strength Strength Option1 Min V Max V Min V 100 µA 2 mA –0.3 0.8 100 µA 4 mA –0.3 100 µA 6 mA 100 µA 100 µA 100 µA 100 µA IOSL IOSH IIL2 IIH3 Max mA4 Max mA4 µA5 µA5 VDD – 0.2 100 100 25 27 10 10 0.2 VDD – 0.2 100 100 25 27 10 10 3.6 0.2 VDD – 0.2 100 100 51 54 10 10 2 3.6 0.2 VDD – 0.2 100 100 51 54 10 10 2 3.6 0.2 VDD – 0.2 100 100 103 109 10 10 0.8 2 3.6 0.2 VDD – 0.2 100 100 132 127 10 10 0.8 2 3.6 0.2 VDD – 0.2 100 100 268 181 10 10 VIL VIH VOL VOH Max V Max V Min V 2 3.6 0.2 0.8 2 3.6 –0.3 0.8 2 8 mA –0.3 0.8 12 mA –0.3 0.8 16 mA –0.3 24 mA –0.3 IOL IOH µA µA Notes: 1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ±100 µA. Drive strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models. 2. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL. 3. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is larger when operating outside recommended ranges 4. Currents are measured at 85°C junction temperature. 5. All LVMCOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8-B specification. 6. Software default selection highlighted in gray. Table 2-48 • Minimum and Maximum DC Input and Output Levels Applicable to Standard Plus I/O Banks 3.3 V LVCMOS Wide Range Equiv. Software Default Drive Strength Option1 Min V Max V Min V 100 µA 2 mA –0.3 0.8 100 µA 4 mA –0.3 100 µA 6 mA –0.3 100 µA 8 mA –0.3 0.8 2 3.6 0.2 VDD – 0.2 100 100 51 54 10 10 100 µA 12 mA –0.3 0.8 2 3.6 0.2 VDD – 0.2 100 100 103 109 10 10 100 A 16 mA –0.3 0.8 2 3.6 0.2 VDD – 0.2 100 100 103 109 10 10 Drive Strength VOL VOH IOL IOH IOSL IOSH IIL2 IIH3 Max V Max V Min V µA Max mA4 Max mA4 µA5 µA5 2 3.6 0.2 VDD – 0.2 100 100 25 27 10 10 0.8 2 3.6 0.2 VDD – 0.2 100 100 25 27 10 10 0.8 2 3.6 0.2 VDD – 0.2 100 100 51 54 10 10 VIL VIH µA Notes: 1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ±100 µA. Drive strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models. 2. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL. 3. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is larger when operating outside recommended ranges 4. Currents are measured at 85°C junction temperature. 5. All LVMCOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8-B specification. 6. Software default selection highlighted in gray. 2 -3 9 R evi s i o n 18 ProASIC3 Flash Family FPGAs Table 2-49 • Minimum and Maximum DC Input and Output Levels Applicable to Standard I/O Banks 3.3 V LVCMOS Wide Range Drive Strength Equiv. Software VIL Default Drive Max Strength Min V V Option1 VIH VOL VOH IOL IOH IOSL IOSH IIL2 IIH3 Min V µA µA Max mA4 Max mA4 µA5 µA5 Min V Max V Max V 100 µA 2 mA –0.3 0.8 2 3.6 0.2 VDD – 0.2 100 100 25 27 10 10 100 µA 4 mA –0.3 0.8 2 3.6 0.2 VDD – 0.2 100 100 25 27 10 10 100 µA 6 mA –0.3 0.8 2 3.6 0.2 VDD – 0.2 100 100 51 54 10 10 100 µA 8 mA –0.3 0.8 2 3.6 0.2 VDD – 0.2 100 100 51 54 10 10 Notes: 1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ±100 µA. Drive strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models. 2. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL. 3. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is larger when operating outside recommended ranges 4. Currents are measured at 85°C junction temperature. 5. All LVMCOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8-B specification. 6. Software default selection highlighted in gray. R ev i si o n 1 8 2-40 ProASIC3 DC and Switching Characteristics Timing Characteristics Table 2-50 • 3.3 V LVTTL / 3.3 V LVCMOS High Slew Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V Applicable to Advanced I/O Banks Drive Strength 100 µA 100 µA 100 µA 100 µA 100 µA 100 µA Equiv. Software Default Drive Strength Option1 Speed Grade tDOUT 4 mA Std. 0.60 11.84 0.04 1.02 0.43 11.84 10.00 4.10 4.04 15.23 13.40 ns –1 0.51 10.07 0.04 0.86 0.36 10.07 8.51 3.48 3.44 12.96 11.40 ns –2 0.45 8.84 0.03 0.76 0.32 8.84 7.47 3.06 3.02 11.38 10.00 ns Std. 0.60 7.59 0.04 1.02 0.43 7.59 6.18 4.62 4.95 10.98 9.57 ns –1 0.51 6.45 0.04 0.86 0.36 6.45 5.25 3.93 4.21 9.34 8.14 ns –2 0.45 5.67 0.03 0.76 0.32 5.67 4.61 3.45 3.70 8.20 7.15 ns Std. 0.60 7.59 0.04 1.02 0.43 7.59 6.18 4.62 4.95 10.98 9.57 ns –1 0.51 6.45 0.04 0.86 0.36 6.45 5.25 3.93 4.21 9.34 8.14 ns –2 0.45 5.67 0.03 0.76 0.32 5.67 4.61 3.45 3.70 8.20 7.15 ns Std. 0.60 5.46 0.04 1.02 0.43 5.46 4.29 4.97 5.54 8.86 7.68 ns –1 0.51 4.65 0.04 0.86 0.36 4.65 3.65 4.22 4.71 7.53 6.54 ns –2 0.45 4.08 0.03 0.76 0.32 4.08 3.20 3.71 4.14 6.61 5.74 ns Std. 0.60 5.15 0.04 1.02 0.43 5.15 3.89 5.04 5.69 8.55 7.29 ns –1 0.51 4.38 0.04 0.86 0.36 4.38 3.31 4.29 4.84 7.27 6.20 ns –2 0.45 3.85 0.03 0.76 0.32 3.85 2.91 3.77 4.25 6.38 5.44 ns Std. 0.60 4.75 0.04 1.02 0.43 4.75 3.22 5.14 6.28 8.15 6.61 ns –1 0.51 4.04 0.04 0.86 0.36 4.04 2.74 4.37 5.34 6.93 5.62 ns –2 0.45 3.55 0.03 0.76 0.32 3.55 2.40 3.84 4.69 6.09 4.94 ns 6 mA 8 mA 12 mA 16 mA 24 mA tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Notes: 1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ±100 µA. Drive strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models. 2. Software default selection highlighted in gray. 3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. 2 -4 1 R evi s i o n 18 ProASIC3 Flash Family FPGAs Table 2-51 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V Applicable to Advanced I/O Banks Drive Strength 100 µA 100 µA 100 µA 100 µA 100 µA 100 µA Equiv. Software Default Drive Strength Option1 Speed Grade tDOUT 2 mA Std. 0.60 15.86 0.04 1.54 0.43 15.86 13.51 4.09 3.80 19.25 16.90 ns –1 0.51 13.49 0.04 1.31 0.36 13.49 11.49 3.48 3.23 16.38 14.38 ns –2 0.45 11.84 0.03 1.15 0.32 11.84 10.09 3.05 2.84 14.38 12.62 ns Std. 0.60 11.25 0.04 1.54 0.43 11.25 9.54 4.61 4.70 14.64 12.93 ns –1 0.51 9.57 0.04 1.31 0.36 9.57 8.11 3.92 4.00 12.46 11.00 ns –2 0.45 8.40 0.03 1.15 0.32 8.40 7.12 3.44 3.51 10.93 9.66 ns Std. 0.60 11.25 0.04 1.54 0.43 11.25 9.54 4.61 4.70 14.64 12.93 ns –1 0.51 9.57 0.04 1.31 0.36 9.57 8.11 3.92 4.00 12.46 11.00 ns –2 0.45 8.40 0.03 1.15 0.32 8.40 7.12 3.44 3.51 10.93 9.66 ns Std. 0.60 8.63 0.04 1.54 0.43 8.63 7.39 4.96 5.28 12.02 10.79 ns –1 0.51 7.34 0.04 1.31 0.36 7.34 6.29 4.22 4.49 10.23 9.18 ns –2 0.45 6.44 0.03 1.15 0.32 6.44 5.52 3.70 3.94 8.06 ns Std. 0.60 8.05 0.04 1.54 0.43 8.05 6.93 5.03 5.43 11.44 10.32 ns –1 0.51 6.85 0.04 1.31 0.36 6.85 5.90 4.28 4.62 9.74 8.78 ns –2 0.45 6.01 0.03 1.15 0.32 6.01 5.18 3.76 4.06 8.55 7.71 ns Std. 0.60 7.50 0.04 1.54 0.43 7.50 6.90 5.13 6.00 10.89 10.29 ns –1 0.51 6.38 0.04 1.31 0.36 6.38 5.87 4.36 5.11 9.27 8.76 ns –2 0.45 5.60 0.03 1.15 0.32 5.60 5.15 3.83 4.48 8.13 7.69 ns 4 mA 6 mA 8 mA 16 mA 24 mA tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS 8.98 tZHS Units Notes: 1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ±100 µA. Drive strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. R ev i si o n 1 8 2-42 ProASIC3 DC and Switching Characteristics Table 2-52 • 3.3 V LVTTL / 3.3 V LVCMOS High Slew Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V Applicable to Standard Plus I/O Banks Drive Strength 100 µA 100 µA 100 µA 100 µA 100 µA Equiv. Software Default Drive Strength Option1 Speed Grade tDOUT 2 mA Std. 0.60 11.14 0.04 1.52 –1 0.51 9.48 –2 0.45 Std. 4 mA 6 mA 8 mA 16 mA tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units 0.43 11.14 9.54 3.51 3.61 14.53 12.94 ns 0.04 1.29 0.36 9.48 8.12 2.99 3.07 12.36 11.00 ns 8.32 0.03 1.14 0.32 8.32 7.13 2.62 2.70 10.85 9.66 ns 0.60 6.96 0.04 1.52 0.43 6.96 5.79 3.99 4.45 10.35 9.19 ns –1 0.51 5.92 0.04 1.29 0.36 5.92 4.93 3.39 3.78 8.81 7.82 ns –2 0.45 5.20 0.03 1.14 0.32 5.20 4.33 2.98 3.32 7.73 6.86 ns Std. 0.60 6.96 0.04 1.52 0.43 6.96 5.79 3.99 4.45 10.35 9.19 ns –1 0.51 5.92 0.04 1.29 0.36 5.92 4.93 3.39 3.78 8.81 7.82 ns –2 0.45 5.20 0.03 1.14 0.32 5.20 4.33 2.98 3.32 7.73 6.86 ns Std. 0.60 4.89 0.04 1.52 0.43 4.89 3.92 4.31 4.98 8.28 7.32 ns –1 0.51 4.16 0.04 1.29 0.36 4.16 3.34 3.67 4.24 7.04 6.22 ns –2 0.45 3.65 0.03 1.14 0.32 3.65 2.93 3.22 3.72 6.18 5.46 ns Std. 0.60 4.89 0.04 1.52 0.43 4.89 3.92 4.31 4.98 8.28 7.32 ns –1 0.51 4.16 0.04 1.29 0.36 4.16 3.34 3.67 4.24 7.04 6.22 ns –2 0.45 3.65 0.03 1.14 0.32 3.65 2.93 3.22 3.72 6.18 5.46 ns Notes: 1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ±100 µA. Drive strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models. 2. Software default selection highlighted in gray. 3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. 2 -4 3 R evi s i o n 18 ProASIC3 Flash Family FPGAs Table 2-53 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V Applicable to Standard Plus I/O Banks Drive Strength 100 µA 100 µA 100 µA 100 µA 100 µA Equiv. Software Default Drive Strength Option1 Speed Grade tDOUT 2 mA Std. 0.60 14.97 0.04 1.52 0.43 14.97 12.79 3.52 3.41 18.36 16.18 ns –1 0.51 12.73 0.04 1.29 0.36 12.73 10.88 2.99 2.90 15.62 13.77 ns –2 0.45 11.18 0.03 1.14 0.32 11.18 9.55 2.63 2.55 13.71 12.08 ns Std. 0.60 10.36 0.04 1.52 0.43 10.36 8.93 3.99 4.24 13.75 12.33 ns –1 0.51 8.81 0.04 1.29 0.36 8.81 7.60 3.39 3.60 11.70 10.49 ns –2 0.45 7.74 0.03 1.14 0.32 7.74 6.67 2.98 3.16 10.27 9.21 ns Std. 0.60 10.36 0.04 1.52 0.43 10.36 8.93 3.99 4.24 13.75 12.33 ns –1 0.51 8.81 0.04 1.29 0.36 8.81 7.60 3.39 3.60 11.70 10.49 ns –2 0.45 7.74 0.03 1.14 0.32 7.74 6.67 2.98 3.16 10.27 9.21 ns Std. 0.60 7.81 0.04 1.52 0.43 7.81 6.85 4.32 4.76 11.20 10.24 ns –1 0.51 6.64 0.04 1.29 0.36 6.64 5.82 3.67 4.05 9.53 8.71 ns –2 0.45 5.83 0.03 1.14 0.32 5.83 5.11 3.22 3.56 8.36 7.65 ns Std. 0.60 7.81 0.04 1.52 0.43 7.81 6.85 4.32 4.76 11.20 10.24 ns –1 0.51 6.64 0.04 1.29 0.36 6.64 5.82 3.67 4.05 9.53 8.71 ns –2 0.45 5.83 0.03 1.14 0.32 5.83 5.11 3.22 3.56 8.36 7.65 ns 4 mA 6 mA 8 mA 16 mA tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Notes: 1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ±100 µA. Drive strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. R ev i si o n 1 8 2-44 ProASIC3 DC and Switching Characteristics Table 2-54 • 3.3 V LVTTL / 3.3 V LVCMOS High Slew Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V Applicable to Standard I/O Banks Drive Strength 100 µA 100 µA 100 µA 100 µA Equiv. Software Default Drive Strength Option1 Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ Units 2 mA Std. 0.60 10.93 0.04 1.52 0.43 10.93 9.46 3.20 3.32 ns –1 0.51 9.29 0.04 1.29 0.36 9.29 8.04 2.72 2.82 ns –2 0.45 8.16 0.03 1.13 0.32 8.16 7.06 2.39 2.48 ns Std. 0.60 10.93 0.04 1.52 0.43 10.93 9.46 3.20 3.32 ns –1 0.51 9.29 0.04 1.29 0.36 9.29 8.04 2.72 2.82 ns –2 0.45 8.16 0.03 1.13 0.32 8.16 7.06 2.39 2.48 ns Std. 0.60 6.82 0.04 1.52 0.43 6.82 5.70 3.70 4.16 ns –1 0.51 5.80 0.04 1.29 0.36 5.80 4.85 3.15 3.54 ns –2 0.45 5.09 0.03 1.13 0.32 5.09 4.25 2.77 3.11 ns Std. 0.60 6.82 0.04 1.52 0.43 6.82 5.70 3.70 4.16 ns –1 0.51 5.80 0.04 1.29 0.36 5.80 4.85 3.15 3.54 ns –2 0.45 5.09 0.03 1.13 0.32 5.09 4.25 2.77 3.11 ns 4 mA 6 mA 8 mA Notes: 1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ±100 µA. Drive strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models. 2. Software default selection highlighted in gray. 3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. 2 -4 5 R evi s i o n 18 ProASIC3 Flash Family FPGAs Table 2-55 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V Applicable to Standard I/O Banks Drive Strength 100 µA 100 µA 100 µA 100 µA Equiv. Software Default Drive Strength Option1 Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ Units 2 mA Std. 0.60 14.64 0.04 1.52 0.43 14.64 12.97 3.21 3.15 ns –1 0.51 12.45 0.04 1.29 0.36 12.45 11.04 2.73 2.68 ns –2 0.45 10.93 0.03 1.13 0.32 10.93 9.69 2.39 2.35 ns Std. 0.60 14.64 0.04 1.52 0.43 14.64 12.97 3.21 3.15 ns –1 0.51 12.45 0.04 1.29 0.36 12.45 11.04 2.73 2.68 ns –2 0.45 10.93 0.03 1.13 0.32 10.93 9.69 2.39 2.35 ns Std. 0.60 10.16 0.04 1.52 0.43 10.16 9.08 3.71 3.98 ns –1 0.51 8.64 0.04 1.29 0.36 8.64 7.73 3.15 3.39 ns –2 0.45 7.58 0.03 1.13 0.32 7.58 6.78 2.77 2.97 ns Std. 0.60 10.16 0.04 1.52 0.43 10.16 9.08 3.71 3.98 ns –1 0.51 8.64 0.04 1.29 0.36 8.64 7.73 3.15 3.39 ns –2 0.45 7.58 0.03 1.13 0.32 7.58 6.78 2.77 2.97 ns 4 mA 6 mA 8 mA Notes: 1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ±100 µA. Drive strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. R ev i si o n 1 8 2-46 ProASIC3 DC and Switching Characteristics 2.5 V LVCMOS Low-Voltage CMOS for 2.5 V is an extension of the LVCMOS standard (JESD8-5) used for general-purpose 2.5 V applications. Table 2-56 • Minimum and Maximum DC Input and Output Levels Applicable to Advanced I/O Banks 2.5 V LVCMOS VIL VIH VOL VOH IOL IOH IOSL IOSH IIL1 IIH2 mA mA Max. mA3 Max. mA3 µA4 µA4 Drive Strength Min. V Max. V Min. V Max. V Max. V Min. V 2 mA –0.3 0.7 1.7 2.7 0.7 1.7 2 2 18 16 10 10 4 mA –0.3 0.7 1.7 2.7 0.7 1.7 4 4 18 16 10 10 6 mA –0.3 0.7 1.7 2.7 0.7 1.7 6 6 37 32 10 10 8 mA –0.3 0.7 1.7 2.7 0.7 1.7 8 8 37 32 10 10 12 mA –0.3 0.7 1.7 2.7 0.7 1.7 12 12 74 65 10 10 16 mA –0.3 0.7 1.7 2.7 0.7 1.7 16 16 87 83 10 10 24 mA –0.3 0.7 1.7 2.7 0.7 1.7 24 24 124 169 10 10 Notes: 1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL. 2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is larger when operating outside recommended ranges 3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage. 4. Currents are measured at 85°C junction temperature. 5. Software default selection highlighted in gray. Table 2-57 • Minimum and Maximum DC Input and Output Levels Applicable to Standard Plus I/O Banks 2.5 V LVCMOS VIL VIH VOL VOH IOL IOH IOSL IOSH IIL1 IIH2 mA mA Max. mA3 Max. mA3 µA4 µA4 Drive Strength Min. V Max. V Min. V Max. V Max. V Min. V 2 mA –0.3 0.7 1.7 2.7 0.7 1.7 2 2 18 16 10 10 4 mA –0.3 0.7 1.7 2.7 0.7 1.7 4 4 18 16 10 10 6 mA –0.3 0.7 1.7 2.7 0.7 1.7 6 6 37 32 10 10 8 mA –0.3 0.7 1.7 2.7 0.7 1.7 8 8 37 32 10 10 12 mA –0.3 0.7 1.7 2.7 0.7 1.7 12 12 74 65 10 10 Notes: 1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL. 2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is larger when operating outside recommended ranges 3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage. 4. Currents are measured at 85°C junction temperature. 5. Software default selection highlighted in gray. 2 -4 7 R evi s i o n 18 ProASIC3 Flash Family FPGAs Table 2-58 • Minimum and Maximum DC Input and Output Levels Applicable to Standard I/O Banks 2.5 V LVCMOS VIL VIH VOL VOH IOL IOH IOSL IOSH IIL1 IIH2 mA mA Max. mA3 Max. mA3 µA4 µA4 16 18 Drive Strength Min. V Max., V Min. V Max. V Max. V Min. V 2 mA –0.3 0.7 1.7 3.6 0.7 1.7 2 2 10 10 4 mA –0.3 0.7 1.7 3.6 0.7 1.7 4 4 16 18 10 10 6 mA –0.3 0.7 1.7 3.6 0.7 1.7 6 6 32 37 10 10 8 mA –0.3 0.7 1.7 3.6 0.7 1.7 8 8 32 37 10 10 Notes: 1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL. 2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is larger when operating outside recommended ranges. 3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage. 4. Currents are measured at 85°C junction temperature. 5. Software default selection highlighted in gray. R = 1 kΩ Test Point Enable Path Test Point Datapath Figure 2-8 • 35 pF R to VCCI for tLZ / tZL / tZLS R to GND for tHZ / tZH / tZHS 35 pF for tZH / tZHS / tZL / tZLS 35 pF for tHZ / tLZ AC Loading Table 2-59 • AC Waveforms, Measuring Points, and Capacitive Loads Input Low (V) 0 Input High (V) Measuring Point* (V) CLOAD (pF) 2.5 1.2 35 Note: *Measuring point = Vtrip. See Table 2-22 on page 2-22 for a complete table of trip points. R ev i si o n 1 8 2-48 ProASIC3 DC and Switching Characteristics Timing Characteristics Table 2-60 • 2.5 V LVCMOS High Slew Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V Applicable to Advanced I/O Banks Drive Strength 4 mA 6 mA 8 mA 12 mA 16 mA 24 mA Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Std. 0.60 8.66 0.04 1.31 0.43 7.83 8.66 2.68 2.30 10.07 10.90 ns –1 0.51 7.37 0.04 1.11 0.36 6.66 7.37 2.28 1.96 8.56 9.27 ns –2 0.45 6.47 0.03 0.98 0.32 5.85 6.47 2.00 1.72 7.52 8.14 ns Std. 0.60 5.17 0.04 1.31 0.43 5.04 5.17 3.05 3.00 7.27 7.40 ns –1 0.51 4.39 0.04 1.11 0.36 4.28 4.39 2.59 2.55 6.19 6.30 ns –2 0.45 3.86 0.03 0.98 0.32 3.76 3.86 2.28 2.24 5.43 5.53 ns Std. 0.60 5.17 0.04 1.31 0.43 5.04 5.17 3.05 3.00 7.27 7.40 ns –1 0.51 4.39 0.04 1.11 0.36 4.28 4.39 2.59 2.55 6.19 6.30 ns –2 0.45 3.86 0.03 0.98 0.32 3.76 3.86 2.28 2.24 5.43 5.53 ns Std. 0.60 3.56 0.04 1.31 0.43 3.63 3.43 3.30 3.44 5.86 5.67 ns –1 0.51 3.03 0.04 1.11 0.36 3.08 2.92 2.81 2.92 4.99 4.82 ns –2 0.45 2.66 0.03 0.98 0.32 2.71 2.56 2.47 2.57 4.38 4.23 ns Std. 0.60 3.35 0.04 1.31 0.43 3.41 3.06 3.36 3.55 5.65 5.30 ns –1 0.51 2.85 0.04 1.11 0.36 2.90 2.60 2.86 3.02 4.81 4.51 ns –2 0.45 2.50 0.03 0.98 0.32 2.55 2.29 2.51 2.65 4.22 3.96 ns Std. 0.60 3.09 0.04 1.31 0.43 3.15 2.44 3.44 4.00 5.38 4.68 ns –1 0.51 2.63 0.04 1.11 0.36 2.68 2.08 2.92 3.40 4.58 3.98 ns –2 0.45 2.31 0.03 0.98 0.32 2.35 1.82 2.57 2.98 4.02 3.49 ns Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. 2 -4 9 R evi s i o n 18 ProASIC3 Flash Family FPGAs Table 2-61 • 2.5 V LVCMOS Low Slew Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V Applicable to Advanced I/O Banks Drive Strength 4 mA 6 mA 8 mA 12 mA 16 mA 24 mA Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Std. 0.60 11.40 0.04 1.31 0.43 11.22 11.40 2.68 2.20 13.45 13.63 ns –1 0.51 9.69 0.04 1.11 0.36 9.54 9.69 2.28 1.88 11.44 11.60 ns –2 0.45 8.51 0.03 0.98 0.32 8.38 8.51 2.00 1.65 10.05 10.18 ns Std. 0.60 7.96 0.04 1.31 0.43 8.11 7.81 3.05 2.89 10.34 10.05 ns –1 0.51 6.77 0.04 1.11 0.36 6.90 6.65 2.59 2.46 8.80 8.55 ns –2 0.45 5.94 0.03 0.98 0.32 6.05 5.84 2.28 2.16 7.72 7.50 ns Std. 0.60 7.96 0.04 1.31 0.43 8.11 7.81 3.05 2.89 10.34 10.05 ns –1 0.51 6.77 0.04 1.11 0.36 6.90 6.65 2.59 2.46 8.80 8.55 ns –2 0.45 5.94 0.03 0.98 0.32 6.05 5.84 2.28 2.16 7.72 7.50 ns Std. 0.60 6.18 0.04 1.31 0.43 6.29 5.92 3.30 3.32 8.53 8.15 ns –1 0.51 5.26 0.04 1.11 0.36 5.35 5.03 2.81 2.83 7.26 6.94 ns –2 0.45 4.61 0.03 0.98 0.32 4.70 4.42 2.47 2.48 6.37 6.09 ns Std. 0.60 5.76 0.04 1.31 0.43 5.87 5.53 3.36 3.44 8.11 7.76 ns –1 0.51 4.90 0.04 1.11 0.36 4.99 4.70 2.86 2.92 6.90 6.60 ns –2 0.45 4.30 0.03 0.98 0.32 4.38 4.13 2.51 2.57 6.05 5.80 ns Std. 0.60 5.51 0.04 1.31 0.43 5.50 5.51 3.43 3.87 7.74 7.74 ns –1 0.51 4.68 0.04 1.11 0.36 4.68 4.68 2.92 3.29 6.58 6.59 ns –2 0.45 4.11 0.03 0.98 0.32 4.11 4.11 2.56 2.89 5.78 5.78 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. R ev i si o n 1 8 2-50 ProASIC3 DC and Switching Characteristics Table 2-62 • 2.5 V LVCMOS High Slew Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V Applicable to Standard Plus I/O Banks Drive Strength 4 mA 6 mA 8 mA 12 mA Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Std. 0.66 8.28 0.04 1.30 0.43 7.41 8.28 2.25 2.07 9.64 10.51 ns –1 0.56 7.04 0.04 1.10 0.36 6.30 7.04 1.92 1.76 8.20 8.94 ns –2 0.49 6.18 0.03 0.97 0.32 5.53 6.18 1.68 1.55 7.20 7.85 ns Std. 0.66 4.85 0.04 1.30 0.43 4.65 4.85 2.59 2.71 6.88 7.09 ns –1 0.56 4.13 0.04 1.10 0.36 3.95 4.13 2.20 2.31 5.85 6.03 ns –2 0.49 3.62 0.03 0.97 0.32 3.47 3.62 1.93 2.02 5.14 5.29 ns Std. 0.66 4.85 0.04 1.30 0.43 4.65 4.85 2.59 2.71 6.88 7.09 ns –1 0.56 4.13 0.04 1.10 0.36 3.95 4.13 2.20 2.31 5.85 6.03 ns –2 0.49 3.62 0.03 0.97 0.32 3.47 3.62 1.93 2.02 5.14 5.29 ns Std. 0.66 3.21 0.04 1.30 0.43 3.27 3.14 2.82 3.11 5.50 5.38 ns –1 0.56 2.73 0.04 1.10 0.36 2.78 2.67 2.40 2.65 4.68 4.57 ns –2 0.49 2.39 0.03 0.97 0.32 2.44 2.35 2.11 2.32 4.11 4.02 ns Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. Table 2-63 • 2.5 V LVCMOS Low Slew Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V Applicable to Standard Plus I/O Banks Drive Strength 4 mA 6 mA 8 mA 12 mA Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units Std. 0.66 10.84 0.04 1.30 0.43 10.64 10.84 2.26 1.99 12.87 13.08 ns –1 0.56 9.22 0.04 1.10 0.36 9.05 9.22 1.92 1.69 10.95 11.12 ns –2 0.49 8.10 0.03 0.97 0.32 7.94 8.10 1.68 1.49 9.61 9.77 ns Std. 0.66 7.37 0.04 1.30 0.43 7.50 7.36 2.59 2.61 9.74 9.60 ns –1 0.56 6.27 0.04 1.10 0.36 6.38 6.26 2.20 2.22 8.29 8.16 ns –2 0.49 5.50 0.03 0.97 0.32 5.60 5.50 1.93 1.95 7.27 7.17 ns Std. 0.66 7.37 0.04 1.30 0.43 7.50 7.36 2.59 2.61 9.74 9.60 ns –1 0.56 6.27 0.04 1.10 0.36 6.38 6.26 2.20 2.22 8.29 8.16 ns –2 0.49 5.50 0.03 0.97 0.32 5.60 5.50 1.93 1.95 7.27 7.17 ns Std. 0.66 5.63 0.04 1.30 0.43 5.73 5.51 2.83 3.01 7.97 7.74 ns –1 0.56 4.79 0.04 1.10 0.36 4.88 4.68 2.41 2.56 6.78 6.59 ns –2 0.49 4.20 0.03 0.97 0.32 4.28 4.11 2.11 2.25 5.95 5.78 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. 2 -5 1 R evi s i o n 18 ProASIC3 Flash Family FPGAs Table 2-64 • 2.5 V LVCMOS High Slew Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V Applicable to Standard I/O Banks Drive Strength 2 mA 4 mA 6 mA 8 mA Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ Units Std. 0.66 8.20 0.04 1.29 0.43 7.24 8.20 2.03 1.91 ns –1 0.56 6.98 0.04 1.10 0.36 6.16 6.98 1.73 1.62 ns –2 0.49 6.13 0.03 0.96 0.32 5.41 6.13 1.52 1.43 ns Std. 0.66 8.20 0.04 1.29 0.43 7.24 8.20 2.03 1.91 ns –1 0.56 6.98 0.04 1.10 0.36 6.16 6.98 1.73 1.62 ns –2 0.49 6.13 0.03 0.96 0.32 5.41 6.13 1.52 1.43 ns Std. 0.66 4.77 0.04 1.29 0.43 4.55 4.77 2.38 2.55 ns –1 0.56 4.05 0.04 1.10 0.36 3.87 4.05 2.03 2.17 ns –2 0.49 3.56 0.03 0.96 0.32 3.40 3.56 1.78 1.91 ns Std. 0.66 4.77 0.04 1.29 0.43 4.55 4.77 2.38 2.55 ns –1 0.56 4.05 0.04 1.10 0.36 3.87 4.05 2.03 2.17 ns –2 0.49 3.56 0.03 0.96 0.32 3.40 3.56 1.78 1.91 ns Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. Table 2-65 • 2.5 V LVCMOS Low Slew Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V Applicable to Standard I/O Banks Drive Strength 2 mA 4 mA 6 mA 8 mA Speed Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ Units Std. 0.66 11.00 0.04 1.29 0.43 10.37 11.00 2.03 1.83 ns –1 0.56 9.35 0.04 1.10 0.36 8.83 9.35 1.73 1.56 ns –2 0.49 8.21 0.03 0.96 0.32 7.75 8.21 1.52 1.37 ns Std. 0.66 11.00 0.04 1.29 0.43 10.37 11.00 2.03 1.83 ns –1 0.56 9.35 0.04 1.10 0.36 8.83 9.35 1.73 1.56 ns –2 0.49 8.21 0.03 0.96 0.32 7.75 8.21 1.52 1.37 ns Std. 0.66 7.50 0.04 1.29 0.43 7.36 7.50 2.39 2.46 ns –1 0.56 6.38 0.04 1.10 0.36 6.26 6.38 2.03 2.10 ns –2 0.49 5.60 0.03 0.96 0.32 5.49 5.60 1.78 1.84 ns Std. 0.66 7.50 0.04 1.29 0.43 7.36 7.50 2.39 2.46 ns –1 0.56 6.38 0.04 1.10 0.36 6.26 6.38 2.03 2.10 ns –2 0.49 5.60 0.03 0.96 0.32 5.49 5.60 1.78 1.84 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. R ev i si o n 1 8 2-52 ProASIC3 DC and Switching Characteristics 1.8 V LVCMOS Low-voltage CMOS for 1.8 V is an extension of the LVCMOS standard (JESD8-5) used for general-purpose 1.8 V applications. It uses a 1.8 V input buffer and a push-pull output buffer. Table 2-66 • Minimum and Maximum DC Input and Output Levels Applicable to Advanced I/O Banks 1.8 V LVCMOS VIL VIH VOL VOH IOL IOH IOSL IOSH IIL1 IIH2 mA mA Max mA3 Max mA3 µA4 µA4 Drive Strength Min V Max V Min V Max V Max V Min V 2 mA –0.3 0.35 * VCCI 0.65 * VCCI 1.9 0.45 VCCI – 0.45 2 2 11 9 10 10 4 mA –0.3 0.35 * VCCI 0.65 * VCCI 1.9 0.45 VCCI – 0.45 4 4 22 17 10 10 6 mA –0.3 0.35 * VCCI 0.65 * VCCI 1.9 0.45 VCCI – 0.45 6 6 44 35 10 10 8 mA –0.3 0.35 * VCCI 0.65 * VCCI 1.9 0.45 VCCI – 0.45 8 8 51 45 10 10 12 mA –0.3 0.35 * VCCI 0.65 * VCCI 1.9 0.45 VCCI – 0.45 12 12 74 91 10 10 16 mA –0.3 0.35 * VCCI 0.65 * VCCI 1.9 0.45 VCCI – 0.45 16 16 74 91 10 10 Notes: 1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL. 2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is larger when operating outside recommended ranges 3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage. 4. Currents are measured at 85°C junction temperature. 5. Software default selection highlighted in gray. Table 2-67 • Minimum and Maximum DC Input and Output Levels Applicable to Standard Plus I/O I/O Banks 1.8 V LVCMOS Drive Strength VIL Min V Max V VIH Min V Max V VOL VOH IOL IOH IOSL Max V Min V mA mA Max mA3 IOSH IIL1 IIH2 Max mA3 µA4 µA4 2 mA –0.3 0.35 * VCCI 0.65 * VCCI 3.6 0.45 VCCI – 0.45 2 2 11 9 10 10 4 mA –0.3 0.35 * VCCI 0.65 * VCCI 3.6 0.45 VCCI – 0.45 4 4 22 17 10 10 6 mA –0.3 0.35 * VCCI 0.65 * VCCI 3.6 0.45 VCCI – 0.45 6 6 44 35 10 10 8 mA –0.3 0.35 * VCCI 0.65 * VCCI 3.6 0.45 VCCI – 0.45 8 8 44 35 10 10 Notes: 1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL. 2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN
A3P400-1FGG144
物料型号 文档中提到了多种型号,例如A3P250、A3P400、A3P600和A3P1000,这些型号可能代表了不同的配置或性能特性。

器件简介 文档中没有提供具体的器件简介,但从上下文中可以推断,这些型号属于Microsemi的ProASIC3 Flash Family FPGAs,即现场可编程门阵列。

引脚分配 文档详细列出了不同封装类型(如FG144、FG256、FG484)的引脚分配情况。例如,FG144封装的A3P250型号的引脚分配包括多种不同的I/O功能和电源引脚。

参数特性 文档中包含了一些参数特性,如VCCIBx I/O Supply Voltage,但具体的参数特性需要结合具体的型号和引脚来分析。

功能详解 文档中没有提供详细的功能解释,但从引脚分配可以推测,这些FPGA支持多种I/O标准和功能,如GFA(通用I/O功能),GFC(配置时钟功能)等。

应用信息 文档中没有直接提供应用信息,但可以推断这些FPGA适用于需要可编程逻辑和I/O灵活性的应用。

封装信息 文档提供了不同型号FPGA的封装信息,包括但不限于FG144、FG256和FG484等封装类型,每种封装都有其特定的引脚分配和功能。
A3P400-1FGG144 价格&库存

很抱歉,暂时无法提供与“A3P400-1FGG144”相匹配的价格&库存,您可以联系我们找货

免费人工找货