A3PE3000-1PQG896PP

v1.0 ProASIC3E Flash Family FPGAs with Optional Soft ARM® Support Features and Benefits High Capacity • 600 k to 3 Million System Gates • 108 to 504 kbits of True Dual-Port SRAM • Up to 620 User I/Os ® Reprogrammable Flash Technology • • • • 130-nm, 7-Layer Metal (6 Copper), Flash-Based CMOS Process Live at Power-Up (LAPU) Level 0 Support Single-Chip Solution Retains Programmed Design when Powered Off On-Chip User Nonvolatile Memory • 1 kbit of FlashROM with Synchronous Interfacing High Performance • 350 MHz System Performance • 3.3 V, 66 MHz 64-Bit PCI In-System Programming (ISP) and Security • Secure ISP Using On-Chip 128-Bit Advanced Encryption Standard (AES) Decryption via JTAG (IEEE 1532–compliant) • FlashLock® to Secure FPGA Contents • 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation • Bank-Selectable I/O Voltages—up to 8 Banks per Chip • Single-Ended I/O Standards: LVTTL, LVCMOS 3.3 V / 2.5 V / 1.8 V / 1.5 V, 3.3 V PCI / 3.3 V PCI-X, and LVCMOS 2.5 V / 5.0 V Input • Differential I/O Standards: LVPECL, LVDS, B-LVDS, and M-LVDS • Voltage-Referenced I/O Standards: GTL+ 2.5 V / 3.3 V, GTL 2.5 V / 3.3 V, HSTL Class I and II, SSTL2 Class I and II, SSTL3 Class I and II • I/O Registers on Input, Output, and Enable Paths • Hot-Swappable and Cold Sparing I/Os • Programmable Output Slew Rate and Drive Strength • Programmable Input Delay • Schmitt Trigger Option on Single-Ended Inputs • Weak Pull-Up/-Down • IEEE 1149.1 (JTAG) Boundary Scan Test • Pin-Compatible Packages across the ProASIC®3E Family Clock Conditioning Circuit (CCC) and PLL • Six CCC Blocks, Each with an Integrated PLL • Configurable Phase-Shift, Multiply/Divide, Capabilities and External Feedback • Wide Input Frequency Range (1.5 MHz to 200 MHz) Delay Low Power • Core Voltage for Low Power • Support for 1.5-V-Only Systems • Low-Impedance Flash Switches SRAMs and FIFOs • Variable-Aspect-Ratio 4,608-Bit RAM Blocks (×1, ×2, ×4, ×9, and ×18 organizations available) • True Dual-Port SRAM (except ×18) • 24 SRAM and FIFO Configurations with Synchronous Operation up to 350 MHz ® • M1 ProASIC3E Devices—Cortex-M1 Soft Processor Available with or without Debug High-Performance Routing Hierarchy • • • • • Segmented, Hierarchical Routing and Clock Structure Ultra-Fast Local and Long-Line Network Enhanced High-Speed, Very-Long-Line Network High-Performance, Low-Skew Global Network Architecture Supports Ultra-High Utilization ARM Processor Support in ProASIC3E FPGAs Pro (Professional) I/O • 700 Mbps DDR, LVDS-Capable I/Os Table 1-1 • ProASIC3E Product Family ProASIC3E Devices Cortex-M1 Devices System Gates VersaTiles (D-flip-flops) RAM kbits (1,024 bits) 4,608-Bit Blocks FlashROM Bits Secure (AES) ISP CCCs with Integrated PLLs2 VersaNet Globals I/O Banks Maximum User I/Os Package Pins PQFP FBGA 3 1 A3PE600 600 k 13,824 108 24 1k Yes 6 18 8 270 PQ208 FG256, FG484 A3PE1500 M1A3PE1500 1.5 M 38,400 270 60 1k Yes 6 18 8 444 PQ208 FG484, FG676 A3PE3000 M1A3PE3000 3M 75,264 504 112 1k Yes 6 18 8 620 PQ208 FG324, FG484, FG896 Notes: 1. Refer to the Cortex-M1 product brief for more information. 2. The PQ208 package has six CCCs and two PLLs. 3. Six chip (main) and three quadrant global networks are available. 4. For devices supporting lower densities, refer to the ProASIC3 Flash Family FPGAs handbook. March 2008 © 2008 Actel Corporation I I/Os Per Package1 ProASIC3E Devices Cortex-M1 Devices2 A3PE600 A3PE1500 3 M1A3PE1500 I/O Types Differential I/O Pairs Differential I/O Pairs Differential I/O Pairs 65 – 110 168 – 310 Single-Ended I/O1 Single-Ended I/O1 Single-Ended I/O1 147 – 221 341 – 620 A3PE3000 3 M1A3PE3000 Package PQ208 FG256 FG324 FG484 FG676 FG896 Notes: 147 165 – 270 – – 65 79 – 135 – – 147 – – 280 444 – 65 – – 139 222 – 1. When considering migrating your design to a lower- or higher-density device, refer to the ProASIC3E Flash Family FPGAs handbook to ensure compliance with design and board migration requirements. 2. Each used differential I/O pair reduces the number of single-ended I/Os available by two. 3. For A3PE1500 and A3PE3000 devices, the usage of certain I/O standards is limited as follows: – SSTL3(I) and (II): up to 40 I/Os per north or south bank – LVPECL / GTL+ 3.3 V / GTL 3.3 V: up to 48 I/Os per north or south bank – SSTL2(I) and (II) / GTL+ 2.5 V/ GTL 2.5 V: up to 72 I/Os per north or south bank 4. FG256 and FG484 are footprint-compatible packages. 5. When using voltage-referenced I/O standards, one I/O pin should be assigned as a voltage-referenced pin (VREF) per minibank (group of I/Os). 6. "G" indicates RoHS-compliant packages. Refer to the "ProASIC3E Ordering Information" on page III for the location of the "G" in the part number. II v1.0 ProASIC3E Flash Family FPGAs ProASIC3E Ordering Information A3PE3000 _ 1 FG G 896 I Application (Temperature Range) Blank = Commercial (0°C to +70°C Ambient Temperature) I = Industrial (–40°C to +85°C Ambient Temperature) PP = Pre-Production ES = Engineering Sample (Room Temperature Only) Package Lead Count Lead-Free Packaging Blank = Standard Packaging G = RoHS-Compliant (Green) Packaging Package Type PQ = Plastic Quad Flat Pack (0.5 mm pitch) FG = Fine Pitch Ball Grid Array (1.0 mm pitch) Speed Grade F= Blank = 1= 2= 20% Slower than Standard* Standard 15% Faster than Standard 25% Faster than Standard Part Number ProASIC3E Devices A3PE600 = 600,000 System Gates A3PE1500 = 1,500,000 System Gates A3PE3000 = 3,000,000 System Gates ProASIC3E Devices with Cortex-M1 M1A3PE1500 = 1,500,000 System Gates M1A3PE3000 = 3,000,000 System Gates * The DC and switching characteristics for the –F speed grade targets are based only on simulation. The characteristics provided for the –F speed grade are subject to change after establishing FPGA specifications. Some restrictions might be added and will be reflected in future revisions of this document. The –F speed grade is only supported in the commercial temperature range. v1.0 III Temperature Grade Offerings Package Cortex-M1 Devices PQ208 FG256 FG324 FG484 FG676 FG896 C, I C, I – C, I – – A3PE600 A3PE1500 M1A3PE1500 C, I – – C, I C, I – A3PE3000 M1A3PE3000 C, I – C, I C, I – C, I Note: C = Commercial temperature range: 0°C to 70°C ambient temperature I = Industrial temperature range: –40°C to 85°C ambient temperature Speed Grade and Temperature Grade Matrix Temperature Grade C2 I3 Notes: 1. The DC and switching characteristics for the –F speed grade targets are based only on simulation. The characteristics provided for the –F speed grade are subject to change after establishing FPGA specifications. Some restrictions might be added and will be reflected in future revisions of this document. The –F speed grade is only supported in the commercial temperature range. 2. C = Commercial temperature range: 0°C to 70°C ambient temperature 3. I = Industrial temperature range: –40°C to 85°C ambient temperature References made to ProASIC3E devices also apply to ARM-enabled ProASIC3E devices. The ARM-enabled part numbers start with M1 (Cortex-M1). Contact your local Actel representative for device availability: http://www.actel.com/contact/default.aspx. –F 1 Std. –1 –2 ✓ – ✓ ✓ ✓ ✓ ✓ ✓ IV v1.0 1 – ProASIC3E Device Family Overview General Description ProASIC3E, the third-generation family of Actel flash FPGAs, offers performance, density, and features beyond those of the ProASICPLUS® family. Nonvolatile flash technology gives ProASIC3E devices the advantage of being a secure, low-power, single-chip solution that is live at power-up (LAPU). ProASIC3E is reprogrammable and offers time-to-market benefits at an ASIC-level unit cost. These features enable designers to create high-density systems using existing ASIC or FPGA design flows and tools. ProASIC3E devices offer 1 kbit of on-chip, programmable, nonvolatile FlashROM storage as well as clock conditioning circuitry based on six integrated phase-locked loops (PLLs). ProASIC3E devices have up to three million system gates, supported with up to 504 kbits of true dual-port SRAM and up to 620 user I/Os. Several ProASIC3E devices support the Cortex-M1 soft IP cores, and the ARM-Enabled devices have Actel ordering numbers that begin with M1A3PE. Flash Advantages Reduced Cost of Ownership Advantages to the designer extend beyond low unit cost, performance, and ease of use. Unlike SRAM-based FPGAs, flash-based ProASIC3E devices allow all functionality to be live at power-up; no external boot PROM is required. On-board security mechanisms prevent access to all the programming information and enable secure remote updates of the FPGA logic. Designers can perform secure remote in-system reprogramming to support future design iterations and field upgrades with confidence that valuable intellectual property (IP) cannot be compromised or copied. Secure ISP can be performed using the industry-standard AES algorithm. The ProASIC3E family device architecture mitigates the need for ASIC migration at higher user volumes. This makes the ProASIC3E family a cost-effective ASIC replacement solution, especially for applications in the consumer, networking/ communications, computing, and avionics markets. Security The nonvolatile, flash-based ProASIC3E devices do not require a boot PROM, so there is no vulnerable external bitstream that can be easily copied. ProASIC3E devices incorporate FlashLock, which provides a unique combination of reprogrammability and design security without external overhead, advantages that only an FPGA with nonvolatile flash programming can offer. ProASIC3E devices utilize a 128-bit flash-based lock and a separate AES key to secure programmed intellectual property and configuration data. In addition, all FlashROM data in ProASIC3E devices can be encrypted prior to loading, using the industry-leading AES-128 (FIPS192) bit block cipher encryption standard. The AES standard was adopted by the National Institute of Standards and Technology (NIST) in 2000 and replaces the 1977 DES standard. ProASIC3E devices have a built-in AES decryption engine and a flash-based AES key that make them the most comprehensive programmable logic device security solution available today. ProASIC3E devices with AES-based security allow for secure, remote field updates over public networks such as the Internet, and ensure that valuable IP remains out of the hands of system overbuilders, system cloners, and IP thieves. The contents of a programmed ProASIC3E device cannot be read back, although secure design verification is possible. Security, built into the FPGA fabric, is an inherent component of the ProASIC3E family. The flash cells are located beneath seven metal layers, and many device design and layout techniques have been used to make invasive attacks extremely difficult. The ProASIC3E family, with FlashLock and AES security, is unique in being highly resistant to both invasive and noninvasive attacks. Your v 1.0 1-1 ProASIC3E Device Family Overview valuable IP is protected and secure, making remote ISP possible. A ProASIC3E device provides the most impenetrable security for programmable logic designs. Single Chip Flash-based FPGAs store their configuration information in on-chip flash cells. Once programmed, the configuration data is an inherent part of the FPGA structure, and no external configuration data needs to be loaded at system power-up (unlike SRAM-based FPGAs). Therefore, flash-based ProASIC3E FPGAs do not require system configuration components such as EEPROMs or microcontrollers to load device configuration data. This reduces bill-of-materials costs and PCB area, and increases security and system reliability. Live at Power-Up The Actel flash-based ProASIC3E devices support Level 0 of the LAPU classification standard. This feature helps in system component initialization, execution of critical tasks before the processor wakes up, setup and configuration of memory blocks, clock generation, and bus activity management. The LAPU feature of flash-based ProASIC3E devices greatly simplifies total system design and reduces total system cost, often eliminating the need for CPLDs and clock generation PLLs that are used for these purposes in a system. In addition, glitches and brownouts in system power will not corrupt the ProASIC3E device's flash configuration, and unlike SRAM-based FPGAs, the device will not have to be reloaded when system power is restored. This enables the reduction or complete removal of the configuration PROM, expensive voltage monitor, brownout detection, and clock generator devices from the PCB design. Flash-based ProASIC3E devices simplify total system design and reduce cost and design risk while increasing system reliability and improving system initialization time. Firm Errors Firm errors occur most commonly when high-energy neutrons, generated in the upper atmosphere, strike a configuration cell of an SRAM FPGA. The energy of the collision can change the state of the configuration cell and thus change the logic, routing, or I/O behavior in an unpredictable way. These errors are impossible to prevent in SRAM FPGAs. The consequence of this type of error can be a complete system failure. Firm errors do not exist in the configuration memory of ProASIC3E flashbased FPGAs. Once it is programmed, the flash cell configuration element of ProASIC3E FPGAs cannot be altered by high-energy neutrons and is therefore immune to them. Recoverable (or soft) errors occur in the user data SRAM of all FPGA devices. These can easily be mitigated by using error detection and correction (EDAC) circuitry built into the FPGA fabric. Low Power Flash-based ProASIC3E devices exhibit power characteristics similar to an ASIC, making them an ideal choice for power-sensitive applications. ProASIC3E devices have only a very limited power-on current surge and no high-current transition period, both of which occur on many FPGAs. ProASIC3E devices also have low dynamic power consumption to further maximize power savings. Advanced Flash Technology The ProASIC3E family offers many benefits, including nonvolatility and reprogrammability through an advanced flash-based, 130-nm LVCMOS process with seven layers of metal. Standard CMOS design techniques are used to implement logic and control functions. The combination of fine granularity, enhanced flexible routing resources, and abundant flash switches allows for very high logic utilization without compromising device routability or performance. Logic functions within the device are interconnected through a four-level routing hierarchy. 1 -2 v1.0 ProASIC3E Flash Family FPGAs Advanced Architecture The proprietary ProASIC3E architecture provides granularity comparable to standard-cell ASICs. The ProASIC3E device consists of five distinct and programmable architectural features (Figure 1-1 on page 3): • • • • • FPGA VersaTiles Dedicated FlashROM Dedicated SRAM/FIFO memory Extensive CCCs and PLLs Pro I/O structure The FPGA core consists of a sea of VersaTiles. Each VersaTile can be configured as a three-input logic function, a D-flip-flop (with or without enable), or a latch by programming the appropriate flash switch interconnections. The versatility of the ProASIC3E core tile as either a three-input lookup table (LUT) equivalent or as a D-flip-flop/latch with enable allows for efficient use of the FPGA fabric. The VersaTile capability is unique to the Actel ProASIC family of third-generation architecture Flash FPGAs. VersaTiles are connected with any of the four levels of routing hierarchy. Flash switches are distributed throughout the device to provide nonvolatile, reconfigurable interconnect programming. Maximum core utilization is possible for virtually any design. In addition, extensive on-chip programming circuitry allows for rapid, single-voltage (3.3 V) programming of ProASIC3E devices via an IEEE 1532 JTAG interface. CCC RAM Block 4,608-Bit Dual-Port SRAM or FIFO Block Pro I/Os VersaTile RAM Block 4,608-Bit Dual-Port SRAM or FIFO Block Charge Pumps ISP AES Decryption User Nonvolatile FlashROM Figure 1-1 • ProASIC3E Device Architecture Overview v1.0 1-3 ProASIC3E Device Family Overview VersaTiles The ProASIC3E core consists of VersaTiles, which have been enhanced beyond the ProASICPLUS® core tiles. The ProASIC3E VersaTile supports the following: • • • • All 3-input logic functions—LUT-3 equivalent Latch with clear or set D-flip-flop with clear or set Enable D-flip-flop with clear or set Refer to Figure 1-2 for VersaTile configurations. LUT-3 Equivalent X1 X2 X3 D-Flip-Flop with Clear or Set Data CLK CLR Y D-FF Enable D-Flip-Flop with Clear or Set Data CLK Enable CLR D-FF Y LUT-3 Y Figure 1-2 • VersaTile Configurations User Nonvolatile FlashROM Actel ProASIC3E devices have 1 kbit of on-chip, user-accessible, nonvolatile FlashROM. The FlashROM can be used in diverse system applications: • • • • • • • • Internet protocol addressing (wireless or fixed) System calibration settings Device serialization and/or inventory control Subscription-based business models (for example, set-top boxes) Secure key storage for secure communications algorithms Asset management/tracking Date stamping Version management The FlashROM is written using the standard ProASIC3E IEEE 1532 JTAG programming interface. The core can be individually programmed (erased and written), and on-chip AES decryption can be used selectively to securely load data over public networks, as in security keys stored in the FlashROM for a user design. The FlashROM can be programmed via the JTAG programming interface, and its contents can be read back either through the JTAG programming interface or via direct FPGA core addressing. Note that the FlashROM can only be programmed from the JTAG interface and cannot be programmed from the internal logic array. The FlashROM is programmed as 8 banks of 128 bits; however, reading is performed on a byte-bybyte basis using a synchronous interface. A 7-bit address from the FPGA core defines which of the 8 banks and which of the 16 bytes within that bank are being read. The three most significant bits (MSBs) of the FlashROM address determine the bank, and the four least significant bits (LSBs) of the FlashROM address define the byte. The Actel ProASIC3E development software solutions, Libero® Integrated Design Environment (IDE) and Designer, have extensive support for the FlashROM. One such feature is auto-generation of sequential programming files for applications requiring a unique serial number in each part. Another feature allows the inclusion of static data for system version control. Data for the FlashROM can be generated quickly and easily using Actel Libero IDE and Designer software tools. Comprehensive programming file support is also included to allow for easy programming of large numbers of parts with differing FlashROM contents. 1 -4 v1.0 ProASIC3E Flash Family FPGAs SRAM and FIFO ProASIC3E devices have embedded SRAM blocks along their north and south sides. Each variableaspect-ratio SRAM block is 4,608 bits in size. Available memory configurations are 256×18, 512×9, 1k×4, 2k×2, and 4k×1 bits. The individual blocks have independent read and write ports that can be configured with different bit widths on each port. For example, data can be sent through a 4-bit port and read as a single bitstream. The embedded SRAM blocks can be initialized via the device JTAG port (ROM emulation mode) using the UJTAG macro. In addition, every SRAM block has an embedded FIFO control unit. The control unit allows the SRAM block to be configured as a synchronous FIFO without using additional core VersaTiles. The FIFO width and depth are programmable. The FIFO also features programmable Almost Empty (AEMPTY) and Almost Full (AFULL) flags in addition to the normal Empty and Full flags. The embedded FIFO control unit contains the counters necessary for generation of the read and write address pointers. The embedded SRAM/FIFO blocks can be cascaded to create larger configurations. PLL and CCC ProASIC3E devices provide designers with very flexible clock conditioning capabilities. Each member of the ProASIC3E family contains six CCCs, each with an integrated PLL. The six CCC blocks are located at the four corners and the centers of the east and west sides. To maximize user I/Os, only the center east and west PLLs are available in devices using the PQ208 package. However, all six CCC blocks are still usable; the four corner CCCs allow simple clock delay operations as well as clock spine access. The inputs of the six CCC blocks are accessible from the FPGA core or from one of several inputs located near the CCC that have dedicated connections to the CCC block. The CCC block has these key features: • • • • • • • • • • • • Wide input frequency range (fIN_CCC) = 1.5 MHz to 350 MHz Output frequency range (fOUT_CCC) = 0.75 MHz to 350 MHz Clock delay adjustment via programmable and fixed delays from –7.56 ns to +11.12 ns 2 programmable delay types for clock skew minimization Clock frequency synthesis Internal phase shift = 0°, 90°, 180°, and 270°. Output phase shift depends on the output divider configuration. Output duty cycle = 50% ± 1.5% or better Low output jitter: worst case < 2.5% × clock period peak-to-peak period jitter when single global network used Maximum acquisition time = 300 µs Low power consumption of 5 mW Exceptional tolerance to input period jitter— allowable input jitter is up to 1.5 ns Four precise phases; maximum misalignment between adjacent phases of 40 ps × (350 MHz / fOUT_CCC) Additional CCC specifications: Global Clocking ProASIC3E devices have extensive support for multiple clocking domains. In addition to the CCC and PLL support described above, there is a comprehensive global clock distribution network. Each VersaTile input and output port has access to nine VersaNets: six chip (main) and three quadrant global networks. The VersaNets can be driven by the CCC or directly accessed from the core via multiplexers (MUXes). The VersaNets can be used to distribute low-skew clock signals or for rapid distribution of high fanout nets. v1.0 1-5 ProASIC3E Device Family Overview Pro I/Os with Advanced I/O Standards The ProASIC3E family of FPGAs features a flexible I/O structure, supporting a range of voltages (1.5 V, 1.8 V, 2.5 V, and 3.3 V). ProASIC3E FPGAs support 19 different I/O standards, including singleended, differential, and voltage-referenced. The I/Os are organized into banks, with eight banks per device (two per side). The configuration of these banks determines the I/O standards supported. Each I/O bank is subdivided into VREF minibanks, which are used by voltage-referenced I/Os. VREF minibanks contain 8 to 18 I/Os. All the I/Os in a given minibank share a common VREF line. Therefore, if any I/O in a given VREF minibank is configured as a VREF pin, the remaining I/Os in that minibank will be able to use that reference voltage. Each I/O module contains several input, output, and enable registers. These registers allow the implementation of the following: • • Single-Data-Rate applications (e.g., PCI 66 MHz, bidirectional SSTL 2 and 3, Class I and II) Double-Data-Rate applications (e.g., DDR LVDS, B-LVDS, and M-LVDS I/Os for point-to-point communications, and DDR 200 MHz SRAM using bidirectional HSTL Class II) ProASIC3E banks support M-LVDS with 20 multi-drop points. Part Number and Revision Date Part Number 51700098-001-1 Revised March 2008 List of Changes The following table lists critical changes that were made in the current version of the document. Previous Version 51700098-001-1 Changes in Current Version (v1.0) This document was divided into two sections and given a version number, starting at v1.0. The first section of the document includes features, benefits, ordering information, and temperature and speed grade offerings. The second section is a device family overview. The FG324 package was added to the "ProASIC3E Product Family" table, the "I/Os Per Package1" table, and the "Temperature Grade Offerings" table for A3PE3000. This document was previously in datasheet v2.1. As a result of moving to the handbook format, Actel has restarted the version numbers. The new version number is 51700098-001-0. CoreMP7 information was removed from the "Features and Benefits" section. Page N/A 51700098-001-0 (January 2008) v2.1 (July 2007) v2.0 (April 2007) I, II, IV N/A i The M1 device part numbers have been updated in Table 4 • ProASIC3E iii, ii, iii, Product Family, "Packaging Tables", "Temperature Grade Offerings", "Speed iv, iv Grade and Temperature Grade Matrix", and "Speed Grade and Temperature Grade Matrix". The words "ambient temperature" were added to the temperature range in the "Temperature Grade Offerings", "Speed Grade and Temperature Grade Matrix", and "Speed Grade and Temperature Grade Matrix" sections. The "Clock Conditioning Circuit (CCC) and PLL" section was updated. iii, iv, iv i iii iii iv Advance v0.6 (January 2007) In the "Temperature Grade Offerings" section, Ambient was deleted. Ambient was deleted from "Temperature Grade Offerings". Ambient was deleted from the "Speed Grade and Temperature Grade Matrix". 1 -6 v1.0 ProASIC3E Flash Family FPGAs Previous Version Advance v0.5 (April 2006) Advance v0.4 (October 2005) Advance v0.2 Changes in Current Version (v1.0) In the "Packaging Tables" table, the number of I/Os for the A3PE1500 was changed for the FG484 and FG676 packages. B-LVDS and M-LDVS are new I/O standards added to the datasheet. The term flow-through was changed to pass-through. The "Packaging Tables" table was updated. Page ii N/A N/A ii Datasheet Categories Categories In order to provide the latest information to designers, some datasheets are published before data has been fully characterized. Datasheets are designated as "Product Brief," "Advance," "Preliminary," and "Production." The definition of these categories are as follows: Product Brief The product brief is a summarized version of a datasheet (advance or production) and contains general product information. This document gives an overview of specific device and family information. Advance This version contains initial estimated information based on simulation, other products, devices, or speed grades. This information can be used as estimates, but not for production. This label only applies to the DC and Switching Characteristics chapter of the datasheet and will only be used when the data has not been fully characterized. Preliminary The datasheet contains information based on simulation and/or initial characterization. The information is believed to be correct, but changes are possible. Unmarked (production) This version contains information that is considered to be final. Export Administration Regulations (EAR) The products described in this document are subject to the Export Administration Regulations (EAR). They could require an approved export license prior to export from the United States. An export includes release of product or disclosure of technology to a foreign national inside or outside the United States. Actel Safety Critical, Life Support, and High-Reliability Applications Policy The Actel products described in this advance status document may not have completed Actel’s qualification process. Actel may amend or enhance products during the product introduction and qualification process, resulting in changes in device functionality or performance. It is the responsibility of each customer to ensure the fitness of any Actel product (but especially a new product) for a particular purpose, including appropriateness for safety-critical, life-support, and other high-reliability applications. Consult Actel’s Terms and Conditions for specific liability exclusions relating to life-support applications. A reliability report covering all of Actel’s products is available on the Actel website at http://www.actel.com/documents/ORT_Report.pdf. Actel also offers a variety of enhanced qualification and lot acceptance screening procedures. Contact your local Actel sales office for additional reliability information. v1.0 1-7 2 – ProASIC3E DC and Switching Characteristics General Specifications DC and switching characteristics for –F speed grade targets are based only on simulation. The characteristics provided for the –F speed grade are subject to change after establishing FPGA specifications. Some restrictions might be added and will be reflected in future revisions of this document. The –F speed grade is only supported in the commercial temperature range. Operating Conditions Stresses beyond those listed in Table 2-1 may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Absolute Maximum Ratings are stress ratings only; functional operation of the device at these or any other conditions beyond those listed under the Recommended Operating Conditions specified in Table 2-2 on page 2-2 is not implied. Table 2-1 • Symbol VCC VJTAG VPUMP VCCPLL VCCI VMV VI Absolute Maximum Ratings Parameter DC core supply voltage JTAG DC voltage Programming voltage Analog power supply (PLL) DC I/O output buffer supply voltage DC I/O input buffer supply voltage I/O input voltage Limits –0.3 to 1.65 –0.3 to 3.75 –0.3 to 3.75 –0.3 to 1.65 –0.3 to 3.75 –0.3 to 3.75 –0.3 V to 3.6 V (when I/O hot insertion mode is enabled) –0.3 V to (VCCI + 1 V) or 3.6 V, whichever voltage is lower (when I/O hot-insertion mode is disabled) TSTG 2 TJ 2 Notes: 1. The device should be operated within the limits specified by the datasheet. During transitions, the input signal may undershoot or overshoot according to the limits shown in Table 2-3 on page 2-2. 2. For flash programming and retention maximum limits, refer to Table 2-3 on page 2-2, and for recommended operating limits, refer to Table 2-2 on page 2-2. Storage temperature Junction temperature –65 to +150 +125 °C °C Units V V V V V V V v 1.2 2-1 ProASIC3E DC and Switching Characteristics Table 2-2 • Symbol TA VCC VJTAG VPUMP VCCPLL VCCI and VMV 2 Recommended Operating Conditions 1 Parameter Ambient temperature 1.5 V DC core supply voltage JTAG DC voltage Programming voltage Programming Mode Operation Analog power supply (PLL) 1.5 V DC supply voltage 1.8 V DC supply voltage 2.5 V DC supply voltage 3.3 V DC supply voltage LVDS/B-LVDS/M-LVDS differential I/O LVPECL differential I/O Notes: 1. All parameters representing voltages are measured with respect to GND unless otherwise specified. 2. The ranges given here are for power supplies only. The recommended input voltage ranges specific to each I/O standard are given in Table 2-13 on page 2-16. VMV and VCCI should be at the same voltage within a given I/O bank. 3. VPUMP can be left floating during normal operation (not programming mode). 4. Maximum TJ = 85 °C. 5. Maximum TJ = 100 °C. 6. To ensure targeted reliability standards are met across ambient and junction operating temperatures, Actel recommends that the user follow best design practices using Actel’s timing and power simulation tools. Table 2-3 • Flash Programming Limits – Retention, Storage and Operating Temperature1 Programming Program Retention Cycles (biased/unbiased) 500 500 20 years 20 years Maximum Storage Temperature TSTG (°C) 2 110 110 Maximum Operating Junction Temperature TJ (°C) 2 100 100 3 Commercial 0 to +70 4,6 Industrial –40 to +85 5,6 Units °C V V V V V V V V V V V 1.425 to 1.575 1.4 to 3.6 3.15 to 3.45 0 to 3.6 1.4 to 1.6 1.425 to 1.575 1.7 to 1.9 2.3 to 2.7 3.0 to 3.6 2.375 to 2.625 3.0 to 3.6 1.425 to 1.575 1.4 to 3.6 3.15 to 3.45 0 to 3.6 1.4 to 1.6 1.425 to 1.575 1.7 to 1.9 2.3 to 2.7 3.0 to 3.6 2.375 to 2.625 3.0 to 3.6 Product Grade Commercial Industrial Notes: 1. This is a stress rating only; functional operation at any condition other than those indicated is not implied. 2. These limits apply for program/data retention only. Refer to Table 2-1 on page 2-1 and Table 2-2 for device operating conditions and absolute limits. 2 -2 v1.2 ProASIC3E DC and Switching Characteristics Table 2-4 • Overshoot and Undershoot Limits 1 Average VCCI–GND Overshoot or Undershoot Duration as a Percentage of Clock Cycle2 10% 5% 3V 3.3 V 3.6 V Notes: 1. Based on reliability requirements at 85°C. 2. The duration is allowed at one out of six clock cycles. If the overshoot/undershoot occurs at one out of two cycles, the maximum overshoot/undershoot has to be reduced by 0.15 V. 3. The device meets overshoot/undershoot specification requirements for PCI inputs with VCCI 3.45 V at 85°C maximum, whereas the average toggling of inputs at one-sixth of PCI frequency is considered. 10% 5% 10% 5% 10% 5% Maximum Overshoot/ Undershoot2 1.4 V 1.49 V 1.1 V 1.19 V 0.79 V 0.88 V 0.45 V 0.54 V VCCI and VMV 2.7 V or less I/O Power-Up and Supply Voltage Thresholds for Power-On Reset (Commercial and Industrial) Sophisticated power-up management circuitry is designed into every ProASIC®3E device. These circuits ensure easy transition from the powered-off state to the powered-up state of the device. The many different supplies can power up in any sequence with minimized current spikes or surges. In addition, the I/O will be in a known state through the power-up sequence. The basic principle is shown in Figure 2-1 on page 2-4. There are five regions to consider during power-up. ProASIC3E I/Os are activated only if ALL of the following three conditions are met: 1. VCC and VCCI are above the minimum specified trip points (Figure 2-1 on page 2-4). 2. VCCI > VCC – 0.75 V (typical) 3. Chip is in the operating mode. VCCI Trip Point: Ramping up: 0.6 V < trip_point_up < 1.2 V Ramping down: 0.5 V < trip_point_down < 1.1 V VCC Trip Point: Ramping up: 0.6 V < trip_point_up < 1.1 V Ramping down: 0.5 V < trip_point_down < 1 V VCC and VCCI ramp-up trip points are about 100 mV higher than ramp-down trip points. This specifically built-in hysteresis prevents undesirable power-up oscillations and current surges. Note the following: • • During programming, I/Os become tristated and weakly pulled up to VCCI. JTAG supply, PLL power supplies, and charge pump VPUMP supply have no influence on I/O behavior. v1.2 2-3 ProASIC3E DC and Switching Characteristics PLL Behavior at Brownout Condition Actel recommends using monotonic power supplies or voltage regulators to ensure proper power-up behavior. Power ramp-up should be monotonic at least until VCC and VCCPLXL exceed brownout activation levels. The VCC activation level is specified as 1.1 V worst-case (see Figure 2-1 on page 2-4 for more details). When PLL power supply voltage and/or VCC levels drop below the VCC brownout levels (0.75 V ± 0.25 V), the PLL output lock signal goes low and/or the output clock is lost. Refer to the Power-Up/-Down Behavior of Low-Power Flash Devices chapter of the handbook for information on clock and lock recovery. Internal Power-Up Activation Sequence 1. Core 2. Input buffers 3. Output buffers, after 200 ns delay from input buffer activation VCC = VCCI + VT where VT can be from 0.58 V to 0.9 V (typically 0.75 V) VCC VCC = 1.575 V Region 1: I/O Buffers are OFF Region 4: I/O buffers are ON. I/Os are functional (except differential inputs) but slower because VCCI is below specification. For the same reason, input buffers do not meet VIH/VIL levels, and output buffers do not meet VOH/VOL levels. Region 5: I/O buffers are ON and power supplies are within specification. I/Os meet the entire datasheet and timer specifications for speed, VIH/VIL , VOH/VOL , etc. VCC = 1.425 V Region 2: I/O buffers are ON. I/Os are functional (except differential inputs) but slower because VCCI/VCC are below specification. For the same reason, input buffers do not meet VIH/VIL levels, and output buffers do not meet VOH/VOL levels. Region 3: I/O buffers are ON. I/Os are functional; I/O DC specifications are met, but I/Os are slower because the VCC is below specification. Activation trip point: Va = 0.85 V ± 0.25 V Deactivation trip point: Vd = 0.75 V ± 0.25 V Region 1: I/O buffers are OFF Activation trip point: Va = 0.9 V ± 0.3 V Deactivation trip point: Vd = 0.8 V ± 0.3 V Min VCCI datasheet specification voltage at a selected I/O standard; i.e., 1.425 V or 1.7 V or 2.3 V or 3.0 V VCCI Figure 2-1 • I/O State as a Function of VCCI and VCC Voltage Levels 2 -4 v1.2 ProASIC3E DC and Switching Characteristics Thermal Characteristics Introduction The temperature variable in Actel Designer software refers to the junction temperature, not the ambient temperature. This is an important distinction because dynamic and static power consumption cause the chip junction to be higher than the ambient temperature. EQ 2-1 can be used to calculate junction temperature. TJ = Junction Temperature = ΔT + TA EQ 2-1 where: TA = Ambient Temperature ΔT = Temperature gradient between junction (silicon) and ambient ΔT = θja * P θja = Junction-to-ambient of the package. θja numbers are located in Table 2-5. P = Power dissipation Package Thermal Characteristics The device junction-to-case thermal resistivity is θjc and the junction-to-ambient air thermal resistivity is θja. The thermal characteristics for θja are shown for two air flow rates. The absolute maximum junction temperature is 110°C. EQ 2-2 shows a sample calculation of the absolute maximum power dissipation allowed for an 896-pin FBGA package at commercial temperature and in still air. 110 ° C – 70 ° C Max. junction temp. ( ° C) – Max. ambient temp. ( ° C) Maximum Power Allowed = -------------------------------------------------------------------------------------------------------------------------------------- = ------------------------------------ = 5.88 W 13.6 ° C/W θ ja ( ° C/W) EQ 2-2 Table 2-5 • Package Thermal Resistivities θja Package Type Plastic Quad Flat Package (PQFP) Plastic Quad Flat Package (PQFP) with embedded heat spreader Fine Pitch Ball Grid Array (FBGA) Pin Count 208 208 256 484 676 896 θjc 8.0 3.8 3.8 3.2 3.2 2.4 Still Air 26.1 16.2 26.9 20.5 16.4 13.6 200 ft./min. 22.5 13.3 22.8 17.0 13.0 10.4 500 ft./min. 20.8 11.9 21.5 15.9 12.0 9.4 Units C/W C/W C/W C/W C/W C/W Temperature and Voltage Derating Factors Table 2-6 • Temperature and Voltage Derating Factors for Timing Delays (normalized to TJ = 70°C, VCC = 1.425 V) Junction Temperature (°C) –40°C 0.87 0.83 0.80 0°C 0.92 0.88 0.85 25°C 0.95 0.90 0.87 70°C 1.00 0.95 0.92 85°C 1.02 0.97 0.94 100°C 1.05 1.00 0.96 Array Voltage VCC (V) 1.425 1.500 1.575 v1.2 2-5 ProASIC3E DC and Switching Characteristics Calculating Power Dissipation Quiescent Supply Current Table 2-7 • Quiescent Supply Current Characteristics A3PE600 Typical (25°C) Maximum (Commercial) Maximum (Industrial) Notes: 1. IDD Includes VCC, VPUMP, VCCI, and VMV currents. Values do not include I/O static contribution, which is shown in Table 2-8 and Table 2-9 on page 2-7. 2. –F speed grade devices may experience higher standby IDD of up to five times the standard IDD and higher I/O leakage. 5 mA 30 mA 45 mA A3PE1500 12 mA 70 mA 105 mA A3PE3000 25 mA 150 mA 225 mA Power per I/O Pin Table 2-8 • Summary of I/O Input Buffer Power (per pin) – Default I/O Software Settings VMV (V) Single-Ended 3.3 V LVTTL/LVCMOS 3.3 V LVTTL/LVCMOS – Schmitt trigger 2.5 V LVCMOS 2.5 V LVCMOS – Schmitt trigger 1.8 V LVCMOS 1.8 V LVCMOS – Schmitt trigger 1.5 V LVCMOS (JESD8-11) 1.5 V LVCMOS (JESD8-11) – Schmitt trigger 3.3 V PCI 3.3 V PCI – Schmitt trigger 3.3 V PCI-X 3.3 V PCI-X – Schmitt trigger Voltage-Referenced 3.3 V GTL 2.5 V GTL 3.3 V GTL+ 2.5 V GTL+ HSTL (I) HSTL (II) SSTL2 (I) SSTL2 (II) SSTL3 (I) SSTL3 (II) Notes: 1. PDC2 is the static power (where applicable) measured on VMV. 2. PAC9 is the total dynamic power measured on VCC and VMV. 3.3 2.5 3.3 2.5 1.5 1.5 2.5 2.5 3.3 3.3 2.90 2.13 2.81 2.57 0.17 0.17 1.38 1.38 3.21 3.21 8.23 4.78 4.14 3.71 2.03 2.03 4.48 4.48 9.26 9.26 3.3 3.3 2.5 2.5 1.8 1.8 1.5 1.5 3.3 3.3 3.3 3.3 – – – – – – – – – – – – 17.39 25.51 5.76 7.16 2.72 2.80 2.08 2.00 18.82 20.12 18.82 20.12 Static Power PDC2 (mW)1 Dynamic Power PAC9 (µW/MHz)2 2 -6 v1.2 ProASIC3E DC and Switching Characteristics Table 2-8 • Summary of I/O Input Buffer Power (per pin) – Default I/O Software Settings (continued) VMV (V) Differential LVDS/B-LVDS/M-LVDS LVPECL Notes: 1. PDC2 is the static power (where applicable) measured on VMV. 2. PAC9 is the total dynamic power measured on VCC and VMV. Table 2-9 • Summary of I/O Output Buffer Power (per pin) – Default I/O Software Settings1 CLOAD (pF) Single-Ended 3.3 V LVTTL/LVCMOS 2.5 V LVCMOS 1.8 V LVCMOS 1.5 V LVCMOS (JESD8-11) 3.3 V PCI 3.3 V PCI-X Voltage-Referenced 3.3 V GTL 2.5 V GTL 3.3 V GTL+ 2.5 V GTL+ HSTL (I) HSTL (II) SSTL2 (I) SSTL2 (II) SSTL3 (I) SSTL3 (II) Differential LVDS/B-LVDS/M-LVDS LVPECL Notes: 1. Dynamic power consumption is given for standard load and software default drive strength and output slew. 2. PDC3 is the static power (where applicable) measured on VCCI. 3. PAC10 is the total dynamic power measured on VCC and VCCI. – – 2.5 3.3 7.70 19.42 89.62 168.02 10 10 10 10 20 20 30 30 30 30 3.3 2.5 3.3 2.5 1.5 1.5 2.5 2.5 3.3 3.3 – – – – 7.08 13.88 16.69 25.91 26.02 42.21 24.08 13.52 24.10 13.54 26.22 27.22 105.56 116.60 114.87 131.76 35 35 35 35 10 10 3.3 2.5 1.8 1.5 3.3 3.3 – – – – – – 474.70 270.73 151.78 104.55 204.61 204.61 VCCI (V) Static Power PDC3 (mW)2 Dynamic Power PAC10 (μW/MHz)3 2.5 3.3 2.26 5.71 1.50 2.17 Static Power PDC2 (mW)1 Dynamic Power PAC9 (µW/MHz)2 v1.2 2-7 ProASIC3E DC and Switching Characteristics Power Consumption of Various Internal Resources Table 2-10 • Different Components Contributing to the Dynamic Power Consumption in ProASIC3E Devices Device-Specific Dynamic Contributions (µW/MHz) Parameter PAC1 PAC2 PAC3 PAC4 PAC5 PAC6 PAC7 PAC8 PAC9 PAC10 PAC11 PAC12 PAC13 PAC14 Definition Clock contribution of a Global Rib Clock contribution of a Global Spine Clock contribution of a VersaTile row Clock contribution of a VersaTile used as a sequential module First contribution of a VersaTile used as a sequential module Second contribution of a VersaTile used as a sequential module Contribution of a VersaTile used as a combinatorial module Average contribution of a routing net Contribution dependent) of an I/O input pin (standardA3PE600 12.77 1.85 A3PE1500 16.21 3.06 0.88 0.12 0.07 0.29 0.29 0.70 See Table 2-8 on page 2-6. See Table 2-9 on page 2-7 25.00 30.00 2.55 mW 2.60 A3PE3000 19.7 4.16 Contribution of an I/O output pin (standarddependent) Average contribution of a RAM block during a read operation Average contribution of a RAM block during a write operation Static PLL contribution Dynamic contribution for PLL Note: For a different output load, drive strength, or slew rate, Actel recommends using the Actel power calculator or SmartPower in Actel Libero® Integrated Design Environment (IDE). 2 -8 v1.2 ProASIC3E DC and Switching Characteristics Power Calculation Methodology This section describes a simplified method to estimate power consumption of an application. For more accurate and detailed power estimations, use the SmartPower tool in the Libero IDE software. The power calculation methodology described below uses the following variables: • • • • • • • • The number of PLLs as well as the number and the frequency of each output clock generated The number of combinatorial and sequential cells used in the design The internal clock frequencies The number and the standard of I/O pins used in the design The number of RAM blocks used in the design Toggle rates of I/O pins as well as VersaTiles—guidelines are provided in Table 2-11 on page 2-11. Enable rates of output buffers—guidelines are provided for typical applications in Table 2-12 on page 2-11. Read rate and write rate to the memory—guidelines are provided for typical applications in Table 2-12 on page 2-11. The calculation should be repeated for each clock domain defined in the design. Methodology Total Power Consumption—PTOTAL PTOTAL = PSTAT + PDYN PSTAT is the total static power consumption. PDYN is the total dynamic power consumption. Total Static Power Consumption—PSTAT PSTAT = PDC1 + NINPUTS * PDC2 + NOUTPUTS * PDC3 NINPUTS is the number of I/O input buffers used in the design. NOUTPUTS is the number of I/O output buffers used in the design. Total Dynamic Power Consumption—PDYN PDYN = PCLOCK + PS-CELL + PC-CELL + PNET + PINPUTS + POUTPUTS + PMEMORY + PPLL Global Clock Contribution—PCLOCK PCLOCK = (PAC1 + NSPINE * PAC2 + NROW * PAC3 + NS-CELL * PAC4) * FCLK NSPINE is the number of global spines used in the user design—guidelines are provided in Table 2-11 on page 2-11. NROW is the number of VersaTile rows used in the design—guidelines are provided in Table 2-11 on page 2-11. FCLK is the global clock signal frequency. NS-CELL is the number of VersaTiles used as sequential modules in the design. PAC1, PAC2, PAC3, and PAC4 are device-dependent. Sequential Cells Contribution—PS-CELL PS-CELL = NS-CELL * (PAC5 + α1 / 2 * PAC6) * FCLK NS-CELL is the number of VersaTiles used as sequential modules in the design. When a multi-tile sequential cell is used, it should be accounted for as 1. α1 is the toggle rate of VersaTile outputs—guidelines are provided in Table 2-11 on page 2-11. FCLK is the global clock signal frequency. v1.2 2-9 ProASIC3E DC and Switching Characteristics Combinatorial Cells Contribution—PC-CELL PC-CELL = NC-CELL* α1 / 2 * PAC7 * FCLK NC-CELL is the number of VersaTiles used as combinatorial modules in the design. α1 is the toggle rate of VersaTile outputs—guidelines are provided in Table 2-11 on page 2-11. FCLK is the global clock signal frequency. Routing Net Contribution—PNET PNET = (NS-CELL + NC-CELL) * α1 / 2 * PAC8 * FCLK NS-CELL is the number of VersaTiles used as sequential modules in the design. NC-CELL is the number of VersaTiles used as combinatorial modules in the design. α1 is the toggle rate of VersaTile outputs—guidelines are provided in Table 2-11 on page 2-11. FCLK is the global clock signal frequency. I/O Input Buffer Contribution—PINPUTS PINPUTS = NINPUTS * α2 / 2 * PAC9 * FCLK NINPUTS is the number of I/O input buffers used in the design. FCLK is the global clock signal frequency. α2 is the I/O buffer toggle rate—guidelines are provided in Table 2-11 on page 2-11. I/O Output Buffer Contribution—POUTPUTS POUTPUTS = NOUTPUTS * α2 / 2 * β1 * PAC10 * FCLK NOUTPUTS is the number of I/O output buffers used in the design. α2 is the I/O buffer toggle rate—guidelines are provided in Table 2-11 on page 2-11. β1 is the I/O buffer enable rate—guidelines are provided in Table 2-12 on page 2-11. FCLK is the global clock signal frequency. RAM Contribution—PMEMORY PMEMORY = PAC11 * NBLOCKS * FREAD-CLOCK * β2 + PAC12 * NBLOCK * FWRITE-CLOCK * β3 NBLOCKS is the number of RAM blocks used in the design. FREAD-CLOCK is the memory read clock frequency. on page 2-11. β2 is the RAM enable rate for read operations—guidelines are provided in Table 2-12 β3 is the RAM enable rate for write operations—guidelines are provided in Table 2-12 FWRITE-CLOCK is the memory write clock frequency. on page 2-11. PLL Contribution—PPLL PPLL = PAC13 + PAC14 * FCLKOUT FCLKOUT is the output clock frequency.1 1. The PLL dynamic contribution depends on the input clock frequency, the number of output clock signals generated by the PLL, and the frequency of each output clock. If a PLL is used to generate more than one output clock, include each output clock in the formula by adding its corresponding contribution (PAC14 * FCLKOUT product) to the total PLL contribution. 2 -1 0 v1.2 ProASIC3E DC and Switching Characteristics Guidelines Toggle Rate Definition A toggle rate defines the frequency of a net or logic element relative to a clock. It is a percentage. If the toggle rate of a net is 100%, this means that this net switches at half the clock frequency. Below are some examples: • • The average toggle rate of a shift register is 100% as all flip-flop outputs toggle at half of the clock frequency. The average toggle rate of an 8-bit counter is 25%: – – – – – – Bit 0 (LSB) = 100% Bit 1 Bit 2 … Bit 7 (MSB) = 0.78125% Average toggle rate = (100% + 50% + 25% + 12.5% + . . . + 0.78125%) / 8 = 50% = 25% Enable Rate Definition Output enable rate is the average percentage of time during which tristate outputs are enabled. When nontristate output buffers are used, the enable rate should be 100%. Table 2-11 • Toggle Rate Guidelines Recommended for Power Calculation Component Definition Toggle rate of VersaTile outputs I/O buffer toggle rate Guideline 10% 10% α1 α2 Component Table 2-12 • Enable Rate Guidelines Recommended for Power Calculation Definition I/O output buffer enable rate RAM enable rate for read operations RAM enable rate for write operations Guideline 100% 12.5% 12.5% β1 β2 β3 v1.2 2 - 11 ProASIC3E DC and Switching Characteristics User I/O Characteristics Timing Model I/O Module (Non-Registered) Combinational Cell Y tPD = 0.56 ns tPD = 0.49 ns tDP = 1.36 ns I/O Module (Non-Registered) Combinational Cell Y LVPECL Combinational Cell Y tPD = 0.87 ns Combinational Cell Y I/O Module (Registered) tPY = 1.22 ns tPD = 0.51 ns LVPECL D Q Combinational Cell Y tICLKQ = 0.24 ns tISUD = 0.26 ns Input LVTTL/LVCMOS Clock Register Cell tPY = 0.90 ns D I/O Module (Non-Registered) LVDS, BLVDS, M-LVDS tPY = 1.36 ns tCLKQ = 0.55 ns tSUD = 0.43 ns Input LVTTL/LVCMOS Clock tPY = 0.90 ns Q tPD = 0.47 ns Combinational Cell Y tPD = 0.47 ns tDP = 2.74 ns I/O Module (Non-Registered) LVTTL/LVCMOS Output drive strength = 12 mA High slew rate tDP = 2.39 ns LVTTL/LVCMOS Output drive strength = 24 mA High slew rate I/O Module (Non-Registered) LVCMOS 1.5V Output drive strength = 12 mA High slew tDP = 3.30 ns Register Cell D Q D I/O Module (Registered) Q GTL+ 3.3V tDP = 1.53 ns tCLKQ = 0.55 ns tSUD = 0.43 ns Input LVTTL/LVCMOS Clock tPY = 0.90 ns tCLKQ = 0.59 ns tSUD = 0.31 ns Figure 2-2 • Timing Model Operating Conditions: –2 Speed, Commercial Temperature Range (TJ = 70°C), Worst-Case VCC = 1.425 V 2 -1 2 v1.2 ProASIC3E DC and Switching Characteristics tPY tDIN D PAD Y Q DIN CLK To Array tPY = MAX(tPY(R), tPY(F)) tDIN = MAX(tDIN(R), tDIN(F)) VIH Vtrip PAD Vtrip VCC 50% Y GND tPY (R) tPYS (R) tPY (F) tPYS (F) VCC 50% DIN GND tDOUT (R) Figure 2-3 • Input Buffer Timing Model and Delays (example) I/O Interface VIL 50% 50% tDOUT (F) v1.2 2 - 13 ProASIC3E DC and Switching Characteristics tDOUT DQ D From Array I/O Interface CLK tDP PAD Std Load tDP = MAX(tDP(R), tDP(F)) tDOUT = MAX(tDOUT(R), tDOUT(F)) tDOUT VCC 50% VCC (F) 0V DOUT tDOUT (R) 50% D DOUT 50% 50% VOH 0V Vtrip PAD tDP (R) Figure 2-4 • Output Buffer Model and Delays (example) Vtrip VOL tDP (F) 2 -1 4 v1.2 ProASIC3E DC and Switching Characteristics tEOUT D E Q tZL, tZH, tHZ, tLZ, tZLS, tZHS CLK EOUT D D Q DOUT CLK PAD I/O Interface tEOUT = MAX(tEOUT(r), tEOUT(f)) VCC D VCC E 50% tEOUT (R) 50% EOUT tZL PAD Vtrip VOL 50% tEOUT (F) VCC 50% tHZ 90% VCCI 50% tZH VCCI Vtrip 10% VCCI 50% tLZ VCC D VCC E 50% tEOUT (R) VCC EOUT PAD Vtrip VOL 50% tZLS 50% VOH 50% tZHS Vtrip 50% tEOUT (F) Figure 2-5 • Tristate Output Buffer Timing Model and Delays (example) v1.2 2 - 15 ProASIC3E DC and Switching Characteristics Overview of I/O Performance Summary of I/O DC Input and Output Levels – Default I/O Software Settings Table 2-13 • Summary of Maximum and Minimum DC Input and Output Levels Applicable to Commercial and Industrial Conditions VIL I/O Standard 3.3 V LVTTL / 3.3 V LVCMOS 2.5 V LVCMOS 1.8 V LVCMOS 1.5 V LVCMOS 3.3 V PCI 3.3 V PCI-X 3.3 V GTL 2.5 V GTL 3.3 V GTL+ 2.5 V GTL+ HSTL (I) HSTL (II) SSTL2 (I) SSTL2 (II) SSTL3 (I) SSTL3 (II) Notes: 1. Currents are measured at 85°C junction temperature. 2. Output drive strength is below JEDEC specification. 3. Output Slew Rates can be extracted from IBIS Models, located at http://www.actel.com/download/ibis/default.aspx. 25 25 mA2 mA2 High High High High High High High High High High –0.3 –0.3 –0.3 –0.3 –0.3 –0.3 –0.3 –0.3 –0.3 –0.3 Drive Strength Slew Rate Min, V 12 mA 12 mA 12 mA 12 mA High High High High –0.3 –0.3 –0.3 –0.3 Max, V 0.8 0.7 2 1.7 VIH Min, V Max, V 3.6 3.6 3.6 3.6 VOL Max, V 0.4 0.7 0.45 VOH Min, V 2.4 1.7 IOL IOH mA mA 12 12 12 12 0.35 * VCCI 0.65 * VCCI 0.30 * VCCI 0.7 * VCCI Per PCI Specification Per PCI-X Specification VREF – 0.05 VREF + 0.05 VREF – 0.05 VREF + 0.05 VREF – 0.1 VREF + 0.1 VREF – 0.1 VREF + 0.1 VREF – 0.1 VREF + 0.1 VREF – 0.1 VREF + 0.1 VREF – 0.2 VREF + 0.2 VREF – 0.2 VREF + 0.2 VREF – 0.2 VREF + 0.2 VREF – 0.2 VREF + 0.2 VCCI – 0.45 12 12 0.25 * VCCI 0.75 * VCCI 12 12 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 0.4 0.4 0.6 0.6 0.4 0.4 0.54 0.35 0.7 0.5 – – – – VCCI – 0.4 25 25 25 25 51 51 40 40 8 8 35 mA 33 mA 8 mA 15 mA2 VCCI – 0.4 15 15 VCCI – 0.62 15 15 VCCI – 0.43 18 18 VCCI – 1.1 14 14 VCCI – 0.9 21 21 15 mA 18 mA 14 mA 21 mA 2 -1 6 v1.2 ProASIC3E DC and Switching Characteristics Table 2-14 • Summary of Maximum and Minimum DC Input Levels Applicable to Commercial and Industrial Conditions Commercial1 IIL DC I/O Standards 3.3 V LVTTL / 3.3 V LVCMOS 2.5 V LVCMOS 1.8 V LVCMOS 1.5 V LVCMOS 3.3 V PCI 3.3 V PCI-X 3.3 V GTL 2.5 V GTL 3.3 V GTL+ 2.5 V GTL+ HSTL (I) HSTL (II) SSTL2 (I) SSTL2 (II) SSTL3 (I) SSTL3 (II) Notes: 1. Commercial range (0°C < TA < 70°C) 2. Industrial range (–40°C < TA < 85°C) µA 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 IIH µA 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 IIL µA 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 Industrial2 IIH µA 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 v1.2 2 - 17 ProASIC3E DC and Switching Characteristics Summary of I/O Timing Characteristics – Default I/O Software Settings Table 2-15 • Summary of AC Measuring Points Standard 3.3 V LVTTL / 3.3 V LVCMOS 2.5 V LVCMOS 1.8 V LVCMOS 1.5 V LVCMOS 3.3 V PCI 3.3 V PCI-X 3.3 V GTL 2.5 V GTL 3.3 V GTL+ 2.5 V GTL+ HSTL (I) HSTL (II) SSTL2 (I) SSTL2 (II) SSTL3 (I) SSTL3 (II) LVDS LVPECL Input Reference Voltage Board Termination Measuring Trip Point (VREF_TYP) Voltage (VTT_REF) (Vtrip) – – – – – – 0.8 V 0.8 V 1.0 V 1.0 V 0.75 V 0.75 V 1.25 V 1.25 V 1.5 V 1.5 V – – – – – – – – 1.2 V 1.2 V 1.5 V 1.5 V 0.75 V 0.75 V 1.25 V 1.25 V 1.485 V 1.485 V – – 1.4 V 1.2 V 0.90 V 0.75 V 0.285 * VCCI (RR) 0.615 * VCCI (FF)) 0.285 * VCCI (RR) 0.615 * VCCI (FF) VREF VREF VREF VREF VREF VREF VREF VREF VREF VREF Cross point Cross point Table 2-16 • I/O AC Parameter Definitions Parameter tDP tPY tDOUT tEOUT tDIN tPYS tHZ tZH tLZ tZL Definition Data to Pad delay through the Output Buffer Pad to Data delay through the Input Buffer with Schmitt trigger disabled Data to Output Buffer delay through the I/O interface Enable to Output Buffer Tristate Control delay through the I/O interface Input Buffer to Data delay through the I/O interface Pad to Data delay through the Input Buffer with Schmitt trigger enabled Enable to Pad delay through the Output Buffer—HIGH to Z Enable to Pad delay through the Output Buffer—Z to HIGH Enable to Pad delay through the Output Buffer—LOW to Z Enable to Pad delay through the Output Buffer—Z to LOW 2 -1 8 v1.2 ProASIC3E DC and Switching Characteristics Table 2-16 • I/O AC Parameter Definitions Parameter tZHS tZLS Definition Enable to Pad delay through the Output Buffer with delayed enable—Z to HIGH Enable to Pad delay through the Output Buffer with delayed enable—Z to LOW Table 2-17 • Summary of I/O Timing Characteristics—Software Default Settings –2 Speed Grade, Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V External Resistor (Ω) Capacitive Load (pF) Drive Strength (mA) tE OUT (ns) Slew Rate tDOUT (ns) tPYS (ns) tDIN (ns) tDP (ns) I/O Standard 3.3 V LVTTL / 3.3 V LVCMOS 2.5 V LVCMOS 1.8 V LVCMOS 1.5 V LVCMOS 3.3 V PCI 3.3 V PCI-X 3.3 V GTL 2.5 V GTL 3.3 V GTL+ 2.5 V GTL+ HSTL (I) HSTL (II) SSTL2 (I) SSTL2 (II) SSTL3 (I) SSTL3 (II) LVDS/B-LVDS/ M-LVDS LVPECL Notes: 12 12 12 12 Per PCI spec High 35 High 35 High 35 High 35 High 10 – – – – 0.49 2.74 0.03 0.90 1.17 0.32 2.79 2.14 2.45 2.70 4.46 3.81 0.49 2.80 0.03 1.13 1.24 0.32 2.85 2.61 2.51 2.61 4.52 4.28 0.49 2.83 0.03 1.08 1.42 0.32 2.89 2.31 2.79 3.16 4.56 3.98 0.49 3.30 0.03 1.27 1.60 0.32 3.36 2.70 2.96 3.27 5.03 4.37 25 2 0.49 2.09 0.03 0.78 1.17 0.32 2.13 1.49 2.45 2.70 3.80 3.16 25 2 0.49 2.09 0.03 0.78 1.17 0.32 2.13 1.49 2.45 2.70 3.80 3.16 25 25 25 25 50 25 50 25 50 25 – – 0.45 1.55 0.03 2.19 0.45 1.59 0.03 1.83 0.45 1.53 0.03 1.19 0.45 1.65 0.03 1.13 0.49 2.37 0.03 1.59 0.49 2.26 0.03 1.59 0.49 1.59 0.03 1.00 0.49 1.62 0.03 1.00 0.49 1.72 0.03 0.93 0.49 1.54 0.03 0.93 0.49 1.40 0.03 1.36 0.49 1.36 0.03 1.22 – – – – – – – – – – – – 0.32 1.52 1.55 0.32 1.61 1.59 0.32 1.56 1.53 0.32 1.68 1.57 0.32 2.42 2.35 0.32 2.30 2.03 0.32 1.62 1.38 0.32 1.65 1.32 0.32 1.75 1.37 0.32 1.57 1.25 – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – 3.19 3.22 3.28 3.26 3.23 3.20 3.35 3.24 4.09 4.02 3.97 3.70 3.29 3.05 3.32 2.99 3.42 3.04 3.24 2.92 – – – – Per PCI-X spec High 10 25 25 35 33 8 15 15 18 14 21 24 24 High 10 High 10 High 10 High 10 High 20 High 20 High 30 High 30 High 30 High 30 High High – – 1. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values. 2. Resistance is used to measure I/O propagation delays as defined in PCI specifications. See Figure 2-10 on page 2-35 for connectivity. This resistor is not required during normal operation. v1.2 tZLS (ns) tPY (ns) tZL (ns) tLZ (ns) 2 - 19 tZHS (ns) tZ H (ns) tHZ (ns) ProASIC3E DC and Switching Characteristics Detailed I/O DC Characteristics Table 2-18 • Input Capacitance Symbol CIN CINCLK Definition Input capacitance Input capacitance on the clock pin Conditions VIN = 0, f = 1.0 MHz VIN = 0, f = 1.0 MHz Min. Max. 8 8 Units pF pF Table 2-19 • I/O Output Buffer Maximum Resistances1 Standard 3.3 V LVTTL / 3.3 V LVCMOS Drive Strength 4 mA 8 mA 12 mA 16 mA 24 mA 2.5 V LVCMOS 4 mA 8 mA 12 mA 16 mA 24 mA 1.8 V LVCMOS 2 mA 4 mA 6 mA 8 mA 12 mA 16 mA 1.5 V LVCMOS 2 mA 4 mA 6 mA 8 mA 12 mA 3.3 V PCI/PCI-X 3.3 V GTL 2.5 V GTL 3.3 V GTL+ 2.5 V GTL+ HSTL (I) Notes: 1. These maximum values are provided for informational reasons only. Minimum output buffer resistance values depend on VCCI, drive strength selection, temperature, and process. For board design considerations and detailed output buffer resistances, use the corresponding IBIS models located on the Actel website at http://www.actel.com/techdocs/models/ibis.html. 2. R(PULL-DOWN-MAX) = (VOLspec) / IOLspec 3. R(PULL-UP-MAX) = (VCCImax – VOHspec) / IOHs pe c Per PCI/PCI-X specification 25 mA 25 mA 35 mA 33 mA 8 mA RPULL-DOWN (Ω)2 100 50 25 17 11 100 50 25 20 11 200 100 50 50 20 20 200 100 67 33 33 25 11 14 12 15 50 RPULL-UP (Ω)3 300 150 75 50 33 200 100 50 40 22 225 112 56 56 22 22 224 112 75 37 37 75 – – – – 50 2 -2 0 v1.2 ProASIC3E DC and Switching Characteristics Table 2-19 • I/O Output Buffer Maximum Resistances1 (continued) Standard HSTL (II) SSTL2 (I) SSTL2 (II) SSTL3 (I) SSTL3 (II) Notes: 1. These maximum values are provided for informational reasons only. Minimum output buffer resistance values depend on VCCI, drive strength selection, temperature, and process. For board design considerations and detailed output buffer resistances, use the corresponding IBIS models located on the Actel website at http://www.actel.com/techdocs/models/ibis.html. 2. R(PULL-DOWN-MAX) = (VOLspec) / IOLspec 3. R(PULL-UP-MAX) = (VCCImax – VOHspec) / IOHs pe c Table 2-20 • I/O Weak Pull-Up/Pull-Down Resistances Minimum and Maximum Weak Pull-Up/Pull-Down Resistance Values R((WEAK PULL-UP)1 (Ω) VCCI 3.3 V 2.5 V 1.8 V 1.5 V Notes: 1. R(WEAK PULL-DOWN-MAX) = (VOLspec) / IWEAK PULL-DOWN-MIN 2. R(WEAK PULL-UP-MAX) = (VCCImax – VOHspec) / IWEAK PULL-UP-MIN Min. 10 k 11 k 18 k 19 k Max. 45 k 55 k 70 k 90 k Min. 10 k 12 k 17 k 19 k R(WEAK PULL-DOWN)2 (Ω) Max. 45 k 74 k 110 k 140 k Drive Strength 15 mA 15 mA 18 mA 14 mA 21 mA RPULL-DOWN (Ω)2 25 27 13 44 18 RPULL-UP (Ω)3 25 31 15 69 32 v1.2 2 - 21 ProASIC3E DC and Switching Characteristics Table 2-21 • I/O Short Currents IOSH/IOSL Drive Strength 3.3 V LVTTL / 3.3 V LVCMOS 4 mA 8 mA 12 mA 16 mA 24 mA 2.5 V LVCMOS 4 mA 8 mA 12 mA 16 mA 24 mA 1.8 V LVCMOS 2 mA 4 mA 6 mA 8 mA 12 mA 16 mA 1.5 V LVCMOS 2 mA 4 mA 6 mA 8 mA 12 mA * TJ = 100°C The length of time an I/O can withstand IOSH/IOSL events depends on the junction temperature. The reliability data below is based on a 3.3 V, 36 mA I/O setting, which is the worst case for this type of analysis. For example, at 110°C, the short current condition would have to be sustained for more than three months to cause a reliability concern. The I/O design does not contain any short circuit protection, but such protection would only be needed in extremely prolonged stress conditions. Table 2-22 • Duration of Short Circuit Event before Failure Temperature –40°C 0°C 25°C 70°C 85°C 100°C 110°C Time before Failure > 20 years > 20 years > 20 years 5 years 2 years 6 months 3 months IOSH (mA)* 25 51 103 132 268 16 32 65 83 169 9 17 35 45 91 91 13 25 32 66 66 IOSL (mA)* 27 54 109 127 181 18 37 74 87 124 11 22 44 51 74 74 16 33 39 55 55 2 -2 2 v1.2 ProASIC3E DC and Switching Characteristics Table 2-23 • Schmitt Trigger Input Hysteresis Hysteresis Voltage Value (typ.) for Schmitt Mode Input Buffers Input Buffer Configuration 3.3 V LVTTL/LVCMOS/PCI/PCI-X (Schmitt trigger mode) 2.5 V LVCMOS (Schmitt trigger mode) 1.8 V LVCMOS (Schmitt trigger mode) 1.5 V LVCMOS (Schmitt trigger mode) Table 2-24 • I/O Input Rise Time, Fall Time, and Related I/O Reliability* Input Buffer LVTTL/LVCMOS (Schmitt trigger disabled) LVTTL/LVCMOS (Schmitt trigger enabled) HSTL/SSTL/GTL LVDS/B-LVDS/M-LVDS/ LVPECL Input Rise/Fall Time (min.) No requirement No requirement Input Rise/Fall Time (max.) 10 ns * Reliability 20 years (110°C) Hysteresis Value (typ.) 240 mV 140 mV 80 mV 60 mV No requirement, but input noise 20 years (110°C) voltage cannot exceed Schmitt hysteresis. 10 ns * 10 ns * 10 years (100°C) 10 years (100°C) No requirement No requirement * For clock signals and similar edge-generating signals, refer to ProASIC3/E SSO and Pin Placement Guidelines. The maximum input rise/fall time is related to the noise induced into the input buffer trace. If the noise is low, then the rise time and fall time of input buffers can be increased beyond the maximum value. The longer the rise/fall times, the more susceptible the input signal is to the board noise. Actel recommends signal integrity evaluation/characterization of the system to ensure that there is no excessive noise coupling into input signals. Single-Ended I/O Characteristics 3.3 V LVTTL / 3.3 V LVCMOS Low-Voltage Transistor–Transistor Logic is a general-purpose standard (EIA/JESD) for 3.3 V applications. It uses an LVTTL input buffer and push-pull output buffer. The 3.3 V LVCMOS standard is supported as part of the 3.3 V LVTTL support. Table 2-25 • Minimum and Maximum DC Input and Output Levels 3.3 V LVTTL / 3.3 V LVCMOS Drive Strength 4 mA 8 mA 12 mA 16 mA 24 mA Notes: 1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage. 2. Currents are measured at 85°C junction temperature. 3. Software default selection highlighted in gray. VIL VIH VOL VOH IOL IOH IOSL mA1 IOSH Max., mA1 IIL µA2 10 10 10 10 10 IIH µA2 10 10 10 10 10 Min., V Max., V Min., V Max., V Max., V Min., V mA mA Max., –0.3 –0.3 –0.3 –0.3 –0.3 0.8 0.8 0.8 0.8 0.8 2 2 2 2 2 3.6 3.6 3.6 3.6 3.6 0.4 0.4 0.4 0.4 0.4 2.4 2.4 2.4 2.4 2.4 4 8 4 8 27 54 109 127 181 25 51 103 132 268 12 12 16 16 24 24 v1.2 2 - 23 ProASIC3E DC and Switching Characteristics Test Point Datapath 35 pF R=1k Test Point Enable Path R to VCCI for tLZ/tZL/tZLS R to GND for tHZ/tZH/tZHS 35 pF for tZH/tZHS/tZL/tZLS 5 pF for tHZ/tLZ Figure 2-6 • AC Loading Table 2-26 • AC Waveforms, Measuring Points, and Capacitive Loads Input LOW (V) 0 Input HIGH (V) 3.3 Measuring Point* (V) 1.4 VREF (typ.) (V) – CLOAD (pF) 35 * Measuring point = Vtrip. See Table 2-15 on page 2-18 for a complete table of trip points. Timing Characteristics Table 2-27 • 3.3 V LVTTL / 3.3 V LVCMOS High Slew Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V Drive Strength 4 mA Speed Grade –F Std. –1 –2 8 mA –F Std. –1 –2 12 mA –F Std. –1 –2 16 mA –F Std. –1 –2 24 mA –F Std. –1 –2 Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values. tDOUT 0.79 0.66 0.56 0.49 0.79 0.66 0.56 0.49 0.79 0.66 0.56 0.49 0.79 0.66 0.56 0.49 0.79 0.66 0.56 0.49 tDP 9.47 7.88 6.71 5.89 6.10 5.08 4.32 3.79 4.41 3.67 3.12 2.74 4.16 3.46 2.95 2.59 3.85 3.21 2.73 2.39 tDIN 0.05 0.04 0.04 0.03 0.05 0.04 0.04 0.03 0.05 0.04 0.04 0.03 0.05 0.04 0.04 0.03 0.05 0.04 0.04 0.03 tPY 1.44 1.20 1.02 0.90 1.44 1.20 1.02 0.90 1.44 1.20 1.02 0.90 1.44 1.20 1.02 0.90 1.44 1.20 1.02 0.90 tPYS 1.88 1.57 1.33 1.17 1.88 1.57 1.33 1.17 1.88 1.57 1.33 1.17 1.88 1.57 1.33 1.17 1.88 1.57 1.33 1.17 tEOUT 0.51 0.43 0.36 0.32 0.51 0.43 0.36 0.32 0.51 0.43 0.36 0.32 0.51 0.43 0.36 0.32 0.51 0.43 0.36 0.32 tZL 9.64 8.03 6.83 6.00 6.21 5.17 4.40 3.86 4.49 3.74 3.18 2.79 4.24 3.53 3.00 2.63 3.92 3.27 2.78 2.44 tZH 8.05 6.70 5.70 5.01 4.98 4.14 3.52 3.09 3.45 2.87 2.44 2.14 3.13 2.61 2.22 1.95 2.59 2.16 1.83 1.61 tLZ 3.23 2.69 2.29 2.01 3.66 3.05 2.59 2.28 3.93 3.28 2.79 2.45 4.00 3.33 2.83 2.49 4.07 3.39 2.88 2.53 tHZ 3.11 2.59 2.20 1.93 3.86 3.21 2.73 2.40 4.34 3.61 3.07 2.70 4.47 3.72 3.17 2.78 4.96 4.13 3.51 3.08 tZLS 12.33 10.26 8.73 7.67 8.90 7.41 6.30 5.53 7.17 5.97 5.08 4.46 6.92 5.76 4.90 4.30 6.61 5.50 4.68 4.11 tZHS 10.74 8.94 7.60 6.67 7.66 6.38 5.43 4.76 6.13 5.11 4.34 3.81 5.82 4.84 4.12 3.62 5.28 4.39 3.74 3.28 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 2 -2 4 v1.2 ProASIC3E DC and Switching Characteristics Table 2-28 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V Drive Strength 4 mA Speed Grade –F Std. –1 –2 8 mA –F Std. –1 –2 12 mA –F Std. –1 –2 16 mA –F Std. –1 –2 24 mA –F Std. –1 –2 tDOUT 0.79 0.66 0.56 0.49 0.79 0.66 0.56 0.49 0.79 0.66 0.56 0.49 0.79 0.66 0.56 0.49 0.79 0.66 0.56 0.49 tDP 13.22 11.01 9.36 8.22 9.45 7.86 6.69 5.87 7.24 6.03 5.13 4.50 6.75 5.62 4.78 4.20 6.30 5.24 4.46 3.92 tDIN tPY tPYS tEOUT 0.51 0.43 0.36 0.32 0.51 0.43 0.36 0.32 0.51 0.43 0.36 0.32 0.51 0.43 0.36 0.32 0.51 0.43 0.36 0.32 tZL 13.47 11.21 9.54 8.37 9.62 8.01 6.81 5.98 7.37 6.14 5.22 4.58 6.87 5.72 4.87 4.27 6.42 5.34 4.54 3.99 tZH 10.87 9.05 7.70 6.76 7.74 6.44 5.48 4.81 6.03 5.02 4.27 3.75 5.68 4.72 4.02 3.53 5.64 4.69 3.99 3.50 tLZ tHZ tZLS 16.16 13.45 11.44 10.04 12.31 10.24 8.71 7.65 10.06 8.37 7.12 6.25 9.56 7.96 6.77 5.94 9.10 7.58 6.44 5.66 tZHS 13.56 11.29 9.60 8.43 10.42 8.68 7.38 6.48 8.72 7.26 6.17 5.42 8.36 6.96 5.92 5.20 8.32 6.93 5.89 5.17 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 0.05 1.44 1.88 0.04 1.20 1.57 0.04 1.02 1.33 0.03 0.90 1.17 0.05 1.44 1.88 0.04 1.20 1.57 0.04 1.02 1.33 0.03 0.90 1.17 0.05 1.44 1.88 0.04 1.20 1.57 0.04 1.02 1.33 0.03 0.90 1.17 0.05 1.44 1.88 0.04 1.20 1.57 0.04 1.02 1.33 0.03 0.90 1.17 0.05 1.44 1.88 0.04 1.20 1.57 0.04 1.02 1.33 0.03 0.90 1.17 3.23 2.93 2.69 2.44 2.29 2.08 2.01 1.82 3.65 3.68 3.04 3.06 2.58 2.61 2.27 2.29 3.93 4.17 3.28 3.47 2.79 2.95 2.45 2.59 3.99 4.30 3.32 3.58 2.83 3.04 2.48 2.67 4.07 4.76 3.39 3.96 2.88 3.37 2.53 2.96 Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values. v1.2 2 - 25 ProASIC3E DC and Switching Characteristics 2.5 V LVCMOS Low-Voltage CMOS for 2.5 V is an extension of the LVCMOS standard (JESD8-5) used for generalpurpose 2.5 V applications. It uses a 5 V–tolerant input buffer and push-pull output buffer. Table 2-29 • Minimum and Maximum DC Input and Output Levels 2.5 V LVCMOS Drive Strength 4 mA 8 mA 12 mA 16 mA 24 mA Notes: 1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage. 2. Currents are measured at 85°C junction temperature. 3. Software default selection highlighted in gray. VIL VIH VOL VOH IOL IOH IOSL IOSH IIL IIH Min., V Max., V Min., V Max., V Max., V Min., V mA mA Max., mA1 –0.3 –0.3 –0.3 –0.3 –0.3 0.7 0.7 0.7 0.7 0.7 1.7 1.7 1.7 1.7 1.7 3.6 3.6 3.6 3.6 3.6 0.7 0.7 0.7 0.7 0.7 1.7 1.7 1.7 1.7 1.7 4 8 12 16 24 4 8 12 16 24 18 37 74 87 124 Max., mA1 µA2 µA2 16 32 65 83 169 10 10 10 10 10 10 10 10 10 10 Test Point Datapath 35 pF R=1k Test Point Enable Path R to VCCI for tLZ/tZL/tZLS R to GND for tHZ/tZH/tZHS 35 pF for tZH/tZHS/tZL/tZLS 5 pF for tHZ/tLZ Figure 2-7 • AC Loading Table 2-30 • AC Waveforms, Measuring Points, and Capacitive Loads Input LOW (V) 0 Input HIGH (V) 2.5 Measuring Point* (V) 1.2 VREF (typ.) (V) – CLOAD (pF) 35 * Measuring point = Vtrip. See Table 2-15 on page 2-18 for a complete table of trip points. 2 -2 6 v1.2 ProASIC3E DC and Switching Characteristics Timing Characteristics Table 2-31 • 2.5 V LVCMOS High Slew Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V Drive Strength 4 mA Speed Grade –F Std. –1 –2 8 mA –F Std. –1 –2 12 mA –F Std. –1 –2 16 mA –F Std. –1 –2 24 mA –F Std. –1 –2 Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values. tDOUT 0.79 0.66 0.56 0.49 0.79 0.66 0.56 0.49 0.79 0.66 0.56 0.49 0.79 0.66 0.56 0.49 0.79 0.66 0.56 0.49 tDP 10.59 8.82 7.50 6.58 6.33 5.27 4.48 3.94 4.50 3.74 3.18 2.80 4.24 3.53 3.00 2.63 3.92 3.26 2.77 2.44 tDIN 0.05 0.04 0.04 0.03 0.05 0.04 0.04 0.03 0.05 0.04 0.04 0.03 0.05 0.04 0.04 0.03 0.05 0.04 0.04 0.03 tPY 1.82 1.51 1.29 1.13 1.82 1.51 1.29 1.13 1.82 1.51 1.29 1.13 1.82 1.51 1.29 1.13 1.82 1.51 1.29 1.13 tPYS 1.99 1.66 1.41 1.24 1.99 1.66 1.41 1.24 1.99 1.66 1.41 1.24 1.99 1.66 1.41 1.24 1.99 1.66 1.41 1.24 tEOUT 0.51 0.43 0.36 0.32 0.51 0.43 0.36 0.32 0.51 0.43 0.36 0.32 0.51 0.43 0.36 0.32 0.51 0.43 0.36 0.32 tZL 9.77 8.13 6.92 6.07 6.33 5.27 4.48 3.93 4.58 3.81 3.24 2.85 4.32 3.59 3.06 2.68 3.99 3.32 2.83 2.48 tZH 10.59 8.82 7.50 6.58 6.33 5.27 4.48 3.94 4.19 3.49 2.97 2.61 3.75 3.12 2.65 2.33 2.98 2.48 2.11 1.85 tLZ 3.26 2.72 2.31 2.03 3.73 3.10 2.64 2.32 4.04 3.37 2.86 2.51 4.11 3.42 2.91 2.56 4.20 3.49 2.97 2.61 tHZ 2.75 2.29 1.95 1.71 3.64 3.03 2.58 2.26 4.20 3.49 2.97 2.61 4.35 3.62 3.08 2.71 4.93 4.11 3.49 3.07 tZLS 12.45 10.37 8.82 7.74 9.02 7.50 6.38 5.60 7.27 6.05 5.15 4.52 7.00 5.83 4.96 4.35 6.68 5.56 4.73 4.15 tZHS 13.28 11.05 9.40 8.25 9.02 7.51 6.38 5.61 6.88 5.73 4.87 4.28 6.43 5.35 4.55 4.00 5.67 4.72 4.01 3.52 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns v1.2 2 - 27 ProASIC3E DC and Switching Characteristics Table 2-32 • 2.5 V LVCMOS Low Slew Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V Drive Strength 4 mA Speed Grade –F Std. –1 –2 8 mA –F Std. –1 –2 12 mA –F Std. –1 –2 16 mA –F Std. –1 –2 24 mA –F Std. –1 –2 tDOUT 0.79 0.66 0.56 0.49 0.79 0.66 0.56 0.49 0.79 0.66 0.56 0.49 0.79 0.66 0.56 0.49 0.79 0.66 0.56 0.49 tDP 14.42 12.00 10.21 8.96 10.49 8.73 7.43 6.52 8.14 6.77 5.76 5.06 7.58 6.31 5.37 4.71 7.13 5.93 5.05 4.43 tDIN tPY tPYS tEOUT 0.51 0.43 0.36 0.32 0.51 0.43 0.36 0.32 0.51 0.43 0.36 0.32 0.51 0.43 0.36 0.32 0.51 0.43 0.36 0.32 tZL 14.69 12.23 10.40 9.13 10.68 8.89 7.57 6.64 8.29 6.90 5.87 5.15 7.72 6.42 5.46 4.80 7.26 6.04 5.14 4.51 tZH 13.95 11.61 9.88 8.67 9.62 8.01 6.82 5.98 7.34 6.11 5.20 4.56 6.88 5.73 4.87 4.28 6.85 5.70 4.85 4.26 tLZ tHZ tZLS 17.37 14.46 12.30 10.80 13.37 11.13 9.47 8.31 10.97 9.14 7.77 6.82 10.40 8.66 7.37 6.47 9.94 8.28 7.04 6.18 tZHS 16.63 13.85 11.78 10.34 12.31 10.25 8.72 7.65 10.02 8.34 7.10 6.23 9.57 7.96 6.77 5.95 9.54 7.94 6.75 5.93 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 0.05 1.82 1.99 0.04 1.51 1.66 0.04 1.29 1.41 0.03 1.13 1.24 0.05 1.82 1.99 0.04 1.51 1.66 0.04 1.29 1.41 0.03 1.13 1.24 0.05 1.82 1.99 0.04 1.51 1.66 0.04 1.29 1.41 0.03 1.13 1.24 0.05 1.82 1.99 0.04 1.51 1.66 0.04 1.29 1.41 0.03 1.13 1.24 0.05 1.82 1.99 0.04 1.51 1.66 0.04 1.29 1.41 0.03 1.13 1.24 3.26 2.64 2.72 2.20 2.31 1.87 2.03 1.64 3.73 3.52 3.10 2.93 2.64 2.49 2.32 2.19 4.04 4.08 3.37 3.39 2.86 2.89 2.51 2.53 4.11 4.23 3.42 3.52 2.91 3.00 2.56 2.63 4.20 4.80 3.49 4.00 2.97 3.40 2.61 2.99 Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values. 2 -2 8 v1.2 ProASIC3E DC and Switching Characteristics 1.8 V LVCMOS Low-Voltage CMOS for 1.8 V is an extension of the LVCMOS standard (JESD8-5) used for generalpurpose 1.8 V applications. It uses a 1.8 V input buffer and a push-pull output buffer. Table 2-33 • Minimum and Maximum DC Input and Output Levels 1.8 V LVCMOS Drive Strength Min., V 2 mA 4 mA 6 mA 8 mA 12 mA 16 mA Notes: 1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage. 2. Currents are measured at 85°C junction temperature. 3. Software default selection highlighted in gray. –0.3 –0.3 –0.3 –0.3 –0.3 –0.3 VIL Max., V VIH Min., V VOL Max., V Max., V 3.6 3.6 3.6 3.6 3.6 3.6 0.45 0.45 0.45 0.45 0.45 0.45 VOH Min., V VCCI – 0.45 VCCI – 0.45 VCCI – 0.45 VCCI – 0.45 IOL IOH IOSL IOSH IIL IIH mA mA Max., mA1 Max., mA1 μA2 μA2 2 4 6 8 2 4 6 8 11 22 44 51 74 74 9 17 35 45 91 91 10 10 10 10 10 10 10 10 10 10 10 10 0.35 * VCCI 0.65 * VCCI 0.35 * VCCI 0.65 * VCCI 0.35 * VCCI 0.65 * VCCI 0.35 * VCCI 0.65 * VCCI 0.35 * VCCI 0.65 * VCCI 0.35 * VCCI 0.65 * VCCI VCCI – 0.45 12 12 VCCI – 0.45 16 16 Test Point Datapath 35 pF R=1k Test Point Enable Path R to VCCI for tLZ/tZL/tZLS R to GND for tHZ/tZH/tZHS 35 pF for tZH/tZHS/tZL/tZLS 5 pF for tHZ/tLZ Figure 2-8 • AC Loading Table 2-34 • AC Waveforms, Measuring Points, and Capacitive Loads Input LOW (V) 0 Input HIGH (V) 1.8 Measuring Point* (V) 0.9 VREF (typ.) (V) – CLOAD (pF) 35 * Measuring point = Vtrip. See Table 2-15 on page 2-18 for a complete table of trip points. v1.2 2 - 29 ProASIC3E DC and Switching Characteristics Timing Characteristics Table 2-35 • 1.8 V LVCMOS High Slew Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.7 V Drive Strength 2 mA Speed Grade –F Std. –1 –2 4 mA –F Std. –1 –2 6 mA –F Std. –1 –2 8 mA –F Std. –1 –2 12 mA –F Std. –1 –2 16 mA –F Std. –1 –2 Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values. tDOUT 0.79 0.66 0.56 0.49 0.79 0.66 0.56 0.49 0.79 0.66 0.56 0.49 0.79 0.66 0.56 0.49 0.79 0.66 0.56 0.49 0.79 0.66 0.56 0.49 tDP 14.54 12.10 10.30 9.04 8.47 7.05 6.00 5.27 5.43 4.52 3.85 3.38 4.95 4.12 3.51 3.08 4.56 3.80 3.23 2.83 4.56 3.80 3.23 2.83 tDIN tPY tPYS tEOUT 0.51 0.43 0.36 0.32 0.51 0.43 0.36 0.32 0.51 0.43 0.36 0.32 0.51 0.43 0.36 0.32 0.51 0.43 0.36 0.32 0.51 0.43 0.36 0.32 tZL 11.52 9.59 8.16 7.16 7.45 6.20 5.28 4.63 5.36 4.47 3.80 3.33 5.04 4.20 3.57 3.14 4.64 3.87 3.29 2.89 4.64 3.87 3.29 2.89 tZH 14.54 12.10 10.30 9.04 8.47 7.05 6.00 5.27 5.43 4.52 3.85 3.38 4.80 3.99 3.40 2.98 3.71 3.09 2.63 2.31 3.71 3.09 2.63 2.31 tLZ tHZ tZLS 14.21 11.83 10.06 8.83 10.14 8.44 7.18 6.30 8.05 6.70 5.70 5.00 7.73 6.43 5.47 4.81 7.33 6.10 5.19 4.56 7.33 6.10 5.19 4.56 tZHS 17.23 14.34 12.20 10.71 11.16 9.29 7.90 6.94 8.12 6.76 5.75 5.05 7.48 6.23 5.30 4.65 6.40 5.32 4.53 3.98 6.40 5.32 4.53 3.98 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 0.05 1.74 2.29 0.04 1.45 1.91 0.04 1.23 1.62 0.03 1.08 1.42 0.05 1.74 2.29 0.04 1.45 1.91 0.04 1.23 1.62 0.03 1.08 1.42 0.05 1.74 2.29 0.04 1.45 1.91 0.04 1.23 1.62 0.03 1.08 1.42 0.05 1.74 2.29 0.04 1.45 1.91 0.04 1.23 1.62 0.03 1.08 1.42 0.05 1.74 2.29 0.04 1.45 1.91 0.04 1.23 1.62 0.03 1.08 1.42 0.05 1.74 2.29 0.04 1.45 1.91 0.04 1.23 1.62 0.03 1.08 1.42 3.34 1.97 2.78 1.64 2.37 1.39 2.08 1.22 3.90 3.44 3.25 2.86 2.76 2.44 2.43 2.14 4.29 4.17 3.57 3.47 3.04 2.95 2.66 2.59 4.36 4.35 3.63 3.62 3.09 3.08 2.71 2.71 4.48 5.09 3.73 4.24 3.18 3.60 2.79 3.16 4.48 5.09 3.73 4.24 3.18 3.60 2.79 3.16 2 -3 0 v1.2 ProASIC3E DC and Switching Characteristics Table 2-36 • 1.8 V LVCMOS Low Slew Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.7 V Drive Strength 2 mA Speed Grade –F Std. –1 –2 4 mA –F Std. –1 –2 6 mA –F Std. –1 –2 8 mA –F Std. –1 –2 12 mA –F Std. –1 –2 16 mA –F Std. –1 –2 tDOUT 0.79 0.66 0.56 0.49 0.79 0.66 0.56 0.49 0.79 0.66 0.56 0.49 0.79 0.66 0.56 0.49 0.79 0.66 0.56 0.49 0.79 0.66 0.56 0.49 tDP 19.03 15.84 13.47 11.83 13.68 11.39 9.69 8.51 10.78 8.97 7.63 6.70 10.03 8.35 7.10 6.24 9.54 7.94 6.75 5.93 9.54 7.94 6.75 5.93 tDIN tPY tPYS tEOUT 0.51 0.43 0.36 0.32 0.51 0.43 0.36 0.32 0.51 0.43 0.36 0.32 0.51 0.43 0.36 0.32 0.51 0.43 0.36 0.32 0.51 0.43 0.36 0.32 tZL 18.80 15.65 13.31 11.69 13.94 11.60 9.87 8.66 10.98 9.14 7.77 6.82 10.22 8.50 7.23 6.35 9.72 8.09 6.88 6.04 9.72 8.09 6.88 6.04 tZH 19.03 15.84 13.47 11.83 12.92 10.76 9.15 8.03 9.73 8.10 6.89 6.05 9.11 7.59 6.45 5.66 9.08 7.56 6.43 5.65 9.08 7.56 6.43 5.65 tLZ tHZ tZLS 21.49 17.89 15.22 13.36 16.62 13.84 11.77 10.33 13.66 11.37 9.67 8.49 12.90 10.74 9.14 8.02 12.40 10.32 8.78 7.71 12.40 10.32 8.78 7.71 tZHS 21.71 18.07 15.37 13.50 15.61 12.99 11.05 9.70 12.41 10.33 8.79 7.72 11.80 9.82 8.35 7.33 11.77 9.80 8.33 7.32 11.77 9.80 8.33 7.32 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 0.05 1.74 2.29 0.04 1.45 1.91 0.04 1.23 1.62 0.03 1.08 1.42 0.05 1.74 2.29 0.04 1.45 1.91 0.04 1.23 1.62 0.03 1.08 1.42 0.05 1.74 2.29 0.04 1.45 1.91 0.04 1.23 1.62 0.03 1.08 1.42 0.05 1.74 2.29 0.04 1.45 1.91 0.04 1.23 1.62 0.03 1.08 1.42 0.05 1.74 2.29 0.04 1.45 1.91 0.04 1.23 1.62 0.03 1.08 1.42 0.05 1.74 2.29 0.04 1.45 1.91 0.04 1.23 1.62 0.03 1.08 1.42 3.34 1.90 2.78 1.58 2.37 1.35 2.08 1.18 3.91 3.33 3.26 2.77 2.77 2.36 2.43 2.07 4.29 4.03 3.57 3.36 3.04 2.86 2.66 2.51 4.37 4.23 3.64 3.52 3.10 3.00 2.72 2.63 4.50 4.93 3.74 4.11 3.18 3.49 2.79 3.07 4.50 4.93 3.74 4.11 3.18 3.49 2.79 3.07 Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values. v1.2 2 - 31 ProASIC3E DC and Switching Characteristics 1.5 V LVCMOS (JESD8-11) Low-Voltage CMOS for 1.5 V is an extension of the LVCMOS standard (JESD8-5) used for generalpurpose 1.5 V applications. It uses a 1.5 V input buffer and a push-pull output buffer. Table 2-37 • Minimum and Maximum DC Input and Output Levels 1.5 V LVCMOS Drive Strength Min., V 2 mA 4 mA 6 mA 8 mA 12 mA Notes: 1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage. 2. Currents are measured at 85°C junction temperature. 3. Software default selection highlighted in gray. –0.3 –0.3 –0.3 –0.3 –0.3 VIL Max., V VIH Min., V Max., V 3.6 3.6 3.6 3.6 3.6 VOL Max., V VOH Min., V IOL IOH IOSL IOSH IIL IIH mA mA Max., mA1 Max., mA1 μA2 μA2 2 4 6 8 16 33 39 55 55 13 25 32 66 66 10 10 10 10 10 10 10 10 10 10 0.30 * VCCI 0.7 * VCCI 0.30 * VCCI 0.7 * VCCI 0.30 * VCCI 0.7 * VCCI 0.30 * VCCI 0.7 * VCCI 0.30 * VCCI 0.7 * VCCI 0.25 * VCCI 0.75 * VCCI 2 0.25 * VCCI 0.75 * VCCI 4 0.25 * VCCI 0.75 * VCCI 6 0.25 * VCCI 0.75 * VCCI 8 0.25 * VCCI 0.75 * VCCI 12 12 Test Point Datapath 35 pF R=1k Test Point Enable Path R to VCCI for tLZ/tZL/tZLS R to GND for tHZ/tZH/tZHS 35 pF for tZH/tZHS/tZL/tZLS 5 pF for tHZ/tLZ Figure 2-9 • AC Loading Table 2-38 • AC Waveforms, Measuring Points, and Capacitive Loads Input LOW (V) 0 Input HIGH (V) 1.5 Measuring Point* (V) 0.75 VREF (typ.) (V) – CLOAD (pF) 35 * Measuring point = Vtrip. See Table 2-15 on page 2-18 for a complete table of trip points. 2 -3 2 v1.2 ProASIC3E DC and Switching Characteristics Timing Characteristics Table 2-39 • 1.5 V LVCMOS High Slew Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.4 V Drive Strength 2 mA Speed Grade –F Std. –1 –2 4 mA –F Std. –1 –2 6 mA –F Std. –1 –2 8 mA –F Std. –1 –2 12 mA –F Std. –1 –2 Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values. tDOUT 0.79 0.66 0.56 0.49 0.79 0.66 0.56 0.49 0.79 0.66 0.56 0.49 0.79 0.66 0.56 0.49 0.79 0.66 0.56 0.49 tDP 10.25 8.53 7.26 6.37 6.50 5.41 4.60 4.04 5.77 4.80 4.09 3.59 5.31 4.42 3.76 3.30 5.31 4.42 3.76 3.30 tDIN 0.05 0.04 0.04 0.03 0.05 0.04 0.04 0.03 0.05 0.04 0.04 0.03 0.05 0.04 0.04 0.03 0.05 0.04 0.04 0.03 tPY 2.04 1.70 1.44 1.27 2.04 1.70 1.44 1.27 2.04 1.70 1.44 1.27 2.04 1.70 1.44 1.27 2.04 1.70 1.44 1.27 tPYS 2.58 2.14 1.82 1.60 2.58 2.14 1.82 1.60 2.58 2.14 1.82 1.60 2.58 2.14 1.82 1.60 2.58 2.14 1.82 1.60 tEOUT 0.51 0.43 0.36 0.32 0.51 0.43 0.36 0.32 0.51 0.43 0.36 0.32 0.51 0.43 0.36 0.32 0.51 0.43 0.36 0.32 tZL 8.72 7.26 6.18 5.42 6.27 5.22 4.44 3.89 5.88 4.89 4.16 3.65 5.41 4.50 3.83 3.36 5.41 4.50 3.83 3.36 tZH 10.25 8.53 7.26 6.37 6.50 5.41 4.60 4.04 5.70 4.75 4.04 3.54 4.35 3.62 3.08 2.70 4.35 3.62 3.08 2.70 tLZ 4.08 3.39 2.89 2.53 4.51 3.75 3.19 2.80 4.60 3.83 3.26 2.86 4.76 3.96 3.37 2.96 4.76 3.96 3.37 2.96 tHZ 3.35 2.79 2.37 2.08 4.18 3.48 2.96 2.60 4.41 3.67 3.12 2.74 5.25 4.37 3.72 3.27 5.25 4.37 3.72 3.27 tZLS 11.41 9.50 8.08 7.09 8.95 7.45 6.34 5.56 8.56 7.13 6.06 5.32 8.09 6.74 5.73 5.03 8.09 6.74 5.73 5.03 tZHS 12.94 10.77 9.16 8.04 9.19 7.65 6.50 5.71 8.39 6.98 5.94 5.21 7.04 5.86 4.98 4.37 7.04 5.86 4.98 4.37 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns v1.2 2 - 33 ProASIC3E DC and Switching Characteristics Table 2-40 • 1.5 V LVCMOS Low Slew Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.4 V Drive Strength 2 mA Speed Grade –F Std. –1 –2 4 mA –F Std. –1 –2 6 mA –F Std. –1 –2 8 mA –F Std. –1 –2 12 mA –F Std. –1 –2 tDOUT 0.79 0.66 0.56 0.49 0.79 0.66 0.56 0.49 0.79 0.66 0.56 0.49 0.79 0.66 0.56 0.49 0.79 0.66 0.56 0.49 tDP 16.95 14.11 12.00 10.54 13.49 11.23 9.55 8.39 12.56 10.45 8.89 7.81 12.04 10.02 8.52 7.48 12.04 10.02 8.52 7.48 tDIN tPY tPYS tEOUT 0.51 0.43 0.36 0.32 0.51 0.43 0.36 0.32 0.51 0.43 0.36 0.32 0.51 0.43 0.36 0.32 0.51 0.43 0.36 0.32 tZL 17.26 14.37 12.22 10.73 13.74 11.44 9.73 8.54 12.79 10.65 9.06 7.95 12.26 10.20 8.68 7.62 12.26 10.20 8.68 7.62 tZH 15.78 13.14 11.17 9.81 11.85 9.87 8.39 7.37 11.10 9.24 7.86 6.90 11.09 9.23 7.85 6.89 11.09 9.23 7.85 6.89 tLZ tHZ tZLS 19.95 16.61 14.13 12.40 16.43 13.68 11.63 10.21 15.48 12.88 10.96 9.62 14.94 12.44 10.58 9.29 14.94 12.44 10.58 9.29 tZHS 18.47 15.37 13.08 11.48 14.54 12.10 10.29 9.04 13.79 11.48 9.76 8.57 13.77 11.47 9.75 8.56 13.77 11.47 9.75 8.56 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 0.05 2.04 2.58 0.04 1.70 2.14 0.04 1.44 1.82 0.03 1.27 1.60 0.05 2.04 2.58 0.04 1.70 2.14 0.04 1.44 1.82 0.03 1.27 1.60 0.05 2.04 2.58 0.04 1.70 2.14 0.04 1.44 1.82 0.03 1.27 1.60 0.05 2.04 2.58 0.04 1.70 2.14 0.04 1.44 1.82 0.03 1.27 1.60 0.05 2.04 2.58 0.04 1.70 2.14 0.04 1.44 1.82 0.03 1.27 1.60 4.09 3.22 3.40 2.68 2.90 2.28 2.54 2.00 4.53 4.03 3.77 3.36 3.21 2.86 2.81 2.51 4.62 4.26 3.84 3.55 3.27 3.02 2.87 2.65 4.77 5.07 3.97 4.22 3.38 3.59 2.97 3.15 4.77 5.07 3.97 4.22 3.38 3.59 2.97 3.15 Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values. 2 -3 4 v1.2 ProASIC3E DC and Switching Characteristics 3.3 V PCI, 3.3 V PCI-X Peripheral Component Interface for 3.3 V standard specifies support for 33 MHz and 66 MHz PCI Bus applications. Table 2-41 • Minimum and Maximum DC Input and Output Levels 3.3 V PCI/PCI-X Drive Strength Per PCI specification Notes: 1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage. 2. Currents are measured at 85°C junction temperature. AC loadings are defined per the PCI/PCI-X specifications for the datapath; Actel loadings for enable path characterization are described in Figure 2-10. VIL VIH VOL VOH IOL IOH IOSL 1 IOSH 1 IIL 2 IIH Min., V Max., V Min., V Max., V Max., V Min., V mA mA Max., mA Max., mA µA µA2 Per PCI curves 10 10 R = 25 Test Point Datapath R to VCCI for tDP (F) R to GND for tDP (R) R=1k Test Point Enable Path R to VCCI for tLZ/tZL/t ZLS R to GND for tHZ /tZH /t ZHS 10 pF for tZH /tZHS /tZL /t ZLS 5 pF for tHZ /tLZ Figure 2-10 • AC Loading AC loadings are defined per PCI/PCI-X specifications for the datapath; Actel loading for tristate is described in Table 2-42. Table 2-42 • AC Waveforms, Measuring Points, and Capacitive Loads Input LOW (V) 0 Input HIGH (V) 3.3 Measuring Point* (V) 0.285 * VCCI for tDP(R) 0.615 * VCCI for tDP(F) * Measuring point = Vtrip. See Table 2-15 on page 2-18 for a complete table of trip points. VREF (typ.) (V) – CLOAD (pF) 10 Timing Characteristics Table 2-43 • 3.3 V PCI/PCI-X Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V Speed Grade –F Std. –1 –2 tDOUT 0.79 0.66 0.56 0.49 tDP 3.37 2.81 2.39 2.09 tDIN 0.05 0.04 0.04 0.03 tPY 1.26 1.05 0.89 0.78 tPYS 2.01 1.67 1.42 1.25 tEOUT 0.51 0.43 0.36 0.32 tZL 3.43 2.86 2.43 2.13 tZH 2.40 2.00 1.70 1.49 tLZ 3.93 3.28 2.79 2.45 tHZ 4.34 3.61 3.07 2.70 tZLS 6.12 5.09 4.33 3.80 tZHS 5.08 4.23 3.60 3.16 Units ns ns ns ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values. v1.2 2 - 35 ProASIC3E DC and Switching Characteristics Voltage-Referenced I/O Characteristics 3.3 V GTL Gunning Transceiver Logic is a high-speed bus standard (JESD8-3). It provides a differential amplifier input buffer and an open-drain output buffer. The VCCI pin should be connected to 3.3 V. Table 2-44 • Minimum and Maximum DC Input and Output Levels 3.3 V GTL Drive Strength 25 mA3 Notes: 1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage. 2. Currents are measured at 85°C junction temperature. 3. Output drive strength is below JEDEC specification. Min., V –0.3 VIL Max., V VIH Min., V VOL VOH IOL IOH IOSL IOSH IIL IIH Max., V Max., V Min., V mA mA Max., mA1 Max., mA1 µA2 µA2 3.6 0.4 – 25 25 181 268 10 10 VREF – 0.05 VREF + 0.05 VTT GTL Test Point 10 pF 25 Figure 2-11 • AC Loading Table 2-45 • AC Waveforms, Measuring Points, and Capacitive Loads Input LOW (V) VREF – 0.05 Input HIGH (V) VREF + 0.05 Measuring Point* (V) 0.8 VREF (typ.) (V) 0.8 VTT (typ.) (V) 1.2 CLOAD (pF) 10 * Measuring point = Vtrip. See Table 2-15 on page 2-18 for a complete table of trip points. Timing Characteristics Table 2-46 • 3.3 V GTL Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V VREF = 0.8 V Speed Grade –F Std. –1 –2 tDOUT 0.72 0.60 0.51 0.45 tDP 2.49 2.08 1.77 1.55 tDIN 0.05 0.04 0.04 0.03 tPY 3.52 2.93 2.50 2.19 tEOUT 0.51 0.43 0.36 0.32 tZL 2.45 2.04 1.73 1.52 tZH 2.49 2.08 1.77 1.55 tLZ tHZ tZLS 5.13 4.27 3.63 3.19 tZHS 5.18 4.31 3.67 3.22 Units ns ns ns ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values. 2 -3 6 v1.2 ProASIC3E DC and Switching Characteristics 2.5 V GTL Gunning Transceiver Logic is a high-speed bus standard (JESD8-3). It provides a differential amplifier input buffer and an open-drain output buffer. The VCCI pin should be connected to 2.5 V. Table 2-47 • Minimum and Maximum DC Input and Output Levels 2.5 GTL Drive Strength Min., V 25 mA3 Notes: 1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage. 2. Currents are measured at 85°C junction temperature. 3. Output drive strength is below JEDEC specification. –0.3 VIL Max., V VIH Min., V VOL VOH IOL IOH IOSL IOSH IIL IIH Max., V Max., V Min., V mA mA Max., mA1 Max., mA1 μA2 μA2 3.6 0.4 – 25 25 124 169 10 10 VREF – 0.05 VREF + 0.05 VTT GTL Test Point 10 pF 25 Figure 2-12 • AC Loading Table 2-48 • AC Waveforms, Measuring Points, and Capacitive Loads Input LOW (V) VREF – 0.05 Input HIGH (V) VREF + 0.05 Measuring Point* (V) 0.8 VREF (typ.) (V) 0.8 VTT (typ.) (V) 1.2 CLOAD (pF) 10 * Measuring point = Vtrip. See Table 2-15 on page 2-18 for a complete table of trip points. Timing Characteristics Table 2-49 • 2.5 V GTL Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V VREF = 0.8 V Speed Grade –F Std. –1 –2 tDOUT 0.72 0.60 0.51 0.45 tDP 2.56 2.13 1.81 1.59 tDIN 0.05 0.04 0.04 0.03 tPY 2.95 2.46 2.09 1.83 tEOUT 0.51 0.43 0.36 0.32 tZL 2.60 2.16 1.84 1.61 tZH 2.56 2.13 1.81 1.59 tLZ tHZ tZLS 5.28 4.40 3.74 3.28 tZHS 5.24 4.36 3.71 3.26 Units ns ns ns ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values. v1.2 2 - 37 ProASIC3E DC and Switching Characteristics 3.3 V GTL+ Gunning Transceiver Logic Plus is a high-speed bus standard (JESD8-3). It provides a differential amplifier input buffer and an open-drain output buffer. The VCCI pin should be connected to 3.3 V. Table 2-50 • Minimum and Maximum DC Input and Output Levels 3.3 V GTL+ Drive Strength 35 mA Notes: 1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage. 2. Currents are measured at 85°C junction temperature. Min., V –0.3 VIL Max., V VIH Min., V VOL VOH IOL IOH IOSL IOSH IIL IIH Max., V Max., V Min., V mA mA Max., mA1 Max., mA1 µA2 µA2 3.6 0.6 – 35 35 181 268 10 10 VREF – 0.1 VREF + 0.1 VTT GTL+ Test Point 10 pF 25 Figure 2-13 • AC Loading Table 2-51 • AC Waveforms, Measuring Points, and Capacitive Loads Input LOW (V) VREF – 0.1 Input HIGH (V) VREF + 0.1 Measuring Point* (V) 1.0 VREF (typ.) (V) 1.0 VTT (typ.) (V) 1.5 CLOAD (pF) 10 * Measuring point = Vtrip. See Table 2-15 on page 2-18 for a complete table of trip points. Timing Characteristics Table 2-52 • 3.3 V GTL+ Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V, VREF = 1.0 V Speed Grade –F Std. –1 –2 tDOUT 0.72 0.60 0.51 0.45 tDP 2.47 2.06 1.75 1.53 tDIN 0.05 0.04 0.04 0.03 tPY 1.91 1.59 1.35 1.19 tEOUT 0.51 0.43 0.36 0.32 tZL 2.51 2.09 1.78 1.56 tZH 2.47 2.06 1.75 1.53 tLZ tHZ tZLS 5.20 4.33 3.68 3.23 tZHS 5.15 4.29 3.65 3.20 Units ns ns ns ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values. 2 -3 8 v1.2 ProASIC3E DC and Switching Characteristics 2.5 V GTL+ Gunning Transceiver Logic Plus is a high-speed bus standard (JESD8-3). It provides a differential amplifier input buffer and an open-drain output buffer. The VCCI pin should be connected to 2.5 V. Table 2-53 • Minimum and Maximum DC Input and Output Levels 2.5 V GTL+ Drive Strength 33 mA Notes: 1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage. 2. Currents are measured at 85°C junction temperature. Min., V –0.3 VIL Max., V VIH Min., V VOL VOH IOL IOH IOSL IOSH IIL IIH Max., V Max., V Min., V mA mA Max., mA1 Max., mA1 µA2 µA2 3.6 0.6 – 33 33 124 169 10 10 VREF – 0.1 VREF + 0.1 VTT GTL+ Test Point 10 pF 25 Figure 2-14 • AC Loading Table 2-54 • AC Waveforms, Measuring Points, and Capacitive Loads Input LOW (V) VREF – 0.1 Input HIGH (V) VREF + 0.1 Measuring Point* (V) 1.0 VREF (typ.) (V) 1.0 VTT (typ.) (V) 1.5 CLOAD (pF) 10 * Measuring point = Vtrip. See Table 2-15 on page 2-18 for a complete table of trip points. Timing Characteristics Table 2-55 • 2.5 V GTL+ Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V, VREF = 1.0 V Speed Grade –F Std. –1 –2 tDOUT 0.72 0.60 0.51 0.45 tDP 2.65 2.21 1.88 1.65 tDIN 0.05 0.04 0.04 0.03 tPY 1.82 1.51 1.29 1.13 tEOUT 0.51 0.43 0.36 0.32 tZL 2.70 2.25 1.91 1.68 tZH 2.52 2.10 1.79 1.57 tLZ tHZ tZLS 5.38 4.48 3.81 3.35 tZHS 5.21 4.34 3.69 3.24 Units ns ns ns ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values. v1.2 2 - 39 ProASIC3E DC and Switching Characteristics HSTL Class I High-Speed Transceiver Logic is a general-purpose high-speed 1.5 V bus standard (EIA/JESD8-6). ProASIC3E devices support Class I. This provides a differential amplifier input buffer and a push-pull output buffer. Table 2-56 • Minimum and Maximum DC Input and Output Levels HSTL Class I Drive Strength 8 mA Notes: 1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage. 2. Currents are measured at 85°C junction temperature. VIL Min., V Max., V –0.3 VIH Min., V VOL VOH IOL IOH IOSL IOSH IIL IIH Max., V Max., V Min., V mA mA Max., mA1 Max., mA1 µA2 µA2 3.6 0.4 VCCI – 0.4 8 8 39 32 10 10 VREF – 0.1 VREF + 0.1 HSTL Class I Test Point VTT 50 20 pF Figure 2-15 • AC Loading Table 2-57 • AC Waveforms, Measuring Points, and Capacitive Loads Input LOW (V) VREF – 0.1 Input HIGH (V) VREF + 0.1 Measuring Point* (V) 0.75 VREF (typ.) (V) 0.75 VTT (typ.) (V) 0.75 CLOAD (pF) 20 * Measuring point = Vtrip. See Table 2-15 on page 2-18 for a complete table of trip points. Timing Characteristics Table 2-58 • HSTL Class I Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = .4 V, VREF = 0.75 V Speed Grade –F Std. –1 –2 tDOUT 0.79 0.66 0.56 0.49 tDP 3.82 3.18 2.70 2.37 tDIN 0.05 0.04 0.04 0.03 tPY 2.55 2.12 1.81 1.59 tEOUT 0.51 0.43 0.36 0.32 tZL 3.89 3.24 2.75 2.42 tZH 3.78 3.14 2.67 2.35 tLZ tHZ tZLS 6.58 5.47 4.66 4.09 tZHS 6.46 5.38 4.58 4.02 Units ns ns ns ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values. 2 -4 0 v1.2 ProASIC3E DC and Switching Characteristics HSTL Class II High-Speed Transceiver Logic is a general-purpose high-speed 1.5 V bus standard (EIA/JESD8-6). ProASIC3E devices support Class II. This provides a differential amplifier input buffer and a pushpull output buffer. Table 2-59 • Minimum and Maximum DC Input and Output Levels HSTL Class II Drive Strength 15 mA3 Notes: 1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage. 2. Currents are measured at 85°C junction temperature. 3. Output drive strength is below JEDEC specification. VIL Min., V Max., V –0.3 VIH Min., V VOL VOH IOL IOH IOSL IOSH IIL IIH Max., V Max., V Min., V mA mA Max., mA1 Max., mA1 µA2 µA2 3.6 0.4 VCCI-0.4 15 15 55 66 10 10 VREF – 0.1 VREF + 0.1 HSTL Class II Test Point VTT 25 20 pF Figure 2-16 • AC Loading Table 2-60 • AC Waveforms, Measuring Points, and Capacitive Loads Input LOW (V) VREF – 0.1 Input HIGH (V) VREF + 0.1 Measuring Point* (V) 0.75 VREF (typ.) (V) 0.75 VTT (typ.) (V) 0.75 CLOAD (pF) 20 * Measuring point = Vtrip. See Table 2-15 on page 2-18 for a complete table of trip points. Timing Characteristics Table 2-61 • HSTL Class II Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.4 V, VREF = 0.75 V Speed Grade –F Std. –1 –2 tDOUT 0.79 0.66 0.56 0.49 tDP 3.63 3.02 2.57 2.26 tDIN 0.05 0.04 0.04 0.03 tPY 2.55 2.12 1.81 1.59 tEOUT 0.51 0.43 0.36 0.32 tZL 3.70 3.08 2.62 2.30 tZH 3.26 2.71 2.31 2.03 tLZ tHZ tZLS 6.39 5.32 4.52 3.97 tZHS 5.95 4.95 4.21 3.70 Units ns ns ns ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values. v1.2 2 - 41 ProASIC3E DC and Switching Characteristics SSTL2 Class I Stub-Speed Terminated Logic for 2.5 V memory bus standard (JESD8-9). ProASIC3E devices support Class I. This provides a differential amplifier input buffer and a push-pull output buffer. Table 2-62 • Minimum and Maximum DC Input and Output Levels SSTL2 Class I Drive Strength 15 mA Notes: 1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage. 2. Currents are measured at 85°C junction temperature. VIL Min., V Max., V –0.3 VIH Min., V VOL VOH Min., V IOL IOH IOSL IOSH IIL IIH Max., V Max., V 3.6 0.54 mA mA Max., mA1 Max., mA1 µA2 µA2 87 83 10 10 VREF – 0.2 VREF + 0.2 VCCI – 0.62 15 15 SSTL2 Class I Test Point 25 VTT 50 30 pF Figure 2-17 • AC Loading Table 2-63 • AC Waveforms, Measuring Points, and Capacitive Loads Input LOW (V) VREF – 0.2 Input HIGH (V) VREF + 0.2 Measuring Point* (V) 1.25 VREF (typ.) (V) 1.25 VTT (typ.) (V) 1.25 CLOAD (pF) 30 * Measuring point = Vtrip. See Table 2-15 on page 2-18 for a complete table of trip points. Timing Characteristics Table 2-64 • SSTL 2 Class I Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V, VREF = 1.25 V Speed Grade –F Std. –1 –2 tDOUT 0.79 0.66 0.56 0.49 tDP 2.56 2.13 1.81 1.59 tDIN 0.05 0.04 0.04 0.03 tPY 1.60 1.33 1.14 1.00 tEOUT 0.51 0.43 0.36 0.32 tZL 2.60 2.17 1.84 1.62 tZH 2.22 1.85 1.57 1.38 tLZ tHZ tZLS 5.29 4.40 3.74 3.29 tZHS 4.90 4.08 3.47 3.05 Units ns ns ns ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values. 2 -4 2 v1.2 ProASIC3E DC and Switching Characteristics SSTL2 Class II Stub-Speed Terminated Logic for 2.5 V memory bus standard (JESD8-9). ProASIC3E devices support Class II. This provides a differential amplifier input buffer and a push-pull output buffer. Table 2-65 • Minimum and Maximum DC Input and Output Levels SSTL2 Class II Drive Strength 18 mA Notes: 1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage. 2. Currents are measured at 85°C junction temperature. VIL Min., V Max., V –0.3 VIH VOL VOH Min., V IOL IOH IOSL IOSH IIL IIH Min., V Max., V Max., V 3.6 0.35 mA mA Max., mA1 Max., mA1 µA2 µA2 124 169 10 10 VREF – 0.2 VREF + 0.2 VCCI – 0.43 18 18 SSTL2 Class II Test Point 25 VTT 25 30 pF Figure 2-18 • AC Loading Table 2-66 • AC Waveforms, Measuring Points, and Capacitive Loads Input LOW (V) VREF – 0.2 Input HIGH (V) VREF + 0.2 Measuring Point* (V) 1.25 VREF (typ.) (V) 1.25 VTT (typ.) (V) 1.25 CLOAD (pF) 30 * Measuring point = Vtrip. See Table 2-15 on page 2-18 for a complete table of trip points. Timing Characteristics Table 2-67 • SSTL 2 Class II Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V, VREF = 1.25 V Speed Grade –F Std. –1 –2 tDOUT 0.79 0.66 0.56 0.49 tDP 0.79 0.66 0.56 0.49 tDIN 2.60 2.17 1.84 1.62 tPY 0.05 0.04 0.04 0.03 tEOUT 1.60 1.33 1.14 1.00 tZL 0.51 0.43 0.36 0.32 tZH 2.65 2.21 1.88 1.65 tLZ 2.13 1.77 1.51 1.32 tHZ tZLS tZHS 5.34 4.44 3.78 3.32 Units ns ns ns ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values. v1.2 2 - 43 ProASIC3E DC and Switching Characteristics SSTL3 Class I Stub-Speed Terminated Logic for 3.3 V memory bus standard (JESD8-8). ProASIC3E devices support Class I. This provides a differential amplifier input buffer and a push-pull output buffer. Table 2-68 • Minimum and Maximum DC Input and Output Levels SSTL3 Class I Drive Strength 14 mA Notes: 1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage. 2. Currents are measured at 85°C junction temperature. VIL Min., V Max., V –0.3 VIH Min., V VOL VOH IOL IOH IOSL IOSH IIL IIH Max., V Max., V Min., V mA mA Max., mA1 Max., mA1 µA2 µA2 3.6 0.7 VCCI – 1.1 14 14 54 51 10 10 VREF – 0.2 VREF + 0.2 SSTL3 Class I Test Point 25 VTT 50 30 pF Figure 2-19 • AC Loading Table 2-69 • AC Waveforms, Measuring Points, and Capacitive Loads Input LOW (V) VREF – 0.2 Input HIGH (V) VREF + 0.2 Measuring Point* (V) 1.5 VREF (typ.) (V) 1.5 VTT (typ.) (V) 1.485 CLOAD (pF) 30 * Measuring point = Vtrip. See Table 2-15 on page 2-18 for a complete table of trip points. Timing Characteristics Table 2-70 • SSTL3 Class I Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V, VREF = 1.5 V Speed Grade –F Std. –1 –2 tDOUT 0.79 0.66 0.56 0.49 tDP 2.77 2.31 1.96 1.72 tDIN 0.05 0.04 0.04 0.03 tPY 1.50 1.25 1.06 0.93 tEOUT 0.51 0.43 0.36 0.32 tZL 2.82 2.35 2.00 1.75 tZH 2.21 1.84 1.56 1.37 tLZ tHZ tZLS 5.51 4.59 3.90 3.42 tZHS 4.89 4.07 3.46 3.04 Units ns ns ns ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values. 2 -4 4 v1.2 ProASIC3E DC and Switching Characteristics SSTL3 Class II Stub-Speed Terminated Logic for 3.3 V memory bus standard (JESD8-8). ProASIC3E devices support Class II. This provides a differential amplifier input buffer and a push-pull output buffer. Table 2-71 • Minimum and Maximum DC Input and Output Levels SSTL3 Class II Drive Strength 21 mA Notes: 1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage. 2. Currents are measured at 85°C junction temperature. VIL Min., V Max., V –0.3 VIH Min., V VOL VOH IOL IOH IOSL IOSH IIL IIH Max., V Max., V Min., V mA mA Max., mA1 Max., mA1 µA2 µA2 3.6 0.5 VCCI – 0.9 21 21 109 103 10 10 VREF – 0.2 VREF + 0.2 SSTL3 Class II Test Point 25 VTT 25 30 pF Figure 2-20 • AC Loading Table 2-72 • AC Waveforms, Measuring Points, and Capacitive Loads Input LOW (V) VREF – 0.2 Input HIGH (V) VREF + 0.2 Measuring Point* (V) 1.5 VREF (typ.) (V) 1.5 VTT (typ.) (V) 1.485 CLOAD (pF) 30 * Measuring point = Vtrip. See Table 2-15 on page 2-18 for a complete table of trip points. Timing Characteristics Table 2-73 • SSTL3 Class II Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V, VREF = 1.5 V Speed Grade –F Std. –1 –2 tDOUT 0.79 0.66 0.56 0.49 tDP 2.48 2.07 1.76 1.54 tDIN 0.05 0.04 0.04 0.03 tPY 1.50 1.25 1.06 0.93 tEOUT 0.51 0.43 0.36 0.32 tZL 2.53 2.10 1.79 1.57 tZH 2.01 1.67 1.42 1.25 tLZ tHZ tZLS 5.21 4.34 3.69 3.24 tZHS 4.69 3.91 3.32 2.92 Units ns ns ns ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values. v1.2 2 - 45 ProASIC3E DC and Switching Characteristics Differential I/O Characteristics Physical Implementation Configuration of the I/O modules as a differential pair is handled by the Actel Designer software when the user instantiates a differential I/O macro in the design. Differential I/Os can also be used in conjunction with the embedded Input Register (InReg), Output Register (OutReg), Enable Register (EnReg), and DDR. However, there is no support for bidirectional I/Os or tristates with the LVPECL standards. LVDS Low-Voltage Differential Signaling (ANSI/TIA/EIA-644) is a high-speed, differential I/O standard. It requires that one data bit be carried through two signal lines, so two pins are needed. It also requires external resistor termination. The full implementation of the LVDS transmitter and receiver is shown in an example in Figure 2-21. The building blocks of the LVDS transmitter-receiver are one transmitter macro, one receiver macro, three board resistors at the transmitter end, and one resistor at the receiver end. The values for the three driver resistors are different from those used in the LVPECL implementation because the output standard specifications are different. Along with LVDS I/O, ProASIC3E also supports Bus LVDS structure and Multipoint LVDS (M-LVDS) configuration (up to 40 nodes). Bourns Part Number: CAT16-LV4F12 OUTBUF_LVDS FPGA P 165 Ω Z0 = 50 Ω 140 Ω N 165 Ω Z0 = 50 Ω 100 Ω N P FPGA + – INBUF_LVDS Figure 2-21 • LVDS Circuit Diagram and Board-Level Implementation 2 -4 6 v1.2 ProASIC3E DC and Switching Characteristics Table 2-74 • LVDS Minimum and Maximum DC Input and Output Levels DC Parameter VCCI VOL VOH IOL IOH VI IIH IIL 3 3 4 4 Description Supply Voltage 1 Min. 2.375 0.9 1.25 0.65 0.65 0 Typ. 2.5 1.075 1.425 0.91 0.91 Max. 2.625 1.25 1.6 1.16 1.16 2.925 10 10 Units V V V mA mA V µA µA mV V V mV Output Low Voltage Output High Voltage Output Lower Current Output High Current Input Voltage Input High Leakage Current Input Low Leakage Current Differential Output Voltage Output Common Mode Voltage Input Common Mode Voltage Input Differential Voltage 2 VODIFF VOCM VICM VIDIFF Notes: 1. ±5% 250 1.125 0.05 100 350 1.25 1.25 350 450 1.375 2.35 2. Differential input voltage = ±350 mV. 3. Currents are measured at 85°C junction temperature. 4. IOL / IOH defined by VODIFF /(Resistor Network). Table 2-75 • AC Waveforms, Measuring Points, and Capacitive Loads Input LOW (V) 1.075 Input HIGH (V) 1.325 Measuring Point* (V) Cross point VREF (typ.) (V) – * Measuring point = Vtrip. See Table 2-15 on page 2-18 for a complete table of trip points. v1.2 2 - 47 ProASIC3E DC and Switching Characteristics Timing Characteristics Table 2-76 • LVDS Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V Speed Grade –F Std. –1 –2 tDOUT 0.79 0.66 0.56 0.49 tDP 2.25 1.87 1.59 1.40 tDIN 0.05 0.04 0.04 0.03 tPY 2.18 1.82 1.55 1.36 Units ns ns ns ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values. B-LVDS/M-LVDS Bus LVDS (B-LVDS) and Multipoint LVDS (M-LVDS) specifications extend the existing LVDS standard to high-performance multipoint bus applications. Multidrop and multipoint bus configurations may contain any combination of drivers, receivers, and transceivers. Actel LVDS drivers provide the higher drive current required by B-LVDS and M-LVDS to accommodate the loading. The drivers require series terminations for better signal quality and to control voltage swing. Termination is also required at both ends of the bus since the driver can be located anywhere on the bus. These configurations can be implemented using the TRIBUF_LVDS and BIBUF_LVDS macros along with appropriate terminations. Multipoint designs using Actel LVDS macros can achieve up to 200 MHz with a maximum of 20 loads. A sample application is given in Figure 2-22. The input and output buffer delays are available in the LVDS section in Table 2-76. Example: For a bus consisting of 20 equidistant loads, the following terminations provide the required differential voltage, in worst-case Industrial operating conditions, at the farthest receiver: RS = 60 Ω and RT = 70 Ω, given Z0 = 50 Ω (2") and Zstub = 50 Ω (~1.5"). Receiver EN Transceiver EN Driver Receiver EN EN Transceiver EN D + R + - T + - - R + - T + BIBUF_LVDS - RS Zstub Z0 RT Z 0 RS Zstub Zstub Z0 Z0 RS RS Zstub Zstub Z0 Z0 RS RS Zstub Zstub Z0 Z0 RS RS Zstub ... Z0 Z0 RS RS Z0 Z0 RT Figure 2-22 • B-LVDS/M-LVDS Multipoint Application Using LVDS I/O Buffers 2 -4 8 v1.2 ProASIC3E DC and Switching Characteristics LVPECL Low-Voltage Positive Emitter-Coupled Logic (LVPECL) is another differential I/O standard. It requires that one data bit be carried through two signal lines. Like LVDS, two pins are needed. It also requires external resistor termination. The full implementation of the LVDS transmitter and receiver is shown in an example in Figure 2-23. The building blocks of the LVPECL transmitter-receiver are one transmitter macro, one receiver macro, three board resistors at the transmitter end, and one resistor at the receiver end. The values for the three driver resistors are different from those used in the LVDS implementation because the output standard specifications are different. Bourns Part Number: CAT16-PC4F12 OUTBUF_LVPECL FPGA P 100 Ω Z0 = 50 Ω 187 W N 100 Ω Z0 = 50 Ω 100 Ω N P FPGA + – INBUF_LVPECL Figure 2-23 • LVPECL Circuit Diagram and Board-Level Implementation Table 2-77 • Minimum and Maximum DC Input and Output Levels DC Parameter VCCI VOL VOH VIL, VIH VODIFF VOCM VICM VIDIFF Description Supply Voltage Output LOW Voltage Output HIGH Voltage Input LOW, Input HIGH Voltages Differential Output Voltage Output Common-Mode Voltage Input Common-Mode Voltage Input Differential Voltage 0.96 1.8 0 0.625 1.762 1.01 300 Min. 3.0 1.27 2.11 3.3 0.97 1.98 2.57 1.06 1.92 0 0.625 1.762 1.01 300 Max. Min. 3.3 1.43 2.28 3.6 0.97 1.98 2.57 1.30 2.13 0 0.625 1.762 1.01 300 Max. Min. 3.6 1.57 2.41 3.9 0.97 1.98 2.57 Max. Units V V V V V V V mV Table 2-78 • AC Waveforms, Measuring Points, and Capacitive Loads Input LOW (V) 1.64 Input HIGH (V) 1.94 Measuring Point* (V) Cross point VREF (typ.) (V) – * Measuring point = Vtrip. See Table 2-15 on page 2-18 for a complete table of trip points. Timing Characteristics Table 2-79 • LVPECL Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V Speed Grade –F Std. –1 –2 tDOUT 0.79 0.66 0.56 0.49 tDP 2.19 1.83 1.55 1.36 tDIN 0.05 0.04 0.04 0.03 tPY 1.96 1.63 1.39 1.22 Units ns ns ns ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values. v1.2 2 - 49 ProASIC3E DC and Switching Characteristics I/O Register Specifications Fully Registered I/O Buffers with Synchronous Enable and Asynchronous Preset INBUF Preset L Pad Out D DOUT Data_out TRIBUF Data PRE D Q C DFN1E1P1 E B E Y Core Array F G PRE D Q DFN1E1P1 E INBUF INBUF Enable EOUT H I CLKBUF CLK A J K Data Input I/O Register with: Active High Enable Active High Preset Positive-Edge Triggered PRE D Q DFN1E1P1 E CLKBUF INBUF INBUF Data Output Register and Enable Output Register with: Active High Enable Active High Preset Postive-Edge Triggered CLK Figure 2-24 • Timing Model of Registered I/O Buffers with Synchronous Enable and Asynchronous Preset 2 -5 0 v1.2 D_Enable Enable ProASIC3E DC and Switching Characteristics Table 2-80 • Parameter Definition and Measuring Nodes Parameter Name tOCLKQ tOSUD tOHD tOSUE tOHE tOPRE2Q tOREMPRE tORECPRE tOECLKQ tOESUD tOEHD tOESUE tOEHE tOEPRE2Q tOEREMPRE tOERECPRE tICLKQ tISUD tIHD tISUE tIHE tIPRE2Q tIREMPRE tIRECPRE Parameter Definition Clock-to-Q of the Output Data Register Data Setup Time for the Output Data Register Data Hold Time for the Output Data Register Enable Setup Time for the Output Data Register Enable Hold Time for the Output Data Register Asynchronous Preset-to-Q of the Output Data Register Asynchronous Preset Removal Time for the Output Data Register Asynchronous Preset Recovery Time for the Output Data Register Clock-to-Q of the Output Enable Register Data Setup Time for the Output Enable Register Data Hold Time for the Output Enable Register Enable Setup Time for the Output Enable Register Enable Hold Time for the Output Enable Register Asynchronous Preset-to-Q of the Output Enable Register Asynchronous Preset Removal Time for the Output Enable Register Asynchronous Preset Recovery Time for the Output Enable Register Clock-to-Q of the Input Data Register Data Setup Time for the Input Data Register Data Hold Time for the Input Data Register Enable Setup Time for the Input Data Register Enable Hold Time for the Input Data Register Asynchronous Preset-to-Q of the Input Data Register Asynchronous Preset Removal Time for the Input Data Register Asynchronous Preset Recovery Time for the Input Data Register Measuring Nodes (from, to)* H, DOUT F, H F, H G, H G, H L, DOUT L, H L, H H, EOUT J, H J, H K, H K, H I, EOUT I, H I, H A, E C, A C, A B, A B, A D, E D, A D, A * See Figure 2-24 on page 2-50 for more information. v1.2 2 - 51 ProASIC3E DC and Switching Characteristics Fully Registered I/O Buffers with Synchronous Enable and Asynchronous Clear Pad Out DOUT Y D CC Q EE DFN1E1C1 E BB CLR LL CLKBUF Data Core Array Data_out FF TRIBUF INBUF INBUF D Q DFN1E1C1 GG E CLR EOUT Enable CLK HH AA JJ DD KK Data Input I/O Register with Active High Enable Active High Clear Positive-Edge Triggered INBUF CLR D Q DFN1E1C1 E CLR INBUF INBUF CLKBUF Data Output Register and Enable Output Register with Active High Enable Active High Clear Positive-Edge Triggered Enable Figure 2-25 • Timing Model of the Registered I/O Buffers with Synchronous Enable and Asynchronous Clear 2 -5 2 v1.2 D_Enable CLK ProASIC3E DC and Switching Characteristics Table 2-81 • Parameter Definition and Measuring Nodes Parameter Name tOCLKQ tOSUD tOHD tOSUE tOHE tOCLR2Q tOREMCLR tORECCLR tOECLKQ tOESUD tOEHD tOESUE tOEHE tOECLR2Q tOEREMCLR tOERECCLR tICLKQ tISUD tIHD tISUE tIHE tICLR2Q tIREMCLR tIRECCLR Parameter Definition Clock-to-Q of the Output Data Register Data Setup Time for the Output Data Register Data Hold Time for the Output Data Register Enable Setup Time for the Output Data Register Enable Hold Time for the Output Data Register Asynchronous Clear-to-Q of the Output Data Register Asynchronous Clear Removal Time for the Output Data Register Asynchronous Clear Recovery Time for the Output Data Register Clock-to-Q of the Output Enable Register Data Setup Time for the Output Enable Register Data Hold Time for the Output Enable Register Enable Setup Time for the Output Enable Register Enable Hold Time for the Output Enable Register Asynchronous Clear-to-Q of the Output Enable Register Asynchronous Clear Removal Time for the Output Enable Register Asynchronous Clear Recovery Time for the Output Enable Register Clock-to-Q of the Input Data Register Data Setup Time for the Input Data Register Data Hold Time for the Input Data Register Enable Setup Time for the Input Data Register Enable Hold Time for the Input Data Register Asynchronous Clear-to-Q of the Input Data Register Asynchronous Clear Removal Time for the Input Data Register Asynchronous Clear Recovery Time for the Input Data Register Measuring Nodes (from, to)* HH, DOUT FF, HH FF, HH GG, HH GG, HH LL, DOUT LL, HH LL, HH HH, EOUT JJ, HH JJ, HH KK, HH KK, HH II, EOUT II, HH II, HH AA, EE CC, AA CC, AA BB, AA BB, AA DD, EE DD, AA DD, AA * See Figure 2-25 on page 2-52 for more information. v1.2 2 - 53 ProASIC3E DC and Switching Characteristics Input Register tICKMPWH tICKMPWL 50% 50% tISUD Data 1 50% 0 tIHD 50% 50% 50% 50% 50% 50% CLK Enable 50% tIHE 50% tIWPRE tISUE tIRECPRE 50% tIWCLR tIRECCLR 50% tIREMPRE 50% tIREMCLR 50% Preset Clear tIPRE2Q Out_1 50% tICLKQ 50% 50% tICLR2Q 50% Figure 2-26 • Input Register Timing Diagram Timing Characteristics Table 2-82 • Input Data Register Propagation Delays Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V Parameter tICLKQ tISUD tIHD tISUE tIHE tICLR2Q tIPRE2Q tIREMCLR tIRECCLR tIREMPRE tIRECPRE tIWCLR tIWPRE tICKMPWH tICKMPWL Description Clock-to-Q of the Input Data Register Data Setup Time for the Input Data Register Data Hold Time for the Input Data Register Enable Setup Time for the Input Data Register Enable Hold Time for the Input Data Register Asynchronous Clear-to-Q of the Input Data Register Asynchronous Preset-to-Q of the Input Data Register Asynchronous Clear Removal Time for the Input Data Register Asynchronous Clear Recovery Time for the Input Data Register Asynchronous Preset Removal Time for the Input Data Register Asynchronous Preset Recovery Time for the Input Data Register –2 –1 Std. –F Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 0.24 0.27 0.32 0.38 0.26 0.30 0.35 0.42 0.00 0.00 0.00 0.00 0.37 0.42 0.50 0.60 0.00 0.00 0.00 0.00 0.45 0.52 0.61 0.73 0.45 0.52 0.61 0.73 0.00 0.00 0.00 0.00 0.22 0.25 0.30 0.36 0.00 0.00 0.00 0.00 0.22 0.25 0.30 0.36 Asynchronous Clear Minimum Pulse Width for the Input Data 0.22 0.25 0.30 0.36 Register Asynchronous Preset Minimum Pulse Width for the Input Data 0.22 0.25 0.30 0.36 Register Clock Minimum Pulse Width HIGH for the Input Data Register Clock Minimum Pulse Width LOW for the Input Data Register 0.36 0.41 0.48 0.57 0.32 0.37 0.43 0.52 Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values. 2 -5 4 v1.2 ProASIC3E DC and Switching Characteristics Output Register tOCKMPWH tOCKMPWL 50% 50% tOSUD tOHD Data_out 1 50% 0 50% 50% 50% 50% 50% 50% CLK Enable 50% tOHE 50% tOWPRE tORECPRE 50% tORECCLR tOREMPRE 50% tOREMCLR 50% Preset tOSUE tOWCLR Clear tOPRE2Q DOUT 50% tOCLKQ 50% tOCLR2Q 50% 50% 50% Figure 2-27 • Output Register Timing Diagram Timing Characteristics Table 2-83 • Output Data Register Propagation Delays Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V Parameter tOCLKQ tOSUD tOHD tOSUE tOHE tOCLR2Q tOPRE2Q tOREMCLR tORECCLR tOREMPRE tORECPRE tOWCLR tOWPRE tOCKMPWH tOCKMPWL Description Clock-to-Q of the Output Data Register Data Setup Time for the Output Data Register Data Hold Time for the Output Data Register Enable Setup Time for the Output Data Register Enable Hold Time for the Output Data Register Asynchronous Clear-to-Q of the Output Data Register Asynchronous Preset-to-Q of the Output Data Register Asynchronous Clear Removal Time for the Output Data Register Asynchronous Clear Recovery Time for the Output Data Register Asynchronous Preset Removal Time for the Output Data Register Asynchronous Preset Recovery Time for the Output Data Register –2 –1 Std. –F Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 0.59 0.67 0.79 0.95 0.31 0.36 0.42 0.50 0.00 0.00 0.00 0.00 0.44 0.50 0.59 0.70 0.00 0.00 0.00 0.00 0.80 0.91 1.07 1.29 0.80 0.91 1.07 1.29 0.00 0.00 0.00 0.00 0.22 0.25 0.30 0.36 0.00 0.00 0.00 0.00 0.22 0.25 0.30 0.36 Asynchronous Clear Minimum Pulse Width for the Output Data 0.22 0.25 0.30 0.36 Register Asynchronous Preset Minimum Pulse Width for the Output Data 0.22 0.25 0.30 0.36 Register Clock Minimum Pulse Width HIGH for the Output Data Register Clock Minimum Pulse Width LOW for the Output Data Register 0.36 0.41 0.48 0.57 0.32 0.37 0.43 0.52 Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values. v1.2 2 - 55 ProASIC3E DC and Switching Characteristics Output Enable Register tOECKMPWH tOECKMPWL 50% CLK 50% tOESUD tOEHD 50% 50% 50% 50% 50% D_Enable 1 50% 0 50% Enable 50% tOEWPRE 50% tOERECPRE 50% tOEREMPRE 50% Preset tOESUEtOEHE tOEWCLR 50% Clear tOEPRE2Q EOUT 50% tOECLKQ 50% tOECLR2Q 50% tOERECCLR 50% tOEREMCLR 50% Figure 2-28 • Output Enable Register Timing Diagram Timing Characteristics Table 2-84 • Output Enable Register Propagation Delays Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V Parameter tOECLKQ tOESUD tOEHD tOESUE tOEHE tOECLR2Q tOEPRE2Q tOEREMCLR tOERECCLR tOEREMPRE tOERECPRE tOEWCLR tOEWPRE Description Clock-to-Q of the Output Enable Register Data Setup Time for the Output Enable Register Data Hold Time for the Output Enable Register Enable Setup Time for the Output Enable Register Enable Hold Time for the Output Enable Register Asynchronous Clear-to-Q of the Output Enable Register Asynchronous Preset-to-Q of the Output Enable Register Asynchronous Clear Removal Time for the Output Enable Register Asynchronous Clear Recovery Time for the Output Enable Register Asynchronous Preset Removal Time for the Output Enable Register Asynchronous Preset Recovery Time for the Output Enable Register –2 –1 Std. –F Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 0.59 0.67 0.79 0.95 0.31 0.36 0.42 0.50 0.00 0.00 0.00 0.00 0.44 0.50 0.58 0.70 0.00 0.00 0.00 0.00 0.67 0.76 0.89 1.07 0.67 0.76 0.89 1.07 0.00 0.00 0.00 0.00 0.22 0.25 0.30 0.36 0.00 0.00 0.00 0.00 0.22 0.25 0.30 0.36 Asynchronous Clear Minimum Pulse Width for the Output Enable 0.22 0.25 0.30 0.36 Register Asynchronous Preset Minimum Pulse Width for the Output Enable 0.22 0.25 0.30 0.36 Register 0.36 0.41 0.48 0.57 0.32 0.37 0.43 0.52 tOECKMPWH Clock Minimum Pulse Width HIGH for the Output Enable Register tOECKMPWL Clock Minimum Pulse Width LOW for the Output Enable Register Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values. 2 -5 6 v1.2 ProASIC3E DC and Switching Characteristics DDR Module Specifications Input DDR Module Input DDR INBUF Data A FF1 D Out_QF (to core) CLK CLKBUF B FF2 E Out_QR (to core) CLR INBUF C DDR_IN Figure 2-29 • Input DDR Timing Model Table 2-85 • Parameter Definitions Parameter Name tDDRICLKQ1 tDDRICLKQ2 tDDRISUD tDDRIHD tDDRICLR2Q1 tDDRICLR2Q2 tDDRIREMCLR tDDRIRECCLR Parameter Definition Clock-to-Out Out_QR Clock-to-Out Out_QF Data Setup Time of DDR input Data Hold Time of DDR input Clear-to-Out Out_QR Clear-to-Out Out_QF Clear Removal Clear Recovery Measuring Nodes (from, to) B, D B, E A, B A, B C, D C, E C, B C, B v1.2 2 - 57 ProASIC3E DC and Switching Characteristics CLK tDDRISUD Data 1 2 3 4 5 6 7 tDDRIHD 8 tDDRIRECCLR CLR tDDRIREMCLR tDDRICLKQ1 tDDRICLR2Q1 Out_QF tDDRICLR2Q2 Out_QR 3 2 4 tDDRICLKQ2 5 7 6 9 Figure 2-30 • Input DDR Timing Diagram Timing Characteristics Table 2-86 • Input DDR Propagation Delays Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V Parameter tDDRICLKQ1 tDDRICLKQ2 tDDRISUD tDDRIHD tDDRICLR2Q1 tDDRICLR2Q2 tDDRIREMCLR tDDRIRECCLR tDDRIWCLR tDDRICKMPWH tDDRICKMPWL FDDRIMAX Description Clock-to-Out Out_QR for Input DDR Clock-to-Out Out_QF for Input DDR Data Setup for Input DDR Data Hold for Input DDR Asynchronous Clear to Out Out_QR for Input DDR Asynchronous Clear-to-Out Out_QF for Input DDR Asynchronous Clear Removal Time for Input DDR Asynchronous Clear Recovery Time for Input DDR Asynchronous Clear Minimum Pulse Width for Input DDR Clock Minimum Pulse Width HIGH for Input DDR Clock Minimum Pulse Width LOW for Input DDR Maximum Frequency for Input DDR –2 0.39 0.27 0.28 0.00 0.57 0.46 0.00 0.22 0.22 0.36 0.32 –1 0.44 0.31 0.32 0.00 0.65 0.53 0.00 0.25 0.25 0.41 0.37 Std. 0.52 0.37 0.38 0.00 0.76 0.62 0.00 0.30 0.30 0.48 0.43 –F 0.62 0.44 0.45 0.00 0.92 0.74 0.00 0.36 0.36 0.57 0.52 871 Units ns ns ns ns ns ns ns ns ns ns ns MHz 1404 1232 1048 Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values. 2 -5 8 v1.2 ProASIC3E DC and Switching Characteristics Output DDR Module Output DDR Data_F (from core) A X FF1 B Out X 0 E X X FF2 1 X OUTBUF CLK CLKBUF C D Data_R (from core) CLR INBUF B C X X DDR_OUT Figure 2-31 • Output DDR Timing Model Table 2-87 • Parameter Definitions Parameter Name tDDROCLKQ tDDROCLR2Q tDDROREMCLR tDDRORECCLR tDDROSUD1 tDDROSUD2 tDDROHD1 tDDROHD2 Parameter Definition Clock-to-Out Asynchronous Clear-to-Out Clear Removal Clear Recovery Data Setup Data_F Data Setup Data_R Data Hold Data_F Data Hold Data_R Measuring Nodes (from, to) B, E C, E C, B C, B A, B D, B A, B D, B v1.2 2 - 59 ProASIC3E DC and Switching Characteristics CLK tDDROSUD2 tDDROHD2 Data_F 1 2 tDDROREMCLR Data_R 6 7 tDDROHD1 8 9 10 tDDRORECCLR CLR tDDROREMCLR tDDROCLR2Q Out tDDROCLKQ 7 2 8 3 9 4 10 11 3 4 5 Figure 2-32 • Output DDR Timing Diagram Timing Characteristics Table 2-88 • Output DDR Propagation Delays Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V Parameter tDDROCLKQ tDDROSUD1 tDDROSUD2 tDDROHD1 tDDROHD2 tDDROCLR2Q tDDROREMCLR tDDRORECCLR tDDROWCLR1 tDDROCKMPWH tDDROCKMPWL FDDOMAX Description Clock-to-Out of DDR for Output DDR Data_F Data Setup for Output DDR Data_R Data Setup for Output DDR Data_F Data Hold for Output DDR Data_R Data Hold for Output DDR Asynchronous Clear-to-Out for Output DDR Asynchronous Clear Removal Time for Output DDR Asynchronous Clear Recovery Time for Output DDR Asynchronous Clear Minimum Pulse Width for Output DDR Clock Minimum Pulse Width HIGH for the Output DDR Clock Minimum Pulse Width LOW for the Output DDR Maximum Frequency for the Output DDR –2 0.70 0.38 0.38 0.00 0.00 0.80 0.00 0.22 0.22 0.36 0.32 –1 0.80 0.43 0.43 0.00 0.00 0.91 0.00 0.25 0.25 0.41 0.37 Std. –F Units ns ns ns ns ns ns ns ns ns ns ns MHz 0.94 1.13 0.51 0.61 0.51 0.61 0.00 0.00 0.00 0.00 1.07 1.29 0.00 0.00 0.30 0.36 0.30 0.36 0.48 0.57 0.43 0.52 1404 1232 1048 871 Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values. 2 -6 0 v1.2 ProASIC3E DC and Switching Characteristics VersaTile Characteristics VersaTile Specifications as a Combinatorial Module The ProASIC3E library offers all combinations of LUT-3 combinatorial functions. In this section, timing characteristics are presented for a sample of the library. For more details, refer to the Fusion, IGLOO®/e, and ProASIC3/E Macro Library Guide. A INV Y A OR2 B A AND2 B Y Y A NOR2 B Y A NAND2 B A B C Y A B XOR2 Y XOR3 Y A A B C B C MAJ3 Y A 0 MUX2 B 1 Y NAND3 S Figure 2-33 • Sample of Combinatorial Cells v1.2 2 - 61 ProASIC3E DC and Switching Characteristics tPD A NAND2 or Any Combinatorial Logic Y B tPD = MAX(tPD(RR), tPD(RF), tPD(FF), tPD(FR)) where edges are applicable for the particular combinatorial cell VCC 50% A, B, C 50% GND VCC 50% OUT GND VCC OUT 50% tPD (RF) Figure 2-34 • Timing Model and Waveforms 50% tPD (RR) tPD (FF) tPD (FR) GND 50% 2 -6 2 v1.2 ProASIC3E DC and Switching Characteristics Timing Characteristics Table 2-89 • Combinatorial Cell Propagation Delays Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V Combinatorial Cell INV AND2 NAND2 OR2 NOR2 XOR2 MAJ3 XOR3 MUX2 AND3 Equation Y = !A Y=A·B Y = !(A · B) Y=A+B Y = !(A + B) Y=A⊕B Y = MAJ(A , B, C) Y=A⊕B⊕C Y = A !S + B S Y=A·B·C Parameter tPD tPD tPD tPD tPD tPD tPD tPD tPD tPD –2 0.40 0.47 0.47 0.49 0.49 0.74 0.70 0.87 0.51 0.56 –1 0.46 0.54 0.54 0.55 0.55 0.84 0.79 1.00 0.58 0.64 Std. 0.54 0.63 0.63 0.65 0.65 0.99 0.93 1.17 0.68 0.75 –F 0.65 0.76 0.76 0.78 0.78 1.19 1.12 1.41 0.81 0.90 Units ns ns ns ns ns ns ns ns ns ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values. VersaTile Specifications as a Sequential Module The ProASIC3E library offers a wide variety of sequential cells, including flip-flops and latches. Each has a data input and optional enable, clear, or preset. In this section, timing characteristics are presented for a representative sample from the library. For more details, refer to the Fusion, IGLOO/e, and ProASIC3/E Macro Library Guide. Data D DFN1 Q Out Data D En CLK Q DFN1E1 Out CLK PRE Data D Q DFN1C1 Out Data En CLK D Q Out DFI1E1P1 CLK CLR Figure 2-35 • Sample of Sequential Cells v1.2 2 - 63 ProASIC3E DC and Switching Characteristics tCKMPWH tCKMPWL 50% 50% tSUD Data 50% tHD 0 50% 50% 50% 50% 50% 50% CLK EN 50% tHE tWPRE tSUE 50% tRECPRE 50% tRECCLR 50% tREMPRE 50% tREMCLR 50% PRE tWCLR CLR tPRE2Q Out tCLKQ 50% 50% 50% tCLR2Q 50% Figure 2-36 • Timing Model and Waveforms Timing Characteristics Table 2-90 • Register Delays Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V Parameter tCLKQ tSUD tHD tSUE tHE tCLR2Q tPRE2Q tREMCLR tRECCLR tREMPRE tRECPRE tWCLR tWPRE tCKMPWH tCKMPWL Description Clock-to-Q of the Core Register Data Setup Time for the Core Register Data Hold Time for the Core Register Enable Setup Time for the Core Register Enable Hold Time for the Core Register Asynchronous Clear-to-Q of the Core Register Asynchronous Preset-to-Q of the Core Register Asynchronous Clear Removal Time for the Core Register Asynchronous Clear Recovery Time for the Core Register Asynchronous Preset Removal Time for the Core Register Asynchronous Preset Recovery Time for the Core Register Asynchronous Clear Minimum Pulse Width for the Core Register Asynchronous Preset Minimum Pulse Width for the Core Register Clock Minimum Pulse Width HIGH for the Core Register Clock Minimum Pulse Width LOW for the Core Register –2 –1 Std. –F Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 0.55 0.63 0.74 0.89 0.43 0.49 0.57 0.69 0.00 0.00 0.00 0.00 0.45 0.52 0.61 0.73 0.00 0.00 0.00 0.00 0.40 0.45 0.53 0.64 0.40 0.45 0.53 0.64 0.00 0.00 0.00 0.00 0.22 0.25 0.30 0.36 0.00 0.00 0.00 0.00 0.22 0.25 0.30 0.36 0.22 0.25 0.30 0.36 0.22 0.25 0.30 0.36 0.32 0.37 0.43 0.52 0.36 0.41 0.48 0.57 Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values. 2 -6 4 v1.2 ProASIC3E DC and Switching Characteristics Global Resource Characteristics A3PE600 Clock Tree Topology Clock delays are device-specific. Figure 2-37 is an example of a global tree used for clock routing. The global tree presented in Figure 2-37 is driven by a CCC located on the west side of the A3PE600 device. It is used to drive all D-flip-flops in the device. Central Global Rib CCC VersaTile Rows Global Spine Figure 2-37 • Example of Global Tree Use in an A3PE600 Device for Clock Routing Global Tree Timing Characteristics Global clock delays include the central rib delay, the spine delay, and the row delay. Delays do not include I/O input buffer clock delays, as these are I/O standard–dependent, and the clock may be driven and conditioned internally by the CCC module. For more details on clock conditioning capabilities, refer to the "Clock Conditioning Circuits" section on page 2-68. Table 2-91 on page 2-66, Table 2-92 on page 2-66, and Table 2-93 on page 2-67 present minimum and maximum global clock delays within the device. Minimum and maximum delays are measured with minimum and maximum loading. v1.2 2 - 65 ProASIC3E DC and Switching Characteristics Timing Characteristics Table 2-91 • A3PE600 Global Resource Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V –2 Parameter tRCKL tRCKH Description Input LOW Delay for Global Clock Input HIGH Delay for Global Clock 1 2 –1 1 2 Std. 1 2 –F 1 Min. Max. Min. Max. Min. Max. Min. Max.2 Units 0.83 1.04 0.94 1.18 1.11 1.39 1.33 1.67 0.81 1.06 0.93 1.21 1.09 1.42 1.31 1.71 ns ns ns ns 0.25 0.28 0.33 0.40 ns MHz tRCKMPWH Minimum Pulse Width HIGH for Global Clock tRCKMPWL Minimum Pulse Width LOW for Global Clock tRCKSW FRMAX Notes: Maximum Skew for Global Clock Maximum Frequency for Global Clock 1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element, located in a lightly loaded row (single element is connected to the global net). 2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row (all available flip-flops are connected to the global net in the row). 3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values. Table 2-92 • A3PE1500 Global Resource Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V –2 Parameter tRCKL tRCKH Description Input LOW Delay for Global Clock Input HIGH Delay for Global Clock Min. –1 Std. –F Units ns ns ns ns 0.26 0.29 0.34 0.41 ns MHz 1 Max.2 Min.1 Max.2 Min.1 Max.2 Min.1 Max.2 1.07 1.29 1.22 1.47 1.43 1.72 1.72 2.07 1.06 1.32 1.21 1.50 1.42 1.76 1.71 2.12 tRCKMPWH Minimum Pulse Width HIGH for Global Clock tRCKMPWL Minimum Pulse Width LOW for Global Clock tRCKSW FRMAX Notes: Maximum Skew for Global Clock Maximum Frequency for Global Clock 1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element, located in a lightly loaded row (single element is connected to the global net). 2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row (all available flip-flops are connected to the global net in the row). 3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values. 2 -6 6 v1.2 ProASIC3E DC and Switching Characteristics Table 2-93 • A3PE3000 Global Resource Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V –2 Parameter tRCKL tRCKH Description Input LOW Delay for Global Clock Input HIGH Delay for Global Clock –1 Std. –F ns ns ns ns 0.26 0.29 0.35 0.41 ns MHz Min.1 Max.2 Min.1 Max.2 Min.1 Max.2 Min.1 Max.2 Units 1.41 1.62 1.60 1.85 1.88 2.17 2.26 2.61 1.40 1.66 1.59 1.89 1.87 2.22 2.25 2.66 tRCKMPWH Minimum Pulse Width HIGH for Global Clock tRCKMPWL Minimum Pulse Width LOW for Global Clock tRCKSW FRMAX Notes: Maximum Skew for Global Clock Maximum Frequency for Global Clock 1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element, located in a lightly loaded row (single element is connected to the global net). 2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row (all available flip-flops are connected to the global net in the row). 3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values. v1.2 2 - 67 ProASIC3E DC and Switching Characteristics Clock Conditioning Circuits CCC Electrical Specifications Timing Characteristics Table 2-94 • ProASIC3E CCC/PLL Specification Parameter Clock Conditioning Circuitry Input Frequency fIN_CCC Clock Conditioning Circuitry Output Frequency fOUT_CCC Delay Increments in Programmable Delay Blocks Serial Clock (SCLK) for Dynamic PLL 1 2, 3 Minimum 1.5 0.75 Typical Maximum 350 350 Units MHz MHz ps 160 125 32 1.5 Max Peak-to-Peak Period Jitter 1 Global Network Used 3 Global Networks Used 0.70% 1.20% 2.00% 5.60% 300 6.0 1.6 0.8 48.5 51.5 5.56 5.56 2.2 MHz Number of Programmable Values in Each Programmable Delay Block Input Period Jitter CCC Output Peak-to-Peak Period Jitter FCCC_OUT ns 0.75 MHz to 24 MHz 24 MHz to 100 MHz 100 MHz to 250 MHz 250 MHz to 350 MHz Acquisition Time LockControl = 0 LockControl = 1 Tracking Jitter 4 0.50% 1.00% 1.75% 2.50% µs ms ns ns % ns ns ns LockControl = 0 LockControl = 1 Output Duty Cycle Delay Range in Block: Programmable Delay 1 2, 3 2, 3 0.6 0.025 Delay Range in Block: Programmable Delay 2 Delay Range in Block: Fixed Notes: Delay1, 2 1. Maximum value obtained for a –2 speed-grade device in worst-case commercial conditions. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values. 2. This delay is a function of voltage and temperature. See Table 2-6 on page 2-5 for deratings. 3. TJ = 25°C, VCC = 1.5 V. 4. Tracking jitter is defined as the variation in clock edge position of PLL outputs with reference to the PLL input clock edge. Tracking jitter does not measure the variation in PLL output period, which is covered by the period jitter parameter. 2 -6 8 v1.2 ProASIC3E DC and Switching Characteristics Output Signal Tperiod_max Tperiod_min Note: Peak-to-peak jitter measurements are defined by Tpeak-to-peak = Tperiod_max – Tperiod_min. Figure 2-38 • Peak-to-Peak Jitter Definition v1.2 2 - 69 ProASIC3E DC and Switching Characteristics Embedded SRAM and FIFO Characteristics SRAM RAM4K9 ADDRA11 ADDRA10 ADDRA0 DINA8 DINA7 DOUTA8 DOUTA7 DOUTA0 RAM512X18 RADDR8 RADDR7 RADDR0 RD17 RD16 RD0 DINA0 RW1 RW0 WIDTHA1 WIDTHA0 PIPEA WMODEA BLKA WENA CLKA ADDRB11 ADDRB10 ADDRB0 DINB8 DINB7 DOUTB8 DOUTB7 DOUTB0 PIPE REN RCLK WADDR8 WADDR7 WADDR0 WD17 WD16 WD0 DINB0 WIDTHB1 WIDTHB0 PIPEB WMODEB BLKB WENB CLKB RESET WW1 WW0 WEN WCLK RESET Figure 2-39 • RAM Models 2 -7 0 v1.2 ProASIC3E DC and Switching Characteristics Timing Waveforms tCYC tCKH CLK tAS ADD A0 tBKS BLK_B tENS WEN_B tCKQ1 DO Dn D0 tDOH1 Figure 2-40 • RAM Read for Pass-Through Output tCKL tAH A1 A2 tBKH tENH D1 D2 tCYC tCKH CLK t ADD tBKS BLK_B tENS WEN_B tCKQ2 DO Dn D0 tDOH2 Figure 2-41 • RAM Read for Pipelined Output AS tCKL tAH A0 A1 A2 tBKH tENH D1 v1.2 2 - 71 ProASIC3E DC and Switching Characteristics tCYC tCKH CLK tAS ADD tBKS tBKH BLK_B tENS WEN_B tDS DI DI0 tDH DI1 tENH A0 tAH A1 A2 tCKL DO Dn D2 Figure 2-42 • RAM Write, Output Retained (WMODE = 0) tCYC tCKH CLK tAS ADD tBKS BLK_B tENS WEN_B tDS DI DO (pass-through) DO (pipelined) DI0 tDH DI1 DI2 tBKH A0 tAH A1 A2 tCKL Dn DI0 DI1 Dn DI0 DI1 Figure 2-43 • RAM Write, Output as Write Data (WMODE = 1) 2 -7 2 v1.2 ProASIC3E DC and Switching Characteristics CLK1 tAS ADD1 tDS DI1 tAH A0 tDH D1 tCCKH CLK2 WEN_B1 WEN_B2 ADD2 DI2 DO2 (pass-through) DO2 (pipelined) A0 D0 tCKQ1 Dn D0 tCKQ2 Dn D0 A1 D2 A3 D3 tAS tAH A0 A4 D4 Figure 2-44 • Write Access after Write onto Same Address v1.2 2 - 73 ProASIC3E DC and Switching Characteristics CLK1 tAS tAH ADD1 DI1 CLK2 WEN_B1 WEN_B2 tAS tAH ADD2 DO2 (pass-through) DO2 (pipelined) Dn Dn A0 tCKQ1 D0 tCKQ2 D0 D1 A1 A4 A0 tDS tDH D0 tWRO A2 D2 A3 D3 Figure 2-45 • Read Access after Write onto Same Address 2 -7 4 v1.2 ProASIC3E DC and Switching Characteristics CLK1 tAS ADD1 WEN_B1 tCKQ1 DO1 (pass-through) DO1 (pipelined) CLK2 tAS ADD2 A0 D1 tAH A1 D2 A3 D3 Dn D0 tCKQ2 Dn tCCKH D0 tCKQ1 D1 tAH A0 A1 A0 DI2 WEN_B2 Figure 2-46 • Write Access after Read onto Same Address tCYC tCKH CLK tCKL RESET_B tRSTBQ DO Dm Dn Figure 2-47 • RAM Reset v1.2 2 - 75 ProASIC3E DC and Switching Characteristics Timing Characteristics Table 2-95 • RAM4K9 Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V Parameter tAS tAH tENS tENH tBKS tBKH tDS tDH tCKQ1 tCKQ2 tWRO tCCKH tRSTBQ tREMRSTB tRECRSTB tMPWRSTB tCYC FMAX Address Setup Time Address Hold Time REN_B, WEN_B Setup Time REN_B, WEN_B Hold Time BLK_B Setup Time BLK_B Hold Time Input Data (DI) Setup Time Input Data (DI) Hold Time Clock HIGH to New Data Valid on DO (pass-through, WMODE = 1) Clock HIGH to New Data Valid on DO (pipelined) Description –2 –1 Std. –F Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 0.25 0.28 0.33 0.40 0.00 0.00 0.00 0.00 0.14 0.16 0.19 0.23 0.10 0.11 0.13 0.16 0.23 0.27 0.31 0.37 0.02 0.02 0.02 0.03 0.18 0.21 0.25 0.29 0.00 0.00 0.00 0.00 2.36 2.68 3.15 3.79 0.89 1.02 1.20 1.44 Clock HIGH to New Data Valid on DO (output retained, WMODE = 0) 1.79 2.03 2.39 2.87 Address collision clk-to-clk delay for reliable read access after write TBD TBD TBD TBD on same address Address collision clk-to-clk delay for reliable write access after TBD TBD TBD TBD write/read on same address RESET_B LOW to Data Out LOW on DO (pass-through) RESET_B LOW to Data Out LOW on DO (pipelined) RESET_B Removal RESET_B Recovery RESET_B Minimum Pulse Width Clock Cycle Time Maximum Frequency 0.92 1.05 1.23 1.48 0.92 1.05 1.23 1.48 0.29 0.33 0.38 0.46 1.50 1.71 2.01 2.41 0.21 0.24 0.29 0.34 3.23 3.68 4.32 5.19 310 272 231 193 MHz Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values. 2 -7 6 v1.2 ProASIC3E DC and Switching Characteristics Table 2-96 • RAM512X18 Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V Parameter tAS tAH tENS tENH tDS tD H tCKQ1 tCKQ2 tWRO tCCKH tRSTBQ tREMRSTB tRECRSTB tMPWRSTB tCYC FMAX Address Setup Time Address Hold Time REN_B, WEN_B Setup Time REB_B, WEN_B Hold Time Input Data (DI) Setup Time Input Data (DI) Hold Time Clock HIGH to New Data Valid on DO (pipelined) Description –2 –1 Std. –F Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 0.25 0.28 0.33 0.40 0.00 0.00 0.00 0.00 0.18 0.20 0.24 0.28 0.06 0.07 0.08 0.09 0.18 0.21 0.25 0.29 0.00 0.00 0.00 0.00 0.90 1.02 1.20 1.44 Clock HIGH to New Data Valid on DO (output retained, WMODE = 0) 2.16 2.46 2.89 3.47 Address collision clk-to-clk delay for reliable read access after write TBD TBD TBD TBD on same address Address collision clk-to-clk delay for reliable write access after TBD TBD TBD TBD write/read on same address RESET_B LOW to Data Out LOW on DO (pass-through) RESET_B LOW to Data Out LOW on DO (pipelined) RESET_B Removal RESET_B Recovery RESET_B Minimum Pulse Width Clock Cycle Time Maximum Frequency 0.92 1.05 1.23 1.48 0.92 1.05 1.23 1.48 0.29 0.33 0.38 0.46 1.50 1.71 2.01 2.41 0.21 0.24 0.29 0.34 3.23 3.68 4.32 5.19 310 272 231 193 MHz Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values. v1.2 2 - 77 ProASIC3E DC and Switching Characteristics FIFO FIFO4K18 RW2 RW1 RW0 WW2 WW1 WW0 ESTOP FSTOP AEVAL11 AEVAL10 RD17 RD16 RD0 FULL AFULL EMPTY AEMPTY AEVAL0 AFVAL11 AFVAL10 AFVAL0 REN RBLK RCLK WD17 WD16 WD0 WEN WBLK WCLK RPIPE RESET Figure 2-48 • FIFO Model 2 -7 8 v1.2 ProASIC3E DC and Switching Characteristics Timing Waveforms RCLK/ WCLK tMPWRSTB RESET_B tRSTFG EMPTY tRSTAF AEMPTY tRSTFG FULL tRSTAF AFULL WA/RA (Address Counter) Figure 2-49 • FIFO Reset tRSTCK MATCH (A0) tCYC RCLK tRCKEF EMPTY tCKAF AEMPTY WA/RA (Address Counter) NO MATCH NO MATCH Dist = AEF_TH MATCH (EMPTY) Figure 2-50 • FIFO EMPTY Flag and AEMPTY Flag Assertion v1.2 2 - 79 ProASIC3E DC and Switching Characteristics tCYC WCLK tWCKFF FULL tCKAF AFULL WA/RA NO MATCH (Address Counter) NO MATCH Dist = AFF_TH MATCH (FULL) Figure 2-51 • FIFO FULL Flag and AFULL Flag Assertion WCLK WA/RA (Address Counter) MATCH (EMPTY) NO MATCH NO MATCH 2nd Rising Edge After 1st Write tRCKEF NO MATCH NO MATCH Dist = AEF_TH + 1 RCLK 1st Rising Edge After 1st Write EMPTY tCKAF AEMPTY Figure 2-52 • FIFO EMPTY Flag and AEMPTY Flag Deassertion RCLK WA/RA MATCH (FULL) NO MATCH (Address Counter) 1st Rising Edge After 1st WCLK Read FULL tCKAF AFULL NO MATCH 1st Rising Edge After 2nd Read tWCKF NO MATCH NO MATCH Dist = AFF_TH – 1 Figure 2-53 • FIFO FULL Flag and AFULL Flag Deassertion 2 -8 0 v1.2 ProASIC3E DC and Switching Characteristics Timing Characteristics Table 2-97 • FIFO Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V Parameter tENS tENH tBKS tBKH tDS tDH tCKQ1 tCKQ2 tRCKEF tWCKFF tCKAF tRSTFG tRSTAF tRSTBQ Description REN_B, WEN_B Setup Time REN_B, WEN_B Hold Time BLK_B Setup Time BLK_B Hold Time Input Data (DI) Setup Time Input Data (DI) Hold Time Clock HIGH to New Data Valid on DO (pass-through) Clock HIGH to New Data Valid on DO (pipelined) RCLK HIGH to Empty Flag Valid WCLK HIGH to Full Flag Valid Clock HIGH to Almost Empty/Full Flag Valid RESET_B LOW to Empty/Full Flag Valid RESET_B LOW to Almost Empty/Full Flag Valid RESET_B LOW to Data Out LOW on DO (pass-through) RESET_B LOW to Data Out LOW on DO (pipelined) tREMRSTB tRECRSTB tMPWRSTB tCYC FMAX RESET_B Removal RESET_B Recovery RESET_B Minimum Pulse Width Clock Cycle Time Maximum Frequency –2 1.38 0.02 0.19 0.00 0.18 0.00 2.36 0.89 1.72 1.63 6.19 1.69 6.13 0.92 0.92 0.29 1.50 0.21 3.23 310 –1 1.57 0.02 0.22 0.00 0.21 0.00 2.68 1.02 1.96 1.86 7.05 1.93 6.98 1.05 1.05 0.33 1.71 0.24 3.68 272 Std. 1.84 0.02 0.26 0.00 0.25 0.00 3.15 1.20 2.30 2.18 8.29 2.27 8.20 1.23 1.23 0.38 2.01 0.29 4.32 231 –F 2.21 0.03 0.31 0.00 0.29 0.00 3.79 1.44 2.76 2.62 9.96 2.72 9.85 1.48 1.48 0.46 2.41 0.34 5.19 193 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHz Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values. v1.2 2 - 81 ProASIC3E DC and Switching Characteristics Embedded FlashROM Characteristics tSU CLK tHOLD tSU tHOLD tSU tHOLD Address A0 tCKQ2 A1 tCKQ2 D0 tCKQ2 D1 Data D0 Figure 2-54 • Timing Diagram Timing Characteristics Table 2-98 • Embedded FlashROM Access Time Parameter tSU tHOLD tCK2Q FMAX Description Address Setup Time Address Hold Time Clock to Out Maximum Clock Frequency –2 0.53 0.00 16.23 15 –1 0.61 0.00 18.48 15 Std. 0.71 0.00 21.73 15 Units ns ns ns MHz JTAG 1532 Characteristics JTAG timing delays do not include JTAG I/Os. To obtain complete JTAG timing, add I/O buffer delays to the corresponding standard selected; refer to the I/O timing characteristics in the "User I/O Characteristics" section on page 2-12 for more details. Timing Characteristics Table 2-99 • JTAG 1532 Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V Parameter tDISU tDIHD tTMSSU tTMDHD tTCK2Q tRSTB2Q FTCKMAX tTRSTREM tTRSTREC tTRSTMPW Description Test Data Input Setup Time Test Data Input Hold Time Test Mode Select Setup Time Test Mode Select Hold Time Clock to Q (data out) Reset to Q (data out) TCK Maximum Frequency ResetB Removal Time ResetB Recovery Time ResetB Minimum Pulse –2 0.50 1.00 0.50 1.00 6.00 –1 0.57 1.13 0.57 1.13 6.80 Std. 0.67 1.33 0.67 1.33 8.00 26.67 19.00 0.00 0.27 TBD Units ns ns ns ns ns ns MHz ns ns ns 20.00 22.67 25.00 22.00 0.00 0.20 TBD 0.00 0.23 TBD Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values. 2 -8 2 v1.2 ProASIC3E DC and Switching Characteristics Part Number and Revision Date Part Number 51700098-002-2 Revised June 2008 List of Changes The following table lists critical changes that were made in the current version of the chapter. Previous Version v1.1 (January 2008) Changes in Current Version (v1.2) The title of Table 2-4 · Overshoot and Undershoot Limits 1 was modified to remove "as measured on quiet I/Os." Table note 2 was revised to remove "estimated SSO density over cycles." Table note 3 was deleted. Table 2-74 · LVDS Minimum and Maximum DC Input and Output Levels was updated. v1.0 (January 2008) In Table 2-3 · Flash Programming Limits – Retention, Storage and Operating Temperature1, Maximum Operating Junction Temperature was changed from 110°C to 100°C for both commercial and industrial grades. The "PLL Behavior at Brownout Condition" section is new. In the "PLL Contribution—PPLL" section, the following was deleted: FCLKIN is the input clock frequency. In Table 2-14 · Summary of Maximum and Minimum DC Input Levels, the note was incorrect. It previously said TJ and it was corrected and changed to TA. In Table 2-94 · ProASIC3E CCC/PLL Specification, the SCLK parameter and note 1 are new. Table 2-99 · JTAG 1532 was populated with the parameter data, which was not in the previous version of the document. v2.1 (July 2007) v2.0 (April 2007) This document was previously in datasheet v2.1. As a result of moving to the handbook format, Actel has restarted the version numbers so the new version number is v1.0. The caption "Main (chip)" in Figure 2-9 • Overview of Automotive ProASIC3 VersaNet Global Network was changed to "Chip (main)." The TJ parameter in Table 3-2 • Recommended Operating Conditions was changed to TA, ambient temperature, and table notes 4–6 were added. The "PLL Macro" section was updated to add information on the VCO and PLL outputs during power-up. Advance v0.6 (January 2007) The "PLL Macro" section was updated to include power-up information. Table 2-13 • ProASIC3E CCC/PLL Specification was updated. Figure 2-19 • Peak-to-Peak Jitter Definition is new. The "SRAM and FIFO" section was updated with operation and timing requirement information. The "RESET" section was updated with read and write information. The "RESET" section was updated with read and write information. The "Introduction" in the "Advanced I/Os" section was updated to include information on input and output buffers being disabled. In the Table 2-15 • Levels of Hot-Swap Support, the ProASIC3 compliance descriptions were updated for levels 3 and 4. 2-17 2-68 2-82 N/A Page 2-3 2-47 2-2 2-4 2-10 2-9 3-2 2-15 2-15 2-30 2-18 2-21 2-25 2-25 2-28 2-34 v1.2 2 - 83 ProASIC3E DC and Switching Characteristics Previous Version Advance v0.6 (continued) Changes in Current Version (v1.2) Table 2-45 • I/O Hot-Swap and 5 V Input Tolerance Capabilities in ProASIC3E Devices was updated. Notes 3, 4, and 5 were added to Table 2-17 • Comparison Table for 5 V– Compliant Receiver Scheme. 5 x 52.72 was changed to 52.7 and the Maximum current was updated from 4 x 52.7 to 5 x 52.7. The "VCCPLF PLL Supply Voltage" section was updated. The "VPUMP Programming Supply Voltage" section was updated. The "GL Globals" section was updated to include information about direct input into quadrant clocks. VJTAG was deleted from the "TCK Test Clock" section. In Table 2-22 • Recommended Tie-Off Values for the TCK and TRST Pins, TSK was changed to TCK in note 2. Note 3 was also updated. Ambient was deleted from Table 3-2 • Recommended Operating Conditions. VPUMP programming mode was changed from "3.0 to 3.6" to "3.15 to 3.45". Note 3 is new in Table 3-4 • Overshoot and Undershoot Limits (as measured on quiet I/Os). In EQ 3-2, 150 was changed to 110 and the result changed to 5.88. Table 3-6 • Temperature and Voltage Derating Factors for Timing Delays was updated. Table 3-5 • Package Thermal Resistivities was updated. Table 3-10 • Different Components Contributing to the Dynamic Power Consumption in ProASIC3E Devices was updated. tWRO and tCCKH were 3-95 • RAM512X18. added to Table 3-94 • RAM4K9 and Table Page 2-64 2-40 2-50 2-50 2-51 2-51 2-51 3-2 3-2 3-5 3-5 3-5 3-8 3-74 to 3-74 3-23 3-71 to 3-73 3-80 N/A N/A 2-8 2-28 2-24 2-21 2-25 2-25 2-25 2-27 2-28 The note in Table 3-24 • I/O Input Rise Time, Fall Time, and Related I/O Reliability was updated. Figure 3-43 • Write Access After Write onto Same Address, Figure 3-44 • Read Access After Write onto Same Address, and Figure 3-45 • Write Access After Read onto Same Address are new. Figure 3-53 • Timing Diagram was updated. Advance v0.4 (October 2005) B-LVDS and M-LDVS are new I/O standards added to the datasheet. The term flow-through was changed to pass-through. Figure 2-8 • Very-Long-Line Resources was updated. The footnotes in Figure 2-27 • CCC/PLL Macro were updated. The Delay Increments in the Programmable Delay Blocks specification in Figure 2-24 • ProASIC3E CCC Options. The "SRAM and FIFO" section was updated. The "RESET" section was updated. The "WCLK and RCLK" section was updated. The "RESET" section was updated. The "RESET" section was updated. The "Introduction" of the "Introduction" section was updated. 2 -8 4 v1.2 ProASIC3E DC and Switching Characteristics Previous Version Advance v0.4 (continued) Changes in Current Version (v1.2) PCI-X 3.3 V was added to the Compatible Standards for 3.3 V in Table 211 • VCCI Voltages and Compatible Standards Table 2-35 • ProASIC3E I/O Features was updated. The "Double Data Rate (DDR) Support" section was updated to include information concerning implementation of the feature. The "Electrostatic Discharge (ESD) Protection" section was updated to include testing information. Level 3 and 4 descriptions were updated in Table 2-43 • I/O Hot-Swap and 5 V Input Tolerance Capabilities in ProASIC3 Devices. The notes in Table 2-45 • I/O Hot-Swap and 5 V Input Tolerance Capabilities in ProASIC3E Devices were updated. The "Simultaneous Switching Outputs (SSOs) and Printed Circuit Board Layout" section is new. A footnote was added to Table 2-37 • Maximum I/O Frequency for SingleEnded and Differential I/Os in All Banks in ProASIC3E Devices (maximum drive strength and high slew selected). Table 2-48 • ProASIC3E I/O Attributes vs. I/O Standard Applications Table 2-55 • ProASIC3 I/O Standards—SLEW and Output Drive (OUT_DRIVE) Settings The "x" was updated in the "Pin Descriptions" section. The "VCC Core Supply Voltage" pin description was updated. The "VMVx I/O Supply Voltage (quiet)" pin description was updated to include information concerning leaving the pin unconnected. EXTFB was removed from Figure 2-24 • ProASIC3E CCC Options. The CCC Output Peak-to-Peak Period Jitter FCCC_OUT was updated in Table 2-13 • ProASIC3E CCC/PLL Specification. EXTFB was removed from Figure 2-27 • CCC/PLL Macro. The LVPECL specification in Table 2-45 • I/O Hot-Swap and 5 V Input Tolerance Capabilities in ProASIC3E Devices was updated. Table 2-15 • Levels of Hot-Swap Support was updated. The "Cold-Sparing Support" section was updated. "Electrostatic Discharge (ESD) Protection" section was updated. The VJTAG and I/O pin descriptions were updated in the "Pin Descriptions" section. The "VJTAG JTAG Supply Voltage" pin description was updated. The "VPUMP Programming Supply Voltage" pin description was updated to include information on what happens when the pin is tied to ground. The "I/O User Input/Output" pin description was updated to include information on what happens when the pin is unused. The "JTAG Pins" section was updated to include information on what happens when the pin is unused. The "Programming" section was updated to include information concerning serialization. The "JTAG 1532" section was updated to include SAMPLE/PRELOAD information. Page 2-29 2-54 2-32 2-35 2-64 2-64 2-41 2-55 2-81 2-85 2-50 2-50 2-50 2-24 2-30 2-28 2-64 2-34 2-34 2-35 2-50 2-50 2-50 2-50 2-51 2-53 2-54 v1.2 2 - 85 ProASIC3E DC and Switching Characteristics Previous Version Advance v0.4 (continued) Changes in Current Version (v1.2) Page The "DC and Switching Characteristics" chapter was updated with new Starting information. on page 3-1 Table 3-6 was updated. In Table 3-10, PAC4 was updated. Table 3-19 was updated. The note in Table 3-24 was updated. All Timing Characteristics tables were updated from LVTTL to Register Delays The Timing Characteristics for RAM4K9, RAM512X18, and FIFO were updated. FTCKMAX was updated in Table 3-98. 3-5 3-8 3-20 3-23 3-26 to 3-64 3-74 to 3-79 3-80 2-9 2-9 2-9 2-15 2-28 2-19 2-25 2-25 2-27 2-51 2-31 2-34 2-64 2-81 2-51 2-50 3-6 3-9 Advance v0.2 Figure 2-11 was updated. The "Clock Resources (VersaNets)" section was updated. The "VersaNet Global Networks and Spine Access" section was updated. The "PLL Macro" section was updated. Figure 2-27 was updated. Figure 2-20 was updated. Table 2-5 was updated. Table 2-6 was updated. The "FIFO Flag Usage Considerations" section was updated. Table 2-33 was updated. Figure 2-24 was updated. The "Cold-Sparing Support" section is new. Table 2-45 was updated. Table 2-48 was updated. Pin descriptions in the "JTAG Pins" section were updated. The "Pin Descriptions" section was updated. Table 3-7 was updated. The "Methodology" section was updated. Actel Safety Critical, Life Support, and High-Reliability Applications Policy The Actel products described in this advance status datasheet may not have completed Actel’s qualification process. Actel may amend or enhance products during the product introduction and qualification process, resulting in changes in device functionality or performance. It is the responsibility of each customer to ensure the fitness of any Actel product (but especially a new product) for a particular purpose, including appropriateness for safety-critical, life-support, and other high-reliability applications. Consult Actel’s Terms and Conditions for specific liability exclusions relating to life-support applications. A reliability report covering all of Actel’s products is available on the Actel website at http://www.actel.com/documents/ORT_Report.pdf. Actel also offers a variety of enhanced qualification and lot acceptance screening procedures. Contact your local Actel sales office for additional reliability information. 2 -8 6 v1.2 ProASIC®3E Packaging 3 – Package Pin Assignments 208-Pin PQFP 1 208 208-Pin PQFP Note: This is the top view of the package. Note For Package Manufacturing and Environmental information, visit the Resource Center at http://www.actel.com/products/solutions/package/docs.aspx. v 1.5 3-1 Package Pin Assignments 208-Pin PQFP Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 A3PE600 Function GND GNDQ VMV7 GAB2/IO133PSB7V1 GAA2/IO134PDB7V1 IO134NDB7V1 GAC2/IO132PDB7V1 IO132NDB7V1 IO130PDB7V1 IO130NDB7V1 IO127PDB7V1 IO127NDB7V1 IO126PDB7V0 IO126NDB7V0 IO124PSB7V0 VCC GND VCCIB7 IO122PPB7V0 IO121PSB7V0 IO122NPB7V0 GFC1/IO120PSB7V0 GFB1/IO119PDB7V0 GFB0/IO119NDB7V0 VCOMPLF GFA0/IO118NPB6V1 VCCPLF GFA1/IO118PPB6V1 GND GFA2/IO117PDB6V1 IO117NDB6V1 GFB2/IO116PPB6V1 GFC2/IO115PPB6V1 IO116NPB6V1 IO115NPB6V1 VCC 208-Pin PQFP Pin Number 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 A3PE600 Function IO112PDB6V1 IO112NDB6V1 IO108PSB6V0 VCCIB6 GND IO106PDB6V0 IO106NDB6V0 GEC1/IO104PDB6V0 GEC0/IO104NDB6V0 GEB1/IO103PPB6V0 GEA1/IO102PPB6V0 GEB0/IO103NPB6V0 GEA0/IO102NPB6V0 VMV6 GNDQ GND VMV5 GNDQ IO101NDB5V2 GEA2/IO101PDB5V2 IO100NDB5V2 GEB2/IO100PDB5V2 IO99NDB5V2 GEC2/IO99PDB5V2 IO98PSB5V2 VCCIB5 IO96PSB5V2 IO94NDB5V1 GND IO94PDB5V1 IO92NDB5V1 IO92PDB5V1 IO88NDB5V0 IO88PDB5V0 VCC VCCIB5 208-Pin PQFP Pin Number 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 A3PE600 Function IO85NPB5V0 IO84NPB5V0 IO85PPB5V0 IO84PPB5V0 IO83NPB5V0 IO82NPB5V0 IO83PPB5V0 IO82PPB5V0 GND IO80NDB4V1 IO80PDB4V1 IO79NPB4V1 IO78NPB4V1 IO79PPB4V1 IO78PPB4V1 VCC VCCIB4 IO76NDB4V1 IO76PDB4V1 IO72NDB4V0 IO72PDB4V0 IO70NDB4V0 GDC2/IO70PDB4V0 IO68NDB4V0 GND GDA2/IO68PDB4V0 GDB2/IO69PSB4V0 GNDQ TCK TDI TMS VMV4 GND VPUMP GNDQ TDO 3 -2 v1.5 ProASIC3E Packaging 208-Pin PQFP Pin Number 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 A3PE600 Function TRST VJTAG VMV3 GDA0/IO67NPB3V1 GDB0/IO66NPB3V1 GDA1/IO67PPB3V1 GDB1/IO66PPB3V1 GDC0/IO65NDB3V1 GDC1/IO65PDB3V1 IO62NDB3V1 IO62PDB3V1 IO58NDB3V0 IO58PDB3V0 GND VCCIB3 GCC2/IO55PSB3V0 GCB2/IO54PSB3V0 NC IO53NDB3V0 GCA2/IO53PDB3V0 GCA1/IO52PPB3V0 GND VCCPLC GCA0/IO52NPB3V0 VCOMPLC GCB0/IO51NDB2V1 GCB1/IO51PDB2V1 GCC1/IO50PSB2V1 IO49NDB2V1 IO49PDB2V1 IO48PSB2V1 VCCIB2 GND VCC IO47NDB2V1 IO47PDB2V1 208-Pin PQFP Pin Number 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 A3PE600 Function IO44NDB2V1 IO44PDB2V1 IO43NDB2V0 IO43PDB2V0 IO40NDB2V0 IO40PDB2V0 GBC2/IO38PSB2V0 GBA2/IO36PSB2V0 GBB2/IO37PSB2V0 VMV2 GNDQ GND VMV1 GNDQ GBA1/IO35PDB1V1 GBA0/IO35NDB1V1 GBB1/IO34PDB1V1 GND GBB0/IO34NDB1V1 GBC1/IO33PDB1V1 GBC0/IO33NDB1V1 IO31PDB1V1 IO31NDB1V1 IO27PDB1V0 IO27NDB1V0 VCCIB1 VCC IO23PPB1V0 IO22PSB1V0 IO23NPB1V0 IO21PDB1V0 IO21NDB1V0 IO19PPB0V2 GND IO18PPB0V2 IO19NPB0V2 208-Pin PQFP Pin Number 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 A3PE600 Function IO18NPB0V2 IO17PPB0V2 IO16PPB0V2 IO17NPB0V2 IO16NPB0V2 VCCIB0 VCC IO15PDB0V2 IO15NDB0V2 IO13PDB0V2 IO13NDB0V2 IO11PSB0V1 IO09PDB0V1 IO09NDB0V1 GND IO07PDB0V1 IO07NDB0V1 IO05PDB0V0 IO05NDB0V0 VCCIB0 GAC1/IO02PDB0V0 GAC0/IO02NDB0V0 GAB1/IO01PDB0V0 GAB0/IO01NDB0V0 GAA1/IO00PDB0V0 GAA0/IO00NDB0V0 GNDQ VMV0 v1.5 3-3 Package Pin Assignments 208-Pin PQFP Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 A3PE1500 Function GND GNDQ VMV7 GAB2/IO220PSB7V3 GAA2/IO221PDB7V3 IO221NDB7V3 GAC2/IO219PDB7V3 IO219NDB7V3 IO215PDB7V3 IO215NDB7V3 IO212PDB7V2 IO212NDB7V2 IO208PDB7V2 IO208NDB7V2 IO204PSB7V1 VCC GND VCCIB7 IO200PDB7V1 IO200NDB7V1 IO196PSB7V0 GFC1/IO192PSB7V0 GFB1/IO191PDB7V0 GFB0/IO191NDB7V0 VCOMPLF GFA0/IO190NPB6V2 VCCPLF GFA1/IO190PPB6V2 GND GFA2/IO189PDB6V2 IO189NDB6V2 GFB2/IO188PPB6V2 GFC2/IO187PPB6V2 IO188NPB6V2 IO187NPB6V2 VCC 208-Pin PQFP Pin Number 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 A3PE1500 Function IO184PDB6V2 IO184NDB6V2 IO180PSB6V1 VCCIB6 GND IO176PDB6V1 IO176NDB6V1 GEC1/IO169PDB6V0 GEC0/IO169NDB6V0 GEB1/IO168PPB6V0 GEA1/IO167PPB6V0 GEB0/IO168NPB6V0 GEA0/IO167NPB6V0 VMV6 GNDQ GND VMV5 GNDQ IO166NDB5V3 GEA2/IO166PDB5V3 IO165NDB5V3 GEB2/IO165PDB5V3 IO164NDB5V3 GEC2/IO164PDB5V3 IO163PSB5V3 VCCIB5 IO161PSB5V3 IO157NDB5V2 GND IO157PDB5V2 IO153NDB5V2 IO153PDB5V2 IO149NDB5V1 IO149PDB5V1 VCC VCCIB5 208-Pin PQFP Pin Number 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 A3PE1500 Function IO145NDB5V1 IO145PDB5V1 IO143NDB5V1 IO143PDB5V1 IO137NDB5V0 IO137PDB5V0 IO135NDB5V0 IO135PDB5V0 GND IO131NDB4V2 IO131PDB4V2 IO129NDB4V2 IO129PDB4V2 IO127NDB4V2 IO127PDB4V2 VCC VCCIB4 IO121NDB4V1 IO121PDB4V1 IO119NDB4V1 IO119PDB4V1 IO113NDB4V0 GDC2/IO113PDB4V0 IO112NDB4V0 GND GDB2/IO112PDB4V0 GDA2/IO111PSB4V0 GNDQ TCK TDI TMS VMV4 GND VPUMP GNDQ TDO 3 -4 v1.5 ProASIC3E Packaging 208-Pin PQFP Pin Number 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 A3PE1500 Function TRST VJTAG VMV3 GDA0/IO110NPB3V2 GDB0/IO109NPB3V2 GDA1/IO110PPB3V2 GDB1/IO109PPB3V2 GDC0/IO108NDB3V2 GDC1/IO108PDB3V2 IO105NDB3V2 IO105PDB3V2 IO101NDB3V1 IO101PDB3V1 GND VCCIB3 GCC2/IO90PSB3V0 GCB2/IO89PSB3V0 NC IO88NDB3V0 GCA2/IO88PDB3V0 GCA1/IO87PPB3V0 GND VCCPLC GCA0/IO87NPB3V0 VCOMPLC GCB0/IO86NDB2V3 GCB1/IO86PDB2V3 GCC1/IO85PSB2V3 IO83NDB2V3 IO83PDB2V3 IO81PSB2V3 VCCIB2 GND VCC IO73NDB2V2 IO73PDB2V2 208-Pin PQFP Pin Number 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 A3PE1500 Function IO71NDB2V2 IO71PDB2V2 IO67NDB2V1 IO67PDB2V1 IO65NDB2V1 IO65PDB2V1 GBC2/IO60PSB2V0 GBA2/IO58PSB2V0 GBB2/IO59PSB2V0 VMV2 GNDQ GND VMV1 GNDQ GBA1/IO57PDB1V3 GBA0/IO57NDB1V3 GBB1/IO56PDB1V3 GND GBB0/IO56NDB1V3 GBC1/IO55PDB1V3 GBC0/IO55NDB1V3 IO51PDB1V2 IO51NDB1V2 IO47PDB1V1 IO47NDB1V1 VCCIB1 VCC IO43PSB1V1 IO41PDB1V1 IO41NDB1V1 IO35PDB1V0 IO35NDB1V0 IO31PDB0V3 GND IO31NDB0V3 IO29PDB0V3 208-Pin PQFP Pin Number 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 A3PE1500 Function IO29NDB0V3 IO27PDB0V3 IO27NDB0V3 IO23PDB0V2 IO23NDB0V2 VCCIB0 VCC IO18PDB0V2 IO18NDB0V2 IO15PDB0V1 IO15NDB0V1 IO12PSB0V1 IO11PDB0V1 IO11NDB0V1 GND IO08PDB0V1 IO08NDB0V1 IO05PDB0V0 IO05NDB0V0 VCCIB0 GAC1/IO02PDB0V0 GAC0/IO02NDB0V0 GAB1/IO01PDB0V0 GAB0/IO01NDB0V0 GAA1/IO00PDB0V0 GAA0/IO00NDB0V0 GNDQ VMV0 v1.5 3-5 Package Pin Assignments 208-Pin PQFP Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 A3PE3000 Function GND GNDQ VMV7 GAB2/IO308PSB7V4 GAA2/IO309PDB7V4 IO309NDB7V4 GAC2/IO307PDB7V4 IO307NDB7V4 IO303PDB7V3 IO303NDB7V3 IO299PDB7V3 IO299NDB7V3 IO295PDB7V2 IO295NDB7V2 IO291PSB7V2 VCC GND VCCIB7 IO285PDB7V1 IO285NDB7V1 IO279PSB7V0 GFC1/IO275PSB7V0 GFB1/IO274PDB7V0 GFB0/IO274NDB7V0 VCOMPLF GFA0/IO273NPB6V4 VCCPLF GFA1/IO273PPB6V4 GND GFA2/IO272PDB6V4 IO272NDB6V4 GFB2/IO271PPB6V4 GFC2/IO270PPB6V4 IO271NPB6V4 IO270NPB6V4 VCC IO252PDB6V2 IO252NDB6V2 IO248PSB6V1 208-Pin PQFP Pin Number 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 A3PE3000 Function VCCIB6 GND IO244PDB6V1 IO244NDB6V1 GEC1/IO236PDB6V0 GEC0/IO236NDB6V0 GEB1/IO235PPB6V0 GEA1/IO234PPB6V0 GEB0/IO235NPB6V0 GEA0/IO234NPB6V0 VMV6 GNDQ GND VMV5 GNDQ IO233NDB5V4 GEA2/IO233PDB5V4 IO232NDB5V4 GEB2/IO232PDB5V4 IO231NDB5V4 GEC2/IO231PDB5V4 IO230PSB5V4 VCCIB5 IO218NDB5V3 IO218PDB5V3 GND IO214PSB5V2 IO212NDB5V2 IO212PDB5V2 IO208NDB5V1 IO208PDB5V1 VCC VCCIB5 IO202NDB5V1 IO202PDB5V1 IO198NDB5V0 IO198PDB5V0 IO197NDB5V0 IO197PDB5V0 208-Pin PQFP Pin Number 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 A3PE3000 Function IO194NDB5V0 IO194PDB5V0 GND IO184NDB4V3 IO184PDB4V3 IO180NDB4V3 IO180PDB4V3 IO176NDB4V2 IO176PDB4V2 VCC VCCIB4 IO170NDB4V2 IO170PDB4V2 IO166NDB4V1 IO166PDB4V1 IO156NDB4V0 GDC2/IO156PDB4V0 IO154NPB4V0 GND GDB2/IO155PSB4V0 GDA2/IO154PPB4V0 GNDQ TCK TDI TMS VMV4 GND VPUMP GNDQ TDO TRST VJTAG VMV3 GDA0/IO153NPB3V4 GDB0/IO152NPB3V4 GDA1/IO153PPB3V4 GDB1/IO152PPB3V4 GDC0/IO151NDB3V 4 3 -6 v1.5 ProASIC3E Packaging 208-Pin PQFP Pin Number 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 A3PE3000 Function GDC1/IO151PDB3V4 IO134NDB3V2 IO134PDB3V2 IO132NDB3V2 IO132PDB3V2 GND VCCIB3 GCC2/IO117PSB3V0 GCB2/IO116PSB3V0 NC IO115NDB3V0 GCA2/IO115PDB3V0 GCA1/IO114PPB3V0 GND VCCPLC GCA0/IO114NPB3V0 VCOMPLC GCB0/IO113NDB2V3 GCB1/IO113PDB2V3 GCC1/IO112PSB2V3 IO110NDB2V3 IO110PDB2V3 IO106PSB2V3 VCCIB2 GND VCC IO99NDB2V2 IO99PDB2V2 IO96NDB2V1 IO96PDB2V1 IO91NDB2V1 IO91PDB2V1 IO88NDB2V0 IO88PDB2V0 GBC2/IO84PSB2V0 GBA2/IO82PSB2V0 GBB2/IO83PSB2V0 VMV2 GNDQ 208-Pin PQFP Pin Number 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 A3PE3000 Function GND VMV1 GNDQ GBA1/IO81PDB1V4 GBA0/IO81NDB1V4 GBB1/IO80PDB1V4 GND GBB0/IO80NDB1V4 GBC1/IO79PDB1V4 GBC0/IO79NDB1V4 IO74PDB1V4 IO74NDB1V4 IO70PDB1V3 IO70NDB1V3 VCCIB1 VCC IO56PSB1V1 IO55PDB1V1 IO55NDB1V1 IO54PDB1V1 IO54NDB1V1 IO40PDB0V4 GND IO40NDB0V4 IO37PDB0V4 IO37NDB0V4 IO35PDB0V4 IO35NDB0V4 IO32PDB0V3 IO32NDB0V3 VCCIB0 VCC IO28PDB0V3 IO28NDB0V3 IO24PDB0V2 IO24NDB0V2 IO21PSB0V2 IO16PDB0V1 IO16NDB0V1 208-Pin PQFP Pin Number 195 196 197 198 199 200 201 202 203 204 205 206 207 208 A3PE3000 Function GND IO11PDB0V1 IO11NDB0V1 IO08PDB0V0 IO08NDB0V0 VCCIB0 GAC1/IO02PDB0V0 GAC0/IO02NDB0V0 GAB1/IO01PDB0V0 GAB0/IO01NDB0V0 GAA1/IO00PDB0V0 GAA0/IO00NDB0V0 GNDQ VMV0 v1.5 3-7 Package Pin Assignments 256-Pin FBGA A1 Ball Pad Corner 16 15 14 13 12 11 10 9 8 7 654 321 A B C D E F G H J K L M N P R T Note: This is the bottom view of the package. Note For Package Manufacturing and Environmental information, visit the Resource Center at http://www.actel.com/products/solutions/package/docs.aspx. 3 -8 v1.5 ProASIC3E Packaging 256-Pin FBGA Pin Number A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 C1 C2 C3 C4 A3PE600 Function GND GAA0/IO00NDB0V0 GAA1/IO00PDB0V0 GAB0/IO01NDB0V0 IO05PDB0V0 IO10PDB0V1 IO12PDB0V2 IO16NDB0V2 IO23NDB1V0 IO23PDB1V0 IO28NDB1V1 IO28PDB1V1 GBB1/IO34PDB1V1 GBA0/IO35NDB1V1 GBA1/IO35PDB1V1 GND GAB2/IO133PDB7V1 GAA2/IO134PDB7V1 GNDQ GAB1/IO01PDB0V0 IO05NDB0V0 IO10NDB0V1 IO12NDB0V2 IO16PDB0V2 IO20NDB1V0 IO24NDB1V0 IO24PDB1V0 GBC1/IO33PDB1V1 GBB0/IO34NDB1V1 GNDQ GBA2/IO36PDB2V0 IO42NDB2V0 IO133NDB7V1 IO134NDB7V1 VMV7 VCCPLA 256-Pin FBGA Pin Number C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 E1 E2 E3 E4 E5 E6 E7 E8 A3PE600 Function GAC0/IO02NDB0V0 GAC1/IO02PDB0V0 IO15NDB0V2 IO15PDB0V2 IO20PDB1V0 IO25NDB1V0 IO27PDB1V0 GBC0/IO33NDB1V1 VCCPLB VMV2 IO36NDB2V0 IO42PDB2V0 IO128PDB7V1 IO129PDB7V1 GAC2/IO132PDB7V1 VCOMPLA GNDQ IO09NDB0V1 IO09PDB0V1 IO13PDB0V2 IO21PDB1V0 IO25PDB1V0 IO27NDB1V0 GNDQ VCOMPLB GBB2/IO37PDB2V0 IO39PDB2V0 IO39NDB2V0 IO128NDB7V1 IO129NDB7V1 IO132NDB7V1 IO130PDB7V1 VMV0 VvB0 VCCIB0 IO13NDB0V2 256-Pin FBGA Pin Number E9 E10 E11 E12 E13 E14 E15 E16 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 A3PE600 Function IO21NDB1V0 VCCIB1 VCCIB1 VMV1 GBC2/IO38PDB2V0 IO37NDB2V0 IO41NDB2V0 IO41PDB2V0 IO124PDB7V0 IO125PDB7V0 IO126PDB7V0 IO130NDB7V1 VCCIB7 GND VCC VCC VCC VCC GND VCCIB2 IO38NDB2V0 IO40NDB2V0 IO40PDB2V0 IO45PSB2V1 IO124NDB7V0 IO125NDB7V0 IO126NDB7V0 GFC1/IO120PPB7V0 VCCIB7 VCC GND GND GND GND VCC VCCIB2 v1.5 3-9 Package Pin Assignments 256-Pin FBGA Pin Number G13 G14 G15 G16 H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 H13 H14 H15 H16 J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 J13 J14 J15 J16 A3PE600 Function GCC1/IO50PPB2V1 IO44NDB2V1 IO44PDB2V1 IO49NSB2V1 GFB0/IO119NPB7V0 GFA0/IO118NDB6V1 GFB1/IO119PPB7V0 VCOMPLF GFC0/IO120NPB7V0 VCC GND GND GND GND VCC GCC0/IO50NPB2V1 GCB1/IO51PPB2V1 GCA0/IO52NPB3V0 VCOMPLC GCB0/IO51NPB2V1 GFA2/IO117PSB6V1 GFA1/IO118PDB6V1 VCCPLF IO116NDB6V1 GFB2/IO116PDB6V1 VCC GND GND GND GND VCC GCB2/IO54PPB3V0 GCA1/IO52PPB3V0 GCC2/IO55PPB3V0 VCCPLC GCA2/IO53PSB3V0 256-Pin FBGA Pin Number K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 K12 K13 K14 K15 K16 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 L15 L16 M1 M2 M3 M4 A3PE600 Function GFC2/IO115PSB6V1 IO113PPB6V1 IO112PDB6V1 IO112NDB6V1 VCCIB6 VCC GND GND GND GND VCC VCCIB3 IO54NPB3V0 IO57NPB3V0 IO55NPB3V0 IO57PPB3V0 IO113NPB6V1 IO109PPB6V0 IO108PDB6V0 IO108NDB6V0 VCCIB6 GND VCC VCC VCC VCC GND VCCIB3 GDB0/IO66NPB3V1 IO60NDB3V1 IO60PDB3V1 IO61PDB3V1 IO109NPB6V0 IO106NDB6V0 IO106PDB6V0 GEC0/IO104NPB6V0 256-Pin FBGA Pin Number M5 M6 M7 M8 M9 M10 M11 M12 M13 M14 M15 M16 N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 N12 N13 N14 N15 N16 P1 P2 P3 P4 P5 P6 P7 P8 A3PE600 Function VMV5 VCCIB5 VCCIB5 IO84NDB5V0 IO84PDB5V0 VCCIB4 VCCIB4 VMV3 VCCPLD GDB1/IO66PPB3V1 GDC1/IO65PDB3V1 IO61NDB3V1 IO105PDB6V0 IO105NDB6V0 GEC1/IO104PPB6V0 VCOMPLE GNDQ GEA2/IO101PPB5V2 IO92NDB5V1 IO90NDB5V1 IO82NDB5V0 IO74NDB4V1 IO74PDB4V1 GNDQ VCOMPLD VJTAG GDC0/IO65NDB3V1 GDA1/IO67PDB3V1 GEB1/IO103PDB6V0 GEB0/IO103NDB6V0 VMV6 VCCPLE IO101NPB5V2 IO95PPB5V1 IO92PDB5V1 IO90PDB5V1 3 -1 0 v1.5 ProASIC3E Packaging 256-Pin FBGA Pin Number P9 P10 P11 P12 P13 P14 P15 P16 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 A3PE600 Function IO82PDB5V0 IO76NDB4V1 IO76PDB4V1 VMV4 TCK VPUMP TRST GDA0/IO67NDB3V1 GEA1/IO102PDB6V0 GEA0/IO102NDB6V0 GNDQ GEC2/IO99PDB5V2 IO95NPB5V1 IO91NDB5V1 IO91PDB5V1 IO83NDB5V0 IO83PDB5V0 IO77NDB4V1 IO77PDB4V1 IO69NDB4V0 GDB2/IO69PDB4V0 TDI GNDQ TDO GND IO100NDB5V2 GEB2/IO100PDB5V2 IO99NDB5V2 IO88NDB5V0 IO88PDB5V0 IO89NSB5V0 IO80NSB4V1 IO81NDB4V1 IO81PDB4V1 IO70NDB4V0 GDC2/IO70PDB4V0 256-Pin FBGA Pin Number T13 T14 T15 T16 A3PE600 Function IO68NDB4V0 GDA2/IO68PDB4V0 TMS GND v1.5 3 - 11 Package Pin Assignments 324-Pin FBGA A1 Ball Pad Corner 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P R T U V Note: This is the bottom view of the package. Note For Package Manufacturing and Environmental information, visit the Resource Center at http://www.actel.com/products/solutions/package/docs.aspx. 3 -1 2 v1.5 ProASIC3E Packaging 324-Pin FBGA Pin Number A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 A3PE3000 FBGA GND IO08NDB0V0 IO08PDB0V0 IO10NDB0V1 IO10PDB0V1 IO12PDB0V1 GND IO32NDB0V3 IO32PDB0V3 IO42PPB1V0 IO52NPB1V1 GND IO66NDB1V3 IO72NDB1V3 IO72PDB1V3 IO74NDB1V4 IO74PDB1V4 GND IO305PDB7V3 GAB2/IO308PDB7V4 GAA0/IO00NPB0V0 VCCIB0 GNDQ IO12NDB0V1 IO18NDB0V2 VCCIB0 IO42NPB1V0 IO44NDB1V0 VCCIB1 IO52PPB1V1 IO66PDB1V3 GNDQ VCCIB1 GBA0/IO81NDB1V4 GBA1/IO81PDB1V4 IO88PDB2V0 324-Pin FBGA Pin Number C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 A3PE3000 FBGA IO305NDB7V3 IO308NDB7V4 GAA2/IO309PPB7V4 GAA1/IO00PPB0V0 VMV0 IO14NDB0V1 IO18PDB0V2 IO40NDB0V4 IO40PDB0V4 IO44PDB1V0 IO56NDB1V1 IO64NDB1V2 IO64PDB1V2 VMV1 GBC0/IO79NDB1V4 GBC1/IO79PDB1V4 GBB2/IO83PPB2V0 IO88NDB2V0 IO303PDB7V3 VCCIB7 GAC2/IO307PPB7V4 IO309NPB7V4 GAB1/IO01PPB0V0 IO14PDB0V1 IO24NDB0V2 IO24PDB0V2 IO28PDB0V3 IO48NDB1V0 IO56PDB1V1 IO60PPB1V2 GBB0/IO80NDB1V4 GBB1/IO80PDB1V4 GBA2/IO82PDB2V0 IO83NPB2V0 VCCIB2 IO90PDB2V1 324-Pin FBGA Pin Number E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 E15 E16 E17 E18 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 A3PE3000 FBGA IO303NDB7V3 GNDQ VMV7 IO307NPB7V4 VCCPLA GAB0/IO01NPB0V0 VCCIB0 GND IO28NDB0V3 IO48PDB1V0 GND VCCIB1 IO60NPB1V2 VCCPLB IO82NDB2V0 VMV2 GNDQ IO90NDB2V1 IO299NDB7V3 IO299PDB7V3 IO295PDB7V2 IO295NDB7V2 VCOMPLA IO291PPB7V2 GAC0/IO02NDB0V0 GAC1/IO02PDB0V0 IO26PDB0V3 IO34PDB0V4 IO58NDB1V2 IO58PDB1V2 IO94PPB2V1 VCOMPLB GBC2/IO84PDB2V0 IO84NDB2V0 IO92NDB2V1 IO92PDB2V1 v1.5 3 - 13 Package Pin Assignments 324-Pin FBGA Pin Number G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 G13 G14 G15 G16 G17 G18 H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 H13 H14 H15 H16 H17 H18 A3PE3000 FBGA GND IO287PDB7V1 IO287NDB7V1 IO283PPB7V1 VCCIB7 IO279PDB7V0 IO291NPB7V2 VCC IO26NDB0V3 IO34NDB0V4 VCC IO94NPB2V1 IO98PDB2V2 VCCIB2 GCC0/IO112NPB2V3 IO104PDB2V2 IO104NDB2V2 GND IO267PDB6V4 VCCIB7 IO283NPB7V1 GFB1/IO274PPB7V0 GND IO279NDB7V0 VCC VCC GND GND VCC VCC IO98NDB2V2 GND GCB1/IO113PDB2V3 GCC1/IO112PPB2V3 VCCIB2 IO108PDB2V3 324-Pin FBGA Pin Number J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 J13 J14 J15 J16 J17 J18 K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 K12 K13 K14 K15 K16 K17 K18 A3PE3000 FBGA IO267NDB6V4 GFA0/IO273NDB6V4 VCOMPLF GFA2/IO272PDB6V4 GFB0/IO274NPB7V0 GFC0/IO275NDB7V0 GFC1/IO275PDB7V0 GND GND GND GND GCA2/IO115PDB3V0 GCA1/IO114PDB3V0 GCA0/IO114NDB3V0 GCB0/IO113NDB2V3 VCOMPLC IO120NPB3V0 IO108NDB2V3 IO263PDB6V3 GFA1/IO273PDB6V4 VCCPLF IO272NDB6V4 GFC2/IO270PPB6V4 GFB2/IO271PDB6V4 IO271NDB6V4 GND GND GND GND IO115NDB3V0 GCB2/IO116PDB3V0 IO116NDB3V0 GCC2/IO117PDB3V0 VCCPLC IO124NPB3V1 IO120PPB3V0 324-Pin FBGA Pin Number L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 L15 L16 L17 L18 M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 M12 M13 M14 M15 M16 M17 M18 A3PE3000 FBGA IO263NDB6V3 VCCIB6 IO259PDB6V3 IO259NDB6V3 GND IO270NPB6V4 VCC VCC GND GND VCC VCC IO132PDB3V2 GND IO117NDB3V0 IO128NPB3V1 VCCIB3 IO124PPB3V1 GND IO255PDB6V2 IO255NDB6V2 IO251PPB6V2 VCCIB6 GEB0/IO235NDB6V0 GEB1/IO235PDB6V0 VCC IO192PPB4V4 IO154NPB4V0 VCC GDA0/IO153NPB3V4 IO132NDB3V2 VCCIB3 IO134NDB3V2 IO134PDB3V2 IO128PPB3V1 GND 3 -1 4 v1.5 ProASIC3E Packaging 324-Pin FBGA Pin Number N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 N12 N13 N14 N15 N16 N17 N18 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 A3PE3000 FBGA IO247NDB6V1 IO247PDB6V1 IO251NPB6V2 GEC0/IO236NDB6V0 VCOMPLE IO212NDB5V2 IO212PDB5V2 IO192NPB4V4 IO174PDB4V2 IO170PDB4V2 GDA2/IO154PPB4V0 GDB2/IO155PPB4V0 GDA1/IO153PPB3V4 VCOMPLD GDB0/IO152NDB3V4 GDB1/IO152PDB3V4 IO138NDB3V3 IO138PDB3V3 IO245PDB6V1 GNDQ VMV6 GEC1/IO236PDB6V0 VCCPLE IO214PDB5V2 VCCIB5 GND IO174NDB4V2 IO170NDB4V2 GND VCCIB4 IO155NPB4V0 VCCPLD VJTAG GDC0/IO151NDB3V4 GDC1/IO151PDB3V4 IO142PDB3V3 324-Pin FBGA Pin Number R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 A3PE3000 FBGA IO245NDB6V1 VCCIB6 GEA1/IO234PPB6V0 IO232NDB5V4 GEB2/IO232PDB5V4 IO214NDB5V2 IO202PDB5V1 IO194PDB5V0 IO186PDB4V4 IO178PDB4V3 IO168NSB4V1 IO164PDB4V1 GDC2/IO156PDB4V0 TCK VPUMP TRST VCCIB3 IO142NDB3V3 IO241PDB6V0 GEA0/IO234NPB6V0 IO233NPB5V4 IO231NPB5V4 VMV5 IO208NDB5V1 IO202NDB5V1 IO194NDB5V0 IO186NDB4V4 IO178NDB4V3 IO166NPB4V1 IO164NDB4V1 IO156NDB4V0 VMV4 TDI GNDQ TDO IO146PDB3V4 324-Pin FBGA Pin Number U1 U2 U3 U4 U5 U6 U7 U8 U9 U10 U11 U12 U13 U14 U15 U16 U17 U18 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 V16 V17 V18 A3PE3000 FBGA IO241NDB6V0 GEA2/IO233PPB5V4 GEC2/IO231PPB5V4 VCCIB5 GNDQ IO208PDB5V1 IO198PPB5V0 VCCIB5 IO182NPB4V3 IO180NPB4V3 VCCIB4 IO166PPB4V1 IO162PDB4V1 GNDQ VCCIB4 TMS VMV3 IO146NDB3V4 GND IO218NDB5V3 IO218PDB5V3 IO206NDB5V1 IO206PDB5V1 IO198NPB5V0 GND IO190NDB4V4 IO190PDB4V4 IO182PPB4V3 IO180PPB4V3 GND IO162NDB4V1 IO160NDB4V0 IO160PDB4V0 IO158NDB4V0 IO158PDB4V0 GND v1.5 3 - 15 Package Pin Assignments 484-Pin FBGA A1 Ball Pad Corner 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P R T U V W Y AA AB Note: This is the bottom view of the package. Note For Package Manufacturing and Environmental information, visit the Resource Center at http://www.actel.com/products/solutions/package/docs.aspx. 3 -1 6 v1.5 ProASIC3E Packaging 484-Pin FBGA Pin Number A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 AA1 AA2 AA3 AA4 AA5 AA6 AA7 AA8 AA9 AA10 AA11 AA12 AA13 AA14 A3PE600 Function GND GND VCCIB0 IO06NDB0V1 IO06PDB0V1 IO08NDB0V1 IO08PDB0V1 IO11PDB0V1 IO17PDB0V2 IO18NDB0V2 IO18PDB0V2 IO22PDB1V0 IO26PDB1V0 IO29NDB1V1 IO29PDB1V1 IO31NDB1V1 IO31PDB1V1 IO32NDB1V1 NC VCCIB1 GND GND GND VCCIB6 NC IO98PDB5V2 IO96NDB5V2 IO96PDB5V2 IO86NDB5V0 IO86PDB5V0 IO85PDB5V0 IO85NDB5V0 IO78PPB4V1 IO79NDB4V1 IO79PDB4V1 NC 484-Pin FBGA Pin Number AA15 AA16 AA17 AA18 AA19 AA20 AA21 AA22 AB1 AB2 AB3 AB4 AB5 AB6 AB7 AB8 AB9 AB10 AB11 AB12 AB13 AB14 AB15 AB16 AB17 AB18 AB19 AB20 AB21 AB22 B1 B2 B3 B4 B5 B6 A3PE600 Function NC IO71NDB4V0 IO71PDB4V0 NC NC NC VCCIB3 GND GND GND VCCIB5 IO97NDB5V2 IO97PDB5V2 IO93NDB5V1 IO93PDB5V1 IO87NDB5V0 IO87PDB5V0 NC NC IO75NDB4V1 IO75PDB4V1 IO72NDB4V0 IO72PDB4V0 IO73NDB4V0 IO73PDB4V0 NC NC VCCIB4 GND GND GND VCCIB7 NC IO03NDB0V0 IO03PDB0V0 IO07NDB0V1 484-Pin FBGA Pin Number B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 A3PE600 Function IO07PDB0V1 IO11NDB0V1 IO17NDB0V2 IO14PDB0V2 IO19PDB0V2 IO22NDB1V0 IO26NDB1V0 NC NC IO30NDB1V1 IO30PDB1V1 IO32PDB1V1 NC NC VCCIB2 GND VCCIB7 NC NC NC GND IO04NDB0V0 IO04PDB0V0 VCC VCC IO14NDB0V2 IO19NDB0V2 NC NC VCC VCC NC NC GND NC NC v1.5 3 - 17 Package Pin Assignments 484-Pin FBGA Pin Number C21 C22 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 A3PE600 Function NC VCCIB2 NC NC NC GND GAA0/IO00NDB0V0 GAA1/IO00PDB0V0 GAB0/IO01NDB0V0 IO05PDB0V0 IO10PDB0V1 IO12PDB0V2 IO16NDB0V2 IO23NDB1V0 IO23PDB1V0 IO28NDB1V1 IO28PDB1V1 GBB1/IO34PDB1V1 GBA0/IO35NDB1V1 GBA1/IO35PDB1V1 GND NC NC NC NC NC GND GAB2/IO133PDB7V 1 GAA2/IO134PDB7V 1 GNDQ GAB1/IO01PDB0V0 IO05NDB0V0 IO10NDB0V1 IO12NDB0V2 484-Pin FBGA Pin Number E11 E12 E13 E14 E15 E16 E17 E18 E19 E20 E21 E22 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 G1 G2 A3PE600 Function IO16PDB0V2 IO20NDB1V0 IO24NDB1V0 IO24PDB1V0 GBC1/IO33PDB1V1 GBB0/IO34NDB1V1 GNDQ GBA2/IO36PDB2V0 IO42NDB2V0 GND NC NC NC IO131NDB7V1 IO131PDB7V1 IO133NDB7V1 IO134NDB7V1 VMV7 VCCPLA GAC0/IO02NDB0V0 GAC1/IO02PDB0V0 IO15NDB0V2 IO15PDB0V2 IO20PDB1V0 IO25NDB1V0 IO27PDB1V0 GBC0/IO33NDB1V1 VCCPLB VMV2 IO36NDB2V0 IO42PDB2V0 NC NC NC IO127NDB7V1 IO127PDB7V1 G7 G8 G9 G10 G11 G12 G13 G14 G15 G16 G17 G18 G19 G20 G21 G22 H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 H13 H14 H15 484-Pin FBGA Pin Number G3 G4 G5 G6 A3PE600 Function NC IO128PDB7V1 IO129PDB7V1 GAC2/IO132PDB7V 1 VCOMPLA GNDQ IO09NDB0V1 IO09PDB0V1 IO13PDB0V2 IO21PDB1V0 IO25PDB1V0 IO27NDB1V0 GNDQ VCOMPLB GBB2/IO37PDB2V0 IO39PDB2V0 IO39NDB2V0 IO43PDB2V0 IO43NDB2V0 NC NC NC VCC IO128NDB7V1 IO129NDB7V1 IO132NDB7V1 IO130PDB7V1 VMV0 VCCIB0 VCCIB0 IO13NDB0V2 IO21NDB1V0 VCCIB1 VCCIB1 VMV1 3 -1 8 v1.5 ProASIC3E Packaging 484-Pin FBGA Pin Number H16 H17 H18 H19 H20 H21 H22 J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 J13 J14 J15 J16 J17 J18 J19 J20 J21 J22 K1 K2 K3 K4 K5 K6 K7 A3PE600 Function GBC2/IO38PDB2V0 IO37NDB2V0 IO41NDB2V0 IO41PDB2V0 VCC NC NC IO123NDB7V0 IO123PDB7V0 NC IO124PDB7V0 IO125PDB7V0 IO126PDB7V0 IO130NDB7V1 VCCIB7 GND VCC VCC VCC VCC GND VCCIB2 IO38NDB2V0 IO40NDB2V0 IO40PDB2V0 IO45PPB2V1 NC IO48PDB2V1 IO46PDB2V1 IO121NDB7V0 IO121PDB7V0 NC IO124NDB7V0 IO125NDB7V0 IO126NDB7V0 GFC1/IO120PPB7V0 L6 L7 L8 L9 L10 L11 L12 L13 L14 L15 L16 L17 L18 L19 L20 484-Pin FBGA Pin Number K8 K9 K10 K11 K12 K13 K14 K15 K16 K17 K18 K19 K20 K21 K22 L1 L2 L3 L4 L5 A3PE600 Function VCCIB7 VCC GND GND GND GND VCC VCCIB2 GCC1/IO50PPB2V1 IO44NDB2V1 IO44PDB2V1 IO49NPB2V1 IO45NPB2V1 IO48NDB2V1 IO46NDB2V1 NC IO122PDB7V0 IO122NDB7V0 GFB0/IO119NPB7V0 GFA0/IO118NDB6V 1 GFB1/IO119PPB7V0 VCOMPLF GFC0/IO120NPB7V0 VCC GND GND GND GND VCC GCC0/IO50NPB2V1 GCB1/IO51PPB2V1 GCA0/IO52NPB3V0 VCOMPLC GCB0/IO51NPB2V1 IO49PPB2V1 484-Pin FBGA Pin Number L21 L22 M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 M12 M13 M14 M15 M16 M17 M18 M19 M20 M21 M22 N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 N12 A3PE600 Function IO47NDB2V1 IO47PDB2V1 NC IO114NPB6V1 IO117NDB6V1 GFA2/IO117PDB6V1 GFA1/IO118PDB6V1 VCCPLF IO116NDB6V1 GFB2/IO116PDB6V1 VCC GND GND GND GND VCC GCB2/IO54PPB3V0 GCA1/IO52PPB3V0 GCC2/IO55PPB3V0 VCCPLC GCA2/IO53PDB3V0 IO53NDB3V0 IO56PDB3V0 NC IO114PPB6V1 IO111NDB6V1 NC GFC2/IO115PPB6V1 IO113PPB6V1 IO112PDB6V1 IO112NDB6V1 VCCIB6 VCC GND GND GND v1.5 3 - 19 Package Pin Assignments 484-Pin FBGA Pin Number N13 N14 N15 N16 N17 N18 N19 N20 N21 N22 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 R1 R2 R3 R4 A3PE600 Function GND VCC VCCIB3 IO54NPB3V0 IO57NPB3V0 IO55NPB3V0 IO57PPB3V0 NC IO56NDB3V0 IO58PDB3V0 NC IO111PDB6V1 IO115NPB6V1 IO113NPB6V1 IO109PPB6V0 IO108PDB6V0 IO108NDB6V0 VCCIB6 GND VCC VCC VCC VCC GND VCCIB3 GDB0/IO66NPB3V1 IO60NDB3V1 IO60PDB3V1 IO61PDB3V1 NC IO59PDB3V0 IO58NDB3V0 NC IO110PDB6V0 VCC IO109NPB6V0 484-Pin FBGA Pin Number R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 A3PE600 Function IO106NDB6V0 IO106PDB6V0 GEC0/IO104NPB6V0 VMV5 VCCIB5 VCCIB5 IO84NDB5V0 IO84PDB5V0 VCCIB4 VCCIB4 VMV3 VCCPLD GDB1/IO66PPB3V1 GDC1/IO65PDB3V1 IO61NDB3V1 VCC IO59NDB3V0 IO62PDB3V1 NC IO110NDB6V0 NC IO105PDB6V0 IO105NDB6V0 GEC1/IO104PPB6V0 VCOMPLE GNDQ GEA2/IO101PPB5V2 IO92NDB5V1 IO90NDB5V1 IO82NDB5V0 IO74NDB4V1 IO74PDB4V1 GNDQ VCOMPLD VJTAG GDC0/IO65NDB3V1 U6 U7 U8 U9 U10 U11 U12 U13 U14 U15 U16 U17 U18 U19 U20 U21 U22 V1 V2 V3 V4 V5 V6 V7 V8 484-Pin FBGA Pin Number T19 T20 T21 T22 U1 U2 U3 U4 U5 A3PE600 Function GDA1/IO67PDB3V1 NC IO64PDB3V1 IO62NDB3V1 NC IO107PDB6V0 IO107NDB6V0 GEB1/IO103PDB6V0 GEB0/IO103NDB6V 0 VMV6 VCCPLE IO101NPB5V2 IO95PPB5V1 IO92PDB5V1 IO90PDB5V1 IO82PDB5V0 IO76NDB4V1 IO76PDB4V1 VMV4 TCK VPUMP TRST GDA0/IO67NDB3V1 NC IO64NDB3V1 IO63PDB3V1 NC NC GND GEA1/IO102PDB6V0 GEA0/IO102NDB6V 0 GNDQ GEC2/IO99PDB5V2 IO95NPB5V1 3 -2 0 v1.5 ProASIC3E Packaging 484-Pin FBGA Pin Number V9 V10 V11 V12 V13 V14 V15 V16 V17 V18 V19 V20 V21 V22 W1 W2 W3 W4 W5 W6 W7 W8 W9 W10 W11 W12 W13 W14 W15 W16 W17 W18 W19 W20 W21 W22 A3PE600 Function IO91NDB5V1 IO91PDB5V1 IO83NDB5V0 IO83PDB5V0 IO77NDB4V1 IO77PDB4V1 IO69NDB4V0 GDB2/IO69PDB4V0 TDI GNDQ TDO GND NC IO63NDB3V1 NC NC NC GND IO100NDB5V2 GEB2/IO100PDB5V2 IO99NDB5V2 IO88NDB5V0 IO88PDB5V0 IO89NDB5V0 IO80NDB4V1 IO81NDB4V1 IO81PDB4V1 IO70NDB4V0 GDC2/IO70PDB4V0 IO68NDB4V0 GDA2/IO68PDB4V0 TMS GND NC NC NC 484-Pin FBGA Pin Number Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 Y11 Y12 Y13 Y14 Y15 Y16 Y17 Y18 Y19 Y20 Y21 Y22 A3PE600 Function VCCIB6 NC NC IO98NDB5V2 GND IO94NDB5V1 IO94PDB5V1 VCC VCC IO89PDB5V0 IO80PDB4V1 IO78NPB4V1 NC VCC VCC NC NC GND NC NC NC VCCIB3 v1.5 3 - 21 Package Pin Assignments 484-Pin FBGA Pin Number A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 AA1 AA2 AA3 AA4 AA5 AA6 AA7 AA8 AA9 AA10 AA11 AA12 AA13 AA14 A3PE1500 Function GND GND VCCIB0 IO05NDB0V0 IO05PDB0V0 IO11NDB0V1 IO11PDB0V1 IO15PDB0V1 IO17PDB0V2 IO27NDB0V3 IO27PDB0V3 IO32PDB1V0 IO43PDB1V1 IO47NDB1V1 IO47PDB1V1 IO51NDB1V2 IO51PDB1V2 IO54NDB1V3 NC VCCIB1 GND GND GND VCCIB6 NC IO161PDB5V3 IO155NDB5V2 IO155PDB5V2 IO154NDB5V2 IO154PDB5V2 IO143PDB5V1 IO143NDB5V1 IO131PPB4V2 IO129NDB4V2 IO129PDB4V2 NC 484-Pin FBGA Pin Number AA15 AA16 AA17 AA18 AA19 AA20 AA21 AA22 AB1 AB2 AB3 AB4 AB5 AB6 AB7 AB8 AB9 AB10 AB11 AB12 AB13 AB14 AB15 AB16 AB17 AB18 AB19 AB20 AB21 AB22 B1 B2 B3 B4 B5 B6 A3PE1500 Function NC IO117NDB4V0 IO117PDB4V0 IO115NDB4V0 IO115PDB4V0 NC VCCIB3 GND GND GND VCCIB5 IO159NDB5V3 IO159PDB5V3 IO149NDB5V1 IO149PDB5V1 IO138NDB5V0 IO138PDB5V0 NC NC IO127NDB4V2 IO127PDB4V2 IO125NDB4V1 IO125PDB4V1 IO122NDB4V1 IO122PDB4V1 NC NC VCCIB4 GND GND GND VCCIB7 NC IO03NDB0V0 IO03PDB0V0 IO10NDB0V1 484-Pin FBGA Pin Number B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 A3PE1500 Function IO10PDB0V1 IO15NDB0V1 IO17NDB0V2 IO20PDB0V2 IO29PDB0V3 IO32NDB1V0 IO43NDB1V1 NC NC IO53NDB1V2 IO53PDB1V2 IO54PDB1V3 NC NC VCCIB2 GND VCCIB7 NC NC NC GND IO07NDB0V0 IO07PDB0V0 VCC VCC IO20NDB0V2 IO29NDB0V3 NC NC VCC VCC NC NC GND NC NC 3 -2 2 v1.5 ProASIC3E Packaging 484-Pin FBGA Pin Number C21 C22 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 A3PE1500 Function NC VCCIB2 NC NC NC GND GAA0/IO00NDB0V0 GAA1/IO00PDB0V0 GAB0/IO01NDB0V0 IO09PDB0V1 IO13PDB0V1 IO21PDB0V2 IO31NDB0V3 IO37NDB1V0 IO37PDB1V0 IO49NDB1V2 IO49PDB1V2 GBB1/IO56PDB1V3 GBA0/IO57NDB1V3 GBA1/IO57PDB1V3 GND NC IO69PDB2V1 NC NC IO218PPB7V3 GND GAB2/IO220PDB7V3 GAA2/IO221PDB7V3 GNDQ GAB1/IO01PDB0V0 IO09NDB0V1 IO13NDB0V1 IO21NDB0V2 IO31PDB0V3 IO35NDB1V0 484-Pin FBGA Pin Number E13 E14 E15 E16 E17 E18 E19 E20 E21 E22 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 G1 G2 G3 G4 A3PE1500 Function IO41NDB1V1 IO41PDB1V1 GBC1/IO55PDB1V3 GBB0/IO56NDB1V3 GNDQ GBA2/IO58PDB2V0 IO63NDB2V0 GND IO69NDB2V1 NC IO218NPB7V3 IO216NDB7V3 IO216PDB7V3 IO220NDB7V3 IO221NDB7V3 VMV7 VCCPLA GAC0/IO02NDB0V0 GAC1/IO02PDB0V0 IO23NDB0V2 IO23PDB0V2 IO35PDB1V0 IO39NDB1V0 IO45PDB1V1 GBC0/IO55NDB1V3 VCCPLB VMV2 IO58NDB2V0 IO63PDB2V0 NC NC NC IO211NDB7V2 IO211PDB7V2 NC IO214PDB7V3 484-Pin FBGA Pin Number G5 G6 G7 G8 G9 G10 G11 G12 G13 G14 G15 G16 G17 G18 G19 G20 G21 G22 H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 H13 H14 H15 H16 H17 H18 A3PE1500 Function IO217PDB7V3 GAC2/IO219PDB7V3 VCOMPLA GNDQ IO19NDB0V2 IO19PDB0V2 IO25PDB0V3 IO33PDB1V0 IO39PDB1V0 IO45NDB1V1 GNDQ VCOMPLB GBB2/IO59PDB2V0 IO62PDB2V0 IO62NDB2V0 IO71PDB2V2 IO71NDB2V2 NC IO209PSB7V2 NC VCC IO214NDB7V3 IO217NDB7V3 IO219NDB7V3 IO215PDB7V3 VMV0 VCCIB0 VCCIB0 IO25NDB0V3 IO33NDB1V0 VCCIB1 VCCIB1 VMV1 GBC2/IO60PDB2V0 IO59NDB2V0 IO67NDB2V1 v1.5 3 - 23 Package Pin Assignments 484-Pin FBGA Pin Number H19 H20 H21 H22 J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 J13 J14 J15 J16 J17 J18 J19 J20 J21 J22 K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 A3PE1500 Function IO67PDB2V1 VCC VMV2 IO74PSB2V2 IO212NDB7V2 IO212PDB7V2 VMV7 IO206PDB7V1 IO204PDB7V1 IO210PDB7V2 IO215NDB7V3 VCCIB7 GND VCC VCC VCC VCC GND VCCIB2 IO60NDB2V0 IO65NDB2V1 IO65PDB2V1 IO75PPB2V2 GNDQ IO77PDB2V2 IO79PDB2V3 IO200NDB7V1 IO200PDB7V1 GNDQ IO206NDB7V1 IO204NDB7V1 IO210NDB7V2 GFC1/IO192PPB7V0 VCCIB7 VCC GND 484-Pin FBGA Pin Number K11 K12 K13 K14 K15 K16 K17 K18 K19 K20 K21 K22 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 L15 L16 L17 L18 L19 L20 L21 L22 M1 M2 A3PE1500 Function GND GND GND VCC VCCIB2 GCC1/IO85PPB2V3 IO73NDB2V2 IO73PDB2V2 IO81NPB2V3 IO75NPB2V2 IO77NDB2V2 IO79NDB2V3 NC IO196PDB7V0 IO196NDB7V0 GFB0/IO191NPB7V0 GFA0/IO190NDB6V2 GFB1/IO191PPB7V0 VCOMPLF GFC0/IO192NPB7V0 VCC GND GND GND GND VCC GCC0/IO85NPB2V3 GCB1/IO86PPB2V3 GCA0/IO87NPB3V0 VCOMPLC GCB0/IO86NPB2V3 IO81PPB2V3 IO83NDB2V3 IO83PDB2V3 GNDQ IO185NPB6V2 484-Pin FBGA Pin Number M3 M4 M5 M6 M7 M8 M9 M10 M11 M12 M13 M14 M15 M16 M17 M18 M19 M20 M21 M22 N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 N12 N13 N14 N15 N16 A3PE1500 Function IO189NDB6V2 GFA2/IO189PDB6V2 GFA1/IO190PDB6V2 VCCPLF IO188NDB6V2 GFB2/IO188PDB6V2 VCC GND GND GND GND VCC GCB2/IO89PPB3V0 GCA1/IO87PPB3V0 GCC2/IO90PPB3V0 VCCPLC GCA2/IO88PDB3V0 IO88NDB3V0 IO93PDB3V0 NC IO185PPB6V2 IO183NDB6V2 VMV6 GFC2/IO187PPB6V2 IO184PPB6V2 IO186PDB6V2 IO186NDB6V2 VCCIB6 VCC GND GND GND GND VCC VCCIB3 IO89NPB3V0 3 -2 4 v1.5 ProASIC3E Packaging 484-Pin FBGA Pin Number N17 N18 N19 N20 N21 N22 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 R1 R2 R3 R4 R5 R6 R7 R8 A3PE1500 Function IO91NPB3V0 IO90NPB3V0 IO91PPB3V0 GNDQ IO93NDB3V0 IO95PDB3V1 NC IO183PDB6V2 IO187NPB6V2 IO184NPB6V2 IO176PPB6V1 IO182PDB6V1 IO182NDB6V1 VCCIB6 GND VCC VCC VCC VCC GND VCCIB3 GDB0/IO109NPB3V2 IO97NDB3V1 IO97PDB3V1 IO99PDB3V1 VMV3 IO98PDB3V1 IO95NDB3V1 NC IO177PDB6V1 VCC IO176NPB6V1 IO174NDB6V0 IO174PDB6V0 GEC0/IO169NPB6V0 VMV5 484-Pin FBGA Pin Number R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 A3PE1500 Function VCCIB5 VCCIB5 IO135NDB5V0 IO135PDB5V0 VCCIB4 VCCIB4 VMV3 VCCPLD GDB1/IO109PPB3V2 GDC1/IO108PDB3V2 IO99NDB3V1 VCC IO98NDB3V1 IO101PDB3V1 NC IO177NDB6V1 NC IO171PDB6V0 IO171NDB6V0 GEC1/IO169PPB6V0 VCOMPLE GNDQ GEA2/IO166PPB5V3 IO145NDB5V1 IO141NDB5V0 IO139NDB5V0 IO119NDB4V1 IO119PDB4V1 GNDQ VCOMPLD VJTAG GDC0/IO108NDB3V2 GDA1/IO110PDB3V2 NC IO103PDB3V2 IO101NDB3V1 U20 U21 U22 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 484-Pin FBGA Pin Number U1 U2 U3 U4 U5 U6 U7 U8 U9 U10 U11 U12 U13 U14 U15 U16 U17 U18 U19 A3PE1500 Function IO175PPB6V1 IO173PDB6V0 IO173NDB6V0 GEB1/IO168PDB6V0 GEB0/IO168NDB6V0 VMV6 VCCPLE IO166NPB5V3 IO157PPB5V2 IO145PDB5V1 IO141PDB5V0 IO139PDB5V0 IO121NDB4V1 IO121PDB4V1 VMV4 TCK VPUMP TRST GDA0/IO110NDB3V 2 NC IO103NDB3V2 IO105PDB3V2 NC IO175NPB6V1 GND GEA1/IO167PDB6V0 GEA0/IO167NDB6V0 GNDQ GEC2/IO164PDB5V3 IO157NPB5V2 IO151NDB5V2 IO151PDB5V2 IO137NDB5V0 IO137PDB5V0 IO123NDB4V1 v1.5 3 - 25 Package Pin Assignments 484-Pin FBGA Pin Number V14 V15 V16 V17 V18 V19 V20 V21 V22 W1 W2 W3 W4 W5 W6 W7 W8 W9 W10 W11 W12 W13 W14 W15 W16 W17 W18 W19 W20 W21 W22 Y1 Y2 Y3 Y4 Y5 A3PE1500 Function IO123PDB4V1 IO112NDB4V0 GDB2/IO112PDB4V0 TDI GNDQ TDO GND NC IO105NDB3V2 NC NC NC GND IO165NDB5V3 GEB2/IO165PDB5V3 IO164NDB5V3 IO153NDB5V2 IO153PDB5V2 IO147NDB5V1 IO133NDB4V2 IO130NDB4V2 IO130PDB4V2 IO113NDB4V0 GDC2/IO113PDB4V0 IO111NDB4V0 GDA2/IO111PDB4V0 TMS GND NC NC NC VCCIB6 NC NC IO161NDB5V3 GND 484-Pin FBGA Pin Number Y6 Y7 Y8 Y9 Y10 Y11 Y12 Y13 Y14 Y15 Y16 Y17 Y18 Y19 Y20 Y21 Y22 A3PE1500 Function IO163NDB5V3 IO163PDB5V3 VCC VCC IO147PDB5V1 IO133PDB4V2 IO131NPB4V2 NC VCC VCC NC NC GND NC NC NC VCCIB3 3 -2 6 v1.5 ProASIC3E Packaging 484-Pin FBGA Pin Number A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 AA1 AA2 AA3 AA4 AA5 AA6 AA7 AA8 AA9 AA10 AA11 AA12 AA13 AA14 A3PE3000 Function GND GND VCCIB0 IO10NDB0V1 IO10PDB0V1 IO16NDB0V1 IO16PDB0V1 IO18PDB0V2 IO24PDB0V2 IO28NDB0V3 IO28PDB0V3 IO46PDB1V0 IO54PDB1V1 IO56NDB1V1 IO56PDB1V1 IO64NDB1V2 IO64PDB1V2 IO72NDB1V3 IO74NDB1V4 VCCIB1 GND GND GND VCCIB6 IO228PDB5V4 IO224PDB5V3 IO218NDB5V3 IO218PDB5V3 IO212NDB5V2 IO212PDB5V2 IO198PDB5V0 IO198NDB5V0 IO188PPB4V4 IO180NDB4V3 IO180PDB4V3 IO170NDB4V2 484-Pin FBGA Pin Number AA15 AA16 AA17 AA18 AA19 AA20 AA21 AA22 AB1 AB2 AB3 AB4 AB5 AB6 AB7 AB8 AB9 AB10 AB11 AB12 AB13 AB14 AB15 AB16 AB17 AB18 AB19 AB20 AB21 AB22 B1 B2 B3 B4 B5 B6 A3PE3000 Function IO170PDB4V2 IO166NDB4V1 IO166PDB4V1 IO160NDB4V0 IO160PDB4V0 IO158NPB4V0 VCCIB3 GND GND GND VCCIB5 IO216NDB5V2 IO216PDB5V2 IO210NDB5V2 IO210PDB5V2 IO208NDB5V1 IO208PDB5V1 IO197NDB5V0 IO197PDB5V0 IO174NDB4V2 IO174PDB4V2 IO172NDB4V2 IO172PDB4V2 IO168NDB4V1 IO168PDB4V1 IO162NDB4V1 IO162PDB4V1 VCCIB4 GND GND GND VCCIB7 IO06PPB0V0 IO08NDB0V0 IO08PDB0V0 IO14NDB0V1 484-Pin FBGA Pin Number B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 A3PE3000 Function IO14PDB0V1 IO18NDB0V2 IO24NDB0V2 IO34PDB0V4 IO40PDB0V4 IO46NDB1V0 IO54NDB1V1 IO62NDB1V2 IO62PDB1V2 IO68NDB1V3 IO68PDB1V3 IO72PDB1V3 IO74PDB1V4 IO76NPB1V4 VCCIB2 GND VCCIB7 IO303PDB7V3 IO305PDB7V3 IO06NPB0V0 GND IO12NDB0V1 IO12PDB0V1 VCC VCC IO34NDB0V4 IO40NDB0V4 IO48NDB1V0 IO48PDB1V0 VCC VCC IO70NDB1V3 IO70PDB1V3 GND IO76PPB1V4 IO88NDB2V0 v1.5 3 - 27 Package Pin Assignments 484-Pin FBGA Pin Number C21 C22 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 A3PE3000 Function IO94PPB2V1 VCCIB2 IO293PDB7V2 IO303NDB7V3 IO305NDB7V3 GND GAA0/IO00NDB0V0 GAA1/IO00PDB0V0 GAB0/IO01NDB0V0 IO20PDB0V2 IO22PDB0V2 IO30PDB0V3 IO38NDB0V4 IO52NDB1V1 IO52PDB1V1 IO66NDB1V3 IO66PDB1V3 GBB1/IO80PDB1V4 GBA0/IO81NDB1V4 GBA1/IO81PDB1V4 GND IO88PDB2V0 IO90PDB2V1 IO94NPB2V1 IO293NDB7V2 IO299PPB7V3 GND GAB2/IO308PDB7V4 GAA2/IO309PDB7V4 GNDQ GAB1/IO01PDB0V0 IO20NDB0V2 IO22NDB0V2 IO30NDB0V3 IO38PDB0V4 IO44NDB1V0 484-Pin FBGA Pin Number E13 E14 E15 E16 E17 E18 E19 E20 E21 E22 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 G1 G2 G3 G4 A3PE3000 Function IO58NDB1V2 IO58PDB1V2 GBC1/IO79PDB1V4 GBB0/IO80NDB1V4 GNDQ GBA2/IO82PDB2V0 IO86NDB2V0 GND IO90NDB2V1 IO98PDB2V2 IO299NPB7V3 IO301NDB7V3 IO301PDB7V3 IO308NDB7V4 IO309NDB7V4 VMV7 VCCPLA GAC0/IO02NDB0V0 GAC1/IO02PDB0V0 IO32NDB0V3 IO32PDB0V3 IO44PDB1V0 IO50NDB1V1 IO60PDB1V2 GBC0/IO79NDB1V4 VCCPLB VMV2 IO82NDB2V0 IO86PDB2V0 IO96PDB2V1 IO96NDB2V1 IO98NDB2V2 IO289NDB7V1 IO289PDB7V1 IO291PPB7V2 IO295PDB7V2 484-Pin FBGA Pin Number G5 G6 G7 G8 G9 G10 G11 G12 G13 G14 G15 G16 G17 G18 G19 G20 G21 G22 H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 H13 H14 H15 H16 H17 H18 A3PE3000 Function IO297PDB7V2 GAC2/IO307PDB7V4 VCOMPLA GNDQ IO26NDB0V3 IO26PDB0V3 IO36PDB0V4 IO42PDB1V0 IO50PDB1V1 IO60NDB1V2 GNDQ VCOMPLB GBB2/IO83PDB2V0 IO92PDB2V1 IO92NDB2V1 IO102PDB2V2 IO102NDB2V2 IO105NDB2V2 IO286PSB7V1 IO291NPB7V2 VCC IO295NDB7V2 IO297NDB7V2 IO307NDB7V4 IO287PDB7V1 VMV0 VCCIB0 VCCIB0 IO36NDB0V4 IO42NDB1V0 VCCIB1 VCCIB1 VMV1 GBC2/IO84PDB2V0 IO83NDB2V0 IO100NDB2V2 3 -2 8 v1.5 ProASIC3E Packaging 484-Pin FBGA Pin Number H19 H20 H21 H22 J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 J13 J14 J15 J16 J17 J18 J19 J20 J21 J22 K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 A3PE3000 Function IO100PDB2V2 VCC VMV2 IO105PDB2V2 IO285NDB7V1 IO285PDB7V1 VMV7 IO279PDB7V0 IO283PDB7V1 IO281PDB7V0 IO287NDB7V1 VCCIB7 GND VCC VCC VCC VCC GND VCCIB2 IO84NDB2V0 IO104NDB2V2 IO104PDB2V2 IO106PPB2V3 GNDQ IO109PDB2V3 IO107PDB2V3 IO277NDB7V0 IO277PDB7V0 GNDQ IO279NDB7V0 IO283NDB7V1 IO281NDB7V0 GFC1/IO275PPB7V0 VCCIB7 VCC GND 484-Pin FBGA Pin Number K11 K12 K13 K14 K15 K16 K17 K18 K19 K20 K21 K22 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 L15 L16 L17 L18 L19 L20 L21 L22 M1 M2 A3PE3000 Function GND GND GND VCC VCCIB2 GCC1/IO112PPB2V3 IO108NDB2V3 IO108PDB2V3 IO110NPB2V3 IO106NPB2V3 IO109NDB2V3 IO107NDB2V3 IO257PSB6V2 IO276PDB7V0 IO276NDB7V0 GFB0/IO274NPB7V0 GFA0/IO273NDB6V4 GFB1/IO274PPB7V0 VCOMPLF GFC0/IO275NPB7V0 VCC GND GND GND GND VCC GCC0/IO112NPB2V3 GCB1/IO113PPB2V3 GCA0/IO114NPB3V0 VCOMPLC GCB0/IO113NPB2V3 IO110PPB2V3 IO111NDB2V3 IO111PDB2V3 GNDQ IO255NPB6V2 484-Pin FBGA Pin Number M3 M4 M5 M6 M7 M8 M9 M10 M11 M12 M13 M14 M15 M16 M17 M18 M19 M20 M21 M22 N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 N12 N13 N14 N15 N16 A3PE3000 Function IO272NDB6V4 GFA2/IO272PDB6V4 GFA1/IO273PDB6V4 VCCPLF IO271NDB6V4 GFB2/IO271PDB6V4 VCC GND GND GND GND VCC GCB2/IO116PPB3V0 GCA1/IO114PPB3V0 GCC2/IO117PPB3V0 VCCPLC GCA2/IO115PDB3V0 IO115NDB3V0 IO126PDB3V1 IO124PSB3V1 IO255PPB6V2 IO253NDB6V2 VMV6 GFC2/IO270PPB6V4 IO261PPB6V3 IO263PDB6V3 IO263NDB6V3 VCCIB6 VCC GND GND GND GND VCC VCCIB3 IO116NPB3V0 v1.5 3 - 29 Package Pin Assignments 484-Pin FBGA Pin Number N17 N18 N19 N20 N21 N22 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 R1 R2 R3 R4 R5 R6 R7 R8 A3PE3000 Function IO132NPB3V2 IO117NPB3V0 IO132PPB3V2 GNDQ IO126NDB3V1 IO128PDB3V1 IO247PDB6V1 IO253PDB6V2 IO270NPB6V4 IO261NPB6V3 IO249PPB6V1 IO259PDB6V3 IO259NDB6V3 VCCIB6 GND VCC VCC VCC VCC GND VCCIB3 GDB0/IO152NPB3V4 IO136NDB3V2 IO136PDB3V2 IO138PDB3V3 VMV3 IO130PDB3V2 IO128NDB3V1 IO247NDB6V1 IO245PDB6V1 VCC IO249NPB6V1 IO251NDB6V2 IO251PDB6V2 GEC0/IO236NPB6V0 VMV5 484-Pin FBGA Pin Number R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 A3PE3000 Function VCCIB5 VCCIB5 IO196NDB5V0 IO196PDB5V0 VCCIB4 VCCIB4 VMV3 VCCPLD GDB1/IO152PPB3V4 GDC1/IO151PDB3V4 IO138NDB3V3 VCC IO130NDB3V2 IO134PDB3V2 IO243PPB6V1 IO245NDB6V1 IO243NPB6V1 IO241PDB6V0 IO241NDB6V0 GEC1/IO236PPB6V0 VCOMPLE GNDQ GEA2/IO233PPB5V4 IO206NDB5V1 IO202NDB5V1 IO194NDB5V0 IO186NDB4V4 IO186PDB4V4 GNDQ VCOMPLD VJTAG GDC0/IO151NDB3V4 GDA1/IO153PDB3V4 IO144PDB3V3 IO140PDB3V3 IO134NDB3V2 484-Pin FBGA Pin Number U1 U2 U3 U4 U5 U6 U7 U8 U9 U10 U11 U12 U13 U14 U15 U16 U17 U18 U19 U20 U21 U22 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 A3PE3000 Function IO240PPB6V0 IO238PDB6V0 IO238NDB6V0 GEB1/IO235PDB6V0 GEB0/IO235NDB6V0 VMV6 VCCPLE IO233NPB5V4 IO222PPB5V3 IO206PDB5V1 IO202PDB5V1 IO194PDB5V0 IO176NDB4V2 IO176PDB4V2 VMV4 TCK VPUMP TRST GDA0/IO153NDB3V4 IO144NDB3V3 IO140NDB3V3 IO142PDB3V3 IO239PDB6V0 IO240NPB6V0 GND GEA1/IO234PDB6V0 GEA0/IO234NDB6V0 GNDQ GEC2/IO231PDB5V4 IO222NPB5V3 IO204NDB5V1 IO204PDB5V1 IO195NDB5V0 IO195PDB5V0 IO178NDB4V3 IO178PDB4V3 3 -3 0 v1.5 ProASIC3E Packaging 484-Pin FBGA Pin Number V15 V16 V17 V18 V19 V20 V21 V22 W1 W2 W3 W4 W5 W6 W7 W8 W9 W10 W11 W12 W13 W14 W15 W16 W17 W18 W19 W20 W21 W22 Y1 Y2 Y3 Y4 Y5 Y6 A3PE3000 Function IO155NDB4V0 GDB2/IO155PDB4V0 TDI GNDQ TDO GND IO146PDB3V4 IO142NDB3V3 IO239NDB6V0 IO237PDB6V0 IO230PSB5V4 GND IO232NDB5V4 GEB2/IO232PDB5V4 IO231NDB5V4 IO214NDB5V2 IO214PDB5V2 IO200NDB5V0 IO192NDB4V4 IO184NDB4V3 IO184PDB4V3 IO156NDB4V0 GDC2/IO156PDB4V0 IO154NDB4V0 GDA2/IO154PDB4V0 TMS GND IO150NDB3V4 IO146NDB3V4 IO148PPB3V4 VCCIB6 IO237NDB6V0 IO228NDB5V4 IO224NDB5V3 GND IO220NDB5V3 484-Pin FBGA Pin Number Y7 Y8 Y9 Y10 Y11 Y12 Y13 Y14 Y15 Y16 Y17 Y18 Y19 Y20 Y21 Y22 A3PE3000 Function IO220PDB5V3 VCC VCC IO200PDB5V0 IO192PDB4V4 IO188NPB4V4 IO187PSB4V4 VCC VCC IO164NDB4V1 IO164PDB4V1 GND IO158PPB4V0 IO150PDB3V4 IO148NPB3V4 VCCIB3 v1.5 3 - 31 Package Pin Assignments 676-Pin FBGA A1 Ball Pad Corner 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 54 3 21 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF Note: This is the bottom view of the package. Note For Package Manufacturing and Environmental information, visit the Resource Center at http://www.actel.com/products/solutions/package/docs.aspx. 3 -3 2 v1.5 ProASIC3E Packaging 676-Pin FBGA Pin Number A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 AA1 AA2 AA3 AA4 AA5 AA6 AA7 AA8 AA9 AA10 A3PE1500 Function GND GND GAA0/IO00NDB0V0 GAA1/IO00PDB0V0 IO06NDB0V0 IO09NDB0V1 IO09PDB0V1 IO14NDB0V1 IO14PDB0V1 IO22NDB0V2 IO22PDB0V2 IO26NDB0V3 IO26PDB0V3 IO30NDB0V3 IO30PDB0V3 IO34NDB1V0 IO34PDB1V0 IO38NDB1V0 IO38PDB1V0 IO41PDB1V1 IO44PDB1V1 IO49PDB1V2 IO50PDB1V2 GBC1/IO55PDB1V3 GND GND IO174PDB6V0 IO171PDB6V0 GEA1/IO167PPB6V0 GEC0/IO169NPB6V0 VCOMPLE GND IO165NDB5V3 GEB2/IO165PDB5V3 IO163PDB5V3 IO159NDB5V3 676-Pin FBGA Pin Number AA11 AA12 AA13 AA14 AA15 AA16 AA17 AA18 AA19 AA20 AA21 AA22 AA23 AA24 AA25 AA26 AB1 AB2 AB3 AB4 AB5 AB6 AB7 AB8 AB9 AB10 AB11 AB12 AB13 AB14 AB15 AB16 AB17 AB18 AB19 AB20 A3PE1500 Function IO153NDB5V2 IO147NDB5V1 IO139NDB5V0 IO137NDB5V0 IO123NDB4V1 IO123PDB4V1 IO117NDB4V0 IO117PDB4V0 GDB2/IO112PDB4V0 GNDQ TDO GND GND IO102NDB3V1 IO102PDB3V1 IO98NDB3V1 IO174NDB6V0 IO171NDB6V0 GEB1/IO168PPB6V0 GEA0/IO167NPB6V0 VCCPLE GND GND IO156NDB5V2 IO156PDB5V2 IO150PDB5V1 IO155PDB5V2 IO142PDB5V0 IO135NDB5V0 IO135PDB5V0 IO132PDB4V2 IO129PDB4V2 IO121PDB4V1 IO119NDB4V1 IO112NDB4V0 VMV4 676-Pin FBGA Pin Number AB21 AB22 AB23 AB24 AB25 AB26 AC1 AC2 AC3 AC4 AC5 AC6 AC7 AC8 AC9 AC10 AC11 AC12 AC13 AC14 AC15 AC16 AC17 AC18 AC19 AC20 AC21 AC22 AC23 AC24 AC25 AC26 AD1 AD2 AD3 AD4 A3PE1500 Function TCK TRST GDC0/IO108NDB3V2 GDC1/IO108PDB3V2 IO104NDB3V2 IO104PDB3V2 IO170PDB6V0 GEB0/IO168NPB6V0 IO166NPB5V3 GNDQ GND IO160PDB5V3 IO161PDB5V3 IO154PDB5V2 GND IO150NDB5V1 IO155NDB5V2 IO142NDB5V0 IO138NDB5V0 IO138PDB5V0 IO132NDB4V2 IO129NDB4V2 IO121NDB4V1 IO119PDB4V1 IO118NDB4V0 IO118PDB4V0 IO114PPB4V0 TMS VJTAG VMV3 IO106NDB3V2 IO106PDB3V2 IO170NDB6V0 GEA2/IO166PPB5V3 VMV5 GEC2/IO164PDB5V3 v1.5 3 - 33 Package Pin Assignments 676-Pin FBGA Pin Number AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AE1 AE2 AE3 AE4 AE5 AE6 AE7 AE8 AE9 AE10 AE11 AE12 AE13 AE14 A3PE1500 Function IO162PDB5V3 IO160NDB5V3 IO161NDB5V3 IO154NDB5V2 IO148PDB5V1 IO151PDB5V2 IO144PDB5V1 IO140PDB5V0 IO143PDB5V1 IO141PDB5V0 IO134PDB4V2 IO133PDB4V2 IO127PDB4V2 IO130PDB4V2 IO126PDB4V1 IO124PDB4V1 IO120PDB4V1 IO114NPB4V0 TDI GNDQ GDA0/IO110NDB3V2 GDA1/IO110PDB3V2 GND GND GND IO164NDB5V3 IO162NDB5V3 IO158PPB5V2 IO157PPB5V2 IO152PPB5V2 IO148NDB5V1 IO151NDB5V2 IO144NDB5V1 IO140NDB5V0 IO143NDB5V1 IO141NDB5V0 676-Pin FBGA Pin Number AE15 AE16 AE17 AE18 AE19 AE20 AE21 AE22 AE23 AE24 AE25 AE26 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 AF16 AF17 AF18 AF19 AF20 AF21 AF22 AF23 AF24 A3PE1500 Function IO134NDB4V2 IO133NDB4V2 IO127NDB4V2 IO130NDB4V2 IO126NDB4V1 IO124NDB4V1 IO120NDB4V1 IO116PDB4V0 GDC2/IO113PDB4V0 GDA2/IO111PDB4V0 GND GND GND GND GND GND IO158NPB5V2 IO157NPB5V2 IO152NPB5V2 IO146NDB5V1 IO146PDB5V1 IO149NDB5V1 IO149PDB5V1 IO145NDB5V1 IO145PDB5V1 IO136NDB5V0 IO136PDB5V0 IO131NDB4V2 IO131PDB4V2 IO128NDB4V2 IO128PDB4V2 IO122NDB4V1 IO122PDB4V1 IO116NDB4V0 IO113NDB4V0 IO111NDB4V0 676-Pin FBGA Pin Number AF25 AF26 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 C1 C2 C3 C4 C5 C6 C7 C8 A3PE1500 Function GND GND GND GND GND GND IO06PDB0V0 IO04NDB0V0 IO07NDB0V0 IO11NDB0V1 IO10NDB0V1 IO16NDB0V2 IO20NDB0V2 IO24NDB0V3 IO23NDB0V2 IO28NDB0V3 IO31NDB0V3 IO32PDB1V0 IO36PDB1V0 IO37PDB1V0 IO42NPB1V1 IO41NDB1V1 IO44NDB1V1 IO49NDB1V2 IO50NDB1V2 GBC0/IO55NDB1V3 GND GND GND GND GND GND GAA2/IO221PDB7V3 IO04PDB0V0 IO07PDB0V0 IO11PDB0V1 3 -3 4 v1.5 ProASIC3E Packaging 676-Pin FBGA Pin Number C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 A3PE1500 Function IO10PDB0V1 IO16PDB0V2 IO20PDB0V2 IO24PDB0V3 IO23PDB0V2 IO28PDB0V3 IO31PDB0V3 IO32NDB1V0 IO36NDB1V0 IO37NDB1V0 IO45NDB1V1 IO42PPB1V1 IO46NPB1V1 IO48NPB1V2 GBB0/IO56NPB1V3 VMV1 GBC2/IO60PDB2V0 IO60NDB2V0 IO218NDB7V3 IO218PDB7V3 GND VMV7 IO221NDB7V3 GAC0/IO02NDB0V0 GAC1/IO02PDB0V0 IO05NDB0V0 IO08PDB0V1 IO12NDB0V1 IO18NDB0V2 IO17NDB0V2 IO25NDB0V3 IO29NDB0V3 IO33NDB1V0 IO40PDB1V1 IO43NDB1V1 IO47PDB1V1 676-Pin FBGA Pin Number D19 D20 D21 D22 D23 D24 D25 D26 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 E15 E16 E17 E18 E19 E20 E21 E22 E23 E24 E25 E26 F1 F2 A3PE1500 Function IO45PDB1V1 IO46PPB1V1 IO48PPB1V2 GBA0/IO57NPB1V3 GNDQ GBB1/IO56PPB1V3 GBB2/IO59PDB2V0 IO59NDB2V0 IO212PDB7V2 IO211NDB7V2 IO211PDB7V2 IO220NPB7V3 GNDQ GAB2/IO220PPB7V3 GAB1/IO01PDB0V0 IO05PDB0V0 IO08NDB0V1 IO12PDB0V1 IO18PDB0V2 IO17PDB0V2 IO25PDB0V3 IO29PDB0V3 IO33PDB1V0 IO40NDB1V1 IO43PDB1V1 IO47NDB1V1 IO54NDB1V3 IO52NDB1V2 IO52PDB1V2 VCCPLB GBA1/IO57PPB1V3 IO63PDB2V0 IO63NDB2V0 IO68PDB2V1 IO212NDB7V2 IO203PPB7V1 676-Pin FBGA Pin Number F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 A3PE1500 Function IO213NDB7V2 IO213PDB7V2 GND VCCPLA GAB0/IO01NDB0V0 GNDQ IO03PDB0V0 IO13PDB0V1 IO15PDB0V1 IO19PDB0V2 IO21PDB0V2 IO27NDB0V3 IO35PDB1V0 IO39NDB1V0 IO51PDB1V2 IO53PDB1V2 IO54PDB1V3 VMV2 VCOMPLB IO61PDB2V0 IO61NDB2V0 IO66PDB2V1 IO66NDB2V1 IO68NDB2V1 IO203NPB7V1 IO207NDB7V2 IO207PDB7V2 IO216NDB7V3 IO216PDB7V3 VCOMPLA VMV0 VCC IO03NDB0V0 IO13NDB0V1 IO15NDB0V1 IO19NDB0V2 v1.5 3 - 35 Package Pin Assignments 676-Pin FBGA Pin Number G13 G14 G15 G16 G17 G18 G19 G20 G21 G22 G23 G24 G25 G26 H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 H13 H14 H15 H16 H17 H18 H19 H20 H21 H22 A3PE1500 Function IO21NDB0V2 IO27PDB0V3 IO35NDB1V0 IO39PDB1V0 IO51NDB1V2 IO53NDB1V2 VCCIB1 GBA2/IO58PPB2V0 GNDQ IO64NDB2V1 IO64PDB2V1 IO72PDB2V2 IO72NDB2V2 IO78PDB2V2 IO208NDB7V2 IO208PDB7V2 IO209NDB7V2 IO209PDB7V2 IO219NDB7V3 GAC2/IO219PDB7V3 VCCIB7 VCC VCCIB0 VCCIB0 VCCIB0 VCCIB0 VCCIB0 VCCIB1 VCCIB1 VCCIB1 VCCIB1 VCCIB1 VCC VCC IO58NPB2V0 IO70PDB2V1 676-Pin FBGA Pin Number H23 H24 H25 H26 J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 J13 J14 J15 J16 J17 J18 J19 J20 J21 J22 J23 J24 J25 J26 K1 K2 K3 K4 K5 K6 A3PE1500 Function IO69PDB2V1 IO76PDB2V2 IO76NDB2V2 IO78NDB2V2 IO197NDB7V0 IO197PDB7V0 VMV7 IO215NDB7V3 IO215PDB7V3 IO214PDB7V3 IO214NDB7V3 VCCIB7 VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCCIB2 IO62PDB2V0 IO62NDB2V0 IO70NDB2V1 IO69NDB2V1 VMV2 IO80PDB2V3 IO80NDB2V3 IO195PDB7V0 IO199NDB7V1 IO199PDB7V1 IO205NDB7V1 IO205PDB7V1 IO217PDB7V3 676-Pin FBGA Pin Number K7 K8 K9 K10 K11 K12 K13 K14 K15 K16 K17 K18 K19 K20 K21 K22 K23 K24 K25 K26 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 L15 L16 A3PE1500 Function IO217NDB7V3 VCCIB7 VCC GND GND GND GND GND GND GND GND VCC VCCIB2 IO65PDB2V1 IO65NDB2V1 IO74PDB2V2 IO74NDB2V2 IO75PDB2V2 IO75NDB2V2 IO84PDB2V3 IO195NDB7V0 IO198PPB7V0 GNDQ IO201PDB7V1 IO201NDB7V1 IO210NDB7V2 IO210PDB7V2 VCCIB7 VCC GND GND GND GND GND GND GND 3 -3 6 v1.5 ProASIC3E Packaging 676-Pin FBGA Pin Number L17 L18 L19 L20 L21 L22 L23 L24 L25 L26 M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 M12 M13 M14 M15 M16 M17 M18 M19 M20 M21 M22 M23 M24 M25 M26 A3PE1500 Function GND VCC VCCIB2 IO67PDB2V1 IO67NDB2V1 IO71PDB2V2 IO71NDB2V2 GNDQ IO82PDB2V3 IO84NDB2V3 IO198NPB7V0 IO202PDB7V1 IO202NDB7V1 IO206NDB7V1 IO206PDB7V1 IO204NDB7V1 IO204PDB7V1 VCCIB7 VCC GND GND GND GND GND GND GND GND VCC VCCIB2 IO73NDB2V2 IO73PDB2V2 IO81PPB2V3 IO77PDB2V2 IO77NDB2V2 IO82NDB2V3 IO83PDB2V3 676-Pin FBGA Pin Number N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 N12 N13 N14 N15 N16 N17 N18 N19 N20 N21 N22 N23 N24 N25 N26 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 A3PE1500 Function GFB0/IO191NPB7V0 VCOMPLF GFB1/IO191PPB7V0 IO196PDB7V0 GFA0/IO190NDB6V2 IO200PDB7V1 IO200NDB7V1 VCCIB7 VCC GND GND GND GND GND GND GND GND VCC VCCIB2 IO79PDB2V3 IO79NDB2V3 GCA2/IO88PPB3V0 IO81NPB2V3 GCA0/IO87NDB3V0 GCB0/IO86NPB2V3 IO83NDB2V3 GFA2/IO189PDB6V2 VCCPLF IO193PPB7V0 IO196NDB7V0 GFA1/IO190PDB6V2 IO194PDB7V0 IO194NDB7V0 VCCIB6 VCC GND 676-Pin FBGA Pin Number P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 A3PE1500 Function GND GND GND GND GND GND GND VCC VCCIB3 GCC0/IO85NDB2V3 GCC1/IO85PDB2V3 GCB1/IO86PPB2V3 IO88NPB3V0 GCA1/IO87PDB3V0 VCCPLC VCOMPLC IO189NDB6V2 IO185PDB6V2 IO187NPB6V2 IO193NPB7V0 GFC2/IO187PPB6V2 GFC1/IO192PDB7V0 GFC0/IO192NDB7V0 VCCIB6 VCC GND GND GND GND GND GND GND GND VCC VCCIB3 NC v1.5 3 - 37 Package Pin Assignments 676-Pin FBGA Pin Number R21 R22 R23 R24 R25 R26 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23 T24 T25 T26 U1 U2 U3 U4 A3PE1500 Function IO89NDB3V0 GCB2/IO89PDB3V0 IO90NDB3V0 GCC2/IO90PDB3V0 IO91PDB3V0 IO91NDB3V0 IO186PDB6V2 IO185NDB6V2 GNDQ IO180PDB6V1 IO180NDB6V1 IO188NDB6V2 GFB2/IO188PDB6V2 VCCIB6 VCC GND GND GND GND GND GND GND GND VCC VCCIB3 IO99PDB3V1 IO99NDB3V1 IO97PDB3V1 IO97NDB3V1 GNDQ IO93PPB3V0 NC IO186NDB6V2 IO184NDB6V2 IO184PDB6V2 IO182NDB6V1 676-Pin FBGA Pin Number U5 U6 U7 U8 U9 U10 U11 U12 U13 U14 U15 U16 U17 U18 U19 U20 U21 U22 U23 U24 U25 U26 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 A3PE1500 Function IO182PDB6V1 IO178PDB6V1 IO178NDB6V1 VCCIB6 VCC GND GND GND GND GND GND GND GND VCC VCCIB3 NC IO101NDB3V1 IO101PDB3V1 IO92NDB3V0 IO92PDB3V0 IO95PDB3V1 IO93NPB3V0 IO183PDB6V2 IO183NDB6V2 VMV6 IO181PDB6V1 IO181NDB6V1 IO176PDB6V1 IO176NDB6V1 VCCIB6 VCC VCC VCC VCC VCC VCC 676-Pin FBGA Pin Number V15 V16 V17 V18 V19 V20 V21 V22 V23 V24 V25 V26 W1 W2 W3 W4 W5 W6 W7 W8 W9 W10 W11 W12 W13 W14 W15 W16 W17 W18 W19 W20 W21 W22 W23 W24 A3PE1500 Function VCC VCC VCC VCC VCCIB3 IO107PDB3V2 IO107NDB3V2 IO103NDB3V2 IO103PDB3V2 VMV3 IO95NDB3V1 IO94PDB3V0 IO179NDB6V1 IO179PDB6V1 IO177NDB6V1 IO177PDB6V1 IO172PDB6V0 IO172NDB6V0 VCC VCC VCCIB5 VCCIB5 VCCIB5 VCCIB5 VCCIB5 VCCIB4 VCCIB4 VCCIB4 VCCIB4 VCCIB4 VCC VCCIB3 GDB0/IO109NDB3V2 GDB1/IO109PDB3V2 IO105NDB3V2 IO105PDB3V2 3 -3 8 v1.5 ProASIC3E Packaging 676-Pin FBGA Pin Number W25 W26 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 Y11 Y12 Y13 Y14 Y15 Y16 Y17 Y18 Y19 Y20 Y21 Y22 Y23 Y24 Y25 Y26 A3PE1500 Function IO96PDB3V1 IO94NDB3V0 IO175NDB6V1 IO175PDB6V1 IO173NDB6V0 IO173PDB6V0 GEC1/IO169PPB6V0 GNDQ VMV6 VCCIB5 IO163NDB5V3 IO159PDB5V3 IO153PDB5V2 IO147PDB5V1 IO139PDB5V0 IO137PDB5V0 IO125NDB4V1 IO125PDB4V1 IO115NDB4V0 IO115PDB4V0 VCC VPUMP VCOMPLD VCCPLD IO100NDB3V1 IO100PDB3V1 IO96NDB3V1 IO98PDB3V1 v1.5 3 - 39 Package Pin Assignments 896-Pin FBGA A1 Ball Pad Corner 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF AG AH AJ AK Note: This is the bottom view of the package. Note For Package Manufacturing and Environmental information, visit the Resource Center at http://www.actel.com/products/solutions/package/docs.aspx. 3 -4 0 v1.5 ProASIC3E Packaging 896-Pin FBGA Pin Number A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 AA1 AA2 AA3 AA4 AA5 AA6 AA7 AA8 A3PE3000 Function GND GND IO14NPB0V1 GND IO07NPB0V0 GND IO09NDB0V1 IO17NDB0V2 IO17PDB0V2 IO21NDB0V2 IO21PDB0V2 IO33NDB0V4 IO33PDB0V4 IO35NDB0V4 IO35PDB0V4 IO41NDB1V0 IO43NDB1V0 IO43PDB1V0 IO45NDB1V0 IO45PDB1V0 IO57NDB1V2 IO57PDB1V2 GND IO69PPB1V3 GND GBC1/IO79PPB1V4 GND GND IO256PDB6V2 IO248PDB6V1 IO248NDB6V1 IO246NDB6V1 GEA1/IO234PDB6V0 GEA0/IO234NDB6V0 IO243PPB6V1 IO245NDB6V1 896-Pin FBGA Pin Number AA9 AA10 AA11 AA12 AA13 AA14 AA15 AA16 AA17 AA18 AA19 AA20 AA21 AA22 AA23 AA24 AA25 AA26 AA27 AA28 AA29 AA30 AB1 AB2 AB3 AB4 AB5 AB6 AB7 AB8 AB9 AB10 AB11 AB12 AB13 AB14 A3PE3000 Function GEB1/IO235PPB6V0 VCC IO226PPB5V4 VCCIB5 VCCIB5 VCCIB5 VCCIB5 VCCIB4 VCCIB4 VCCIB4 VCCIB4 IO174PDB4V2 VCC IO142NPB3V3 IO144NDB3V3 IO144PDB3V3 IO146NDB3V4 IO146PDB3V4 IO147PDB3V4 IO139NDB3V3 IO139PDB3V3 IO133NDB3V2 IO256NDB6V2 IO244PDB6V1 IO244NDB6V1 IO241PDB6V0 IO241NDB6V0 IO243NPB6V1 VCCIB6 VCCPLE VCC IO222PDB5V3 IO218PPB5V3 IO206NDB5V1 IO206PDB5V1 IO198NDB5V0 896-Pin FBGA Pin Number AB15 AB16 AB17 AB18 AB19 AB20 AB21 AB22 AB23 AB24 AB25 AB26 AB27 AB28 AB29 AB30 AC1 AC2 AC3 AC4 AC5 AC6 AC7 AC8 AC9 AC10 AC11 AC12 AC13 AC14 AC15 AC16 AC17 AC18 AC19 AC20 A3PE3000 Function IO198PDB5V0 IO192NDB4V4 IO192PDB4V4 IO178NDB4V3 IO178PDB4V3 IO174NDB4V2 IO162NPB4V1 VCC VCCPLD VCCIB3 IO150PDB3V4 IO148PDB3V4 IO147NDB3V4 IO145PDB3V3 IO143PDB3V3 IO137PDB3V2 IO254PDB6V2 IO254NDB6V2 IO240PDB6V0 GEC1/IO236PDB6V0 IO237PDB6V0 IO237NDB6V0 VCOMPLE GND IO226NPB5V4 IO222NDB5V3 IO216NPB5V2 IO210NPB5V2 IO204NDB5V1 IO204PDB5V1 IO194NDB5V0 IO188NDB4V4 IO188PDB4V4 IO182PPB4V3 IO170NPB4V2 IO164NDB4V1 v1.5 3 - 41 Package Pin Assignments 896-Pin FBGA Pin Number AC21 AC22 AC23 AC24 AC25 AC26 AC27 AC28 AC29 AC30 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 A3PE3000 Function IO164PDB4V1 IO162PPB4V1 GND VCOMPLD IO150NDB3V4 IO148NDB3V4 GDA1/IO153PDB3V4 IO145NDB3V3 IO143NDB3V3 IO137NDB3V2 GND IO242NPB6V1 IO240NDB6V0 GEC0/IO236NDB6V0 VCCIB6 GNDQ VCC VMV5 VCCIB5 IO224PPB5V3 IO218NPB5V3 IO216PPB5V2 IO210PPB5V2 IO202PPB5V1 IO194PDB5V0 IO190PDB4V4 IO182NPB4V3 IO176NDB4V2 IO176PDB4V2 IO170PPB4V2 IO166PDB4V1 VCCIB4 TCK VCC TRST VCCIB3 896-Pin FBGA Pin Number AD27 AD28 AD29 AD30 AE1 AE2 AE3 AE4 AE5 AE6 AE7 AE8 AE9 AE10 AE11 AE12 AE13 AE14 AE15 AE16 AE17 AE18 AE19 AE20 AE21 AE22 AE23 AE24 AE25 AE26 AE27 AE28 AE29 AE30 AF1 AF2 A3PE3000 Function GDA0/IO153NDB3V4 GDC0/IO151NDB3V4 GDC1/IO151PDB3V4 GND IO242PPB6V1 VCC IO239PDB6V0 IO239NDB6V0 VMV6 GND GNDQ IO230NDB5V4 IO224NPB5V3 IO214NPB5V2 IO212NDB5V2 IO212PDB5V2 IO202NPB5V1 IO200NDB5V0 IO196PDB5V0 IO190NDB4V4 IO184PDB4V3 IO184NDB4V3 IO172PDB4V2 IO172NDB4V2 IO166NDB4V1 IO160PDB4V0 GNDQ VMV4 GND GDB0/IO152NDB3V4 GDB1/IO152PDB3V4 VMV3 VCC IO149PDB3V4 GND IO238PPB6V0 896-Pin FBGA Pin Number AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 AF16 AF17 AF18 AF19 AF20 AF21 AF22 AF23 AF24 AF25 AF26 AF27 AF28 AF29 AF30 AG1 AG2 AG3 AG4 AG5 AG6 AG7 AG8 A3PE3000 Function VCCIB6 IO220NPB5V3 VCC IO228NDB5V4 VCCIB5 IO230PDB5V4 IO229NDB5V4 IO229PDB5V4 IO214PPB5V2 IO208NDB5V1 IO208PDB5V1 IO200PDB5V0 IO196NDB5V0 IO186NDB4V4 IO186PDB4V4 IO180NDB4V3 IO180PDB4V3 IO168NDB4V1 IO168PDB4V1 IO160NDB4V0 IO158NPB4V0 VCCIB4 IO154NPB4V0 VCC TDO VCCIB3 GNDQ GND IO238NPB6V0 VCC IO232NPB5V4 GND IO220PPB5V3 IO228PDB5V4 IO231NDB5V4 GEC2/IO231PDB5V4 3 -4 2 v1.5 ProASIC3E Packaging 896-Pin FBGA Pin Number AG9 AG10 AG11 AG12 AG13 AG14 AG15 AG16 AG17 AG18 AG19 AG20 AG21 AG22 AG23 AG24 AG25 AG26 AG27 AG28 AG29 AG30 AH1 AH2 AH3 AH4 AH5 AH6 AH7 AH8 AH9 AH10 AH11 AH12 AH13 AH14 A3PE3000 Function IO225NPB5V3 IO223NPB5V3 IO221PDB5V3 IO221NDB5V3 IO205NPB5V1 IO199NDB5V0 IO199PDB5V0 IO187NDB4V4 IO187PDB4V4 IO181NDB4V3 IO171PPB4V2 IO165NPB4V1 IO161NPB4V0 IO159NDB4V0 IO159PDB4V0 IO158PPB4V0 GDB2/IO155PDB4V0 GDA2/IO154PPB4V0 GND VJTAG VCC IO149NDB3V4 GND IO233NPB5V4 VCC GEB2/IO232PPB5V4 VCCIB5 IO219NDB5V3 IO219PDB5V3 IO227NDB5V4 IO227PDB5V4 IO225PPB5V3 IO223PPB5V3 IO211NDB5V2 IO211PDB5V2 IO205PPB5V1 896-Pin FBGA Pin Number AH15 AH16 AH17 AH18 AH19 AH20 AH21 AH22 AH23 AH24 AH25 AH26 AH27 AH28 AH29 AH30 AJ1 AJ2 AJ3 AJ4 AJ5 AJ6 AJ7 AJ8 AJ9 AJ10 AJ11 AJ12 AJ13 AJ14 AJ15 AJ16 AJ17 AJ18 AJ19 AJ20 A3PE3000 Function IO195NDB5V0 IO185NDB4V3 IO185PDB4V3 IO181PDB4V3 IO177NDB4V2 IO171NPB4V2 IO165PPB4V1 IO161PPB4V0 IO157NDB4V0 IO157PDB4V0 IO155NDB4V0 VCCIB4 TDI VCC VPUMP GND GND GND GEA2/IO233PPB5V4 VCC IO217NPB5V2 VCC IO215NPB5V2 IO213NDB5V2 IO213PDB5V2 IO209NDB5V1 IO209PDB5V1 IO203NDB5V1 IO203PDB5V1 IO197NDB5V0 IO195PDB5V0 IO183NDB4V3 IO183PDB4V3 IO179NPB4V3 IO177PDB4V2 IO173NDB4V2 896-Pin FBGA Pin Number AJ21 AJ22 AJ23 AJ24 AJ25 AJ26 AJ27 AJ28 AJ29 AJ30 AK2 AK3 AK4 AK5 AK6 AK7 AK8 AK9 AK10 AK11 AK12 AK13 AK14 AK15 AK16 AK17 AK18 AK19 AK20 AK21 AK22 AK23 AK24 AK25 AK26 AK27 A3PE3000 Function IO173PDB4V2 IO163NDB4V1 IO163PDB4V1 IO167NPB4V1 VCC IO156NPB4V0 VCC TMS GND GND GND GND IO217PPB5V2 GND IO215PPB5V2 GND IO207NDB5V1 IO207PDB5V1 IO201NDB5V0 IO201PDB5V0 IO193NDB4V4 IO193PDB4V4 IO197PDB5V0 IO191NDB4V4 IO191PDB4V4 IO189NDB4V4 IO189PDB4V4 IO179PPB4V3 IO175NDB4V2 IO175PDB4V2 IO169NDB4V1 IO169PDB4V1 GND IO167PPB4V1 GND GDC2/IO156PPB4V0 v1.5 3 - 43 Package Pin Assignments 896-Pin FBGA Pin Number AK28 AK29 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 C1 C2 C3 C4 A3PE3000 Function GND GND GND GND GAA2/IO309PPB7V4 VCC IO14PPB0V1 VCC IO07PPB0V0 IO09PDB0V1 IO15PPB0V1 IO19NDB0V2 IO19PDB0V2 IO29NDB0V3 IO29PDB0V3 IO31PPB0V3 IO37NDB0V4 IO37PDB0V4 IO41PDB1V0 IO51NDB1V1 IO59PDB1V2 IO53PDB1V1 IO53NDB1V1 IO61NDB1V2 IO61PDB1V2 IO69NPB1V3 VCC GBC0/IO79NPB1V4 VCC IO64NPB1V2 GND GND GND IO309NPB7V4 VCC GAA0/IO00NPB0V0 896-Pin FBGA Pin Number C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 C27 C28 C29 C30 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 A3PE3000 Function VCCIB0 IO03PDB0V0 IO03NDB0V0 GAB1/IO01PDB0V0 IO05PDB0V0 IO15NPB0V1 IO25NDB0V3 IO25PDB0V3 IO31NPB0V3 IO27NDB0V3 IO39NDB0V4 IO39PDB0V4 IO55PPB1V1 IO51PDB1V1 IO59NDB1V2 IO63NDB1V2 IO63PDB1V2 IO67NDB1V3 IO67PDB1V3 IO75NDB1V4 IO75PDB1V4 VCCIB1 IO64PPB1V2 VCC GBA1/IO81PPB1V4 GND IO303PPB7V3 VCC IO305NPB7V3 GND GAA1/IO00PPB0V0 GAC1/IO02PDB0V0 IO06NPB0V0 GAB0/IO01NDB0V0 IO05NDB0V0 IO11NDB0V1 896-Pin FBGA Pin Number D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 E15 E16 A3PE3000 Function IO11PDB0V1 IO23NDB0V2 IO23PDB0V2 IO27PDB0V3 IO40PDB0V4 IO47NDB1V0 IO47PDB1V0 IO55NPB1V1 IO65NDB1V3 IO65PDB1V3 IO71NDB1V3 IO71PDB1V3 IO73NDB1V4 IO73PDB1V4 IO74NDB1V4 GBB0/IO80NPB1V4 GND GBA0/IO81NPB1V4 VCC GBA2/IO82PPB2V0 GND IO303NPB7V3 VCCIB7 IO305PPB7V3 VCC GAC0/IO02NDB0V0 VCCIB0 IO06PPB0V0 IO24NDB0V2 IO24PDB0V2 IO13NDB0V1 IO13PDB0V1 IO34NDB0V4 IO34PDB0V4 IO40NDB0V4 IO49NDB1V1 3 -4 4 v1.5 ProASIC3E Packaging 896-Pin FBGA Pin Number E17 E18 E19 E20 E21 E22 E23 E24 E25 E26 E27 E28 E29 E30 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 A3PE3000 Function IO49PDB1V1 IO50PDB1V1 IO58PDB1V2 IO60NDB1V2 IO77PDB1V4 IO68NDB1V3 IO68PDB1V3 VCCIB1 IO74PDB1V4 VCC GBB1/IO80PPB1V4 VCCIB2 IO82NPB2V0 GND IO296PPB7V2 VCC IO306PDB7V4 IO297PDB7V2 VMV7 GND GNDQ IO12NDB0V1 IO12PDB0V1 IO10PDB0V1 IO16PDB0V1 IO22NDB0V2 IO30NDB0V3 IO30PDB0V3 IO36PDB0V4 IO48NDB1V0 IO48PDB1V0 IO50NDB1V1 IO58NDB1V2 IO60PDB1V2 IO77NDB1V4 IO72NDB1V3 896-Pin FBGA Pin Number F23 F24 F25 F26 F27 F28 F29 F30 G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 G13 G14 G15 G16 G17 G18 G19 G20 G21 G22 G23 G24 G25 G26 G27 G28 A3PE3000 Function IO72PDB1V3 GNDQ GND VMV2 IO86PDB2V0 IO92PDB2V1 VCC IO100NPB2V2 GND IO296NPB7V2 IO306NDB7V4 IO297NDB7V2 VCCIB7 GNDQ VCC VMV0 VCCIB0 IO10NDB0V1 IO16NDB0V1 IO22PDB0V2 IO26PPB0V3 IO38NPB0V4 IO36NDB0V4 IO46NDB1V0 IO46PDB1V0 IO56NDB1V1 IO56PDB1V1 IO66NDB1V3 IO66PDB1V3 VCCIB1 VMV1 VCC GNDQ VCCIB2 IO86NDB2V0 IO92NDB2V1 896-Pin FBGA Pin Number G29 G30 H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 H13 H14 H15 H16 H17 H18 H19 H20 H21 H22 H23 H24 H25 H26 H27 H28 H29 H30 J1 J2 J3 J4 A3PE3000 Function IO100PPB2V2 GND IO294PDB7V2 IO294NDB7V2 IO300NDB7V3 IO300PDB7V3 IO295PDB7V2 IO299PDB7V3 VCOMPLA GND IO08NDB0V0 IO08PDB0V0 IO18PDB0V2 IO26NPB0V3 IO28NDB0V3 IO28PDB0V3 IO38PPB0V4 IO42NDB1V0 IO52NDB1V1 IO52PDB1V1 IO62NDB1V2 IO62PDB1V2 IO70NDB1V3 IO70PDB1V3 GND VCOMPLB GBC2/IO84PDB2V0 IO84NDB2V0 IO96PDB2V1 IO96NDB2V1 IO89PDB2V0 IO89NDB2V0 IO290NDB7V2 IO290PDB7V2 IO302NDB7V3 IO302PDB7V3 v1.5 3 - 45 Package Pin Assignments 896-Pin FBGA Pin Number J5 J6 J7 J8 J9 J10 J11 J12 J13 J14 J15 J16 J17 J18 J19 J20 J21 J22 J23 J24 J25 J26 J27 J28 J29 J30 K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 A3PE3000 Function IO295NDB7V2 IO299NDB7V3 VCCIB7 VCCPLA VCC IO04NPB0V0 IO18NDB0V2 IO20NDB0V2 IO20PDB0V2 IO32NDB0V3 IO32PDB0V3 IO42PDB1V0 IO44NDB1V0 IO44PDB1V0 IO54NDB1V1 IO54PDB1V1 IO76NPB1V4 VCC VCCPLB VCCIB2 IO90PDB2V1 IO90NDB2V1 GBB2/IO83PDB2V0 IO83NDB2V0 IO91PDB2V1 IO91NDB2V1 IO288NDB7V1 IO288PDB7V1 IO304NDB7V3 IO304PDB7V3 GAB2/IO308PDB7V4 IO308NDB7V4 IO301PDB7V3 IO301NDB7V3 GAC2/IO307PPB7V4 VCC 896-Pin FBGA Pin Number K11 K12 K13 K14 K15 K16 K17 K18 K19 K20 K21 K22 K23 K24 K25 K26 K27 K28 K29 K30 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 L15 L16 A3PE3000 Function IO04PPB0V0 VCCIB0 VCCIB0 VCCIB0 VCCIB0 VCCIB1 VCCIB1 VCCIB1 VCCIB1 IO76PPB1V4 VCC IO78PPB1V4 IO88NDB2V0 IO88PDB2V0 IO94PDB2V1 IO94NDB2V1 IO85PDB2V0 IO85NDB2V0 IO93PDB2V1 IO93NDB2V1 IO286NDB7V1 IO286PDB7V1 IO298NDB7V3 IO298PDB7V3 IO283PDB7V1 IO291NDB7V2 IO291PDB7V2 IO293PDB7V2 IO293NDB7V2 IO307NPB7V4 VCC VCC VCC VCC VCC VCC 896-Pin FBGA Pin Number L17 L18 L19 L20 L21 L22 L23 L24 L25 L26 L27 L28 L29 L30 M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 M12 M13 M14 M15 M16 M17 M18 M19 M20 M21 M22 A3PE3000 Function VCC VCC VCC VCC IO78NPB1V4 IO104NPB2V2 IO98NDB2V2 IO98PDB2V2 IO87PDB2V0 IO87NDB2V0 IO97PDB2V1 IO101PDB2V2 IO103PDB2V2 IO119NDB3V0 IO282NDB7V1 IO282PDB7V1 IO292NDB7V2 IO292PDB7V2 IO283NDB7V1 IO285PDB7V1 IO287PDB7V1 IO289PDB7V1 IO289NDB7V1 VCCIB7 VCC GND GND GND GND GND GND GND GND VCC VCCIB2 NC 3 -4 6 v1.5 ProASIC3E Packaging 896-Pin FBGA Pin Number M23 M24 M25 M26 M27 M28 M29 M30 N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 N12 N13 N14 N15 N16 N17 N18 N19 N20 N21 N22 N23 N24 N25 N26 N27 N28 A3PE3000 Function IO104PPB2V2 IO102PDB2V2 IO102NDB2V2 IO95PDB2V1 IO97NDB2V1 IO101NDB2V2 IO103NDB2V2 IO119PDB3V0 IO276PDB7V0 IO278PDB7V0 IO280PDB7V0 IO284PDB7V1 IO279PDB7V0 IO285NDB7V1 IO287NDB7V1 IO281NDB7V0 IO281PDB7V0 VCCIB7 VCC GND GND GND GND GND GND GND GND VCC VCCIB2 IO106NDB2V3 IO106PDB2V3 IO108PDB2V3 IO108NDB2V3 IO95NDB2V1 IO99NDB2V2 IO99PDB2V2 896-Pin FBGA Pin Number N29 N30 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 R1 R2 R3 R4 A3PE3000 Function IO107PDB2V3 IO107NDB2V3 IO276NDB7V0 IO278NDB7V0 IO280NDB7V0 IO284NDB7V1 IO279NDB7V0 GFC1/IO275PDB7V0 GFC0/IO275NDB7V0 IO277PDB7V0 IO277NDB7V0 VCCIB7 VCC GND GND GND GND GND GND GND GND VCC VCCIB2 GCC1/IO112PDB2V3 IO110PDB2V3 IO110NDB2V3 IO109PPB2V3 IO111NPB2V3 IO105PDB2V2 IO105NDB2V2 GCC2/IO117PDB3V0 IO117NDB3V0 GFC2/IO270PDB6V4 GFB1/IO274PPB7V0 VCOMPLF GFA0/IO273NDB6V4 896-Pin FBGA Pin Number R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 R30 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 A3PE3000 Function GFB0/IO274NPB7V0 IO271NDB6V4 GFB2/IO271PDB6V4 IO269PDB6V4 IO269NDB6V4 VCCIB7 VCC GND GND GND GND GND GND GND GND VCC VCCIB2 GCC0/IO112NDB2V3 GCB2/IO116PDB3V0 IO118PDB3V0 IO111PPB2V3 IO122PPB3V1 GCA0/IO114NPB3V0 VCOMPLC GCB1/IO113PPB2V3 IO115NPB3V0 IO270NDB6V4 VCCPLF GFA2/IO272PPB6V4 GFA1/IO273PDB6V4 IO272NPB6V4 IO267NDB6V4 IO267PDB6V4 IO265PDB6V3 IO263PDB6V3 VCCIB6 v1.5 3 - 47 Package Pin Assignments 896-Pin FBGA Pin Number T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23 T24 T25 T26 T27 T28 T29 T30 U1 U2 U3 U4 U5 U6 U7 U8 U9 U10 U11 U12 U13 U14 U15 U16 A3PE3000 Function VCC GND GND GND GND GND GND GND GND VCC VCCIB3 IO109NPB2V3 IO116NDB3V0 IO118NDB3V0 IO122NPB3V1 GCA1/IO114PPB3V0 GCB0/IO113NPB2V3 GCA2/IO115PPB3V0 VCCPLC IO121PDB3V0 IO268PDB6V4 IO264NDB6V3 IO264PDB6V3 IO258PDB6V3 IO258NDB6V3 IO257PPB6V2 IO261PPB6V3 IO265NDB6V3 IO263NDB6V3 VCCIB6 VCC GND GND GND GND GND 896-Pin FBGA Pin Number U17 U18 U19 U20 U21 U22 U23 U24 U25 U26 U27 U28 U29 U30 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 V16 V17 V18 V19 V20 V21 V22 A3PE3000 Function GND GND GND VCC VCCIB3 IO120PDB3V0 IO128PDB3V1 IO124PDB3V1 IO124NDB3V1 IO126PDB3V1 IO129PDB3V1 IO127PDB3V1 IO125PDB3V1 IO121NDB3V0 IO268NDB6V4 IO262PDB6V3 IO260PDB6V3 IO252PDB6V2 IO257NPB6V2 IO261NPB6V3 IO255PDB6V2 IO259PDB6V3 IO259NDB6V3 VCCIB6 VCC GND GND GND GND GND GND GND GND VCC VCCIB3 IO120NDB3V0 896-Pin FBGA Pin Number V23 V24 V25 V26 V27 V28 V29 V30 W1 W2 W3 W4 W5 W6 W7 W8 W9 W10 W11 W12 W13 W14 W15 W16 W17 W18 W19 W20 W21 W22 W23 W24 W25 W26 W27 W28 A3PE3000 Function IO128NDB3V1 IO132PDB3V2 IO130PPB3V2 IO126NDB3V1 IO129NDB3V1 IO127NDB3V1 IO125NDB3V1 IO123PDB3V1 IO266NDB6V4 IO262NDB6V3 IO260NDB6V3 IO252NDB6V2 IO251NDB6V2 IO251PDB6V2 IO255NDB6V2 IO249PPB6V1 IO253PDB6V2 VCCIB6 VCC GND GND GND GND GND GND GND GND VCC VCCIB3 IO134PDB3V2 IO138PDB3V3 IO132NDB3V2 IO136NPB3V2 IO130NPB3V2 IO141PDB3V3 IO135PDB3V2 3 -4 8 v1.5 ProASIC3E Packaging 896-Pin FBGA Pin Number W29 W30 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 Y11 Y12 Y13 Y14 Y15 Y16 Y17 Y18 Y19 Y20 Y21 Y22 Y23 Y24 Y25 Y26 Y27 Y28 Y29 Y30 A3PE3000 Function IO131PDB3V2 IO123NDB3V1 IO266PDB6V4 IO250PDB6V2 IO250NDB6V2 IO246PDB6V1 IO247NDB6V1 IO247PDB6V1 IO249NPB6V1 IO245PDB6V1 IO253NDB6V2 GEB0/IO235NPB6V0 VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC IO142PPB3V3 IO134NDB3V2 IO138NDB3V3 IO140NDB3V3 IO140PDB3V3 IO136PPB3V2 IO141NDB3V3 IO135NDB3V2 IO131NDB3V2 IO133PDB3V2 v1.5 3 - 49 Package Pin Assignments Part Number and Revision Date Part Number 51700098-003-5 Revised June 2008 List of Changes The following table lists critical changes that were made in the current version of the chapter. Previous Version v1.4 (June 2008) v1.3 (April 2008) Changes in Current Version (v1.5) The A3PE600 "484-Pin FBGA" table was missing G22. The pin and its function were added to the table. The naming conventions changed for the following pins in the "484-Pin FBGA" for the A3PE600: Pin Number J19 K20 M2 N1 N4 P3 v1.2 (April 2008) v1.1 New Function Name IO45PPB2V1 IO45NPB2V1 IO114NPB6V1 IO114PPB6V1 GFC2/IO115PPB6V1 IO115NPB6V1 3-12 3-6 Page 3-17 3-17 The "324-Pin FBGA" package diagram was replaced. The following pins had duplicates and the extra pins were deleted from the "208-Pin PQFP" A3PE3000 table: 36, 62, 171 Note: There were no pin function changes in this update. The following pins had duplicates and the extra pins were deleted from the "324-Pin FBGA" table: E2, E3, E16, E17, P2, P3, T16, U17 Note: There were no pin function changes in this update. The "256-Pin FBGA" was updated for the A3PE600 device because the old PAT where based on the IFX die, and this is the final UMC die version. The "484-Pin FBGA" was updated for the A3PE600 device because the old PAT where based on the IFX die, and this is the final UMC die version. The following pins had duplicates and the extra pins were deleted from the "896-Pin FBGA" table: AD6, AE5, AE28, AF29, F5, F26, G6, G25 Note: There were no pin function changes in this update. 3-13 3-17 3-17 3-41 v1.0 (January 2008) The "208-Pin PQFP" pin table for A3PE3000 was updated. The "324-Pin FBGA" pin table for A3PE3000 is new. The "484-Pin FBGA" pin table for A3PE3000 is new. The "896-Pin FBGA" pin table for A3PE3000 is new. 3-6 3-13 3-27 3-41 N/A v2.1 (July 2007) This document was previously in datasheet v2.1. As a result of moving to the handbook format, Actel has restarted the version numbers so the new version number is v1.0. 3 -5 0 v1.5 ProASIC3E Packaging Previous Version Advance v0.6 (January 2007) Changes in Current Version (v1.5) Notes were added to the package diagrams identifying if they were top or bottom view. The A3PE1500 "208-Pin PQFP" table is new. The A3PE1500 "484-Pin FBGA" table is new. The A3PE1500 "A3PE1500 Function" table is new. Page N/A 4-4 4-18 4-24 4-6 Advance v0.2 The A3PE3000 "208-Pin PQFP" pin table was updated. v1.5 3 - 51 Package Pin Assignments Datasheet Categories Categories In order to provide the latest information to designers, some datasheets are published before data has been fully characterized. Datasheets are designated as "Product Brief," "Advance," "Preliminary," and "Production." The definition of these categories are as follows: Product Brief The product brief is a summarized version of a datasheet (advance or production) and contains general product information. This document gives an overview of specific device and family information. Advance This version contains initial estimated information based on simulation, other products, devices, or speed grades. This information can be used as estimates, but not for production. This label only applies to the DC and Switching Characteristics chapter of the datasheet and will only be used when the data has not been fully characterized. Preliminary The datasheet contains information based on simulation and/or initial characterization. The information is believed to be correct, but changes are possible. Unmarked (production) This version contains information that is considered to be final. Export Administration Regulations (EAR) The products described in this document are subject to the Export Administration Regulations (EAR). They could require an approved export license prior to export from the United States. An export includes release of product or disclosure of technology to a foreign national inside or outside the United States. Actel Safety Critical, Life Support, and High-Reliability Applications Policy The Actel products described in this advance status document may not have completed Actel’s qualification process. Actel may amend or enhance products during the product introduction and qualification process, resulting in changes in device functionality or performance. It is the responsibility of each customer to ensure the fitness of any Actel product (but especially a new product) for a particular purpose, including appropriateness for safety-critical, life-support, and other high-reliability applications. Consult Actel’s Terms and Conditions for specific liability exclusions relating to life-support applications. A reliability report covering all of Actel’s products is available on the Actel website at http://www.actel.com/documents/ORT_Report.pdf. Actel also offers a variety of enhanced qualification and lot acceptance screening procedures. Contact your local Actel sales office for additional reliability information. 3 -5 2 v1.5 Actel and the Actel logo are registered trademarks of Actel Corporation. All other trademarks are the property of their owners. w w w. a c t e l . c o m Actel Corporation 2061 Stierlin Court Mountain View, CA 94043-4655 USA Phone 650.318.4200 Fax 650.318.4600 Actel Europe Ltd. River Court,Meadows Business Park Station Approach, Blackwater Camberley Surrey GU17 9AB United Kingdom Phone +44 (0) 1276 609 300 Fax +44 (0) 1276 607 540 Actel Japan EXOS Ebisu Buillding 4F 1-24-14 Ebisu Shibuya-ku Tokyo 150 Japan Phone +81.03.3445.7671 Fax +81.03.3445.7668 http://jp.actel.com Actel Hong Kong Room 2107, China Resources Building 26 Harbour Road Wanchai, Hong Kong Phone +852 2185 6460 Fax +852 2185 6488 www.actel.com.cn 51700098-005-7/6.08