AC244044

PIC16(L)F1825/9 14/20-Pin Flash Microcontrollers with XLP Technology High-Performance RISC CPU • Only 49 Instructions to Learn: - All single-cycle instructions except branches • Operating Speed: - DC – 32 MHz oscillator/clock input - DC – 125 ns instruction cycle • Up to 16 Kbytes Linear Program Memory Addressing • Up to 1024 bytes Linear Data Memory Addressing • Interrupt Capability with Automatic Context Saving • 16-Level Deep Hardware Stack with Optional Overflow/Underflow Reset • Direct, Indirect and Relative Addressing modes: - Two full 16-bit File Select Registers (FSRs) - FSRs can read program and data memory Flexible Oscillator Structure • Precision 32 MHz Internal Oscillator Block: - Factory calibrated to ± 1%, typical - Software selectable frequencies range of 31 kHz to 32 MHz • 31 kHz Low-Power Internal Oscillator • Four Crystal modes up to 32 MHz • Three External Clock modes up to 32 MHz • 4x Phase Lock Loop (PLL) • Fail-Safe Clock Monitor: - Allows for safe shutdown if peripheral clock stops • Two-Speed Oscillator Start-Up • Reference Clock Module: - Programmable clock output frequency and duty cycle Special Microcontroller Features • • • • • • • • • • • 1.8V-5.5V Operation – PIC16F1825/9 1.8V-3.6V Operation – PIC16LF1825/9 Self-Programmable under Software Control Power-on Reset (POR), Power-up Timer (PWRT) and Oscillator Start-up Timer (OST) Programmable Brown-out Reset (BOR) Extended Watchdog Timer (WDT) In-Circuit Serial Programming™ (ICSP™) via Two Pins In-Circuit Debug (ICD) via Two Pins Enhanced Low-Voltage Programming (LVP) Programmable Code Protection Power-Saving Sleep mode  2010-2015 Microchip Technology Inc. Extreme Low-Power Management PIC16LF1825/9 with XLP • • • • Sleep mode: 20 nA @ 1.8V, typical Watchdog Timer: 300 nA @ 1.8V, typical Timer1 Oscillator: 650 nA @ 32 kHz, 1.8V, typical Operating Current: 48 µA/MHz @ 1.8V, typical Analog Features • Analog-to-Digital Converter (ADC) Module: - 10-bit resolution, up to 12 channels - Auto acquisition capability - Conversion available during Sleep • Analog Comparator Module: - Two rail-to-rail analog comparators - Power mode control - Software controllable hysteresis • Voltage Reference Module: - Fixed Voltage Reference (FVR) with 1.024V, 2.048V and 4.096V output levels - 5-bit rail-to-rail resistive DAC with positive and negative reference selection Peripheral Highlights • Up to 17 I/O Pins and 1 Input Only Pin: - High current sink/source 25 mA/25 mA - Programmable weak pull-ups - Programmable interrupt-on-change pins • Timer0: 8-Bit Timer/Counter with 8-Bit Prescaler • Enhanced Timer1: - 16-bit timer/counter with prescaler - External Gate Input mode - Dedicated, low-power 32 kHz oscillator driver • Three Timer2-types: 8-Bit Timer/Counter with 8-Bit Period Register, Prescaler and Postscaler • Two Capture, Compare, PWM (CCP) Modules • Two Enhanced CCP (ECCP) Modules: - Software selectable time bases - Auto-shutdown and auto-restart - PWM steering • Up to Two Master Synchronous Serial Port (MSSP) with SPI and I2CTM with: - 7-bit address masking - SMBus/PMBusTM compatibility • Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) Module • mTouch™ Sensing Oscillator Module: - Up to 12 input channels DS40001440E-page 1 PIC16(L)F1825/9 Peripheral Highlights (Continued) • Data Signal Modulator Module: - Selectable modulator and carrier sources • SR Latch: - Multiple Set/Reset input options - Emulates 555 Timer applications Note: For other small form-factor package availability and marking www.microchip.com/packaging or contact your local sales office. DS40001440E-page 2 information, Debug(1) XLP PIC12(L)F1822 (1) 2K 256 128 6 4 4 1 2/1 1 1 0/1/0 PIC12(L)F1840 (2) 4K 256 256 6 4 4 1 2/1 1 1 0/1/0 PIC16(L)F1823 (1) 2K 256 128 12 8 8 2 2/1 1 1 1/0/0 PIC16(L)F1824 (3) 4K 256 256 12 8 8 2 4/1 1 1 1/1/2 PIC16(L)F1825 (4) 8K 256 1024 12 8 8 2 4/1 1 1 1/1/2 PIC16(L)F1826 (5) 2K 256 256 16 12 12 2 2/1 1 1 1/0/0 PIC16(L)F1827 (5) 4K 256 384 16 12 12 2 4/1 1 2 1/1/2 PIC16(L)F1828 (3) 4K 256 256 18 12 12 2 4/1 1 1 1/1/2 PIC16(L)F1829 (4) 8K 256 1024 18 12 12 2 4/1 1 2 1/1/2 PIC16(L)F1847 (6) 8K 256 1024 16 12 12 2 4/1 1 2 1/1/2 Note 1: I - Debugging, Integrated on Chip; H - Debugging, available using Debug Header. 2: One pin is input-only. Data Sheet Index: (Unshaded devices are described in this document.) 1: DS41413 PIC12(L)F1822/PIC16(L)F1823 Data Sheet, 8/14-Pin Flash Microcontrollers. 2: DS41441 PIC12(L)F1840 Data Sheet, 8-Pin Flash Microcontrollers. 3: DS41419 PIC16(L)F1824/1828 Data Sheet, 28/40/44-Pin Flash Microcontrollers. 4: DS41440 PIC16(L)F1825/1829 Data Sheet, 14/20-Pin Flash Microcontrollers. 5: DS41391 PIC16(L)F1826/1827 Data Sheet, 18/20/28-Pin Flash Microcontrollers. 6: DS41453 PIC16(L)F1847 Data Sheet, 18/20/28-Pin Flash Microcontrollers. SR Latch ECCP (Full-Bridge) ECCP (Half-Bridge) CCP MSSP (I2C™/SPI) EUSART Timers (8/16-bit) Comparators CapSense (ch) 10-bit ADC (ch) I/O’s(2) Data SRAM (bytes) Data EEPROM (bytes) Program Memory Flash (words) Device Data Sheet Index PIC12(L)F1822/1840/PIC16(L)F182x/1847 Family Types Y Y Y Y Y Y Y Y Y Y I/H I/H I/H I/H I/H I/H I/H I/H I/H I/H Y Y Y Y Y Y Y Y Y Y please visit  2010-2015 Microchip Technology Inc. PIC16(L)F1825/9 FIGURE 1: 14-PIN DIAGRAM FOR PIC16(L)F1825 PDIP, SOIC, TSSOP FIGURE 2: 1 14 VSS RA5 2 13 RA0/ICSPDAT 12 RA1/ICSPCLK 11 RA2 10 RC0 9 RC1 8 RC2 RA4 3 MCLR/VPP/RA3 4 RC5 5 RC4 6 RC3 7 PIC16(L)F1825 VDD 16-PIN DIAGRAM FOR PIC16(L)F1825 RA4 2 13 VSS NC 14 15 NC RA5 1 16 VDD QFN, UQFN 12 RA0/ICSPDAT 11 RA1/ICSPCLK PIC16(L)F1825  2010-2015 Microchip Technology Inc. RC1 8 9 RC0 RC2 7 RC5 4 RC3 6 10 RA2 RC4 5 MCLR/VPP/RA3 3 DS40001440E-page 3 PIC16(L)F1825/9 14-PIN AND 16-PIN ALLOCATION TABLE (PIC16(L)F1825) Comparator SR Latch Timers ECCP MSSP Interrupt Modulator Pull-up Basic AN0 VREFDACOUT CPS0 C1IN+ — — — TX(1) CK(1) — IOC — Y ICSPDAT ICDDAT RA1 12 11 AN1 VREF+ CPS1 C12IN0- SRI — — RX(1) DT(1) — IOC — Y ICSPCLK ICDCLK RA2 11 10 AN2 — CPS2 C1OUT SRQ T0CKI CCP3 FLT0 — — INT/ IOC — Y — RA3 4 3 — — — — — T1G(1) — — SS1(1) IOC — Y MCLR VPP RA4 3 2 AN3 — CPS3 — — T1G(1) T1OSO P2B(1) — SDO1(1) IOC — Y OSC2 CLKOUT CLKR RA5 2 1 — — — — — T1CKI T1OSI CCP2 P2A(1) — — IOC — Y OSC1 CLKIN RC0 10 9 AN4 — CPS4 C2IN+ — — P1D(1) — SCL SCK — — Y — RC1 9 8 AN5 — CPS5 C12IN1- — — CCP4 P1C(1) — SDA SDI — — Y — RC2 8 7 AN6 — CPS6 C12IN2- — — P1D(1) P2B(1) — SDO1(1) — MDCIN1 Y — RC3 7 6 AN7 — CPS7 C12IN3- — — CCP2(1) P1C(1) P2A(1) — SS1(1) — MDMIN Y — RC4 6 5 — — — C2OUT SRNQ — P1B TX(1) CK(1) — — MDOUT Y — RC5 5 4 — — — — — — CCP1 P1A RX(1) DT(1) — — MDCIN2 Y — VDD 1 16 — — — — — — — — — — — — VDD VSS 14 13 — — — — — — — — — — — — VSS Note 1: EUSART Cap Sense 13 12 A/D RA0 I/O Reference 16-Pin QFN/UQFN 14-Pin PDIP/SOIC/TSSOP TABLE 1: Pin function is selectable via the APFCON0 or APFCON1 register. DS40001440E-page 4  2010-2015 Microchip Technology Inc. PIC16(L)F1825/9 FIGURE 3: 20-PIN DIAGRAM FOR PIC16(L)F1829 PDIP, SOIC, SSOP 20 VSS 2 19 RA0/ICSPDAT RA4 3 18 RA1/ICSPCLK MCLR/VPP/RA3 4 17 RA2 RC5 5 VDD FIGURE 4: RC4 6 RC3 7 RC6 8 RC7 RB7 PIC16(L)F1829 1 RA5 16 RC0 15 RC1 14 RC2 13 RB4 9 12 RB5 10 11 RB6 20-PIN DIAGRAM FOR PIC16(L)F1829 16 ICSPDAT/RA0 VDD Vss 20 19 18 17 RA4 RA5 QFN, UQFN RC6 5  2010-2015 Microchip Technology Inc. RC7 6 RB7 7 RB6 8 RB5 9 RB4 10 15 RA1/ICSPCLK MCLR/VPP/RA3 1 14 RA2 RC5 2 RC4 3 PIC16(L)F1829 13 RC0 12 RC1 RC3 4 11 RC2 DS40001440E-page 5 PIC16(L)F1825/9 20-PIN ALLOCATION TABLE (PIC16(L)F1829) Cap Sense Comparator SR Latch Timers CCP EUSART SSP Interrupt Modulator Pull-up Basic 19 16 AN0 VREFDACOUT CPS0 C1IN+ — — — — — IOC — Y ICSPDAT/ ICDDAT RA1 18 15 AN1 VREF+ CPS1 C12IN0- SRI — — — — IOC — Y ICSPCLK/ ICDCLK RA2 17 14 AN2 — CPS2 C1OUT SRQ T0CKI CCP3 FLT0 — — INT/ IOC — Y — RA3 4 1 — — — — T1G(1) — — — IOC — Y(4) MCLR VPP RA4 3 20 AN3 — CPS3 — — T1G(1) T1OSO P2B(1) — SS2(1) IOC — Y OSC2 CLKOUT CLKR RA5 2 19 — — — — — T1CKI T1OSI CCP2(1) P2A(1) — SDO2(1) IOC — Y OSC1 CLKIN RB4 13 10 AN10 — CPS10 — — — — SDA1 SDI1 IOC — Y — RB5 12 9 AN11 — CPS11 — — — — RX(1) DT(1) SDA2 SDI2 IOC — Y — RB6 11 8 — — — — — — — — SCL1 SCK1 IOC — Y — RB7 10 7 — — — — — — — TX(1) CK(1) SCL2 SCK2 IOC — Y — RC0 16 13 AN4 — CPS4 C2IN+ — — P1D(1) — SS2(1) — — Y — RC1 15 12 AN5 — CPS5 C12IN1- — — P1C(1) — SDO2(1) — — Y — RC2 14 11 AN6 — CPS6 C12IN2- — — P1D(1) P2B(1) — — — MDCIN1 Y — RC3 7 4 AN7 — CPS7 C12IN3- — — P1C(1) CCP2(1) P2A(1) — — — MDMIN Y — RC4 6 3 — — — C2OUT SRNQ — P1B TX(1) CK(1) — — MDOUT Y — RC5 5 2 — — — — — — CCP1 P1A RX(1) DT(1) — — MDCIN2 Y — RC6 8 5 AN8 — CPS8 — — — CCP4 — SS1 — — Y — RC7 9 6 AN9 — CPS9 — — — — — SDO1 — — Y — VDD 1 18 — — — — — — — — — — — — VDD Vss 20 17 — — — — — — — — — — — — VSS Note 1: A/D RA0 I/O Reference 20-Pin QFN/UQFN 20-Pin PDIP/SOIC/SSOP TABLE 2: Pin function is selectable via the APFCON0 or APFCON1 register. DS40001440E-page 6  2010-2015 Microchip Technology Inc. PIC16(L)F1825/9 Table of Contents 1.0 Device Overview .......................................................................................................................................................................... 9 2.0 Enhanced Mid-range CPU ......................................................................................................................................................... 17 3.0 Memory Organization ................................................................................................................................................................. 19 4.0 Device Configuration .................................................................................................................................................................. 47 5.0 Oscillator Module (With Fail-Safe Clock Monitor)....................................................................................................................... 53 6.0 Reference Clock Module ............................................................................................................................................................ 71 7.0 Resets ........................................................................................................................................................................................ 74 8.0 Interrupts .................................................................................................................................................................................... 82 9.0 Power-Down Mode (Sleep) ........................................................................................................................................................ 96 10.0 Watchdog Timer ......................................................................................................................................................................... 98 11.0 Data EEPROM and Flash Program Memory Control ............................................................................................................... 102 12.0 I/O Ports ................................................................................................................................................................................... 116 13.0 Interrupt-on-Change ................................................................................................................................................................. 136 14.0 Fixed Voltage Reference (FVR) ............................................................................................................................................... 141 15.0 Temperature Indicator Module ................................................................................................................................................. 143 16.0 Analog-to-Digital Converter (ADC) Module .............................................................................................................................. 144 17.0 Digital-to-Analog Converter (DAC) Module .............................................................................................................................. 157 18.0 SR Latch................................................................................................................................................................................... 162 19.0 Comparator Module.................................................................................................................................................................. 167 20.0 Timer0 Module ......................................................................................................................................................................... 174 21.0 Timer1 Module with Gate Control............................................................................................................................................. 177 22.0 Timer2/4/6 Modules.................................................................................................................................................................. 188 23.0 Data Signal Modulator.............................................................................................................................................................. 192 24.0 Capture/Compare/PWM Modules ............................................................................................................................................ 201 25.0 Master Synchronous Serial Port (MSSP1 and MSSP2) Module .............................................................................................. 229 26.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) ............................................................... 281 27.0 Capacitive Sensing (CPS) Module ........................................................................................................................................... 309 28.0 In-Circuit Serial Programming™ (ICSP™) ............................................................................................................................... 317 29.0 Instruction Set Summary .......................................................................................................................................................... 320 30.0 Electrical Specifications............................................................................................................................................................ 334 31.0 DC and AC Characteristics Graphs and Charts ....................................................................................................................... 370 32.0 Development Support............................................................................................................................................................... 401 33.0 Packaging Information.............................................................................................................................................................. 405 Appendix A: Data Sheet Revision History.......................................................................................................................................... 432 Appendix B: Migrating From Other PIC® Devices ............................................................................................................................. 432 The Microchip Web Site ..................................................................................................................................................................... 433 Customer Change Notification Service .............................................................................................................................................. 433 Customer Support .............................................................................................................................................................................. 433 Product Identification System ............................................................................................................................................................ 434  2010-2015 Microchip Technology Inc. DS40001440E-page 7 PIC16(L)F1825/9 TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@microchip.com. We welcome your feedback. Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at: http://www.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000000A is version A of document DS30000000). Errata An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: • Microchip’s Worldwide Web site; http://www.microchip.com • Your local Microchip sales office (see last page) When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. DS40001440E-page 8  2010-2015 Microchip Technology Inc. PIC16(L)F1825/9 1.0 DEVICE OVERVIEW The PIC16(L)F1825/9 are described within this data sheet. They are available in 14/20 pin packages. Figure 1-1 shows a block diagram of the PIC16(L)F1825/9 devices. Tables 1-2 and 1-3 show the pinout descriptions. Reference Table 1-1 for peripherals available per device. Peripheral PIC16(L)F1829 DEVICE PERIPHERAL SUMMARY PIC16(L)F1825 TABLE 1-1: ADC ● ● Capacitive Sensing (CPS) Module ● ● Data EEPROM ● ● Digital-to-Analog Converter (DAC) ● ● Digital Signal Modulator (DSM) ● ● EUSART ● ● Fixed Voltage Reference (FVR) ● ● SR Latch ● ● ECCP1 ● ● ECCP2 ● ● CCP3 ● ● CCP4 ● ● C1 ● ● C2 ● ● ● ● Capture/Compare/PWM Modules Comparators Master Synchronous Serial Ports MSSP1 MSSP2 ● Timers Timer0 ● ● Timer1 ● ● Timer2 ● ● Timer4 ● ● Timer6 ● ●  2010-2015 Microchip Technology Inc. DS40001440E-page 9 PIC16(L)F1825/9 FIGURE 1-1: PIC16(L)F1825/9 BLOCK DIAGRAM Program Flash Memory CLKR OSC2/CLKOUT OSC1/CLKIN RAM EEPROM Clock Reference Timing Generation PORTA CPU INTRC Oscillator PORTB(3) (Figure 2-1) MCLR Note PORTC ADC 10-Bit Timer0 Timer1 Timer2 Timer4 Timer6 Comparators SR Latch ECCP1 ECCP2 CCP3 CCP4 MSSP EUSART 1: 2: 3: DS40001440E-page 10 See applicable chapters for more information on peripherals. See Table 1-1 for peripherals available on specific devices. PIC16(L)F1829 only.  2010-2015 Microchip Technology Inc. PIC16(L)F1825/9 TABLE 1-2: PIC16(L)F1825 PINOUT DESCRIPTION Name RA0/AN0/CPS0/C1IN+/VREF-/ DACOUT/TX(1)/CK(1)/ ICSPDAT/ICDDAT RA1/AN1/CPS1/C12IN0-/VREF+/ SRI/RX(1)/DT(1)/ICSPCLK/ ICDCLK RA2/AN2/CPS2/T0CKI/INT/ C1OUT/SRQ/CCP3/FLT0 RA3/SS1(1)/T1G(1)/VPP/MCLR Function Input Type RA0 TTL AN0 AN Output Type Description CMOS General purpose I/O. — A/D Channel 0 input. CPS0 AN — Capacitive sensing input 0. C1IN+ AN — Comparator C1 positive input. VREF- AN — A/D and DAC Negative Voltage Reference input. DACOUT — AN Digital-to-Analog Converter output. TX — CK ST CMOS USART asynchronous transmit. CMOS USART synchronous clock. ICSPDAT ST CMOS ICSP™ Data I/O. ICDDAT ST CMOS In-Circuit Data I/O. RA1 TTL CMOS General purpose I/O. AN1 AN — CPS1 AN — Capacitive sensing input 1. C12IN0- AN — Comparator C1 or C2 negative input. VREF+ AN — A/D and DAC Positive Voltage Reference input. SRI ST — SR Latch input. RX ST — USART asynchronous input. DT ST A/D Channel 1 input. CMOS USART synchronous data. ICSPCLK ST — Serial Programming Clock. ICDCLK ST — In-Circuit Debug Clock. RA2 ST AN2 AN CMOS General purpose I/O. — A/D Channel 2 input. CPS2 AN — Capacitive sensing input 2. T0CKI ST — Timer0 clock input. INT ST — External interrupt. C1OUT — CMOS Comparator C1 output. SRQ — CMOS SR Latch non-inverting output. CCP3 ST CMOS Capture/Compare/PWM3. FLT0 ST — ECCP Auto-Shutdown Fault input. RA3 TTL — General purpose input. SS1 ST — Slave Select input. T1G ST — Timer1 Gate input. VPP HV — Programming voltage. MCLR ST — Master Clear with internal pull-up. Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open Drain TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I2C™ = Schmitt Trigger input with I2C HV = High Voltage XTAL = Crystal levels Note 1: Pin functions can be moved using the APFCON0 or APFCON1 register. 2: Default function location.  2010-2015 Microchip Technology Inc. DS40001440E-page 11 PIC16(L)F1825/9 TABLE 1-2: PIC16(L)F1825 PINOUT DESCRIPTION (CONTINUED) Name RA4/AN3/CPS3/OSC2/ CLKOUT/T1OSO/CLKR/ SDO1(1)/P2B(1)/T1G(1,2) RA5/CLKIN/OSC1/T1OSI/ T1CKI/P2A(1)/CCP2(1) RC0/AN4/CPS4/C2IN+/SCL/ SCK/P1D(1) RC1/AN5/CPS5/C12IN1-/SDA/ SDI/P1C(1)/CCP4 RC2/AN6/CPS6/C12IN2-/ P1D(1,2)/P2B(1,2)/SDO1(1,2)/ MDCIN1 Function Input Type RA4 TTL Output Type Description CMOS General purpose I/O. AN3 AN — A/D Channel 3 input. CPS3 AN — Capacitive sensing input 3. OSC2 — CMOS Comparator C2 output. CLKOUT — CMOS FOSC/4 output. T1OSO XTAL CLKR — XTAL Timer1 oscillator connection. CMOS Clock Reference output. SDO1 — CMOS SPI data output. P2B — CMOS PWM output. T1G ST RA5 TTL — Timer1 Gate input. CLKIN CMOS — External clock input (EC mode). OSC1 XTAL — Crystal/Resonator (LP, XT, HS modes). T1OSI XTAL XTAL T1CKI ST — CMOS General purpose I/O. Timer1 oscillator connection. Timer1 clock input. P2A — CMOS PWM output. CCP2 ST CMOS Capture/Compare/PWM2. RC0 TTL CMOS General purpose I/O. AN4 AN — CPS4 AN — Capacitive sensing input 4. C2IN+ AN — Comparator C2 positive input. SCL I2C OD I2C™ clock. SCK ST P1D — RC1 TTL A/D Channel 4 input. CMOS SPI clock. CMOS PWM output. CMOS General purpose I/O. AN5 AN — CPS5 AN — Capacitive sensing input 5. C12IN1- AN — Comparator C1 or C2 negative input. SDA I2C OD I2C data input/output. SDI CMOS — SPI data input. P1C — CCP4 AN RC2 TTL A/D Channel 5 input. CMOS PWM output. — Capture/Compare/PWM4. CMOS General purpose I/O. AN6 AN — CPS6 AN — A/D Channel 6 input. Capacitive sensing input 6. C12IN2- AN — Comparator C1 or C2 negative input. P1D — CMOS PWM output. P2B — CMOS PWM output. SDO1 — CMOS SPI data output. MDCIN1 ST — Modulator Carrier Input 1. Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open Drain TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I2C™ = Schmitt Trigger input with I2C HV = High Voltage XTAL = Crystal levels Note 1: Pin functions can be moved using the APFCON0 or APFCON1 register. 2: Default function location. DS40001440E-page 12  2010-2015 Microchip Technology Inc. PIC16(L)F1825/9 TABLE 1-2: PIC16(L)F1825 PINOUT DESCRIPTION (CONTINUED) Name RC3/AN7/CPS7/C12IN3-/ P2A(1,2)/CCP2(1,2)/P1C(1,2)/ SS1(1,2)/MDMIN RC4/C2OUT/SRNQ/P1B/TX(1,2)/ CK(1,2)/MDOUT RC5/P1A/CCP1/DT(1,2)/RX(1,2)/ MDCIN2 Function Input Type RC3 TTL Output Type Description CMOS General purpose I/O. AN7 AN — CPS7 AN — A/D Channel 7 input. Capacitive sensing input 7. C12IN3- AN — Comparator C1 or C2 negative input. P2A — CCP2 AN P1C — CMOS PWM output. — Capture/Compare/PWM2. CMOS PWM output. SS1 ST — Slave Select input. MDMIN ST — Modulator source input. RC4 TTL C2OUT — CMOS General purpose I/O. CMOS Comparator C2 output. SRNQ — CMOS SR Latch inverting output. P1B — CMOS PWM output. TX — CMOS USART asynchronous transmit. CK ST CMOS USART synchronous clock. MDOUT — RC5 TTL CMOS Modulator output. CMOS General purpose I/O. P1A — CMOS PWM output. CCP1 ST CMOS Capture/Compare/PWM1. RX ST DT ST — USART asynchronous input. CMOS USART synchronous data. MDCIN2 ST — Modulator Carrier Input 2. VDD VDD Power — Positive supply. VSS VSS Power — Ground reference. Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open Drain TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I2C™ = Schmitt Trigger input with I2C HV = High Voltage XTAL = Crystal levels Note 1: Pin functions can be moved using the APFCON0 or APFCON1 register. 2: Default function location.  2010-2015 Microchip Technology Inc. DS40001440E-page 13 PIC16(L)F1825/9 TABLE 1-3: PIC16(L)F1829 PINOUT DESCRIPTION Name RA0/AN0/CPS0/C1IN+/VREF-/ DACOUT/ICSPDAT/ICDDAT RA1/AN1/CPS1/C12IN0-/VREF+/ SRI/ICSPCLK/ICDCLK RA2/AN2/CPS2/T0CKI/INT/ C1OUT/SRQ/CCP3/FLT0 RA3/T1G(1)/VPP/MCLR RA4/AN3/CPS3/OSC2/ CLKOUT/T1OSO/CLKR/SS2(1)/ P2B(1)/T1G(1,2) Function Input Type RA0 TTL AN0 AN Output Type Description CMOS General purpose I/O. — A/D Channel 0 input. CPS0 AN — Capacitive sensing input 0. C1IN+ AN — Comparator C1 positive input. VREF- AN — A/D and DAC Negative Voltage Reference input. DACOUT — AN Digital-to-Analog Converter output. ICSPDAT ST CMOS ICSP™ Data I/O. ICDDAT ST CMOS In-Circuit Data I/O. RA1 TTL CMOS General purpose I/O. AN1 AN — A/D Channel 1 input. CPS1 AN — Capacitive sensing input 1. C12IN0- AN — Comparator C1 or C2 negative input. VREF+ AN — A/D and DAC Positive Voltage Reference input. SRI ST — SR Latch input. ICSPCLK ST — Serial Programming Clock. ICDCLK ST — In-Circuit Debug Clock. RA2 ST AN2 AN CMOS General purpose I/O. — A/D Channel 2 input. CPS2 AN — Capacitive sensing input 2. T0CKI ST — Timer0 clock input. INT ST — External interrupt. C1OUT — CMOS Comparator C1 output. SRQ — CMOS SR Latch non-inverting output. CCP3 ST CMOS Capture/Compare/PWM3. FLT0 ST — ECCP Auto-Shutdown Fault input. RA3 TTL — General purpose input. T1G ST — Timer1 Gate input. VPP HV — Programming voltage. — Master Clear with internal pull-up. MCLR ST RA4 TTL CMOS General purpose I/O. AN3 AN — A/D Channel 3 input. CPS3 AN — Capacitive sensing input 3. OSC2 — CMOS Comparator C2 output. CLKOUT — CMOS FOSC/4 output. T1OSO XTAL CLKR — SS2 ST P2B — T1G ST XTAL Timer1 oscillator connection. CMOS Clock Reference output. — Slave Select input 2. CMOS PWM output. — Timer1 Gate input. Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open Drain TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I2C™ = Schmitt Trigger input with I2C HV = High Voltage XTAL = Crystal levels Note 1: Pin functions can be moved using the APFCON0 or APFCON1 register. 2: Default function location. DS40001440E-page 14  2010-2015 Microchip Technology Inc. PIC16(L)F1825/9 TABLE 1-3: PIC16(L)F1829 PINOUT DESCRIPTION (CONTINUED) Name RA5/CLKIN/OSC1/T1OSI/ SD02(1)/T1CKI/P2A(1)/CCP2(1) RB4/AN10/CPS10/SDA1/SDI1 RB5/AN11/CPS11/RX DT(1,2)/SDA2/SDI2 (1,2) / RB6/SCL1/SCK1 RB7/TX(1,2)/CK(1,2)/SCL2/SCK2 RC0/AN4/CPS4/C2IN+/P1D(1)/ SS2(1,2) RC1/AN5/CPS5/C12IN1-/P1C(1)/ SD02(1,2) Function Input Type Output Type RA5 TTL CLKIN CMOS — OSC1 XTAL — T1OSI XTAL XTAL SD02 — T1CKI ST P2A — CMOS PWM output. CCP2 ST CMOS Capture/Compare/PWM2. RB4 TTL CMOS General purpose I/O. Description CMOS General purpose I/O. External clock input (EC mode). Crystal/Resonator (LP, XT, HS modes). Timer1 oscillator connection. CMOS SPI data output 2. — Timer1 clock input. AN10 AN — A/D Channel 10 input. CPS10 AN — Capacitive sensing input 10. SDA1 I2C OD I2C™ data input/output. SDI1 CMOS — SPI data input. RB5 TTL AN11 AN — A/D Channel 11 input. CPS11 AN — Capacitive sensing input 11. RX ST — USART asynchronous input. DT ST SDA2 I2C SDI2 CMOS RB6 TTL SCL1 I2C CMOS General purpose I/O. CMOS USART synchronous data. OD I2C data input/output 2. — SPI data input 2. CMOS General purpose I/O. OD I2C™ clock 1. SCK1 ST CMOS SPI clock 1. RB7 TTL CMOS General purpose I/O. TX — CMOS USART asynchronous transmit. CK ST CMOS USART synchronous clock. SCL2 I2C OD I2C™ clock 2. SCK2 ST CMOS SPI clock 2. RC0 TTL CMOS General purpose I/O. AN4 AN — CPS4 AN — Capacitive sensing input 4. C2IN+ AN — Comparator C2 positive input. P1D — SS2 ST RC1 TTL A/D Channel 4 input. CMOS PWM output. — Slave Select input 2. CMOS General purpose I/O. AN5 AN — A/D Channel 5 input. CPS5 AN — Capacitive sensing input 5. C12IN1- AN — Comparator C1 or C2 negative input. P1C — CMOS PWM output. SDO2 — CMOS SPI data output 2. Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open Drain TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I2C™ = Schmitt Trigger input with I2C HV = High Voltage XTAL = Crystal levels Note 1: Pin functions can be moved using the APFCON0 or APFCON1 register. 2: Default function location.  2010-2015 Microchip Technology Inc. DS40001440E-page 15 PIC16(L)F1825/9 TABLE 1-3: PIC16(L)F1829 PINOUT DESCRIPTION (CONTINUED) Name RC2/AN6/CPS6/C12IN2-/ P1D(1,2)/P2B(1,2)/MDCIN1 RC3/AN7/CPS7/C12IN3-/ P2A(1,2)/CCP2(1,2)/P1C(1,2)/ MDMIN RC4/C2OUT/SRNQ/P1B/TX(1)/ CK(1)/MDOUT RC5/P1A/CCP1/DT(1)/RX(1)/ MDCIN2 RC6/AN8/CPS8/CCP4/SS1 Function Input Type RC2 TTL Output Type Description CMOS General purpose I/O. AN6 AN — CPS6 AN — Capacitive sensing input 6. C12IN2- AN — Comparator C1 or C2 negative input. P1D — CMOS PWM output. CMOS PWM output. P2B — MDCIN1 ST RC3 TTL AN7 AN — A/D Channel 6 input. Modulator Carrier Input 1. CMOS General purpose I/O. — A/D Channel 7 input. CPS7 AN — Capacitive sensing input 7. C12IN3- AN — Comparator C1 or C2 negative input. P2A — CCP2 AN CMOS PWM output. — Capture/Compare/PWM2. P1C — MDMIN ST RC4 TTL C2OUT — CMOS Comparator C2 output. SRNQ — CMOS SR Latch inverting output. P1B — CMOS PWM output. TX — CMOS USART asynchronous transmit. CK ST CMOS USART synchronous clock. MDOUT — RC5 TTL CMOS PWM output. — Modulator source input. CMOS General purpose I/O. CMOS Modulator output. CMOS General purpose I/O. P1A — CMOS PWM output. CCP1 ST CMOS Capture/Compare/PWM1. RX ST DT ST MDCIN2 ST RC6 TTL — USART asynchronous input. CMOS USART synchronous data. — Modulator Carrier Input 2. CMOS General purpose I/O. AN8 AN — CPS8 AN — Capacitive sensing input 8. CCP4 AN — Capture/Compare/PWM4. SS1 ST — Slave Select input. RC7 TTL AN9 AN — A/D Channel 9 input. CPS9 AN — Capacitive sensing input 9. SDO1 — VDD VDD Power — Positive supply. VSS VSS Power — Ground reference. RC7/AN9/CPS9/SDO1 A/D Channel 8 input. CMOS General purpose I/O. CMOS SPI data output. Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open Drain TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I2C™ = Schmitt Trigger input with I2C HV = High Voltage XTAL = Crystal levels Note 1: Pin functions can be moved using the APFCON0 or APFCON1 register. 2: Default function location. DS40001440E-page 16  2010-2015 Microchip Technology Inc. PIC16(L)F1825/9 2.0 ENHANCED MID-RANGE CPU This family of devices contain an enhanced mid-range 8-bit CPU core. The CPU has 49 instructions. Interrupt capability includes automatic context saving. The hardware stack is 16 levels deep and has Overflow and Underflow Reset capability. Direct, Indirect, and Relative Addressing modes are available. Two File Select Registers (FSRs) provide the ability to read program and data memory. • • • • Automatic Interrupt Context Saving 16-level Stack with Overflow and Underflow File Select Registers Instruction Set 2.1 Automatic Interrupt Context Saving During interrupts, certain registers are automatically saved in shadow registers and restored when returning from the interrupt. This saves stack space and user code. See Section 8.5 “Automatic Context Saving”, for more information. 2.2 16-level Stack with Overflow and Underflow These devices have an external stack memory 15 bits wide and 16 words deep. A Stack Overflow or Underflow will set the appropriate bit (STKOVF or STKUNF) in the PCON register, and if enabled will cause a software Reset. See section Section 3.4 “Stack” for more details. 2.3 File Select Registers There are two 16-bit File Select Registers (FSR). FSRs can access all file registers and program memory, which allows one Data Pointer for all memory. When an FSR points to program memory, there is one additional instruction cycle in instructions using INDF to allow the data to be fetched. General purpose memory can now also be addressed linearly, providing the ability to access contiguous data larger than 80 bytes. There are also new instructions to support the FSRs. See Section 3.5 “Indirect Addressing” for more details. 2.4 Instruction Set There are 49 instructions for the enhanced mid-range CPU to support the features of the CPU. See Section 29.0 “Instruction Set Summary” for more details.  2010-2015 Microchip Technology Inc. DS40001440E-page 17 PIC16(L)F1825/9 FIGURE 2-1: CORE BLOCK DIAGRAM 15 Configuration 15 MUX Flash Program Memory Program Bus 16-Level 8 Level Stack Stack (15-bit) (13-bit) 14 Instruction Instruction Reg reg 8 Data Bus Program Counter RAM Program Memory Read (PMR) 12 RAM Addr Addr MUX Indirect Addr 12 12 Direct Addr 7 5 BSR FSR Reg reg 15 FSR0reg Reg FSR FSR1 Reg FSR reg 15 STATUS Reg reg STATUS 8 3 Power-up Timer OSC1/CLKIN OSC2/CLKOUT Instruction Decodeand & Decode Control Timing Generation Oscillator Start-up Timer Power-on Reset Watchdog Timer Brown-out Reset MUX ALU 8 W Reg Internal Oscillator Block VDD DS40001440E-page 18 VSS  2010-2015 Microchip Technology Inc. PIC16(L)F1825/9 3.0 MEMORY ORGANIZATION These devices contain the following types of memory: • Program Memory - Configuration Words - Device ID - User ID - Flash Program Memory • Data Memory - Core Registers - Special Function Registers - General Purpose RAM - Common RAM • Data EEPROM memory(1) The following features are associated with access and control of program memory and data memory: • PCL and PCLATH • Stack • Indirect Addressing 3.1 Program Memory Organization The enhanced mid-range core has a 15-bit program counter capable of addressing 32K x 14 program memory space. Table 3-1 shows the memory sizes implemented for the PIC16(L)F1825/9 family. Accessing a location above these boundaries will cause a wrap-around within the implemented memory space. The Reset vector is at 0000h and the interrupt vector is at 0004h (See Figure 3-1). Note 1: The Data EEPROM Memory and the method to access Flash memory through the EECON registers is described in Section 11.0 “Data EEPROM and Flash Program Memory Control”. TABLE 3-1: DEVICE SIZES AND ADDRESSES Device PIC16(L)F1825 PIC16(L)F1829  2010-2015 Microchip Technology Inc. Program Memory Space (Words) Last Program Memory Address 8,192 7FFFh DS40001440E-page 19 PIC16(L)F1825/9 FIGURE 3-1: PROGRAM MEMORY MAP AND STACK FOR PIC16(L)F1825/9 PC CALL, CALLW RETURN, RETLW Interrupt, RETFIE 15 RETLW Instruction Stack Level 0 Stack Level 1 The RETLW instruction can be used to provide access to tables of constants. The recommended way to create such a table is shown in Example 3-1. Stack Level 15 EXAMPLE 3-1: 0000h Interrupt Vector 0004h 0005h Page 0 07FFh 0800h Page 1 0FFFh 1000h Page 2 Page 3 Rollover to Page 0 Rollover to Page 3 DS40001440E-page 20 READING PROGRAM MEMORY AS DATA There are two methods of accessing constants in program memory. The first method is to use tables of RETLW instructions. The second method is to set an FSR to point to the program memory. 3.1.1.1 Reset Vector On-chip Program Memory 3.1.1 17FFh 1800h 1FFFh 2000h constants BRW RETLW RETLW RETLW RETLW DATA0 DATA1 DATA2 DATA3 RETLW INSTRUCTION ;Add Index in W to ;program counter to ;select data ;Index0 data ;Index1 data my_function ;… LOTS OF CODE… MOVLW DATA_INDEX call constants ;… THE CONSTANT IS IN W The BRW instruction makes this type of table very simple to implement. If your code must remain portable with previous generations of microcontrollers, then the BRW instruction is not available so the older table read method must be used. 7FFFh  2010-2015 Microchip Technology Inc. PIC16(L)F1825/9 3.1.1.2 Indirect Read with FSR The program memory can be accessed as data by setting bit 7 of the FSRxH register and reading the matching INDFx register. The MOVIW instruction will place the lower eight bits of the addressed word in the W register. Writes to the program memory cannot be performed via the INDF registers. Instructions that access the program memory via the FSR require one extra instruction cycle to complete. Example 3-2 demonstrates accessing the program memory via an FSR. The High directive will set bit if a label points to a location in program memory. EXAMPLE 3-2: ACCESSING PROGRAM MEMORY VIA FSR constants RETLW DATA0 ;Index0 data RETLW DATA1 ;Index1 data RETLW DATA2 RETLW DATA3 my_function ;… LOTS OF CODE… MOVLW LOW constants MOVWF FSR1L MOVLW HIGH constants MOVWF FSR1H MOVIW 0[FSR1] ;THE PROGRAM MEMORY IS IN W 3.2 3.2.1 CORE REGISTERS The core registers contain the registers that directly affect the basic operation of the PIC16(L)F1825/9. These registers are listed below: • • • • • • • • • • • • INDF0 INDF1 PCL STATUS FSR0 Low FSR0 High FSR1 Low FSR1 High BSR WREG PCLATH INTCON Note: The core registers are the first 12 addresses of every data memory bank. Data Memory Organization The data memory is partitioned in 32 memory banks with 128 bytes in a bank. Each bank consists of (Figure 3-2): • • • • 12 core registers 20 Special Function Registers (SFR) Up to 80 bytes of General Purpose RAM (GPR) 16 bytes of common RAM The active bank is selected by writing the bank number into the Bank Select Register (BSR). Unimplemented memory will read as ‘0’. All data memory can be accessed either directly (via instructions that use the file registers) or indirectly via the two File Select Registers (FSR). See Section 3.5 “Indirect Addressing” for more information. Data Memory uses a 12-bit address. The upper seven bits of the address define the Bank address and the lower five bits select the registers/RAM in that bank.  2010-2015 Microchip Technology Inc. DS40001440E-page 21 PIC16(L)F1825/9 3.2.1.1 STATUS Register The STATUS register, shown in Register 3-1, contains: • the arithmetic status of the ALU • the Reset status The STATUS register can be the destination for any instruction, like any other register. If the STATUS register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. These bits are set or cleared according to the device logic. Furthermore, the TO and PD bits are not writable. Therefore, the result of an instruction with the STATUS register as destination may be different than intended. REGISTER 3-1: U-0 It is recommended, therefore, that only BCF, BSF, SWAPF and MOVWF instructions are used to alter the STATUS register, because these instructions do not affect any Status bits. For other instructions not affecting any Status bits (Refer to Section 29.0 “Instruction Set Summary”). Note 1: The C and DC bits operate as Borrow and Digit Borrow out bits, respectively, in subtraction. STATUS: STATUS REGISTER U-0 — For example, CLRF STATUS will clear the upper three bits and set the Z bit. This leaves the STATUS register as ‘000u u1uu’ (where u = unchanged). — U-0 R-1/q R-1/q R/W-0/u R/W-0/u R/W-0/u — TO PD Z DC(1) C(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition bit 7-5 Unimplemented: Read as ‘0’ bit 4 TO: Time-out bit 1 = After power-up, CLRWDT instruction or SLEEP instruction 0 = A WDT time-out occurred bit 3 PD: Power-down bit 1 = After power-up or by the CLRWDT instruction 0 = By execution of the SLEEP instruction bit 2 Z: Zero bit 1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero bit 1 DC: Digit Carry/Digit Borrow bit (ADDWF, ADDLW, SUBLW, SUBWF instructions)(1) 1 = A carry-out from the 4th low-order bit of the result occurred 0 = No carry-out from the 4th low-order bit of the result bit 0 C: Carry/Borrow bit(1) (ADDWF, ADDLW, SUBLW, SUBWF instructions)(1) 1 = A carry-out from the Most Significant bit of the result occurred 0 = No carry-out from the Most Significant bit of the result occurred Note 1: For Borrow, the polarity is reversed. A subtraction is executed by adding the two’s complement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high-order or low-order bit of the source register. DS40001440E-page 22  2010-2015 Microchip Technology Inc. PIC16(L)F1825/9 3.2.2 SPECIAL FUNCTION REGISTER The Special Function Registers (FSR) are registers used by the application to control the desired operation of peripheral functions in the device. The Special Function Registers occupy the 20 bytes after the core registers of every data memory bank (addresses x0Ch/x8Ch through x1Fh/x9Fh). The registers associated with the operation of the peripherals are described in the appropriate peripheral chapter of this data sheet. 3.2.3 FIGURE 3-2: 7-bit Bank Offset 0Bh 0Ch GENERAL PURPOSE RAM Core Registers (12 bytes) Special Function Registers (20 bytes maximum) 1Fh 20h Linear Access to GPR The general purpose RAM can be accessed in a non-banked method via the FSRs. This can simplify access to large memory structures. See Section 3.5.2 “Linear Data Memory” for more information. 3.2.4 Memory Region 00h There are up to 80 bytes of GPR in each data memory bank. The Special Function Registers occupy the 20 bytes after the core registers of every data memory bank (addresses x0Ch/x8Ch through x1Fh/x9Fh). 3.2.3.1 BANKED MEMORY PARTITIONING General Purpose RAM (80 bytes maximum) COMMON RAM There are 16 bytes of common RAM accessible from all banks. 6Fh 70h Common RAM (16 bytes) 7Fh 3.2.5 DEVICE MEMORY MAPS The memory maps for the device family are as shown in Table 3-2. TABLE 3-2: MEMORY MAP TABLES Device PIC16(L)F1825 PIC16(L)F1829  2010-2015 Microchip Technology Inc. Banks Table No. 0-7 Table 3-3 8-15 Table 3-4 16-23 Table 3-5 24-31 Table 3-6 31 Table 3-7 DS40001440E-page 23 PIC16(L)F1825/9 MEMORY MAP, BANKS 0-7 BANK 0 BANK 1 BANK 2 BANK 3 BANK 4 BANK 5 280h 281h 282h 283h 284h 285h 286h 287h 288h 289h 28Ah 28Bh 28Ch 28Dh 28Eh 28Fh 290h 291h 292h 293h 294h 295h 296h 297h 298h INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON — — — — — CCPR1L CCPR1H CCP1CON PWM1CON CCP1AS PSTR1CON — CCPR2L BANK 6 300h 301h 302h 303h 304h 305h 306h 307h 308h 309h 30Ah 30Bh 30Ch 30Dh 30Eh 30Fh 310h 311h 312h 313h 314h 315h 316h 317h 318h INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON — — — — — CCPR3L CCPR3H CCP3CON — — — — CCPR4L BANK 7 000h 001h 002h 003h 004h 005h 006h 007h 008h 009h 00Ah 00Bh 00Ch 00Dh 00Eh 00Fh 010h 011h 012h 013h 014h 015h 016h 017h 018h INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON PORTA PORTB(1) PORTC — — PIR1 PIR2 PIR3 PIR4(1) TMR0 TMR1L TMR1H T1CON 080h 081h 082h 083h 084h 085h 086h 087h 088h 089h 08Ah 08Bh 08Ch 08Dh 08Eh 08Fh 090h 091h 092h 093h 094h 095h 096h 097h 098h INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON TRISA TRISB(1) TRISC — — PIE1 PIE2 PIE3 PIE4(1) OPTION_REG PCON WDTCON OSCTUNE 100h 101h 102h 103h 104h 105h 106h 107h 108h 109h 10Ah 10Bh 10Ch 10Dh 10Eh 10Fh 110h 111h 112h 113h 114h 115h 116h 117h 118h INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON LATA LATB(1) LATC — — CM1CON0 CM1CON1 CM2CON0 CM2CON1 CMOUT BORCON FVRCON DACCON0 180h 181h 182h 183h 184h 185h 186h 187h 188h 189h 18Ah 18Bh 18Ch 18Dh 18Eh 18Fh 190h 191h 192h 193h 194h 195h 196h 197h 198h INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON ANSELA ANSELB(1) ANSELC — — EEADRL EEADRH EEDATL EEDATH EECON1 EECON2 — — 200h 201h 202h 203h 204h 205h 206h 207h 208h 209h 20Ah 20Bh 20Ch 20Dh 20Eh 20Fh 210h 211h 212h 213h 214h 215h 216h 217h 218h INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON WPUA WPUB(1) WPUC — — SSP1BUF SSP1ADD SSP1MSK SSP1STAT SSP1CON1 SSP1CON2 SSP1CON3 — 380h 381h 382h 383h 384h 385h 386h 387h 388h 389h 38Ah 38Bh 38Ch 38Dh 38Eh 38Fh 390h 391h 392h 393h 394h 395h 396h 397h 398h INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON INLVLA INLVLB(1) INLVLC — — IOCAP IOCAN IOCAF 019h T1GCON 099h OSCCON 119h DACCON1 199h RCREG 219h SSP2BUF(1) 299h CCPR2H 319h CCPR4H 399h — 01Ah TMR2 09Ah OSCSTAT 11Ah SRCON0 19Ah TXREG 21Ah SSP2ADD(1) 29Ah CCP2CON 31Ah CCP4CON 39Ah CLKRCON IOCBP(1) IOCBN(1) IOCBF(1) — —  2010-2015 Microchip Technology Inc. 01Bh PR2 09Bh ADRESL 11Bh SRCON1 19Bh SPBRGL 21Bh SSP2MSK(1) 29Bh PWM2CON 31Bh — 39Bh — 01Ch T2CON 09Ch ADRESH 11Ch — 19Ch SPBRGH 21Ch SSP2STAT(1) 29Ch CCP2AS 31Ch — 39Ch MDCON 01Dh — 09Dh ADCON0 11Dh APFCON0 19Dh RCSTA 21Dh SSP2CON1(1) 29Dh PSTR2CON 31Dh — 39Dh MDSRC 01Eh CPSCON0 09Eh ADCON1 11Eh APFCON1 19Eh TXSTA 21Eh SSP2CON2(1) 29Eh CCPTMRS 31Eh — 39Eh MDCARL 01Fh 020h CPSCON1 09Fh 0A0h — 11Fh 120h — 19Fh 1A0h BAUDCON 21Fh 220h SSP2CON3(1) 29Fh 2A0h — 31Fh 320h — 39Fh 3A0h MDCARH General Purpose Register 96 Bytes 06Fh 070h General Purpose Register 80 Bytes 0EFh 0F0h 07Fh Note 1: 16Fh 170h Accesses 70h – 7Fh Common RAM Legend: General Purpose Register 80 Bytes 0FFh 1EFh 1F0h Accesses 70h – 7Fh 17Fh = Unimplemented data memory locations, read as ‘0’ Available only on PIC16(L)F1829. General Purpose Register 80 Bytes General Purpose Register 80 Bytes 26Fh 270h Accesses 70h – 7Fh 1FFh General Purpose Register 80 Bytes 27Fh Accesses 70h – 7Fh 2FFh General Purpose Register 80 Bytes 3EFh 3F0h 36Fh 370h 2EFh 2F0h Accesses 70h – 7Fh General Purpose Register 80 Bytes Accesses 70h – 7Fh 37Fh Accesses 70h – 7Fh 3FFh PIC16(L)F1825/9 DS40001440E-page 24 TABLE 3-3:  2010-2015 Microchip Technology Inc. TABLE 3-4: PIC16(L)F1825/9 MEMORY MAP, BANKS 8-15 BANK 8 INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON — — — — — — — — — TMR4 PR4 T4CON — — — — TMR6 PR6 T6CON — BANK 9 480h 481h 482h 483h 484h 485h 486h 487h 488h 489h 48Ah 48Bh 48Ch 48Dh 48Eh 48Fh 490h 491h 492h 493h 494h 495h 496h 497h 498h 499h 49Ah 49Bh 49Ch 49Dh 49Eh 49Fh 4A0h General Purpose Register 80 Bytes 46Fh 470h DS40001440E-page 25 Legend: BANK 10 500h 501h 502h 503h 504h 505h 506h 507h 508h 509h 50Ah 50Bh 50Ch 50Dh 50Eh 50Fh 510h 511h 512h 513h 514h 515h 516h 517h 518h 519h 51Ah 51Bh 51Ch 51Dh 51Eh 51Fh 520h General Purpose Register 80 Bytes 4EFh 4F0h Accesses 70h – 7Fh 47Fh INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON — — — — — — — — — — — — — — — — — — — — BANK 11 580h 581h 582h 583h 584h 585h 586h 587h 588h 589h 58Ah 58Bh 58Ch 58Dh 58Eh 58Fh 590h 591h 592h 593h 594h 595h 596h 597h 598h 599h 59Ah 59Bh 59Ch 59Dh 59Eh 59Fh 5A0h General Purpose Register 80 Bytes 56Fh 570h Accesses 70h – 7Fh 4FFh INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON — — — — — — — — — — — — — — — — — — — — INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON — — — — — — — — — — — — — — — — — — — — General Purpose Register 80 Bytes 5EFh 5F0h Accesses 70h – 7Fh 57Fh = Unimplemented data memory locations, read as ‘0’ BANK 12 600h INDF0 601h INDF1 602h PCL 603h STATUS 604h FSR0L 605h FSR0H 606h FSR1L 607h FSR1H 608h BSR 609h WREG 60Ah PCLATH 60Bh INTCON 60Ch — 60Dh — 60Eh — 60Fh — 610h — 611h — 612h — 613h — 614h — 615h — 616h — 617h — 618h — 619h — 61Ah — 61Bh — 61Ch — 61Dh — 61Eh — 61Fh — 620h General Purpose Register 48 Bytes 64Fh 650h Unimplemented Read as ‘0’ 66Fh 670h Accesses 70h – 7Fh 5FFh BANK 13 680h 681h 682h 683h 684h 685h 686h 687h 688h 689h 68Ah 68Bh 68Ch 68Dh 68Eh 68Fh 690h 691h 692h 693h 694h 695h 696h 697h 698h 699h 69Ah 69Bh 69Ch 69Dh 69Eh 69Fh 6A0h BANK 14 700h 701h 702h 703h 704h 705h 706h 707h 708h 709h 70Ah 70Bh 70Ch 70Dh 70Eh 70Fh 710h 711h 712h 713h 714h 715h 716h 717h 718h 719h 71Ah 71Bh 71Ch 71Dh 71Eh 71Fh 720h Unimplemented Read as ‘0’ 6EFh 6F0h Accesses 70h – 7Fh 67Fh INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON — — — — — — — — — — — — — — — — — — — — BANK 15 780h 781h 782h 783h 784h 785h 786h 787h 788h 789h 78Ah 78Bh 78Ch 78Dh 78Eh 78Fh 790h 791h 792h 793h 794h 795h 796h 797h 798h 799h 79Ah 79Bh 79Ch 79Dh 79Eh 79Fh 7A0h Unimplemented Read as ‘0’ 76Fh 770h Accesses 70h – 7Fh 6FFh INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON — — — — — — — — — — — — — — — — — — — — Unimplemented Read as ‘0’ 7EFh 7F0h Accesses 70h – 7Fh 77Fh INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON — — — — — — — — — — — — — — — — — — — — Accesses 70h – 7Fh 7FFh PIC16(L)F1825/9 400h 401h 402h 403h 404h 405h 406h 407h 408h 409h 40Ah 40Bh 40Ch 40Dh 40Eh 40Fh 410h 411h 412h 413h 414h 415h 416h 417h 418h 419h 41Ah 41Bh 41Ch 41Dh 41Eh 41Fh 420h PIC16(L)F1825/9 MEMORY MAP, BANKS 16-23 BANK 16  2010-2015 Microchip Technology Inc. 800h 801h 802h 803h 804h 805h 806h 807h 808h 809h 80Ah 80Bh 80Ch 80Dh 80Eh 80Fh 810h 811h 812h 813h 814h 815h 816h 817h 818h 819h 81Ah 81Bh 81Ch 81Dh 81Eh 81Fh 820h INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON — — — — — — — — — — — — — — — — — — — — BANK 17 880h 881h 882h 883h 884h 885h 886h 887h 888h 889h 88Ah 88Bh 88Ch 88Dh 88Eh 88Fh 890h 891h 892h 893h 894h 895h 896h 897h 898h 899h 89Ah 89Bh 89Ch 89Dh 89Eh 89Fh 8A0h Unimplemented Read as ‘0’ 86Fh 870h Legend: BANK 18 900h 901h 902h 903h 904h 905h 906h 907h 908h 909h 90Ah 90Bh 90Ch 90Dh 90Eh 90Fh 910h 911h 912h 913h 914h 915h 916h 917h 918h 919h 91Ah 91Bh 91Ch 91Dh 91Eh 91Fh 920h Unimplemented Read as ‘0’ 8EFh 8F0h 8FFh INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON — — — — — — — — — — — — — — — — — — — — BANK 19 980h 981h 982h 983h 984h 985h 986h 987h 988h 989h 98Ah 98Bh 98Ch 98Dh 98Eh 98Fh 990h 991h 992h 993h 994h 995h 996h 997h 998h 999h 99Ah 99Bh 99Ch 99Dh 99Eh 99Fh 9A0h Unimplemented Read as ‘0’ INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON — — — — — — — — — — — — — — — — — — — — Accesses 70h – 7Fh 97Fh = Unimplemented data memory locations, read as ‘0’. BANK 20 A00h A01h A02h A03h A04h A05h A06h A07h A08h A09h A0Ah A0Bh A0Ch A0Dh A0Eh A0Fh A10h A11h A12h A13h A14h A15h A16h A17h A18h A19h A1Ah A1Bh A1Ch A1Dh A1Eh A1Fh A20h Unimplemented Read as ‘0’ 9EFh 9F0h 96Fh 970h Accesses 70h – 7Fh Accesses 70h – 7Fh 87Fh INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON — — — — — — — — — — — — — — — — — — — — BANK 21 A80h A81h A82h A83h A84h A85h A86h A87h A88h A89h A8Ah A8Bh A8Ch A8Dh A8Eh A8Fh A90h A91h A92h A93h A94h A95h A96h A97h A98h A99h A9Ah A9Bh A9Ch A9Dh A9Eh A9Fh AA0h Unimplemented Read as ‘0’ BANK 22 B00h B01h B02h B03h B04h B05h B06h B07h B08h B09h B0Ah B0Bh B0Ch B0Dh B0Eh B0Fh B10h B11h B12h B13h B14h B15h B16h B17h B18h B19h B1Ah B1Bh B1Ch B1Dh B1Eh B1Fh B20h Unimplemented Read as ‘0’ Accesses 70h – 7Fh A7Fh INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON — — — — — — — — — — — — — — — — — — — — AEFh AF0h A6Fh A70h Accesses 70h – 7Fh 9FFh INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON — — — — — — — — — — — — — — — — — — — — BANK 23 B80h B81h B82h B83h B84h B85h B86h B87h B88h B89h B8Ah B8Bh B8Ch B8Dh B8Eh B8Fh B90h B91h B92h B93h B94h B95h B96h B97h B98h B99h B9Ah B9Bh B9Ch B9Dh B9Eh B9Fh BA0h Unimplemented Read as ‘0’ Unimplemented Read as ‘0’ Accesses 70h – 7Fh B7Fh INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON — — — — — — — — — — — — — — — — — — — — BEFh BF0h B6Fh B70h Accesses 70h – 7Fh AFFh INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON — — — — — — — — — — — — — — — — — — — — Accesses 70h – 7Fh BFFh PIC16(L)F1825/9 DS40001440E-page 26 TABLE 3-5:  2010-2015 Microchip Technology Inc. TABLE 3-6: PIC16(L)F1825/9 MEMORY MAP, BANKS 24-31 BANK 24 INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON — — — — — — — — — — — — — — — — — — — — BANK 25 C80h C81h C82h C83h C84h C85h C86h C87h C88h C89h C8Ah C8Bh C8Ch C8Dh C8Eh C8Fh C90h C91h C92h C93h C94h C95h C96h C97h C98h C99h C9Ah C9Bh C9Ch C9Dh C9Eh C9Fh CA0h Unimplemented Read as ‘0’ DS40001440E-page 27 C6Fh C70h CFFh BANK 26 D00h D01h D02h D03h D04h D05h D06h D07h D08h D09h D0Ah D0Bh D0Ch D0Dh D0Eh D0Fh D10h D11h D12h D13h D14h D15h D16h D17h D18h D19h D1Ah D1Bh D1Ch D1Dh D1Eh D1Fh D20h Unimplemented Read as ‘0’ CEFh CF0h Accesses 70h – 7Fh Legend: INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON — — — — — — — — — — — — — — — — — — — — BANK 27 D80h D81h D82h D83h D84h D85h D86h D87h D88h D89h D8Ah D8Bh D8Ch D8Dh D8Eh D8Fh D90h D91h D92h D93h D94h D95h D96h D97h D98h D99h D9Ah D9Bh D9Ch D9Dh D9Eh D9Fh DA0h Unimplemented Read as ‘0’ D6Fh D70h Accesses 70h – 7Fh CFFh INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON — — — — — — — — — — — — — — — — — — — — INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON — — — — — — — — — — — — — — — — — — — — Unimplemented Read as ‘0’ DEFh DF0h Accesses 70h – 7Fh D7Fh = Unimplemented data memory locations, read as ‘0’. BANK 28 E00h E01h E02h E03h E04h E05h E06h E07h E08h E09h E0Ah E0Bh E0Ch E0Dh E0Eh E0Fh E10h E11h E12h E13h E14h E15h E16h E17h E18h E19h E1Ah E1Bh E1Ch E1Dh E1Eh E1Fh E20h BANK 29 E80h E81h E82h E83h E84h E85h E86h E87h E88h E89h E8Ah E8Bh E8Ch E8Dh E8Eh E8Fh E90h E91h E92h E93h E94h E95h E96h E97h E98h E99h E9Ah E9Bh E9Ch E9Dh E9Eh E9Fh EA0h Unimplemented Read as ‘0’ E6Fh E70h Accesses 70h – 7Fh DFFh INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON — — — — — — — — — — — — — — — — — — — — BANK 30 F00h F01h F02h F03h F04h F05h F06h F07h F08h F09h F0Ah F0Bh F0Ch F0Dh F0Eh F0Fh F10h F11h F12h F13h F14h F15h F16h F17h F18h F19h F1Ah F1Bh F1Ch F1Dh F1Eh F1Fh F20h Unimplemented Read as ‘0’ EEFh EF0h Accesses 70h – 7Fh E7Fh INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON — — — — — — — — — — — — — — — — — — — — BANK 31 F80h INDF0 F81h INDF1 F82h PCL F83h STATUS F84h FSR0L F85h FSR0H F86h FSR1L F87h FSR1H F88h BSR F89h WREG F8Ah PCLATH F8Bh INTCON F8Ch F8Dh F8Eh F8Fh F90h F91h F92h F93h F94h F95h F96h F97h See Table 3-7 for F98h register mapping F99h details F9Ah F9Bh F9Ch F9Dh F9Eh F9Fh FA0h Unimplemented Read as ‘0’ F6Fh F70h Accesses 70h – 7Fh EFFh INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON — — — — — — — — — — — — — — — — — — — — FEFh FF0h Accesses 70h – 7Fh F7Fh Accesses 70h – 7Fh FFFh PIC16(L)F1825/9 C00h C01h C02h C03h C04h C05h C06h C07h C08h C09h C0Ah C0Bh C0Ch C0Dh C0Eh C0Fh C10h C11h C12h C13h C14h C15h C16h C17h C18h C19h C1Ah C1Bh C1Ch C1Dh C1Eh C1Fh C20h PIC16(L)F1825/9 TABLE 3-7: PIC16(L)F1825/9 MEMORY MAP, BANK 31 Bank 31(1) F8Ch Unimplemented Read as ‘0’ FE3h FE4h FE5h FE6h FE7h FE8h FE9h FEAh FEBh FECh FEDh FEEh FEFh Legend: STATUS_SHAD WREG_SHAD BSR_SHAD PCLATH_SHAD FSR0L_SHAD FSR0H_SHAD FSR1L_SHAD FSR1H_SHAD — STKPTR TOSL TOSH 3.2.6 SPECIAL FUNCTION REGISTERS SUMMARY The Special Function Register summary for the device family are as follows: Device PIC16(L)F1825 PIC16(L)F1829 Bank(s) Page No. 0 29 1 30 2 31 3 32 4 33 5 34 6 35 7 36 8 37 9-30 38 31 39 = Unimplemented data memory locations, read as ‘0’. DS40001440E-page 28  2010-2015 Microchip Technology Inc. PIC16(L)F1825/9 TABLE 3-8: Address Name SPECIAL FUNCTION REGISTER SUMMARY Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets Bank 0 000h(1) INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory (not a physical register) xxxx xxxx xxxx xxxx 001h(1) INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory (not a physical register) xxxx xxxx xxxx xxxx 002h(1) PCL Program Counter (PC) Least Significant Byte 003h(1) STATUS 004h(1) FSR0L Indirect Data Memory Address 0 Low Pointer 0000 0000 uuuu uuuu 005h(1) FSR0H Indirect Data Memory Address 0 High Pointer 0000 0000 0000 0000 006h(1) FSR1L Indirect Data Memory Address 1 Low Pointer 0000 0000 uuuu uuuu 007h(1) FSR1H Indirect Data Memory Address 1 High Pointer 008h(1) BSR 009h(1) WREG 00Ah(1) PCLATH — 00Bh(1) INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 0000 0000 0000 0000 00Ch PORTA — — RA5 RA4 RA3 RA2 RA1 RA0 --xx xxxx --xx xxxx 00Dh PORTB(2) 00Eh PORTC 00Fh — Unimplemented — — 010h — Unimplemented — — 011h PIR1 TMR1GIF ADIF 012h PIR2 OSFIF C2IF C1IF 013h PIR3 — — CCP4IF 014h PIR4(2) — — — — 015h TMR0 Timer0 Module Register xxxx xxxx uuuu uuuu 016h TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu 017h TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register 018h T1CON TMR1CS1 TMR1CS0 019h T1GCON TMR1GE T1GPOL 01Ah TMR2 Timer2 Module Register 01Bh PR2 Timer2 Period Register 01Ch T2CON — — — — — 0000 0000 0000 0000 TO C ---1 1000 ---q quuu ---0 0000 ---0 0000 Working Register 0000 0000 uuuu uuuu Write Buffer for the upper 7 bits of the Program Counter -000 0000 -000 0000 RB7 RB6 RB5 RB4 — — — — xxxx ---- xxxx ---- RC7(2) RC6(2) RC5 RC4 RC3 RC2 RC1 RC0 xxxx xxxx xxxx xxxx — RCIF TXIF SSP1IF CCP1IF EEIF BCL1IF CCP3IF TMR6IF — T1CKPS T1GTM T1GSPM TMR2IF TMR1IF 0000 0000 0000 0000 — — CCP2IF 0000 0--0 0000 0--0 — TMR4IF — --00 0-0- --00 0-0- — BCL2IF SSP2IF ---- --00 ---- --00 xxxx xxxx uuuu uuuu T1OSCEN T1SYNC T1GGO/ DONE T1GVAL — TMR1ON T1GSS 0000 00-0 uuuu uu-u 0000 0x00 uuuu uxuu 0000 0000 0000 0000 1111 1111 1111 1111 T2OUTPS — CPSCON0 CPSON CPSRM — — 01Fh CPSCON1 — — — — 1: 2: 3: 4: DC BSR 01Eh Note Z 0000 0000 0000 0000 — 01Dh Legend: PD TMR2ON T2CKPS Unimplemented -000 0000 -000 0000 — CPSRNG CPSOUT CPSCH T0XCS ---- 0000 ---- 0000 x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved. Shaded locations are unimplemented, read as ‘0’. These registers can be addressed from any bank. PIC16(L)F1829 only. PIC16(L)F1825 only. Unimplemented, read as ‘1’.  2010-2015 Microchip Technology Inc. — 00-- 0000 00-- 0000 DS40001440E-page 29 PIC16(L)F1825/9 TABLE 3-8: Address SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets Bank 1 080h(1) INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory (not a physical register) xxxx xxxx xxxx xxxx 081h(1) INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory (not a physical register) xxxx xxxx xxxx xxxx 082h(1) PCL Program Counter (PC) Least Significant Byte 083h(1) STATUS 084h(1) FSR0L Indirect Data Memory Address 0 Low Pointer 0000 0000 uuuu uuuu 085h(1) FSR0H Indirect Data Memory Address 0 High Pointer 0000 0000 0000 0000 086h(1) FSR1L Indirect Data Memory Address 1 Low Pointer 0000 0000 uuuu uuuu 087h(1) FSR1H Indirect Data Memory Address 1 High Pointer 088h(1) BSR 089h(1) WREG 08Ah(1) PCLATH — 08Bh(1) INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 0000 0000 0000 0000 08Ch TRISA — — TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 --11 1111 --11 1111 08Dh TRISB(2) 08Eh TRISC 08Fh — Unimplemented — — 090h — Unimplemented — — 091h PIE1 TMR1GIE ADIE 092h PIE2 OSFIE C2IE C1IE 093h PIE3 — — CCP4IE 094h PIE4(2) — — — 095h OPTION_REG WPUEN INTEDG STKOVF STKUNF — — — — — — — Z DC C ---1 1000 ---q quuu 0000 0000 0000 0000 — BSR ---0 0000 ---0 0000 Write Buffer for the upper 7 bits of the Program Counter -000 0000 -000 0000 TRISB7 TRISB6 TRISB5 TRISB4 — — — — 1111 ---- 1111 ---- TRISC7(2) TRISC6(2) TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 1111 1111 1111 1111 PCON WDTCON 098h OSCTUNE — 099h OSCCON SPLLEN 09Ah OSCSTAT T1OSCR 09Bh ADRESL A/D Result Register Low 09Ch ADRESH A/D Result Register High 09Dh ADCON0 — 09Eh ADCON1 ADFM 09Fh — 1: 2: 3: 4: PD 0000 0000 uuuu uuuu 096h Note TO Working Register 097h Legend: 0000 0000 0000 0000 — RCIE TXIE SSP1IE CCP1IE EEIE BCL1IE CCP3IE TMR6IE — — TMR0CS TMR0SE PSA — — TMR1IE 0000 0000 0000 0000 — — CCP2IE 0000 0--0 0000 0--0 — TMR4IE — --00 0-0- --00 0-0- — BCL2IE SSP2IE PS RMCLR RI POR WDTPS OSTS HFIOFR BOR 00-- 11qq qq-- qquu SWDTEN --01 0110 --01 0110 --00 0000 --00 0000 — HFIOFL ---- --00 ---- --00 1111 1111 1111 1111 TUN IRCF PLLR TMR2IE SCS MFIOFR LFIOFR HFIOFS 0011 1-00 0011 1-00 10q0 0q00 qqqq qq0q xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu CHS ADCS GO/DONE — ADNREF Unimplemented ADON ADPREF -000 0000 -000 0000 0000 -000 0000 -000 — x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved. Shaded locations are unimplemented, read as ‘0’. These registers can be addressed from any bank. PIC16(L)F1829 only. PIC16(L)F1825 only. Unimplemented, read as ‘1’. DS40001440E-page 30  2010-2015 Microchip Technology Inc. — PIC16(L)F1825/9 TABLE 3-8: Address Name SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets Bank 2 100h(1) INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory (not a physical register) xxxx xxxx xxxx xxxx 101h(1) INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory (not a physical register) xxxx xxxx xxxx xxxx 102h(1) PCL Program Counter (PC) Least Significant Byte 103h(1) STATUS 104h(1) FSR0L Indirect Data Memory Address 0 Low Pointer 0000 0000 uuuu uuuu 105h(1) FSR0H Indirect Data Memory Address 0 High Pointer 0000 0000 0000 0000 106h(1) FSR1L Indirect Data Memory Address 1 Low Pointer 0000 0000 uuuu uuuu 107h(1) FSR1H Indirect Data Memory Address 1 High Pointer 108h(1) BSR 109h(1) WREG 10Ah(1) PCLATH — 10Bh(1) INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 0000 0000 0000 0000 10Ch LATA — — LATA5 LATA4 — LATA2 LATA1 LATA0 --xx -xxx --uu -uuu 10Dh LATB(2) 10Eh LATC 10Fh — Unimplemented — — 110h — Unimplemented — — 111h CM1CON0 C1ON C1OUT 112h CM1CON1 C1INTP C1INTN 113h CM2CON0 C2ON C2OUT 114h CM2CON1 C2INTP C2INTN 115h CMOUT — — — — 116h BORCON SBOREN — — — — — — — 0000 0000 0000 0000 — TO PD Z BSR 0000 0000 uuuu uuuu Write Buffer for the upper 7 bits of the Program Counter -000 0000 -000 0000 LATB7 LATB6 LATB5 LATB4 — — — — xxxx ---- xxxx ---- LATC7(2) LATC6(2) LATC5 LATC4 LATC3 LATC2 LATC1 LATC0 xxxx xxxx uuuu uuuu C1OE C1POL C1PCH C2OE C2POL C2PCH — C1SP C1HYS — — C1NCH1 C1NCH0 0000 ---0 0000 ---0 — C2SP C2HYS C2SYNC 0000 -100 0000 -100 — — — — — — FVRCON FVREN FVRRDY TSEN TSRNG CDAFVR DACCON0 DACEN DACLPS DACOE — DACPSS 119h DACCON1 — — — 11Ah SRCON0 SRLEN 11Bh SRCON1 SRSPE 11Ch — 11Dh APFCON0 RXDTSEL 11Eh APFCON1 — 11Fh — 1: 2: 3: 4: ---1 1000 ---q quuu ---0 0000 ---0 0000 Working Register 118h Note C 0000 0000 0000 0000 — 117h Legend: DC C1SYNC C2NCH MC2OUT — MC1OUT DACNSS DACR SRCLK 0000 --00 0000 --00 ---- --00 ---- --00 BORRDY 1--- ---q u--- ---u ADFVR — 0000 -100 0000 -100 0q00 0000 0q00 0000 000- 00-0 000- 00-0 ---0 0000 ---0 0000 SRQEN SRNQEN SRPS SRPR 0000 0000 0000 0000 SRSC2E(2) SRSC1E SRRPE SRRCKE SRRC2E(2) SRRC1E 0000 0000 0000 0000 SDO1SEL(3) SS1SEL(3) — T1GSEL TXCKSEL — — 000- 0000 000- 0000 — SDO2SEL(2) SS2SEL(2) P1DSEL P1CSEL P2BSEL SRSCKE Unimplemented — Unimplemented CCP2SEL --00 0000 --00 0000 — x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved. Shaded locations are unimplemented, read as ‘0’. These registers can be addressed from any bank. PIC16(L)F1829 only. PIC16(L)F1825 only. Unimplemented, read as ‘1’.  2010-2015 Microchip Technology Inc. — DS40001440E-page 31 — PIC16(L)F1825/9 TABLE 3-8: Address SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets Bank 3 180h(1) INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory (not a physical register) xxxx xxxx xxxx xxxx 181h(1) INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory (not a physical register) xxxx xxxx xxxx xxxx 182h(1) PCL Program Counter (PC) Least Significant Byte 183h(1) STATUS 184h(1) FSR0L Indirect Data Memory Address 0 Low Pointer 0000 0000 uuuu uuuu 185h(1) FSR0H Indirect Data Memory Address 0 High Pointer 0000 0000 0000 0000 186h(1) FSR1L Indirect Data Memory Address 1 Low Pointer 0000 0000 uuuu uuuu 187h(1) FSR1H Indirect Data Memory Address 1 High Pointer 188h(1) BSR 189h(1) WREG 18Ah(1) PCLATH — 18Bh(1) INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 0000 0000 0000 0000 18Ch ANSELA — — — ANSA4 — ANSA2 ANSA1 ANSA0 ---1 -111 ---1 -111 18Dh ANSELB(2) — ANSB5 ANSB4 — — — — --11 ---- --11 ---- 18Eh ANSELC ANSC7(2) — — ANSC3 ANSC2 ANSC1 ANSC0 11-- 1111 11-- 1111 18Fh — Unimplemented — — 190h — Unimplemented — — 191h EEADRL EEPROM / Program Memory Address Register Low Byte 192h EEADRH 193h EEDATL 194h EEDATH 195h EECON1 196h EECON2 EEPROM control register 2 197h — Unimplemented — — 198h — Unimplemented — — 199h RCREG USART Receive Data Register 0000 0000 0000 0000 19Ah TXREG USART Transmit Data Register 0000 0000 0000 0000 19Bh SPBRGL Baud Rate Generator Data Register Low 0000 0000 0000 0000 19Ch SPBRGH Baud Rate Generator Data Register High 19Dh RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x 19Eh TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 0000 0010 19Fh BAUDCON ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 01-0 0-00 01-0 0-00 Legend: Note 1: 2: 3: 4: — — — 0000 0000 0000 0000 — — TO PD Z DC C 0000 0000 0000 0000 — BSR ---0 0000 ---0 0000 Working Register —(4) 0000 0000 uuuu uuuu Write Buffer for the upper 7 bits of the Program Counter — ---1 1000 ---q quuu ANSC6(2) -000 0000 -000 0000 0000 0000 0000 0000 EEPROM / Program Memory Address Register High Byte 1000 0000 1000 0000 EEPROM / Program Memory Read Data Register Low Byte — — EEPGD CFGS xxxx xxxx uuuu uuuu EEPROM / Program Memory Read Data Register High Byte LWLO FREE WRERR WREN WR --xx xxxx --uu uuuu RD 0000 x000 0000 q000 0000 0000 0000 0000 0000 0000 0000 0000 x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved. Shaded locations are unimplemented, read as ‘0’. These registers can be addressed from any bank. PIC16(L)F1829 only. PIC16(L)F1825 only. Unimplemented, read as ‘1’. DS40001440E-page 32  2010-2015 Microchip Technology Inc. PIC16(L)F1825/9 TABLE 3-8: Address SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets Bank 4 200h(1) INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory (not a physical register) xxxx xxxx xxxx xxxx 201h(1) INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory (not a physical register) xxxx xxxx xxxx xxxx 202h(1) PCL Program Counter (PC) Least Significant Byte 203h(1) STATUS 204h(1) FSR0L Indirect Data Memory Address 0 Low Pointer 0000 0000 uuuu uuuu 205h(1) FSR0H Indirect Data Memory Address 0 High Pointer 0000 0000 0000 0000 206h(1) FSR1L Indirect Data Memory Address 1 Low Pointer 0000 0000 uuuu uuuu 207h(1) FSR1H Indirect Data Memory Address 1 High Pointer 208h(1) BSR 209h(1) WREG 20Ah(1) PCLATH — 20Bh(1) INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 0000 0000 0000 0000 20Ch WPUA — — WPUA5 WPUA4 WPUA3 WPUA2 WPUA1 WPUA0 --11 1111 --11 1111 — — — — 0000 0000 0000 0000 — TO PD Z DC C ---1 1000 ---q quuu 0000 0000 0000 0000 — BSR ---0 0000 ---0 0000 Working Register 0000 0000 uuuu uuuu Write Buffer for the upper 7 bits of the Program Counter -000 0000 -000 0000 20Dh WPUB WPUB7 WPUB6 WPUB5 WPUB4 — — — — 1111 ---- 1111 ---- 20Eh WPUC WPUC7(2) WPUC6(2) WPUC5 WPUC4 WPUC3 WPUC2 WPUC1 WPUC0 1111 1111 1111 1111 20Fh — Unimplemented — — 210h — Unimplemented — — 211h SSP1BUF Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx uuuu uuuu 0000 0000 0000 0000 212h SSP1ADD ADD 213h SSP1MSK MSK 214h SSP1STAT SMP CKE D/A P 215h SSP1CON1 WCOL SSPOV SSPEN CKP 216h SSP1CON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 0000 0000 0000 0000 217h SSP1CON3 ACKTIM PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN 0000 0000 0000 0000 218h — Unimplemented 219h SSP2BUF(2) Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx uuuu uuuu 21Ah SSP2ADD(2) ADD 0000 0000 0000 0000 21Bh SSP2MSK(2) MSK 21Ch SSP2STAT(2) SMP CKE D/A P 21Dh SSP2CON1(2) WCOL SSPOV SSPEN CKP 21Eh SSP2CON2(2) GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 0000 0000 0000 0000 21Fh SSP2CON3(2) ACKTIM PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN 0000 0000 0000 0000 Legend: Note 1: 2: 3: 4: 1111 1111 1111 1111 S R/W UA BF SSPM 0000 0000 0000 0000 0000 0000 0000 0000 — 1111 1111 1111 1111 S R/W UA BF SSPM 0000 0000 0000 0000 0000 0000 0000 0000 x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved. Shaded locations are unimplemented, read as ‘0’. These registers can be addressed from any bank. PIC16(L)F1829 only. PIC16(L)F1825 only. Unimplemented, read as ‘1’.  2010-2015 Microchip Technology Inc. — DS40001440E-page 33 PIC16(L)F1825/9 TABLE 3-8: Address SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets Bank 5 280h(1) INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory (not a physical register) xxxx xxxx xxxx xxxx 281h(1) INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory (not a physical register) xxxx xxxx xxxx xxxx 282h(1) PCL Program Counter (PC) Least Significant Byte 283h(1) STATUS 284h(1) FSR0L Indirect Data Memory Address 0 Low Pointer 0000 0000 uuuu uuuu 285h(1) FSR0H Indirect Data Memory Address 0 High Pointer 0000 0000 0000 0000 286h(1) FSR1L Indirect Data Memory Address 1 Low Pointer 0000 0000 uuuu uuuu 287h(1) FSR1H Indirect Data Memory Address 1 High Pointer 288h(1) BSR 289h(1) WREG 28Ah(1) PCLATH — 28Bh(1) INTCON GIE 28Ch — Unimplemented — — 28Dh — Unimplemented — — 28Eh — Unimplemented — — 28Fh — Unimplemented — — 290h — Unimplemented — — 291h CCPR1L Capture/Compare/PWM Register 1 (LSB) 292h CCPR1H Capture/Compare/PWM Register 1 (MSB) 293h CCP1CON 294h PWM1CON 295h CCP1AS 296h PSTR1CON 297h — Unimplemented 298h CCPR2L Capture/Compare/PWM Register 2 (LSB) 299h CCPR2H Capture/Compare/PWM Register 2 (MSB) 29Ah CCP2CON P2M1 P2M0 DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 0000 0000 0000 0000 29Bh PWM2CON P2RSEN P2DC6 P2DC5 P2DC4 P2DC3 P2DC2 P2DC1 P2DC0 0000 0000 0000 0000 29Ch CCP2AS CCP2ASE CCP2AS2 CCP2AS1 CCP2AS0 PSS2AC1 PSS2AC0 PSS2BD1 — — — — — 0000 0000 0000 0000 TO PD Z DC BSR ---0 0000 ---0 0000 Working Register 0000 0000 uuuu uuuu Write Buffer for the upper 7 bits of the Program Counter PEIE P1M TMR0IE INTE IOCIE -000 0000 -000 0000 TMR0IF INTF CCP1M CCP1AS — — 0000 0000 0000 0000 PSS1AC STR1SYNC STR1D PSS1BD STR1C STR1B STR1A 0000 0000 0000 0000 ---0 0001 ---0 0001 — xxxx xxxx uuuu uuuu PSTR2CON — — — STR2SYNC STR2D STR2C STR2B C4TSEL1 C4TSEL0 C3TSEL1 C3TSEL0 C2TSEL1 C2TSEL0 C1TSEL1 29Fh — Unimplemented PSS2BD0 0000 0000 0000 0000 STR2A ---0 0001 ---0 0001 C1TSEL0 0000 0000 0000 0000 — x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved. Shaded locations are unimplemented, read as ‘0’. These registers can be addressed from any bank. PIC16(L)F1829 only. PIC16(L)F1825 only. Unimplemented, read as ‘1’. DS40001440E-page 34 — xxxx xxxx uuuu uuuu CCPTMRS 1: 2: 3: 4: 0000 0000 0000 0000 P1DC CCP1ASE 0000 0000 0000 0000 xxxx xxxx uuuu uuuu DC1B 29Dh Note IOCIF xxxx xxxx uuuu uuuu P1RSEN — ---1 1000 ---q quuu 0000 0000 0000 0000 — 29Eh Legend: C  2010-2015 Microchip Technology Inc. — PIC16(L)F1825/9 TABLE 3-8: Address Name SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets Bank 6 300h(1) INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory (not a physical register) xxxx xxxx xxxx xxxx 301h(1) INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory (not a physical register) xxxx xxxx xxxx xxxx 302h(1) PCL Program Counter (PC) Least Significant Byte 303h(1) STATUS 304h(1) FSR0L Indirect Data Memory Address 0 Low Pointer 0000 0000 uuuu uuuu 305h(1) FSR0H Indirect Data Memory Address 0 High Pointer 0000 0000 0000 0000 306h(1) FSR1L Indirect Data Memory Address 1 Low Pointer 0000 0000 uuuu uuuu 307h(1) FSR1H Indirect Data Memory Address 1 High Pointer 308h(1) BSR 309h(1) WREG 30Ah(1) PCLATH — 30Bh(1) INTCON GIE 30Ch — Unimplemented — — 30Dh — Unimplemented — — 30Eh — Unimplemented — — 30Fh — Unimplemented — — 310h — Unimplemented — — 311h CCPR3L Capture/Compare/PWM Register 3 (LSB) 312h CCPR3H Capture/Compare/PWM Register 3 (MSB) 313h CCP3CON 314h — Unimplemented — — 315h — Unimplemented — — 316h — Unimplemented — — 317h — Unimplemented — — 318h CCPR4L Capture/Compare/PWM Register 4 (LSB) 319h CCPR4H Capture/Compare/PWM Register 4 (MSB) 31Ah CCP4CON 31Bh — Unimplemented — — 31Ch — Unimplemented — — 31Dh — Unimplemented — — 31Eh — Unimplemented — — 31Fh — Unimplemented — — Legend: Note 1: 2: 3: 4: — — — — — 0000 0000 0000 0000 TO PD Z DC C ---1 1000 ---q quuu 0000 0000 0000 0000 — BSR ---0 0000 ---0 0000 Working Register 0000 0000 uuuu uuuu Write Buffer for the upper 7 bits of the Program Counter PEIE — — — — TMR0IE DC3B1 DC4B1 INTE IOCIE -000 0000 -000 0000 TMR0IF INTF IOCIF 0000 0000 0000 0000 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu DC3B0 CCP3M3 CCP3M2 CCP3M1 CCP3M0 --00 0000 --00 0000 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu DC4B0 CCP4M3 CCP4M2 CCP4M1 CCP4M0 --00 0000 --00 0000 x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved. Shaded locations are unimplemented, read as ‘0’. These registers can be addressed from any bank. PIC16(L)F1829 only. PIC16(L)F1825 only. Unimplemented, read as ‘1’.  2010-2015 Microchip Technology Inc. DS40001440E-page 35 PIC16(L)F1825/9 TABLE 3-8: Address SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets Bank 7 380h(1) INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory (not a physical register) xxxx xxxx xxxx xxxx 381h(1) INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory (not a physical register) xxxx xxxx xxxx xxxx 382h(1) PCL Program Counter (PC) Least Significant Byte 383h(1) STATUS 384h(1) FSR0L Indirect Data Memory Address 0 Low Pointer 0000 0000 uuuu uuuu 385h(1) FSR0H Indirect Data Memory Address 0 High Pointer 0000 0000 0000 0000 386h(1) FSR1L Indirect Data Memory Address 1 Low Pointer 0000 0000 uuuu uuuu 387h(1) FSR1H Indirect Data Memory Address 1 High Pointer 388h(1) BSR 389h(1) WREG 38Ah(1) PCLATH — 38Bh(1) INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 0000 0000 0000 0000 38Ch INLVLA — — INLVLA5 INLVLA4 INLVLA3 INLVLA2 INLVLA1 INLVLA0 --00 0100 --00 0100 38Dh INLVLB(2) INLVLB7 INLVLB6 INLVLB5 INLVLB4 — — — — 0000 ---- 0000 ---- 38Eh INLVLC(3) — — INLVLC5 INLVLC4 INLVLC3 INLVLC2 INLVLC1 INLVLC0 --00 0000 --00 0000 INLVLC7 INLVLC6 INLVLC5 INLVLC4 INLVLC3 INLVLC2 INLVLC1 INLVLC0 1111 1111 1111 1111 — — — — — 0000 0000 0000 0000 TO PD Z DC C 0000 0000 0000 0000 — BSR ---0 0000 ---0 0000 Working Register INLVLC(2) ---1 1000 ---q quuu 0000 0000 uuuu uuuu Write Buffer for the upper 7 bits of the Program Counter -000 0000 -000 0000 38Fh — Unimplemented — — 390h — Unimplemented — — 391h IOCAP — — IOCAP5 IOCAP4 IOCAP3 IOCAP2 IOCAP1 IOCAP0 --00 0000 --00 0000 392h IOCAN — — IOCAN5 IOCAN4 IOCAN3 IOCAN2 IOCAN1 IOCAN0 --00 0000 --00 0000 393h IOCAF — — IOCAF5 IOCAF4 IOCAF3 IOCAF2 IOCAF1 IOCAF0 --00 0000 --00 0000 394h IOCBP(2) IOCBP7 IOCBP6 IOCBP5 IOCBP4 — — — — 0000 ---- 0000 ---- 395h IOCBN(2) IOCBN7 IOCBN6 IOCBN5 IOCBN4 — — — — 0000 ---- 0000 ---- 396h IOCBF(2) IOCBF7 IOCBF6 IOCBF5 IOCBF4 — — — — 0000 ---- 0000 ---- 397h — Unimplemented — — 398h — Unimplemented — — 399h — Unimplemented — — 39Ah CLKRCON CLKREN 39Bh — 39Ch MDCON MDEN 39Dh MDSRC MDMSODIS 39Eh MDCARL MDCLODIS 39Fh MDCARH MDCHODIS Legend: Note 1: 2: 3: 4: CLKROE CLKRSLR CLKRDC CLKRDIV 0011 0000 0011 0000 Unimplemented — MDOE MDOUT MDOPOL — — — MDMS x--- xxxx u--- uuuu MDCLPOL MDCLSYNC — MDCL xxx- xxxx uuu- uuuu MDCHPOL MDCHSYNC — MDCH xxx- xxxx uuu- uuuu — — MDBIT 0010 ---0 0010 ---0 x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved. Shaded locations are unimplemented, read as ‘0’. These registers can be addressed from any bank. PIC16(L)F1829 only. PIC16(L)F1825 only. Unimplemented, read as ‘1’. DS40001440E-page 36 — MDSLR  2010-2015 Microchip Technology Inc. PIC16(L)F1825/9 TABLE 3-8: Address Name SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets Bank 8 400h(1) INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory (not a physical register) xxxx xxxx xxxx xxxx 401h(1) INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory (not a physical register) xxxx xxxx xxxx xxxx 402h(1) PCL Program Counter (PC) Least Significant Byte 403h(1) STATUS 404h(1) FSR0L Indirect Data Memory Address 0 Low Pointer 0000 0000 uuuu uuuu 405h(1) FSR0H Indirect Data Memory Address 0 High Pointer 0000 0000 0000 0000 406h(1) FSR1L Indirect Data Memory Address 1 Low Pointer 0000 0000 uuuu uuuu 407h(1) FSR1H Indirect Data Memory Address 1 High Pointer 408h(1) BSR 409h(1) WREG 40Ah(1) PCLATH — 40Bh(1) INTCON GIE 40Ch — Unimplemented — — 40Dh — Unimplemented — — 40Eh — Unimplemented — — 40Fh — Unimplemented — — 410h — Unimplemented — — 411h — Unimplemented — — 412h — Unimplemented — — 413h — Unimplemented — — 414h — Unimplemented — — 415h TMR4 Timer4 Module Register 416h PR4 Timer4 Period Register 417h T4CON 418h — Unimplemented — — 419h — Unimplemented — — 41Ah — Unimplemented — — 41Bh — Unimplemented — — 41Ch TMR6 Timer6 Module Register 41Dh PR6 Timer6 Period Register 41Eh T6CON 41Fh — Legend: Note 1: 2: 3: 4: — — — — — 0000 0000 0000 0000 TO PD Z DC C ---1 1000 ---q quuu 0000 0000 0000 0000 — BSR ---0 0000 ---0 0000 Working Register 0000 0000 uuuu uuuu Write Buffer for the upper 7 bits of the Program Counter PEIE — — TMR0IE INTE IOCIE -000 0000 -000 0000 TMR0IF INTF IOCIF 0000 0000 0000 0000 0000 0000 0000 0000 1111 1111 1111 1111 T4OUTPS TMR4ON T4CKPS -000 0000 -000 0000 0000 0000 0000 0000 1111 1111 1111 1111 T6OUTPS TMR6ON Unimplemented T6CKPS -000 0000 -000 0000 — x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved. Shaded locations are unimplemented, read as ‘0’. These registers can be addressed from any bank. PIC16(L)F1829 only. PIC16(L)F1825 only. Unimplemented, read as ‘1’.  2010-2015 Microchip Technology Inc. DS40001440E-page 37 — PIC16(L)F1825/9 TABLE 3-8: Address SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets Banks 9-30 x00h/ x80h(1) INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory (not a physical register) xxxx xxxx xxxx xxxx x00h/ x81h(1) INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory (not a physical register) xxxx xxxx xxxx xxxx x02h/ x82h(1) PCL Program Counter (PC) Least Significant Byte 0000 0000 0000 0000 x03h/ x83h(1) STATUS x04h/ x84h(1) FSR0L Indirect Data Memory Address 0 Low Pointer 0000 0000 uuuu uuuu x05h/ x85h(1) FSR0H Indirect Data Memory Address 0 High Pointer 0000 0000 0000 0000 x06h/ x86h(1) FSR1L Indirect Data Memory Address 1 Low Pointer 0000 0000 uuuu uuuu x07h/ x87h(1) FSR1H Indirect Data Memory Address 1 High Pointer 0000 0000 0000 0000 x08h/ x88h(1) BSR x09h/ x89h(1) WREG x0Ah/ x8Ah(1) PCLATH — x0Bh/ x8Bh(1) INTCON GIE x0Ch/ x8Ch — x1Fh/ x9Fh — Legend: Note 1: 2: 3: 4: — — — — — TO PD — Z DC C BSR ---1 1000 ---q quuu ---0 0000 ---0 0000 Working Register 0000 0000 uuuu uuuu Write Buffer for the upper 7 bits of the Program Counter PEIE TMR0IE INTE IOCIE -000 0000 -000 0000 TMR0IF Unimplemented INTF IOCIF 0000 0000 0000 0000 — x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved. Shaded locations are unimplemented, read as ‘0’. These registers can be addressed from any bank. PIC16(L)F1829 only. PIC16(L)F1825 only. Unimplemented, read as ‘1’. DS40001440E-page 38  2010-2015 Microchip Technology Inc. — PIC16(L)F1825/9 TABLE 3-8: Address Name SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets Bank 31 F80h(1) INDF0 Addressing this location uses contents of FSR0H/FSR0L to address data memory (not a physical register) xxxx xxxx xxxx xxxx F81h(1) INDF1 Addressing this location uses contents of FSR1H/FSR1L to address data memory (not a physical register) xxxx xxxx xxxx xxxx F82h(1) PCL Program Counter (PC) Least Significant Byte F83h(1) STATUS F84h(1) FSR0L Indirect Data Memory Address 0 Low Pointer 0000 0000 uuuu uuuu F85h(1) FSR0H Indirect Data Memory Address 0 High Pointer 0000 0000 0000 0000 F86h(1) FSR1L Indirect Data Memory Address 1 Low Pointer 0000 0000 uuuu uuuu F87h(1) FSR1H Indirect Data Memory Address 1 High Pointer F88h(1) BSR F89h(1) WREG F8Ah(1) PCLATH — F8Bh(1) INTCON GIE F8Ch — FE3h — FE4h STATUS_ — — — — — 0000 0000 0000 0000 TO PD Z DC C ---1 1000 ---q quuu 0000 0000 0000 0000 — BSR ---0 0000 ---0 0000 Working Register 0000 0000 uuuu uuuu Write Buffer for the upper 7 bits of the Program Counter PEIE TMR0IE INTE IOCIE -000 0000 -000 0000 TMR0IF INTF IOCIF Unimplemented — 0000 0000 0000 0000 — — — — — Z_SHAD DC_SHAD C_SHAD — ---- -xxx ---- -uuu SHAD FE5h WREG_ Working Register Shadow 0000 0000 uuuu uuuu SHAD FE6h BSR_ — — — Bank Select Register Shadow ---x xxxx ---u uuuu SHAD FE7h PCLATH_ — Program Counter Latch High Register Shadow -xxx xxxx uuuu uuuu SHAD FE8h FSR0L_ Indirect Data Memory Address 0 Low Pointer Shadow xxxx xxxx uuuu uuuu Indirect Data Memory Address 0 High Pointer Shadow xxxx xxxx uuuu uuuu Indirect Data Memory Address 1 Low Pointer Shadow xxxx xxxx uuuu uuuu Indirect Data Memory Address 1 High Pointer Shadow xxxx xxxx uuuu uuuu SHAD FE9h FSR0H_ SHAD FEAh FSR1L_ SHAD FEBh FSR1H_ SHAD FECh — FEDh STKPTR FEEh TOSL FEFh TOSH Legend: Note 1: 2: 3: 4: Unimplemented — — — — Current Stack pointer Top-of-Stack Low byte — Top-of-Stack High byte xxxx xxxx uuuu uuuu -xxx xxxx -uuu uuuu x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved. Shaded locations are unimplemented, read as ‘0’. These registers can be addressed from any bank. PIC16(L)F1829 only. PIC16(L)F1825 only. Unimplemented, read as ‘1’.  2010-2015 Microchip Technology Inc. — ---1 1111 ---1 1111 DS40001440E-page 39 PIC16(L)F1825/9 3.3 3.3.2 PCL and PCLATH The Program Counter (PC) is 15 bits wide. The low byte comes from the PCL register, which is a readable and writable register. The high byte (PC) is not directly readable or writable and comes from PCLATH. On any Reset, the PC is cleared. Figure 3-3 shows the five situations for the loading of the PC. FIGURE 3-3: 14 LOADING OF PC IN DIFFERENT SITUATIONS PCH PCL 0 PC 6 7 8 0 PCLATH Instruction with PCL as Destination ALU Result 14 PCH PCL 0 GOTO, CALL PC 6 4 0 PCLATH 11 OPCODE 14 PCH PCL 0 PC 6 7 0 PCLATH CALLW W 14 PCH PCL 0 PC BRW 15 PC + W 14 PCH PCL PC 0 BRA 15 PC + OPCODE 3.3.1 A computed GOTO is accomplished by adding an offset to the program counter (ADDWF PCL). When performing a table read using a computed GOTO method, care should be exercised if the table location crosses a PCL memory boundary (each 256-byte block). Refer to the Application Note AN556, “Implementing a Table Read” (DS00556). 3.3.3 COMPUTED FUNCTION CALLS A computed function CALL allows programs to maintain tables of functions and provide another way to execute state machines or look-up tables. When performing a table read using a computed function CALL, care should be exercised if the table location crosses a PCL memory boundary (each 256-byte block). If using the CALL instruction, the PCH and PCL registers are loaded with the operand of the CALL instruction. PCH is loaded with PCLATH. The CALLW instruction enables computed calls by combining PCLATH and W to form the destination address. A computed CALLW is accomplished by loading the W register with the desired address and executing CALLW. The PCL register is loaded with the value of W and PCH is loaded with PCLATH. 3.3.4 8 COMPUTED GOTO BRANCHING The branching instructions add an offset to the PC. This allows relocatable code and code that crosses page boundaries. There are two forms of branching, BRW and BRA. The PC will have incremented to fetch the next instruction in both cases. When using either branching instruction, a PCL memory boundary may be crossed. If using BRW, load the W register with the desired unsigned address and execute BRW. The entire PC will be loaded with the address PC + 1 + W. If using BRA, the entire PC will be loaded with PC + 1 +, the signed value of the operand of the BRA instruction. MODIFYING PCL Executing any instruction with the PCL register as the destination simultaneously causes the Program Counter PC bits (PCH) to be replaced by the contents of the PCLATH register. This allows the entire contents of the program counter to be changed by writing the desired upper seven bits to the PCLATH register. When the lower eight bits are written to the PCL register, all 15 bits of the program counter will change to the values contained in the PCLATH register and those being written to the PCL register. DS40001440E-page 40  2010-2015 Microchip Technology Inc. PIC16(L)F1825/9 3.4 3.4.1 Stack The stack is available through the TOSH, TOSL and STKPTR registers. STKPTR is the current value of the Stack Pointer. TOSH:TOSL register pair points to the TOP of the stack. Both registers are read/writable. TOS is split into TOSH and TOSL due to the 15-bit size of the PC. To access the stack, adjust the value of STKPTR, which will position TOSH:TOSL, then read/write to TOSH:TOSL. STKPTR is five bits to allow detection of overflow and underflow. All devices have a 16-level x 15-bit wide hardware stack (refer to Figures 3-4 through 3-7). The stack space is not part of either program or data space. The PC is PUSHed onto the stack when CALL or CALLW instructions are executed or an interrupt causes a branch. The stack is POPed in the event of a RETURN, RETLW or a RETFIE instruction execution. PCLATH is not affected by a PUSH or POP operation. The stack operates as a circular buffer if the STVREN bit is programmed to ‘0‘ (Configuration Word 2). This means that after the stack has been PUSHed sixteen times, the seventeenth PUSH overwrites the value that was stored from the first PUSH. The eighteenth PUSH overwrites the second PUSH (and so on). The STKOVF and STKUNF flag bits will be set on an Overflow/Underflow, regardless of whether the Reset is enabled. Note: Care should be taken when modifying the STKPTR while interrupts are enabled. During normal program operation, CALL, CALLW and Interrupts will increment STKPTR while RETLW, RETURN, and RETFIE will decrement STKPTR. At any time STKPTR can be inspected to see how much stack is left. The STKPTR always points at the currently used place on the stack. Therefore, a CALL or CALLW will increment the STKPTR and then write the PC, and a return will unload the PC and then decrement the STKPTR. Note 1: There are no instructions/mnemonics called PUSH or POP. These are actions that occur from the execution of the CALL, CALLW, RETURN, RETLW and RETFIE instructions or the vectoring to an interrupt address. FIGURE 3-4: ACCESSING THE STACK Reference Figure 3-4 through Figure 3-7 for examples of accessing the stack. ACCESSING THE STACK EXAMPLE 1 TOSH:TOSL 0x0F STKPTR = 0x1F Stack Reset Disabled (STVREN = 0) 0x0E 0x0D 0x0C 0x0B 0x0A Initial Stack Configuration: 0x09 After Reset, the stack is empty. The empty stack is initialized so the Stack Pointer is pointing at 0x1F. If the Stack Overflow/Underflow Reset is enabled, the TOSH/TOSL registers will return ‘0’. If the Stack Overflow/Underflow Reset is disabled, the TOSH/TOSL registers will return the contents of stack address 0x0F. 0x08 0x07 0x06 0x05 0x04 0x03 0x02 0x01 0x00 TOSH:TOSL  2010-2015 Microchip Technology Inc. 0x1F 0x0000 STKPTR = 0x1F Stack Reset Enabled (STVREN = 1) DS40001440E-page 41 PIC16(L)F1825/9 FIGURE 3-5: ACCESSING THE STACK EXAMPLE 2 0x0F 0x0E 0x0D 0x0C 0x0B 0x0A 0x09 This figure shows the stack configuration after the first CALL or a single interrupt. If a RETURN instruction is executed, the return address will be placed in the Program Counter and the Stack Pointer decremented to the empty state (0x1F). 0x08 0x07 0x06 0x05 0x04 0x03 0x02 0x01 TOSH:TOSL FIGURE 3-6: 0x00 Return Address STKPTR = 0x00 ACCESSING THE STACK EXAMPLE 3 0x0F 0x0E 0x0D 0x0C After seven CALLs or six CALLs and an interrupt, the stack looks like the figure on the left. A series of RETURN instructions will repeatedly place the return addresses into the Program Counter and pop the stack. 0x0B 0x0A 0x09 0x08 0x07 TOSH:TOSL DS40001440E-page 42 0x06 Return Address 0x05 Return Address 0x04 Return Address 0x03 Return Address 0x02 Return Address 0x01 Return Address 0x00 Return Address STKPTR = 0x06  2010-2015 Microchip Technology Inc. PIC16(L)F1825/9 FIGURE 3-7: ACCESSING THE STACK EXAMPLE 4 TOSH:TOSL 3.4.2 0x0F Return Address 0x0E Return Address 0x0D Return Address 0x0C Return Address 0x0B Return Address 0x0A Return Address 0x09 Return Address 0x08 Return Address 0x07 Return Address 0x06 Return Address 0x05 Return Address 0x04 Return Address 0x03 Return Address 0x02 Return Address 0x01 Return Address 0x00 Return Address When the stack is full, the next CALL or an interrupt will set the Stack Pointer to 0x10. This is identical to address 0x00 so the stack will wrap and overwrite the return address at 0x00. If the Stack Overflow/Underflow Reset is enabled, a Reset will occur and location 0x00 will not be overwritten. STKPTR = 0x10 OVERFLOW/UNDERFLOW RESET If the STVREN bit in Configuration Word 2 is programmed to ‘1’, the device will be reset if the stack is PUSHed beyond the sixteenth level or POPed beyond the first level, setting the appropriate bits (STKOVF or STKUNF, respectively) in the PCON register. 3.5 Indirect Addressing The INDFn registers are not physical registers. Any instruction that accesses an INDFn register actually accesses the register at the address specified by the File Select Registers (FSR). If the FSRn address specifies one of the two INDFn registers, the read will return ‘0’ and the write will not occur (though Status bits may be affected). The FSRn register value is created by the pair FSRnH and FSRnL. The FSR registers form a 16-bit address that allows an addressing space with 65536 locations. These locations are divided into three memory regions: • Traditional Data Memory • Linear Data Memory • Program Flash Memory  2010-2015 Microchip Technology Inc. DS40001440E-page 43 PIC16(L)F1825/9 FIGURE 3-8: INDIRECT ADDRESSING 0x0000 0x0000 Traditional Data Memory 0x0FFF 0x1000 0x1FFF 0x0FFF Reserved 0x2000 Linear Data Memory 0x29AF 0x29B0 FSR Address Range 0x7FFF 0x8000 Reserved 0x0000 Program Flash Memory 0xFFFF Note: 0x7FFF Not all memory regions are completely implemented. Consult device memory tables for memory limits. DS40001440E-page 44  2010-2015 Microchip Technology Inc. PIC16(L)F1825/9 3.5.1 TRADITIONAL DATA MEMORY The traditional data memory is a region from FSR address 0x000 to FSR address 0xFFF. The addresses correspond to the absolute addresses of all SFR, GPR and common registers. FIGURE 3-9: TRADITIONAL DATA MEMORY MAP Direct Addressing 4 BSR 0 6 Indirect Addressing From Opcode 0 7 0 Bank Select Location Select FSRxH 0 0 0 7 FSRxL 0 0 Bank Select 00000 00001 00010 11111 Bank 0 Bank 1 Bank 2 Bank 31 Location Select 0x00 0x7F  2010-2015 Microchip Technology Inc. DS40001440E-page 45 PIC16(L)F1825/9 3.5.2 3.5.3 LINEAR DATA MEMORY The linear data memory is the region from FSR address 0x2000 to FSR address 0x29AF. This region is a virtual region that points back to the 80-byte blocks of GPR memory in all the banks. Unimplemented memory reads as 0x00. Use of the linear data memory region allows buffers to be larger than 80 bytes because incrementing the FSR beyond one bank will go directly to the GPR memory of the next bank. The 16 bytes of common memory are not included in the linear data memory region. FIGURE 3-10: 7 FSRnH 0 0 1 LINEAR DATA MEMORY MAP 0 7 FSRnL 0 PROGRAM FLASH MEMORY To make constant data access easier, the entire program Flash memory is mapped to the upper half of the FSR address space. When the MSB of FSRnH is set, the lower 15 bits are the address in program memory which will be accessed through INDF. Only the lower eight bits of each memory location is accessible via INDF. Writing to the program Flash memory cannot be accomplished via the FSR/INDF interface. All instructions that access program Flash memory via the FSR/INDF interface will require one additional instruction cycle to complete. FIGURE 3-11: 7 1 FSRnH PROGRAM FLASH MEMORY MAP 0 Location Select Location Select 0x2000 7 FSRnL 0x8000 0 0x0000 0x020 Bank 0 0x06F 0x0A0 Bank 1 0x0EF 0x120 Program Flash Memory (low 8 bits) Bank 2 0x16F 0xF20 Bank 30 0x29AF DS40001440E-page 46 0xF6F 0xFFFF 0x7FFF  2010-2015 Microchip Technology Inc. PIC16(L)F1825/9 4.0 DEVICE CONFIGURATION Device Configuration consists of Configuration Word 1 and Configuration Word 2, Code Protection and Device ID. 4.1 Configuration Words There are several Configuration Word bits that allow different oscillator and memory protection options. These are implemented as Configuration Word 1 at 8007h and Configuration Word 2 at 8008h. Note: The DEBUG bit in Configuration Word 2 is managed automatically by device development tools including debuggers and programmers. For normal device operation, this bit should be maintained as a ‘1’.  2010-2015 Microchip Technology Inc. DS40001440E-page 47 PIC16(L)F1825/9 REGISTER 4-1: CONFIGURATION WORD 1 R/P-1/1 R/P-1/1 R/P-1/1 FCMEN IESO CLKOUTEN R/P-1/1 R/P-1/1 BOREN bit 13 R/P-1/1 R/P-1/1 R/P-1/1 CP MCLRE PWRTE R/P-1/1 CPD bit 8 R/P-1/1 R/P-1/1 R/P-1/1 WDTE R/P-1/1 R/P-1/1 FOSC  0 ( 0 ?  (  >  1 < < 6 9"="% 9 ) 9"="% :  )* 1+ ,     !"#$%! & '(!%&! %( %")%%%"   *$%+ %  % , &   "-"  %!"& "$   % !    "$   % !     %#".  "  &  "%   -/0 1+21 &    %#%!  ))% !%%          ) +01  2010-2015 Microchip Technology Inc. DS40001440E-page 409 PIC16(L)F1825/9 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS40001440E-page 410  2010-2015 Microchip Technology Inc. PIC16(L)F1825/9 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2010-2015 Microchip Technology Inc. DS40001440E-page 411 PIC16(L)F1825/9   3 %& %! %4" ) '  % 4$%  %"% %%255)))&  &54 DS40001440E-page 412  2010-2015 Microchip Technology Inc. PIC16(L)F1825/9 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2010-2015 Microchip Technology Inc. DS40001440E-page 413 PIC16(L)F1825/9 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS40001440E-page 414  2010-2015 Microchip Technology Inc. PIC16(L)F1825/9 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2010-2015 Microchip Technology Inc. DS40001440E-page 415 PIC16(L)F1825/9 !   " # $   %& '  (()*   "#   3 %& %! %4" ) '  % 4$%  %"% %%255)))&  &54 D2 D EXPOSED PAD e E2 E 2 2 1 1 b TOP VIEW K N N NOTE 1 L BOTTOM VIEW A3 A A1 6% &  9&% 7!&(  $ 99- - 7 7 7: ; ? %  : 8%  >   %" $$    0 + %% 4 , : ="% - -# ""="% - : 9%  -# ""9% ?01+ -3 1+ 0 ?0 > 1+  0 ?0 + %%="% ( 0 , ,0 + %%9% 9 ,  0 + %%% -# "" V  <     !"#$%! & '(!%&! %( %")%%%"   4  ) !%" , &  "%   -/0 1+2 1 &    %#%!  ))% !%%    -32 $ &  '! !)% !%%  '$ $ &% !     > <       ) +1 DS40001440E-page 416  2010-2015 Microchip Technology Inc. PIC16(L)F1825/9 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2010-2015 Microchip Technology Inc. DS40001440E-page 417 PIC16(L)F1825/9 16-Lead Ultra Thin Plastic Quad Flat, No Lead Package (JQ) - 4x4x0.5 mm Body [UQFN] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D A B N NOTE 1 1 2 E (DATUM B) (DATUM A) 2X 0.20 C 2X TOP VIEW 0.20 C SEATING PLANE A1 0.10 C C A 16X (A3) 0.08 C SIDE VIEW 0.10 C A B D2 0.10 C A B E2 2 e 2 1 NOTE 1 K N 16X b 0.10 L e C A B BOTTOM VIEW Microchip Technology Drawing C04-257A Sheet 1 of 2 DS40001440E-page 418  2010-2015 Microchip Technology Inc. PIC16(L)F1825/9 16-Lead Ultra Thin Plastic Quad Flat, No Lead Package (JQ) - 4x4x0.5 mm Body [UQFN] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Units Dimension Limits Number of Pins N e Pitch A Overall Height Standoff A1 A3 Terminal Thickness Overall Width E E2 Exposed Pad Width D Overall Length D2 Exposed Pad Length b Terminal Width Terminal Length L K Terminal-to-Exposed-Pad MIN 0.45 0.00 2.50 2.50 0.25 0.30 0.20 MILLIMETERS NOM 16 0.65 BSC 0.50 0.02 0.127 REF 4.00 BSC 2.60 4.00 BSC 2.60 0.30 0.40 - MAX 0.55 0.05 2.70 2.70 0.35 0.50 - Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Package is saw singulated 3. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Microchip Technology Drawing C04-257A Sheet 2 of 2  2010-2015 Microchip Technology Inc. DS40001440E-page 419 PIC16(L)F1825/9 16-Lead Ultra Thin Plastic Quad Flat, No Lead Package (JQ) - 4x4x0.5 mm Body [UQFN] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging C1 X2 16 1 2 C2 Y2 Y1 X1 E SILK SCREEN RECOMMENDED LAND PATTERN Units Dimension Limits E Contact Pitch Optional Center Pad Width X2 Optional Center Pad Length Y2 Contact Pad Spacing C1 Contact Pad Spacing C2 Contact Pad Width (X16) X1 Contact Pad Length (X16) Y1 MIN MILLIMETERS NOM 0.65 BSC MAX 2.70 2.70 4.00 4.00 0.35 0.80 Notes: 1. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. Microchip Technology Drawing C04-2257A DS40001440E-page 420  2010-2015 Microchip Technology Inc. PIC16(L)F1825/9 +                3 %& %! %4" ) '  % 4$%  %"% %%255)))&  &54  N E1 NOTE 1 1 2 3 D E A2 A L c A1 b1 b eB e 6% &  9&% 7!&(  $ 7+8- 7 7 7: ;  %  % %  < <   ""4 4  0 , 0 1 % %  0 < <  !" %  !" ="% - , , ,0  ""4="% -  0 > : 9%  > , ? % % 9 0 , 0 9" 4  >  0 ( 0 ?  (  >  1 < < 6 9"="% 9 ) 9"="% :  )* 1+ ,     !"#$%! & '(!%&! %( %")%%%"   *$%+ %  % , &   "-"  %!"& "$   % !    "$   % !     %#".  "  &  "%   -/0 1+2 1 &    %#%!  ))% !%%          ) +1  2010-2015 Microchip Technology Inc. DS40001440E-page 421 PIC16(L)F1825/9 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS40001440E-page 422  2010-2015 Microchip Technology Inc. PIC16(L)F1825/9 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2010-2015 Microchip Technology Inc. DS40001440E-page 423 PIC16(L)F1825/9 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS40001440E-page 424  2010-2015 Microchip Technology Inc. PIC16(L)F1825/9 +   ,-.% , /  ,,  0)   ,,/    3 %& %! %4" ) '  % 4$%  %"% %%255)))&  &54 D N E E1 NOTE 1 1 2 e b c A2 A φ A1 L1 6% &  9&% 7!&(  $ L 99- - 7 7 7: ;  %  : 8%  < ?01+ <   ""4 4  ?0 0 >0 %" $$  0 < < : ="% -  > >  ""4="% - 0 0, 0? : 9%  ?  0 3 %9% 9 00 0 0 3 % % 9 0-3 9" 4   < 3 %  W W 0 >W 9"="% (  < ,>     !"#$%! & '(!%&! %( %")%%%"   &   "-"  %!"& "$   % !    "$   % !     %#"&&  " , &  "%   -/0 1+2 1 &    %#%!  ))% !%%    -32 $ &  '! !)% !%%  '$ $ &% !           ) +1  2010-2015 Microchip Technology Inc. DS40001440E-page 425 PIC16(L)F1825/9 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS40001440E-page 426  2010-2015 Microchip Technology Inc. PIC16(L)F1825/9 +   " # $   %& '  (()*   "#   3 %& %! %4" ) '  % 4$%  %"% %%255)))&  &54  D D2 EXPOSED PAD e E2 2 E b 2 1 1 K N N NOTE 1 TOP VIEW L BOTTOM VIEW A A1 A3 6% &  9&% 7!&(  $ 99- - 7 7 7: ;  %  : 8%  >   %" $$    0 + %% 4 , : ="% - -# ""="% - : 9%  -# ""9% 01+ -3 1+ ?  > 1+  ?  > + %%="% ( > 0 , + %%9% 9 ,  0 + %%% -# "" V  < <     !"#$%! & '(!%&! %( %")%%%"   4  ) !%" , &  "%   -/0 1+2 1 &    %#%!  ))% !%%    -32 $ &  '! !)% !%%  '$ $ &% !           ) +?1  2010-2015 Microchip Technology Inc. DS40001440E-page 427 PIC16(L)F1825/9   3 %& %! %4" ) '  % 4$%  %"% %%255)))&  &54 DS40001440E-page 428  2010-2015 Microchip Technology Inc. PIC16(L)F1825/9 20-Lead Ultra Thin Plastic Quad Flat, No Lead Package (GZ) - 4x4x0.5 mm Body [UQFN] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D A B N NOTE 1 1 2 E (DATUM B) (DATUM A) 2X 0.20 C 2X TOP VIEW 0.20 C SEATING PLANE A1 0.10 C C A 20X (A3) 0.08 C SIDE VIEW 0.10 C A B D2 L 0.10 C A B E2 2 K 1 NOTE 1 N 20X b 0.10 e C A B BOTTOM VIEW Microchip Technology Drawing C04-255A Sheet 1 of 2  2010-2015 Microchip Technology Inc. DS40001440E-page 429 PIC16(L)F1825/9 20-Lead Ultra Thin Plastic Quad Flat, No Lead Package (GZ) - 4x4x0.5 mm Body [UQFN] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Units Dimension Limits Number of Terminals N e Pitch Overall Height A Standoff A1 A3 Terminal Thickness Overall Width E E2 Exposed Pad Width Overall Length D D2 Exposed Pad Length Terminal Width b Terminal Length L K Terminal-to-Exposed-Pad MIN 0.45 0.00 2.60 2.60 0.20 0.30 0.20 MILLIMETERS NOM 20 0.50 BSC 0.50 0.02 0.127 REF 4.00 BSC 2.70 4.00 BSC 2.70 0.25 0.40 - MAX 0.55 0.05 2.80 2.80 0.30 0.50 - Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Package is saw singulated 3. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Microchip Technology Drawing C04-255A Sheet 2 of 2 DS40001440E-page 430  2010-2015 Microchip Technology Inc. PIC16(L)F1825/9 20-Lead Ultra Thin Plastic Quad Flat, No Lead Package (GZ) - 4x4x0.5 mm Body [UQFN] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging C1 X2 20 1 2 C2 Y2 G1 Y1 X1 E SILK SCREEN RECOMMENDED LAND PATTERN Units Dimension Limits E Contact Pitch Optional Center Pad Width X2 Optional Center Pad Length Y2 Contact Pad Spacing C1 Contact Pad Spacing C2 Contact Pad Width (X20) X1 Contact Pad Length (X20) Y1 Contact Pad to Center Pad (X20) G1 MIN MILLIMETERS NOM 0.50 BSC MAX 2.80 2.80 4.00 4.00 0.30 0.80 0.20 Notes: 1. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. Microchip Technology Drawing C04-2255A  2010-2015 Microchip Technology Inc. DS40001440E-page 431 PIC16(L)F1825/9 APPENDIX A: DATA SHEET REVISION HISTORY Revision A (08/2010) Original release. Revision B (05/2011) Revised Electrical Specifications. Revision C (06/2012) Updated the Family Types table; Updated Figures 1, 2 and 3; Updated Table 3-3; Changed all instances of SDO into SDO1, SDOSEL into SDO1SEL and SSSEL into SS1SEL; Added PIR3, PIR4, PIE3 and PIE4 to Table 3-3; Updated Register 4-2; Updated Sections 5.2.2.5 and 5.5.3; Added Note 1 to Table 11-3; Updated Figure 13-1 and Equation 16-1; Updated Section 19.9; Added charts to the DC and AC Characteristics Graphs section; Revised the Electrical Specifications section; Updated the Packaging Information section; Updated the Product Identification System section; Other minor corrections. Revision D (05/2014) Added new UQFN packages: 16-Lead, UQFN, 4x4x0.5, (JQ) and 20-Lead, UQFN, 4x4x0.5, (GZ) packages. Minor corrections. Revision E (4/2015) APPENDIX B: MIGRATING FROM OTHER PIC® DEVICES This shows a comparison of features in the migration from the PIC16F648 device to the PIC16(L)F1825/9 family of devices. This section provides comparisons when migrating from other similar PIC® devices to the PIC16(L)F1825/9 family of devices. B.1 PIC16F648A to PIC16F1825/9 TABLE B-1: FEATURE COMPARISON Feature PIC16F648A PIC16F1825/9 Max. Operating Speed 20 MHz 32 MHz Max. Program Memory (Words) 4K 8K Max. SRAM (Bytes) 256 1024 Max. EEPROM (Bytes) 256 256 A/D Resolution 10-bit 10-bit Timers (8/16-bit) 2/1 4/1 Brown-out Reset Y Y Internal Pull-ups RB PIC16F1825: RA, RC PIC16F1829: RA, RB, RC Interrupt-on-change RB PIC16F1825: RA, Edge Selectable PIC16F1829: RA, RB, Edge Selectable Added Section 30.9: High Temperature Operation in the Electrical Specifications section. Comparator AUSART/EUSART 2 0/1 Extended WDT N Y Software Control Option of WDT/BOR N Y 48 kHz or 4 MHz 31 kHz - 32 MHz Y Y INTOSC Frequencies Clock Switching Capacitive Sensing N Y 2/0 2/2 N Y MSSPx/SSPx 0 2/0 Reference Clock N Y Data Signal Modulator N Y SR Latch N Y Voltage Reference N Y DAC Y Y CCP/ECCP Enhanced PIC16 CPU DS40001440E-page 432 2 1/0  2010-2015 Microchip Technology Inc. PIC16(L)F1825/9 THE MICROCHIP WEB SITE CUSTOMER SUPPORT Microchip provides online support via our web site at www.microchip.com. This web site is used as a means to make files and information easily available to customers. Accessible by using your favorite Internet browser, the web site contains the following information: Users of Microchip products can receive assistance through several channels: • Product Support – Data sheets and errata, application notes and sample programs, design resources, user’s guides and hardware support documents, latest software releases and archived software • General Technical Support – Frequently Asked Questions (FAQ), technical support requests, online discussion groups, Microchip consultant program member listing • Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives • • • • Distributor or Representative Local Sales Office Field Application Engineer (FAE) Technical Support Customers should contact their distributor, representative or Field Application Engineer (FAE) for support. Local sales offices are also available to help customers. A listing of sales offices and locations is included in the back of this document. Technical support is available through the web site at: http://www.microchip.com/support CUSTOMER CHANGE NOTIFICATION SERVICE Microchip’s customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, access the Microchip web site at www.microchip.com. Under “Support”, click on “Customer Change Notification” and follow the registration instructions.  2010-2015 Microchip Technology Inc. DS40001440E-page 433 PIC16(L)F1825/1829 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. Device [X] - Tape and Reel Option X /XX XXX Temperature Range Package Pattern PIC16F1825, PIC16LF1825 PIC16F1829T, PIC16LF1829 Tape and Reel Option: Blank = Standard packaging (tube or tray) T = Tape and Reel(1) Temperature Range: I E Package:(2) GZ JQ ML P SL SO SS ST Pattern: = = = = = = = = b) PIC16F1825 - E/SL 301 = Extended temp., SOIC package, QTP pattern #301. PIC16LF1829 - E/SS = Extended temp., SSOP package. PIC16LF1829 - E/ML= Extended temp., QFN package. (Industrial) (Extended) UQFN, 20-lead (4x4x0.5mm) UQFN, 16-lead (4x4x0.5mm) QFN, 16-lead, 20-lead (4x4x0.9mm) Plastic DIP SOIC, 14-lead SOIC, 20-lead SSOP, 20-lead TSSOP, 14-lead QTP, SQTP, Code or Special Requirements (blank otherwise) DS40001440E-page 434 a) c) Device: = -40C to +85C = -40C to +125C Examples: Note 1: 2: Tape and Reel identifier only appears in the catalog part number description. This identifier is used for ordering purposes and is not printed on the device package. Check with your Microchip Sales Office for package availability with the Tape and Reel option. For other small form-factor package availability and marking information, please visit www.microchip.com/packaging or contact your local sales office.  2010-2015 Microchip Technology Inc. Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, dsPIC, FlashFlex, flexPWR, JukeBlox, KEELOQ, KEELOQ logo, Kleer, LANCheck, MediaLB, MOST, MOST logo, MPLAB, OptoLyzer, PIC, PICSTART, PIC32 logo, RightTouch, SpyNIC, SST, SST Logo, SuperFlash and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. The Embedded Control Solutions Company and mTouch are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, BodyCom, chipKIT, chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net, ECAN, In-Circuit Serial Programming, ICSP, Inter-Chip Connectivity, KleerNet, KleerNet logo, MiWi, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, RightTouch logo, REAL ICE, SQI, Serial Quad I/O, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries. GestIC is a registered trademarks of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. © 2010-2015, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. ISBN: 978-1-63277-254-1 QUALITY MANAGEMENT SYSTEM CERTIFIED BY DNV == ISO/TS 16949 ==  2010-2015 Microchip Technology Inc. Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. DS40001440E-page 435 Worldwide Sales and Service AMERICAS ASIA/PACIFIC ASIA/PACIFIC EUROPE Corporate Office 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: http://www.microchip.com/ support Web Address: www.microchip.com Asia Pacific Office Suites 3707-14, 37th Floor Tower 6, The Gateway Harbour City, Kowloon China - Xiamen Tel: 86-592-2388138 Fax: 86-592-2388130 Austria - Wels Tel: 43-7242-2244-39 Fax: 43-7242-2244-393 China - Zhuhai Tel: 86-756-3210040 Fax: 86-756-3210049 Denmark - Copenhagen Tel: 45-4450-2828 Fax: 45-4485-2829 India - Bangalore Tel: 91-80-3090-4444 Fax: 91-80-3090-4123 France - Paris Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79 India - New Delhi Tel: 91-11-4160-8631 Fax: 91-11-4160-8632 Germany - Dusseldorf Tel: 49-2129-3766400 Atlanta Duluth, GA Tel: 678-957-9614 Fax: 678-957-1455 Hong Kong Tel: 852-2943-5100 Fax: 852-2401-3431 Australia - Sydney Tel: 61-2-9868-6733 Fax: 61-2-9868-6755 China - Beijing Tel: 86-10-8569-7000 Fax: 86-10-8528-2104 Austin, TX Tel: 512-257-3370 China - Chengdu Tel: 86-28-8665-5511 Fax: 86-28-8665-7889 Boston Westborough, MA Tel: 774-760-0087 Fax: 774-760-0088 China - Chongqing Tel: 86-23-8980-9588 Fax: 86-23-8980-9500 Chicago Itasca, IL Tel: 630-285-0071 Fax: 630-285-0075 Cleveland Independence, OH Tel: 216-447-0464 Fax: 216-447-0643 Dallas Addison, TX Tel: 972-818-7423 Fax: 972-818-2924 Detroit Novi, MI Tel: 248-848-4000 Houston, TX Tel: 281-894-5983 Indianapolis Noblesville, IN Tel: 317-773-8323 Fax: 317-773-5453 Los Angeles Mission Viejo, CA Tel: 949-462-9523 Fax: 949-462-9608 New York, NY Tel: 631-435-6000 San Jose, CA Tel: 408-735-9110 Canada - Toronto Tel: 905-673-0699 Fax: 905-673-6509 China - Dongguan Tel: 86-769-8702-9880 China - Hangzhou Tel: 86-571-8792-8115 Fax: 86-571-8792-8116 Germany - Munich Tel: 49-89-627-144-0 Fax: 49-89-627-144-44 India - Pune Tel: 91-20-3019-1500 Japan - Osaka Tel: 81-6-6152-7160 Fax: 81-6-6152-9310 Germany - Pforzheim Tel: 49-7231-424750 Italy - Milan Tel: 39-0331-742611 Fax: 39-0331-466781 Japan - Tokyo Tel: 81-3-6880- 3770 Fax: 81-3-6880-3771 Italy - Venice Tel: 39-049-7625286 Korea - Daegu Tel: 82-53-744-4301 Fax: 82-53-744-4302 Netherlands - Drunen Tel: 31-416-690399 Fax: 31-416-690340 China - Hong Kong SAR Tel: 852-2943-5100 Fax: 852-2401-3431 Korea - Seoul Tel: 82-2-554-7200 Fax: 82-2-558-5932 or 82-2-558-5934 China - Nanjing Tel: 86-25-8473-2460 Fax: 86-25-8473-2470 Malaysia - Kuala Lumpur Tel: 60-3-6201-9857 Fax: 60-3-6201-9859 China - Qingdao Tel: 86-532-8502-7355 Fax: 86-532-8502-7205 Malaysia - Penang Tel: 60-4-227-8870 Fax: 60-4-227-4068 China - Shanghai Tel: 86-21-5407-5533 Fax: 86-21-5407-5066 Philippines - Manila Tel: 63-2-634-9065 Fax: 63-2-634-9069 China - Shenyang Tel: 86-24-2334-2829 Fax: 86-24-2334-2393 Singapore Tel: 65-6334-8870 Fax: 65-6334-8850 China - Shenzhen Tel: 86-755-8864-2200 Fax: 86-755-8203-1760 Taiwan - Hsin Chu Tel: 886-3-5778-366 Fax: 886-3-5770-955 China - Wuhan Tel: 86-27-5980-5300 Fax: 86-27-5980-5118 Taiwan - Kaohsiung Tel: 886-7-213-7828 China - Xian Tel: 86-29-8833-7252 Fax: 86-29-8833-7256 Poland - Warsaw Tel: 48-22-3325737 Spain - Madrid Tel: 34-91-708-08-90 Fax: 34-91-708-08-91 Sweden - Stockholm Tel: 46-8-5090-4654 UK - Wokingham Tel: 44-118-921-5800 Fax: 44-118-921-5820 Taiwan - Taipei Tel: 886-2-2508-8600 Fax: 886-2-2508-0102 Thailand - Bangkok Tel: 66-2-694-1351 Fax: 66-2-694-1350 01/27/15 DS40001440E-page 436  2010-2015 Microchip Technology Inc.