v1.3
IGLOO Low-Power Flash FPGAs
with Flash*Freeze Technology Features and Benefits
Low Power
• • • • • 1.2 V to 1.5 V Core Voltage Support for Low Power Supports Single-Voltage System Operation 5 µW Power Consumption in Flash*Freeze Mode Low-Power Active FPGA Operation Flash*Freeze Technology Enables Ultra-Low Power Consumption while Maintaining FPGA Content • Easy Entry to / Exit from Ultra-Low-Power Flash*Freeze Mode
®
Advanced I/O
• • • • • • • • • • • 700 Mbps DDR, LVDS-Capable I/Os (AGL250 and above) 1.2 V, 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation Bank-Selectable I/O Voltages—up to 4 Banks per Chip Single-Ended I/O Standards: LVTTL, LVCMOS 3.3 V / 2.5 V / 1.8 V / 1.5 V / 1.2 V, 3.3 V PCI / 3.3 V PCI-X1, and LVCMOS 2.5 V / 5.0 V Input1 Differential I/O Standards: LVPECL, LVDS, B-LVDS, and MLVDS (AGL250 and above) I/O Registers on Input, Output, and Enable Paths Hot-Swappable and Cold-Sparing I/Os‡ Programmable Output Slew Rate1 and Drive Strength Weak Pull-Up/-Down IEEE 1149.1 (JTAG) Boundary Scan Test Pin-Compatible Packages across the IGLOO Family 1
High Capacity
• 15 k to 1 Million System Gates • Up to 144 kbits of True Dual-Port SRAM • Up to 300 User I/Os
Reprogrammable Flash Technology
• • • • 130-nm, 7-Layer Metal, Flash-Based CMOS Process Live-at-Power-Up (LAPU) Level 0 Support Single-Chip Solution Retains Programmed Design When Powered Off
Clock Conditioning Circuit (CCC) and PLL
In-System Programming (ISP) and Security
• Secure ISP Using On-Chip 128-Bit Advanced Encryption Standard (AES) Decryption (except ARM®-enabled IGLOO® devices) via JTAG (IEEE 1532–compliant)1 • FlashLock® to Secure FPGA Contents
• Six CCC Blocks, One with an Integrated PLL • Configurable Phase Shift, Multiply/Divide, Delay Capabilities, and External Feedback • Wide Input Frequency Range (1.5 MHz up to 250 MHz)
Embedded Memory
• 1 kbit of FlashROM User Nonvolatile Memory 1 • SRAMs and FIFOs with Variable-Aspect-Ratio 4,608-Bit RAM Blocks (×1, ×2, ×4, ×9, and ×18 organizations) 1 • True Dual-Port SRAM (except ×18)
High-Performance Routing Hierarchy
• Segmented, Hierarchical Routing and Clock Structure
ARM Processor Support in IGLOO FPGAs
• M1 IGLOO Devices—Cortex™-M1 Soft Processor Available with or without Debug AGL060 60 k 512 1,536 10 18 4 1k Yes 1 18 2 96 CS121 QN132 VQ100 FG144 5 AGL125 125 k 1,024 3,072 16 36 8 1k Yes 1 18 2 133 CS196 QN132 VQ100 FG144 AGL250 AGL400 AGL600 AGL1000 M1AGL250 M1AGL400 M1AGL600 M1AGL1000 250 k 400 k 600 k 1M 2,048 – – – 6,144 9,216 13,824 24,576 24 36 53 32 36 54 108 144 8 12 24 32 1k 1k 1k 1k Yes Yes Yes Yes 1 1 1 1 18 18 18 18 4 4 4 4 143 194 235 300 CS196 4 QN132 4,5 VQ100 FG144 CS196 CS281 CS281
IGLOO Product Family
IGLOO Devices ARM-Enabled IGLOO Devices System Gates Typical Equivalent Macrocells VersaTiles (D-flip-flops) Flash*Freeze Mode (typical, µW) RAM kbits (1,024 bits) 4,608-Bit Blocks FlashROM Bits Secure (AES) ISP 1 Integrated PLL in CCCs 2 VersaNet Globals 3 I/O Banks Maximum User I/Os Package Pins UC/CS QFN VQFP FBGA AGL015 15 k 128 384 5 – – 1k – – 6 2 49 QN68 AGL030 30 k 256 768 5 – – 1k – – 6 2 81 UC81/CS81 QN48, QN68, QN132 VQ100
FG144, FG256, FG484
FG144, FG256, FG484
FG144, FG256, FG484
Notes: 1. AES is not available for ARM-enabled IGLOO devices.
2. 3. 4. 5. 6.
AGL060 in CS121 does not support the PLL. Six chip (main) and twelve quadrant global networks are available for AGL060 and above. The M1AGL250 device does not support this package. Device/package support TBD For higher densities and support of additional features, refer to the IGLOOe Low-Power Flash FPGAs with Flash*Freeze Technology handbook.
‡ Supported only by AGL015 and AGL030 devices.
I
1 AGL015 and AGL030 devices do not support this feature.
December 2008 © 2008 Actel Corporation
IGLOO Low-Power Flash FPGAs
I/Os Per Package1
IGLOO Devices ARM-Enabled IGLOO Devices AGL015 AGL030 AGL060 AGL125 AGL250 M1AGL250 3 I/O Type Differential I/O Pairs Differential I/O Pairs Differential I/O Pairs Differential I/O Pairs – – – – – – – – 25 44 53 74 FG484 23 × 23 529 1.0 2.23 Single-Ended I/O 2 Single-Ended I/O 2 Single-Ended I/O 2 Single-Ended I/O 2 – – – – – – – – 97 177 215 300 FG256 17 × 17 289 1.0 1.60 AGL400 M1AGL400 AGL600 M1AGL600 AGL1000 M1AGL1000
Single-Ended I/O
Single-Ended I/O
Single-Ended I/O
Package QN48 QN68 UC81 CS81 CS121 VQ100 QN132 CS196 FG144 FG256 CS281 FG484 Notes:
– 49 – – – – – – – – – –
34 49 66 66 – 77 81 – – – – –
– – – – 96 71 80 – 96 7 – – –
Single-Ended I/O – – – – – 71 84 133 97 – – –
– – – – – 68 87
7
– – – – – 13 19
7
– – – – – – – 143 97 178 – 194
– – – – – – – 35 25 38 – 38
– – – – – – – – 97 177 215 235
– – – – – – – – 25 43 53 60
143 97 – – –
35 24 – – –
1. When considering migrating your design to a lower- or higher-density device, refer to the IGLOO Low-Power Flash FPGAs handbook to ensure compliance with design and board migration requirements.
2. Each used differential I/O pair reduces the number of single-ended I/Os available by two. 3. The M1AGL250 device does not support QN132 or CS196 packages. Refer to the IGLOO Low-Power Flash FPGAs handbook for position assignments of the 15 LVPECL pairs. 4. FG256 and FG484 are footprint-compatible packages. 5. When the Flash*Freeze pin is used to directly enable Flash*Freeze mode and not used as a regular I/O, the number of single-ended user I/Os available is reduced by one. 6. "G" indicates RoHS-compliant packages. Refer to "IGLOO Ordering Information" on page III for the location of the "G" in the part number. 7. Device/package support TBD. IGLOO FPGAs Package Sizes Dimensions Package Length × (mm\mm) Nominal Area (mm2) Pitch (mm) Height (mm) UC81 Width 4 × 4 16 0.4 0.80 CS81 5×5 25 0.5 0.80 CS121 6×6 36 0.5 0.99 QN68 8×8 64 0.4 0.90 QN132 8×8 64 0.5 0.75 CS196 8×8 64 0.5 1.20 CS281 10 × 10 100 0.5 1.05 FG144 13 × 13 169 1.0 1.45 VQ100 14 × 14 196 0.5 1.00
II
v1.3
IGLOO Low-Power Flash FPGAs
IGLOO Ordering Information
AGL1000 V2 _ FG G 144 I Application (Temperature Range) Blank = Commercial (0°C to +70°C Ambient Temperature) I = Industrial (–40°C to +85°C Ambient Temperature) PP = Pre-Production ES = Engineering Sample (Room Temperature Only) Package Lead Count Lead-Free Packaging Blank = Standard Packaging G = RoHS-Compliant Packaging Package Type UC = Micro Chip Scale Package (0.4 mm pitch) CS = Chip Scale Package (0.4 mm and 0.5 mm pitches) QN = Quad Flat Pack No Leads (0.4 mm and 0.5 mm pitch) VQ = Very Thin Quad Flat Pack (0.5 mm pitch) FG = Fine Pitch Ball Grid Array (1.0 mm pitch) Speed Grade F = 20% Slower than Standard* Blank = Standard Supply Voltage 2 = 1.2 V to 1.5 V 5 = 1.5 V only Part Number IGLOO Devices AGL015 = 15,000 System Gates AGL030 = 30,000 System Gates AGL060 = 60,000 System Gates AGL125 = 125,000 System Gates AGL250 = 250,000 System Gates AGL400 = 400,000 System Gates AGL600 = 600,000 System Gates AGL1000 = 1,000,000 System Gates IGLOO Devices with Cortex-M1 M1AGL250 = M1AGL400 = M1AGL600 = M1AGL1000= 250,000 System Gates 400,000 System Gates 600,000 System Gates 1,000,000 System Gates
Notes:
1. Marking Information: IGLOO V2 devices do not have V2 marking, but IGLOO V5 devices are marked accordingly.
2. The DC and switching characteristics for the –F speed grade targets are based only on simulation. The characteristics provided for the –F speed grade are subject to change after establishing FPGA specifications. Some restrictions might be added and will be reflected in future revisions of this document. The –F speed grade is only supported in the commercial temperature range.
v1.3
III
IGLOO Low-Power Flash FPGAs
Temperature Grade Offerings
AGL015 Package QN48 QN68 UC81 CS81 CS121 VQ100 QN132 CS196 FG144 FG256 CS281 FG484 Notes:
1. C = Commercial temperature range: 0°C to 70°C ambient temperature.
AGL030
AGL060
AGL125
AGL250
AGL400
AGL600
AGL1000
M1AGL250 4 M1AGL400 – C, I – – – – – – – – – – C, I – C, I C, I – C, I C, I – – – – – – – – – C, I C, I C, I – C, I3
3
M1AGL600 M1AGL1000 – – – – – – – – C, I C, I C, I C, I – – – – – – – – C, I C, I C, I C, I
– – – – – C, I C, I C, I C, I – – –
– – – – – C, I C, I C, I C, I – – –
3
– – – – – – – C, I C, I C, I – C, I
– – –
2. I = Industrial temperature range: –40°C to 85°C ambient temperature. 3. Device/package support TBD. 4. The M1AGL250 device does not support FG256 or QN132 packages.
Speed Grade and Temperature Grade Matrix
Temperature Grade C2 I
3
–F 1
Std.
✓
–
✓ ✓
Notes:
1. The characteristics provided for the –F speed grade are subject to change after establishing FPGA specifications. Some restrictions might be added and will be reflected in future revisions of this document. The –F speed grade is only supported in the commercial temperature range.
2. C = Commercial temperature range: 0°C to 70°C ambient temperature. 3. I = Industrial temperature range: –40°C to 85°C ambient temperature. References made to IGLOO devices also apply to ARM-enabled IGLOOe devices. The ARM-enabled part numbers start with M1 (Cortex-M1). Contact your local Actel representative for device availability: http://www.actel.com/contact/default.aspx.
AGL015 and AGL030
The AGL015 and AGL030 are architecturally compatible; there are no RAM or PLL features.
IV
v1.3
1 – IGLOO Device Family Overview
General Description
The IGLOO family of flash FPGAs, based on a 130-nm flash process, offers the lowest power FPGA, a single-chip solution, small footprint packages, reprogrammability, and an abundance of advanced features. The Flash*Freeze technology used in IGLOO devices enables entering and exiting an ultra-lowpower mode that consumes as little as 5 µW while retaining SRAM and register data. Flash*Freeze technology simplifies power management through I/O and clock management with rapid recovery to operation mode. The Low Power Active capability (static idle) allows for ultra-low-power consumption (from 12 µW) while the IGLOO device is completely functional in the system. This allows the IGLOO device to control system power management based on external inputs (e.g., scanning for keyboard stimulus) while consuming minimal power. Nonvolatile flash technology gives IGLOO devices the advantage of being a secure, low power, single-chip solution that is live at power-up (LAPU). IGLOO is reprogrammable and offers time-tomarket benefits at an ASIC-level unit cost. These features enable designers to create high-density systems using existing ASIC or FPGA design flows and tools. IGLOO devices offer 1 kbit of on-chip, reprogrammable, nonvolatile FlashROM storage as well as clock conditioning circuitry based on an integrated phase-locked loop (PLL). The AGL015 and AGL030 devices have no PLL or RAM support. IGLOO devices have up to 1 million system gates, supported with up to 144 kbits of true dual-port SRAM and up to 300 user I/Os. M1 IGLOO devices support the high-performance, 32-bit Cortex-M1 processor developed by ARM for implementation in FPGAs. Cortex-M1 is a soft processor that is fully implemented in the FPGA fabric. It has a three-stage pipeline that offers a good balance between low-power consumption and speed when implemented in an M1 IGLOO device. The processor runs the ARMv6-M instruction set, has a configurable nested interrupt controller, and can be implemented with or without the debug block. Cortex-M1 is available for free from Actel for use in M1 IGLOO FPGAs. The ARM-enabled devices have Actel ordering numbers that begin with M1AGL and do not support AES decryption.
Flash*Freeze Technology
The IGLOO device offers unique Flash*Freeze technology, allowing the device to enter and exit ultra-low-power Flash*Freeze mode. IGLOO devices do not need additional components to turn off I/Os or clocks while retaining the design information, SRAM content, and registers. Flash*Freeze technology is combined with in-system programmability, which enables users to quickly and easily upgrade and update their designs in the final stages of manufacturing or in the field. The ability of IGLOO V2 devices to support a wide range of core voltage (1.2 V to 1.5 V) allows further reduction in power consumption, thus achieving the lowest total system power. When the IGLOO device enters Flash*Freeze mode, the device automatically shuts off the clocks and inputs to the FPGA core; when the device exits Flash*Freeze mode, all activity resumes and data is retained. The availability of low-power modes, combined with reprogrammability, a single-chip and singlevoltage solution, and availability of small-footprint, high pin-count packages, make IGLOO devices the best fit for portable electronics.
v 1.3
1-1
IGLOO Device Family Overview
Flash Advantages
Low Power
Flash-based IGLOO devices exhibit power characteristics similar to those of an ASIC, making them an ideal choice for power-sensitive applications. IGLOO devices have only a very limited power-on current surge and no high-current transition period, both of which occur on many FPGAs. IGLOO devices also have low dynamic power consumption to further maximize power savings; power is even further reduced by the use of a 1.2 V core voltage. Low dynamic power consumption, combined with low static power consumption and Flash*Freeze technology, gives the IGLOO device the lowest total system power offered by any FPGA.
Security
The nonvolatile, flash-based IGLOO devices do not require a boot PROM, so there is no vulnerable external bitstream that can be easily copied. IGLOO devices incorporate FlashLock, which provides a unique combination of reprogrammability and design security without external overhead, advantages that only an FPGA with nonvolatile flash programming can offer. IGLOO devices utilize a 128-bit flash-based lock and a separate AES key to secure programmed intellectual property and configuration data. In addition, all FlashROM data in IGLOO devices can be encrypted prior to loading, using the industry-leading AES-128 (FIPS192) bit block cipher encryption standard. AES was adopted by the National Institute of Standards and Technology (NIST) in 2000 and replaces the 1977 DES standard. IGLOO devices have a built-in AES decryption engine and a flash-based AES key that make them the most comprehensive programmable logic device security solution available today. IGLOO devices with AES-based security allow for secure, remote field updates over public networks such as the Internet, and ensure that valuable IP remains out of the hands of system overbuilders, system cloners, and IP thieves. The contents of a programmed IGLOO device cannot be read back, although secure design verification is possible. Security, built into the FPGA fabric, is an inherent component of the IGLOO family. The flash cells are located beneath seven metal layers, and many device design and layout techniques have been used to make invasive attacks extremely difficult. The IGLOO family, with FlashLock and AES security, is unique in being highly resistant to both invasive and noninvasive attacks. Your valuable IP is protected and secure, making remote ISP possible. An IGLOO device provides the most impenetrable security for programmable logic designs.
Single Chip
Flash-based FPGAs store their configuration information in on-chip flash cells. Once programmed, the configuration data is an inherent part of the FPGA structure, and no external configuration data needs to be loaded at system power-up (unlike SRAM-based FPGAs). Therefore, flash-based IGLOO FPGAs do not require system configuration components such as EEPROMs or microcontrollers to load device configuration data. This reduces bill-of-materials costs and PCB area, and increases security and system reliability.
Live at Power-Up
The Actel flash-based IGLOO devices support Level 0 of the LAPU classification standard. This feature helps in system component initialization, execution of critical tasks before the processor wakes up, setup and configuration of memory blocks, clock generation, and bus activity management. The LAPU feature of flash-based IGLOO devices greatly simplifies total system design and reduces total system cost, often eliminating the need for CPLDs and clock generation PLLs. In addition, glitches and brownouts in system power will not corrupt the IGLOO device's flash configuration, and unlike SRAM-based FPGAs, the device will not have to be reloaded when system power is restored. This enables the reduction or complete removal of the configuration PROM, expensive voltage monitor, brownout detection, and clock generator devices from the PCB design. Flash-based IGLOO devices simplify total system design and reduce cost and design risk while increasing system reliability and improving system initialization time. IGLOO flash FPGAs allow the user to quickly enter and exit Flash*Freeze mode. This is done almost instantly (within 1 µs) and the device retains configuration and data in registers and RAM. Unlike SRAM-based FPGAs the device does not need to reload configuration and design state from
1 -2
v1.3
IGLOO Low-Power Flash FPGAs external memory components; instead it retains all necessary information to resume operation immediately.
Reduced Cost of Ownership
Advantages to the designer extend beyond low unit cost, performance, and ease of use. Unlike SRAM-based FPGAs, Flash-based IGLOO devices allow all functionality to be live at power-up; no external boot PROM is required. On-board security mechanisms prevent access to all the programming information and enable secure remote updates of the FPGA logic. Designers can perform secure remote in-system reprogramming to support future design iterations and field upgrades with confidence that valuable intellectual property cannot be compromised or copied. Secure ISP can be performed using the industry-standard AES algorithm. The IGLOO family device architecture mitigates the need for ASIC migration at higher user volumes. This makes the IGLOO family a cost-effective ASIC replacement solution, especially for applications in the consumer, networking/communications, computing, and avionics markets.
Firm-Error Immunity
Firm errors occur most commonly when high-energy neutrons, generated in the upper atmosphere, strike a configuration cell of an SRAM FPGA. The energy of the collision can change the state of the configuration cell and thus change the logic, routing, or I/O behavior in an unpredictable way. These errors are impossible to prevent in SRAM FPGAs. The consequence of this type of error can be a complete system failure. Firm errors do not exist in the configuration memory of IGLOO flashbased FPGAs. Once it is programmed, the flash cell configuration element of IGLOO FPGAs cannot be altered by high-energy neutrons and is therefore immune to them. Recoverable (or soft) errors occur in the user data SRAM of all FPGA devices. These can easily be mitigated by using error detection and correction (EDAC) circuitry built into the FPGA fabric.
Advanced Flash Technology
The IGLOO family offers many benefits, including nonvolatility and reprogrammability, through an advanced flash-based, 130-nm LVCMOS process with seven layers of metal. Standard CMOS design techniques are used to implement logic and control functions. The combination of fine granularity, enhanced flexible routing resources, and abundant flash switches allows for very high logic utilization without compromising device routability or performance. Logic functions within the device are interconnected through a four-level routing hierarchy. IGLOO family FPGAs utilize design and process techniques to minimize power consumption in all modes of operation.
Advanced Architecture
The proprietary IGLOO architecture provides granularity comparable to standard-cell ASICs. The IGLOO device consists of five distinct and programmable architectural features (Figure 1-1 on page 1-4 and Figure 1-2 on page 1-4): • • • • • • Flash*Freeze technology FPGA VersaTiles Dedicated FlashROM Dedicated SRAM/FIFO memory† Extensive CCCs and PLLs† Advanced I/O structure
The FPGA core consists of a sea of VersaTiles. Each VersaTile can be configured as a three-input logic function, a D-flip-flop (with or without enable), or a latch by programming the appropriate flash switch interconnections. The versatility of the IGLOO core tile as either a three-input lookup table (LUT) equivalent or a D-flip-flop/latch with enable allows for efficient use of the FPGA fabric. The VersaTile capability is unique to the Actel ProASIC® family of third-generation-architecture flash FPGAs. VersaTiles are connected with any of the four levels of routing hierarchy. Flash switches are distributed throughout the device to provide nonvolatile, reconfigurable interconnect programming. Maximum core utilization is possible for virtually any design.
†
The AGL015 and AGL030 do not support PLL or SRAM.
v1.3
1-3
IGLOO Device Family Overview In addition, extensive on-chip programming circuitry allows for rapid, single-voltage (3.3 V) programming of IGLOO devices via an IEEE 1532 JTAG interface.
Bank 0
CCC RAM Block 4,608-Bit Dual-Port SRAM or FIFO Block*
Bank 1
Bank 0 Bank 0
I/Os
VersaTile
Bank 1
ISP AES Decryption*
User Nonvolatile FlashRom
Flash*Freeze Technology
Charge Pumps
Bank 1
* Not supported by AGL015 and AGL030 devices Figure 1-1 • IGLOO Device Architecture Overview with Two I/O Banks (AGL015, AGL030, AGL060, and AGL125)
Bank 0
CCC RAM Block 4,608-Bit Dual-Port SRAM or FIFO Block
Bank 3
Bank 1 Bank 1
I/Os
VersaTile
Bank 3
ISP AES Decryption*
User Nonvolatile FlashRom
Flash*Freeze Technology
Charge Pumps
RAM Block 4,608-Bit Dual-Port SRAM or FIFO Block (AGL600 and AGL1000)
Bank 2
Figure 1-2 • IGLOO Device Architecture Overview with Four I/O Banks (AGL250, AGL600, AGL400, and AGL1000)
1 -4
v1.3
IGLOO Low-Power Flash FPGAs
Flash*Freeze Technology
The IGLOO device has an ultra-low power static mode, called Flash*Freeze mode, which retains all SRAM and register information and can still quickly return to normal operation. Flash*Freeze technology enables the user to quickly (within 1 µs) enter and exit Flash*Freeze mode by activating the Flash*Freeze pin while all power supplies are kept at their original values. In addition, I/Os and global I/Os can still be driven and can be toggling without impact on power consumption, clocks can still be driven or can be toggling without impact on power consumption, and the device retains all core registers, SRAM information, and states. I/O states are tristated during Flash*Freeze mode or can be set to a certain state using weak pull-up or pull-down I/O attribute configuration. No power is consumed by the I/O banks, clocks, JTAG pins, or PLL, and the device consumes as little as 5 µW in this mode. Flash*Freeze technology allows the user to switch to active mode on demand, thus simplifying the power management of the device. The Flash*Freeze pin (active low) can be routed internally to the core to allow the user's logic to decide when it is safe to transition to this mode. It is also possible to use the Flash*Freeze pin as a regular I/O if Flash*Freeze mode usage is not planned, which is advantageous because of the inherent low power static (as low as 12 µW) and dynamic capabilities of the IGLOO device. Refer to Figure 1-3 for an illustration of entering/exiting Flash*Freeze mode.
Flash*Freeze Mode Control
Actel IGLOOe FPGA
Flash*Freeze Pin
Figure 1-3 • IGLOO Flash*Freeze Mode
VersaTiles
The IGLOO core consists of VersaTiles, which have been enhanced beyond the ProASICPLUS® core tiles. The IGLOO VersaTile supports the following: • • • • All 3-input logic functions—LUT-3 equivalent Latch with clear or set D-flip-flop with clear or set Enable D-flip-flop with clear or set
Refer to Figure 1-4 for VersaTile configurations.
LUT-3 Equivalent X1 X2 X3
D-Flip-Flop with Clear or Set Data CLK CLR Y D-FF
Enable D-Flip-Flop with Clear or Set Data CLK Enable CLR D-FF Y
LUT-3
Y
Figure 1-4 • VersaTile Configurations
v1.3
1-5
IGLOO Device Family Overview
User Nonvolatile FlashROM
Actel IGLOO devices have 1 kbit of on-chip, user-accessible, nonvolatile FlashROM. The FlashROM can be used in diverse system applications: • • • • • • • • Internet protocol addressing (wireless or fixed) System calibration settings Device serialization and/or inventory control Subscription-based business models (for example, set-top boxes) Secure key storage for secure communications algorithms Asset management/tracking Date stamping Version management
The FlashROM is written using the standard IGLOO IEEE 1532 JTAG programming interface. The core can be individually programmed (erased and written), and on-chip AES decryption can be used selectively to securely load data over public networks (except in the AGL015 and AGL030 devices), as in security keys stored in the FlashROM for a user design. The FlashROM can be programmed via the JTAG programming interface, and its contents can be read back either through the JTAG programming interface or via direct FPGA core addressing. Note that the FlashROM can only be programmed from the JTAG interface and cannot be programmed from the internal logic array. The FlashROM is programmed as 8 banks of 128 bits; however, reading is performed on a byte-bybyte basis using a synchronous interface. A 7-bit address from the FPGA core defines which of the 8 banks and which of the 16 bytes within that bank are being read. The three most significant bits (MSBs) of the FlashROM address determine the bank, and the four least significant bits (LSBs) of the FlashROM address define the byte. The Actel IGLOO development software solutions, Libero® Integrated Design Environment (IDE) and Designer, have extensive support for the FlashROM. One such feature is auto-generation of sequential programming files for applications requiring a unique serial number in each part. Another feature allows the inclusion of static data for system version control. Data for the FlashROM can be generated quickly and easily using Actel Libero IDE and Designer software tools. Comprehensive programming file support is also included to allow for easy programming of large numbers of parts with differing FlashROM contents.
SRAM and FIFO
IGLOO devices (except the AGL015 and AGL030 devices) have embedded SRAM blocks along their north and south sides. Each variable-aspect-ratio SRAM block is 4,608 bits in size. Available memory configurations are 256×18, 512×9, 1k×4, 2k×2, and 4k×1 bits. The individual blocks have independent read and write ports that can be configured with different bit widths on each port. For example, data can be sent through a 4-bit port and read as a single bitstream. The embedded SRAM blocks can be initialized via the device JTAG port (ROM emulation mode) using the UJTAG macro (except in the AGL015 and AGL030 devices). In addition, every SRAM block has an embedded FIFO control unit. The control unit allows the SRAM block to be configured as a synchronous FIFO without using additional core VersaTiles. The FIFO width and depth are programmable. The FIFO also features programmable Almost Empty (AEMPTY) and Almost Full (AFULL) flags in addition to the normal Empty and Full flags. The embedded FIFO control unit contains the counters necessary for generation of the read and write address pointers. The embedded SRAM/FIFO blocks can be cascaded to create larger configurations.
PLL and CCC
IGLOO devices provide designers with very flexible clock conditioning circuit (CCC) capabilities. Each member of the IGLOO family contains six CCCs. One CCC (center west side) has a PLL. The AGL015 and AGL030 do not have a PLL. The six CCC blocks are located at the four corners and the centers of the east and west sides. One CCC (center west side) has a PLL.
1 -6
v1.3
IGLOO Low-Power Flash FPGAs All six CCC blocks are usable; the four corner CCCs and the east CCC allow simple clock delay operations as well as clock spine access. The inputs of the six CCC blocks are accessible from the FPGA core or from one of several inputs located near the CCC that have dedicated connections to the CCC block. The CCC block has these key features: • • • • • • • • • • Wide input frequency range (fIN_CCC) = 1.5 MHz up to 250 MHz Output frequency range (fOUT_CCC) = 0.75 MHz up to 250 MHz 2 programmable delay types for clock skew minimization Clock frequency synthesis (for PLL only) Internal phase shift = 0°, 90°, 180°, and 270°. Output phase shift depends on the output divider configuration (for PLL only). Output duty cycle = 50% ± 1.5% or better (for PLL only) Low output jitter: worst case < 2.5% × clock period peak-to-peak period jitter when single global network used (for PLL only) Maximum acquisition time is 300 µs (for PLL only) Exceptional tolerance to input period jitter—allowable input jitter is up to 1.5 ns (for PLL only) Four precise phases; maximum misalignment between adjacent phases of 40 ps × 250 MHz / fOUT_CCC (for PLL only)
Additional CCC specifications:
Global Clocking
IGLOO devices have extensive support for multiple clocking domains. In addition to the CCC and PLL support described above, there is a comprehensive global clock distribution network. Each VersaTile input and output port has access to nine VersaNets: six chip (main) and three quadrant global networks. The VersaNets can be driven by the CCC or directly accessed from the core via multiplexers (MUXes). The VersaNets can be used to distribute low-skew clock signals or for rapid distribution of high-fanout nets.
I/Os with Advanced I/O Standards
The IGLOO family of FPGAs features a flexible I/O structure, supporting a range of voltages (1.2 V, 1.5 V, 1.8 V, 2.5 V, and 3.3 V). IGLOO FPGAs support many different I/O standards—single-ended and differential. The I/Os are organized into banks, with two or four banks per device. The configuration of these banks determines the I/O standards supported. Each I/O module contains several input, output, and enable registers. These registers allow the implementation of the following: • • Single-Data-Rate applications Double-Data-Rate applications—DDR LVDS, B-LVDS, and M-LVDS I/Os for point-to-point communications
IGLOO banks for the AGL250 device and above support LVPECL, LVDS, B-LVDS, and M-LVDS. B-LVDS and M-LVDS can support up to 20 loads.
v1.3
1-7
IGLOO Device Family Overview
Part Number and Revision Date
Part Number 51700095-001-6 Revised December 2008
List of Changes
The following table lists critical changes that were made in the current version of the document. Previous Version v1.2 (October 2008) Changes in Current Version (v1.3) QN48 and QN68 were added to the AGL030 for the following tables: "IGLOO Product Family" "IGLOO Ordering Information" "Temperature Grade Offerings" QN132 is fully supported by AGL125 so footnote 3 was removed. v1.1 (July 2008) This document was updated to include AGL400 device information. The following sections were updated: "IGLOO Product Family" "IGLOO Ordering Information" "Temperature Grade Offerings" "IGLOO Product Family" Figure 1-2 · IGLOO Device Architecture Overview with Four I/O Banks (AGL250, AGL600, AGL400, and AGL1000) v1.0 (March 2008) 51700095-001-3 (March 2008) As a result of the Libero IDE v8.4 release, Actel now offers a wide range of core voltage support. The document was updated to change 1.2 V / 1.5 V to 1.2 V to 1.5 V. This document was divided into two sections and given a version number, starting at v1.0. The first section of the document includes features, benefits, ordering information, and temperature and speed grade offerings. The second section is a device family overview. The "Low Power" section was updated to change "1.2 V and 1.5 V Core Voltage" to "1.2 V and 1.5 V Core and I/O Voltage." The text "(from 12 µW)" was removed from "Low-Power Active FPGA Operation." 1.2_V was added to the list of core and I/O voltages in the "Advanced I/O" and "I/Os with Advanced I/O Standards" sections. The "Embedded Memory" section was updated to remove the footnote reference from the section heading and place it instead after "4,608-Bit" and "True Dual-Port
SRAM (except ×18)."
Page N/A
N/A
N/A
N/A
51700095-001-2 (February 2008)
I
I, 1-7 I
1 -8
v1.3
IGLOO Low-Power Flash FPGAs
Previous Version 51700095-001-1 (January 2008)
Changes in Current Version (v1.3) This document was updated to include AGL015 device information. QN68 is a new package that was added because it is offered in the AGL015. The following sections were updated: "Features and Benefits" "IGLOO Ordering Information" "Temperature Grade Offerings" "IGLOO Product Family" "IGLOO FPGAs Package Sizes Dimensions" "AGL015 and AGL030" note "IGLOO Device Family Overview" The "Temperature Grade Offerings" table was updated to include M1AGL600. In the "IGLOO Ordering Information" table, the QN package measurements were updated to include both 0.4 mm and 0.5 mm. In the "General Description" section, the number of I/Os was updated from 288 to 300.
Page N/A
IV III 1-5
51700095-001-0 (January 2008)
The "Low Power" section was updated to change the description of low-power I, 1-1, 1-5 active FPGA operation to "from 12 µW" from "from 25 µW." The same update was made in the "General Description" section and the "Flash*Freeze Technology" section. This document was previously in datasheet Advance v0.7. As a result of moving to the handbook format, Actel has restarted the version numbers. The new version number is 51700095-001-0. Table 1 • IGLOO Product Family, the "I/Os Per Package1" table, and the Temperature Grade Offerings table were updated to reflect the following: CS196 is now supported for AGL250; device/package support for QN132 is to be determined for AGL250; the CS281 package was added for AGL600 and AGL1000. Table 2 • IGLOO FPGAs Package Sizes Dimensions is new, and package sizes were removed from the "I/Os Per Package1" table. The "I/Os Per Package1"table was updated to reflect 77 instead of 79 singleended I/Os for the VG100 package for AGL030. N/A
Advance v0.7 (November 2007) Advance v0.6 (November 2007)
i, ii, iv
ii ii iii
Advance v0.6 (November 2007) Advance v0.5 (September 2007) Advance v0.4 (September 2007) Advance v0.3 (August 2007)
A note was added to "IGLOO Ordering Information" regarding marking information.
Table 1 • IGLOO Product Family, the "I/Os Per Package1" table, and the "IGLOO i, ii, iii, iv Ordering Information", and the Temperature Grade Offerings table were updated to add the UC81 package. Table 1 • IGLOO Product Family was updated for AGL030 in the Package Pins section to change CS181 to CS81. i
Cortex-M1 device information was added to Table 1 • IGLOO Product Family, the i, ii, iii, iv "I/Os Per Package1" table, "IGLOO Ordering Information", and Temperature Grade Offerings. The number of single-ended I/Os for the CS81 package for AGL030 was updated to 66 in the "I/Os Per Package1" table. ii i
Advance v0.2 (July 2007)
In Table 1 • IGLOO Product Family, the CS81 package was added for AGL030. The CS196 was replaced by the CS121 for AGL060. Table note 3 was moved to the specific packages to which it applies for AGL060: QN132 and FG144. The CS81 and CS121 packages were added to the "I/Os Per Package1" table. The number of single-ended I/Os was removed for the CS196 package in AGL060. Table note 6 was moved to the specific packages to which it applies for AGL060: QN132 and FG144.
ii
v1.3
1-9
IGLOO Device Family Overview Previous Version Changes in Current Version (v1.3) The CS81 and CS121 packages were added to the Temperature Grade Offerings table. The temperature grade offerings were removed for the CS196 package in AGL060. Table note 3 was moved to the specific packages to which it applies for AGL060: QN132 and FG144. Advance v0.1 The words "ambient temperature" were added to the temperature range in the "IGLOO Ordering Information", Temperature Grade Offerings, and "Speed Grade and Temperature Grade Matrix" sections. Page iv
iii, iv
Datasheet Categories
Categories
In order to provide the latest information to designers, some datasheets are published before data has been fully characterized. Datasheets are designated as "Product Brief," "Advance," "Preliminary," and "Production." The definition of these categories are as follows:
Product Brief
The product brief is a summarized version of a datasheet (advance or production) and contains general product information. This document gives an overview of specific device and family information.
Advance
This version contains initial estimated information based on simulation, other products, devices, or speed grades. This information can be used as estimates, but not for production. This label only applies to the DC and Switching Characteristics chapter of the datasheet and will only be used when the data has not been fully characterized.
Preliminary
The datasheet contains information based on simulation and/or initial characterization. The information is believed to be correct, but changes are possible.
Unmarked (production)
This version contains information that is considered to be final.
Export Administration Regulations (EAR)
The products described in this document are subject to the Export Administration Regulations (EAR). They could require an approved export license prior to export from the United States. An export includes release of product or disclosure of technology to a foreign national inside or outside the United States.
Actel Safety Critical, Life Support, and High-Reliability Applications Policy
The Actel products described in this advance status document may not have completed Actel’s qualification process. Actel may amend or enhance products during the product introduction and qualification process, resulting in changes in device functionality or performance. It is the responsibility of each customer to ensure the fitness of any Actel product (but especially a new product) for a particular purpose, including appropriateness for safety-critical, life-support, and other high-reliability applications. Consult Actel’s Terms and Conditions for specific liability exclusions relating to life-support applications. A reliability report covering all of Actel’s products is available on the Actel website at http://www.actel.com/documents/ORT_Report.pdf. Actel also offers a variety of enhanced qualification and lot acceptance screening procedures. Contact your local Actel sales office for additional reliability information.
1 -1 0
v1.3
2 – IGLOO DC and Switching Characteristics
General Specifications
DC and switching characteristics for –F speed grade targets are based only on simulation. The characteristics provided for the –F speed grade are subject to change after establishing FPGA specifications. Some restrictions might be added and will be reflected in future revisions of this document. The –F speed grade is only supported in the commercial temperature range.
Operating Conditions
Stresses beyond those listed in Table 2-1 may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Absolute Maximum Ratings are stress ratings only; functional operation of the device at these or any other conditions beyond those listed under the Recommended Operating Conditions specified in Table 2-2 on page 2-2 is not implied. Table 2-1 • Symbol VCC VJTAG VPUMP VCCPLL Absolute Maximum Ratings Parameter DC core supply voltage JTAG DC voltage Programming voltage Analog power supply (PLL) Limits –0.3 to 1.65 –0.3 to 3.75 –0.3 to 3.75 –0.3 to 1.65 –0.3 to 3.75 –0.3 V to 3.6 V (when I/O hot insertion mode is enabled) –0.3 V to (VCCI + 1 V) or 3.6 V, whichever voltage is lower (when I/O hot-insertion mode is disabled) TSTG 2 TJ 2 Notes: 1. The device should be operated within the limits specified by the datasheet. During transitions, the input signal may undershoot or overshoot according to the limits shown in Table 2-4 on page 2-3. 2. For flash programming and retention, maximum limits refer to Table 2-3 on page 2-2, and for recommended operating limits, refer to Table 2-2 on page 2-2. 3. VMV pins must be connected to the corresponding VCCI pins. See Pin Descriptions for further information. Storage Temperature Junction Temperature –65 to +150 +125 °C °C Units V V V V V V
VCCI and VMV 3 DC I/O buffer supply voltage VI I/O input voltage
A dv a n c e v 0. 5
2-1
IGLOO DC and Switching Characteristics Table 2-2 • Symbol TA TJ VCC
3
Recommended Operating Conditions 4 Parameter Commercial 0 to +70
1 6
Industrial –40 to +85
7
Units °C °C V V V V V V V V V V V V V V V
Ambient Temperature Junction Temperature 8 1.5 V DC core supply voltage 1.2 V–1.5 V wide range core voltage 2
0 to + 85 1.425 to 1.575 1.14 to 1.575 1.4 to 3.6 Programming Mode Operation
5 1
–40 to +100 1.425 to 1.575 1.14 to 1.575 1.4 to 3.6 3.15 to 3.45 0 to 3.45 1.4 to 1.6 1.14 to 1.575 1.14 to 1.26 1.425 to 1.575 1.7 to 1.9 2.3 to 2.7 2.7 to 3.6 3.0 to 3.6 2.375 to 2.625 3.0 to 3.6
VJTAG VPUMP VCCPLL
9
JTAG DC voltage Programming voltage Analog power supply (PLL)
3.15 to 3.45 0 to 3.45 1.4 to 1.6 1.14 to 1.575 1.14 to 1.26 1.425 to 1.575 1.7 to 1.9 2.3 to 2.7 2.7 to 3.6 3.0 to 3.6 2.375 to 2.625 3.0 to 3.6
1.5 V DC core supply voltage
1.2 V–1.5 V wide range core voltage2 VCCI and 1.2 V DC core supply voltage2 VMV 10 1.5 V DC supply voltage 1.8 V DC supply voltage 2.5 V DC supply voltage 3.3 V wide range DC supply voltage 11 3.3 V DC supply voltage LVDS differential I/O LVPECL differential I/O Notes: 1. For IGLOO® V5 devices 2. For IGLOO V2 devices only, operating at VCCI ≥ VCC
3. The ranges given here are for power supplies only. The recommended input voltage ranges specific to each I/O standard are given in Table 2-24 on page 2-23. VCCI should be at the same voltage within a given I/O bank. 4. All parameters representing voltages are measured with respect to GND unless otherwise specified. 5. VPUMP can be left floating during operation (not programming mode). 6. Maximum TJ = 85 °C. 7. Maximum TJ = 100 °C. 8. To ensure targeted reliability standards are met across ambient and junction operating temperatures, Actel recommends that the user follow best design practices using Actel’s timing and power simulation tools. 9. VCCPLL pins should be tied to VCC pins. See Pin Descriptions for further information. 10. VMV pins must be connected to the corresponding VCCI pins. See Pin Descriptions for further information. 11. 3.3 V wide range is compliant to the JDEC8a specification and supports 3.0 V VCCI operation. Table 2-3 • Flash Programming Limits – Retention, Storage, and Operating Temperature1
Program Retention Maximum Storage Maximum Operating Junction Product Grade Programming Cycles (biased/unbiased) Temperature TSTG (°C) 2 Temperature TJ (°C) 2 Commercial 500 20 years 110 100 Industrial Notes: 1. This is a stress rating only; functional operation at any condition other than those indicated is not implied. 2. These limits apply for program/data retention only. Refer to Table 2-1 on page 2-1 and Table 2-2 for device operating conditions and absolute limits. 500 20 years 110 100
2 -2
A dv a n c e v 0. 5
IGLOO DC and Switching Characteristics Table 2-4 • Overshoot and Undershoot Limits 1 Average VCCI–GND Overshoot or Undershoot Duration as a Percentage of Clock Cycle2 10% 5% 3V 3.3 V 3.6 V Notes: 1. Based on reliability requirements at junction temperature at 85°C. 2. The duration is allowed at one out of six clock cycles. If the overshoot/undershoot occurs at one out of two cycles, the maximum overshoot/undershoot has to be reduced by 0.15 V. 3. This table does not provide PCI overshoot/undershoot limits. 10% 5% 10% 5% 10% 5% Maximum Overshoot/ Undershoot2 1.4 V 1.49 V 1.1 V 1.19 V 0.79 V 0.88 V 0.45 V 0.54 V
VCCI 2.7 V or less
I/O Power-Up and Supply Voltage Thresholds for Power-On Reset (Commercial and Industrial)
Sophisticated power-up management circuitry is designed into every IGLOO device. These circuits ensure easy transition from the powered-off state to the powered-up state of the device. The many different supplies can power up in any sequence with minimized current spikes or surges. In addition, the I/O will be in a known state through the power-up sequence. The basic principle is shown in Figure 2-1 on page 2-4 and Figure 2-2 on page 2-5. There are five regions to consider during power-up. IGLOO I/Os are activated only if ALL of the following three conditions are met: 1. VCC and VCCI are above the minimum specified trip points (Figure 2-1 on page 2-4 and Figure 2-2 on page 2-5). 2. VCCI > VCC – 0.75 V (typical) 3. Chip is in the operating mode. VCCI Trip Point: Ramping up (V5 devices): 0.6 V < trip_point_up < 1.2 V Ramping down (V5 Devices): 0.5 V < trip_point_down < 1.1 V Ramping up (V2 devices): 0.75 V < trip_point_up < 1.05 V Ramping down (V2 devices): 0.65 V < trip_point_down < 0.95 V VCC Trip Point: Ramping up (V5 devices): 0.6 V < trip_point_up < 1.1 V Ramping down (V5 devices): 0.5 V < trip_point_down < 1.0 V Ramping up (V2 devices): 0.65 V < trip_point_up < 1.05 V Ramping down (V2 devices): 0.55 V < trip_point_down < 0.95 V VCC and VCCI ramp-up trip points are about 100 mV higher than ramp-down trip points. This specifically built-in hysteresis prevents undesirable power-up oscillations and current surges. Note the following: • • During programming, I/Os become tristated and weakly pulled up to VCCI. JTAG supply, PLL power supplies, and charge pump VPUMP supply have no influence on I/O behavior.
A dv a n c e v 0. 5
2-3
IGLOO DC and Switching Characteristics
PLL Behavior at Brownout Condition
Actel recommends using monotonic power supplies or voltage regulators to ensure proper powerup behavior. Power ramp-up should be monotonic at least until VCC and VCCPLX exceed brownout activation levels (see Figure 2-1 and Figure 2-2 on page 2-5 for more details). When PLL power supply voltage and/or VCC levels drop below the VCC brownout levels (0.75 V ± 0.25 V for V5 devices, and 0.75 V ± 0.2 V for V2 devices), the PLL output lock signal goes low and/or the output clock is lost. Refer to the Brownout Voltage section in the Power-Up/-Down Behavior of Low-Power Flash Devices chapter of the ProASIC®3 and ProASIC3E handbooks for information on clock and lock recovery.
Internal Power-Up Activation Sequence
1. Core 2. Input buffers 3. Output buffers, after 200 ns delay from input buffer activation To make sure the transition from input buffers to output buffers is clean, ensure that there is no path longer than 100 ns from input buffer to output buffer in your design.
VCC = VCCI + VT where VT can be from 0.58 V to 0.9 V (typically 0.75 V) VCC VCC = 1.575 V Region 1: I/O Buffers are OFF
Region 4: I/O buffers are ON. I/Os are functional (except differential inputs) but slower because VCCI is below specification. For the same reason, input buffers do not meet VIH/VIL levels, and output buffers do not meet VOH/VOL levels. Region 5: I/O buffers are ON and power supplies are within specification. I/Os meet the entire datasheet and timer specifications for speed, VIH/VIL , VOH/VOL , etc.
VCC = 1.425 V
Region 2: I/O buffers are ON. I/Os are functional (except differential inputs) but slower because VCCI/VCC are below specification. For the same reason, input buffers do not meet VIH/VIL levels, and output buffers do not meet VOH/VOL levels. Region 3: I/O buffers are ON. I/Os are functional; I/O DC specifications are met, but I/Os are slower because the VCC is below specification.
Activation trip point: Va = 0.85 V ± 0.25 V Deactivation trip point: Vd = 0.75 V ± 0.25 V
Region 1: I/O buffers are OFF
Activation trip point: Va = 0.9 V ± 0.3 V Deactivation trip point: Vd = 0.8 V ± 0.3 V
Min VCCI datasheet specification voltage at a selected I/O standard; i.e., 1.425 V or 1.7 V or 2.3 V or 3.0 V
VCCI
Figure 2-1 • V5 Devices – I/O State as a Function of VCCI and VCC Voltage Levels
2 -4
A dv a n c e v 0. 5
IGLOO DC and Switching Characteristics
VCC = VCCI + VT where VT can be from 0.58 V to 0.9 V (typically 0.75 V) VCC VCC = 1.575 V Region 1: I/O Buffers are OFF
Region 4: I/O buffers are ON. I/Os are functional (except differential inputs) but slower because VCCI is below specification. For the same reason, input buffers do not meet VIH/VIL levels, and output buffers do not meet VOH/VOL levels. Region 5: I/O buffers are ON and power supplies are within specification. I/Os meet the entire datasheet and timer specifications for speed, VIH/VIL , VOH/VOL , etc.
VCC = 1.14 V
Region 2: I/O buffers are ON. I/Os are functional (except differential inputs) but slower because VCCI/VCC are below specification. For the same reason, input buffers do not meet VIH/VIL levels, and output buffers do not meet VOH/VOL levels. Region 3: I/O buffers are ON. I/Os are functional; I/O DC specifications are met, but I/Os are slower because the VCC is below specification.
Activation trip point: Va = 0.85 V ± 0.2 V Deactivation trip point: Vd = 0.75 V ± 0.2 V
Region 1: I/O buffers are OFF
Activation trip point: Va = 0.9 V ± 0.15 V Deactivation trip point: Vd = 0.8 V ± 0.15 V
Min VCCI datasheet specification voltage at a selected I/O standard; i.e., 1.14 V,1.425 V, 1.7 V, 2.3 V, or 3.0 V
VCCI
Figure 2-2 • V2 Devices – I/O State as a Function of VCCI and VCC Voltage Levels
Thermal Characteristics
Introduction
The temperature variable in the Actel Designer software refers to the junction temperature, not the ambient temperature. This is an important distinction because dynamic and static power consumption cause the chip junction to be higher than the ambient temperature. EQ 2-1 can be used to calculate junction temperature. TJ = Junction Temperature = ∆T + TA EQ 2-1 where: TA = Ambient Temperature ∆T = Temperature gradient between junction (silicon) and ambient ∆T = θja * P θja = Junction-to-ambient of the package. θja numbers are located in Table 2-5 on page 2-6. P = Power dissipation
A dv a n c e v 0. 5
2-5
IGLOO DC and Switching Characteristics
Package Thermal Characteristics
The device junction-to-case thermal resistivity is θ jc and the junction-to-ambient air thermal resistivity is θ ja. The thermal characteristics for θja are shown for two air flow rates. The absolute maximum junction temperature is 110°C. EQ 2-2 shows a sample calculation of the absolute maximum power dissipation allowed for a 484-pin FBGA package at commercial temperature and in still air. 100 ° C – 70 ° C Max. junction temp. ( ° C) – Max. ambient temp. ( ° C) Maximum Power Allowed = ---------------------------------------------------------------------------------------------------------------------------------------- = ------------------------------------- = 1.463 W 20.5°C/W θ ja ( ° C/W) EQ 2-2 Table 2-5 • Package Thermal Resistivities θja Package Type Quad Flat No Lead Device AGL015 AGL030 AGL060 AGL125 AGL250 Very Thin Quad Flat Pack (VQFP) Chip Scale Package (CSP) Fine Pitch Ball Grid Array (FBGA) All devices All devices See note* See note* See note* See note* AGL060 AGL1000 AGL250 AGL1000 AGL1000 Pin Count 68 132 132 132 132 100 196 144 256 484 896 144 144 256 256 484 3.8 3.8 3.2 2.4 18.6 6.3 12.0 6.6 8.0 θjc TBD 0.4 0.3 0.2 0.1 10.0 Still Air TBD 21.4 21.2 21.1 21.0 35.3 57.8 26.9 26.6 20.5 13.6 55.2 31.6 38.6 28.1 23.3 200 ft./ min. TBD 16.8 16.6 16.5 16.4 29.4 47.6 22.9 22.8 17.0 10.4 49.4 26.2 34.7 24.4 19.0 500 ft./ min. TBD 15.3 15.0 14.9 14.8 27.1 43.3 21.5 21.5 15.9 9.4 47.2 24.2 33.0 22.7 16.7 Units C/W C/W C/W C/W C/W C/W C/W C/W C/W C/W C/W C/W C/W C/W C/W C/W
* This information applies to all IGLOO devices except those listed below. Detailed device/package thermal information for all IGLOO devices will be available in future revisions of the datasheet.
Temperature and Voltage Derating Factors
Table 2-6 • Temperature and Voltage Derating Factors for Timing Delays (normalized to TJ = 70°C, VCC = 1.425 V) For IGLOO V2 or V5 devices, 1.5 V DC Core Supply Voltage Junction Temperature (°C) –40°C 0.95 0.88 0.82 0°C 0.96 0.89 0.84 25°C 0.98 0.91 0.85 70°C 1.00 0.93 0.87 85°C 1.01 0.93 0.88 110°C 1.02 0.94 0.89
Array Voltage VCC (V) 1.425 1.5 1.575
2 -6
A dv a n c e v 0. 5
IGLOO DC and Switching Characteristics Table 2-7 • Temperature and Voltage Derating Factors for Timing Delays (normalized to TJ = 70°C, VCC = 1.14 V) For IGLOO V2, 1.2 V DC Core Supply Voltage Junction Temperature (°C) –40°C 0.97 0.86 0.79 0°C 0.98 0.87 0.80 25°C 0.99 0.89 0.81 70°C 1.00 0.89 0.82 85°C 1.01 0.90 0.83 110°C 1.01 0.91 0.83
Array Voltage VCC (V) 1.14 1.2 1.26
Calculating Power Dissipation
Quiescent Supply Current
Quiescent supply current (IDD) calculation depends on multiple factors, including operating voltages (VCC, VCCI, and VJTAG), operating temperature, system clock frequency, and power modes usage. Actel recommends using the PowerCalculator and SmartPower software estimation tools to evaluate the projected static and active power based on the user design, power mode usage, operating voltage, and temperature. Table 2-8 • Quiescent Supply Current (IDD) Characteristics, IGLOO Flash*Freeze Mode* Core Voltage Typical (25°C) 1.2 V 1.5 V AGL015 AGL030 4 6 4 6 AGL060 8 10 AGL125 13 18 AGL250 20 34 AGL400 27 51 AGL600 30 72 AGL1000 44 127 Units µA µA
* IDD includes VCC, VPUMP, VCCI, VJTAG , and VCCPLL currents. Values do not include I/O static contribution (PDC6 and PDC7). Table 2-9 • Quiescent Supply Current (IDD) Characteristics, IGLOO Sleep Mode (VCC = 0 V)* Core Voltage AGL015 AGL030 AGL060 AGL125 AGL250 AGL400 AGL600 AGL1000 Units VCCI / VJTAG = 1.2 V (per bank) Typical (25°C) 1.2 V 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 µA µA µA
VCCI /VJTAG = 1.5 V (per 1.2 V / bank) Typical (25°C) 1.5 V VCCI / VJTAG = 1.8 V 1.2 V / (per bank) Typical 1.5 V (25°C) VCCI / VJTAG = 2.5 V 1.2 V / (per bank) Typical 1.5 V (25°C) VCCI / VJTAG = 3.3 V 1.2 V / (per bank) Typical 1.5 V (25°C)
2.2
2.2
2.2
2.2
2.2
2.2
2.2
2.2
µA
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
µA
* IDD includes VCC, VPUMP, and VCCPLL currents. Values do not include I/O static contribution (PDC6 and PDC7). Table 2-10 • Quiescent Supply Current (IDD) Characteristics, IGLOO Shutdown Mode (VCC, VCCI = 0 V)* Core Voltage Typical (25°C) 1.2 V / 1.5 V AGL015 0 AGL030 0 Units µA
* IDD includes VCC, VPUMP, VCCI, VJTAG , and VCCPLL currents. Values do not include I/O static contribution (PDC6 and PDC7).
A dv a n c e v 0. 5
2-7
IGLOO DC and Switching Characteristics Table 2-11 • Quiescent Supply Current (IDD), No IGLOO Flash*Freeze Mode1 Core Voltage AGL015 AGL030 AGL060 AGL125 AGL250 AGL400 AGL600 AGL1000 Units ICCA Current2 Typical (25°C) 1.2 V 1.5 V ICCI or IJTAG Current
3, 4
5 14
6 16
10 20
13 28
18 44
25 66
28 82
42 137
µA µA
VCCI /VJTAG = 1.2 V (per bank) Typical (25°C)
1.2 V
1.7
1.7
1.7
1.7
1.7
1.7
1.7
1.7
µA
VCCI / VJTAG = 1.5 V 1.2 V / (per bank) Typical 1.5 V (25°C) VCCI /VJTAG = 1.8 V 1.2 V / (per bank) Typical 1.5 V (25°C) VCCI /VJTAG = 2.5 V 1.2 V / (per bank) Typical 1.5 V (25°C) VCCI /VJTAG = 3.3 V 1.2 V / (per bank) Typical 1.5 V (25°C) Notes:
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
µA
1.9
1.9
1.9
1.9
1.9
1.9
1.9
1.9
µA
2.2
2.2
2.2
2.2
2.2
2.2
2.2
2.2
µA
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
µA
1. To calculate total device IDD, multiply the number of banks used by ICCI and add ICCA contribution. 2. Includes VCC , VPUMP and VCCPLL currents. 3. Per VCCI or VJTAG bank 4. Values do not include I/O static contribution (PDC6 and PDC7).
2 -8
A dv a n c e v 0. 5
IGLOO DC and Switching Characteristics
Power per I/O Pin
Table 2-12 • Summary of I/O Input Buffer Power (per pin) – Default I/O Software Settings Applicable to Advanced I/O Banks VCCI (V) Single-Ended 3.3 V LVTTL / 3.3 V LVCMOS 2.5 V LVCMOS 1.8 V LVCMOS 1.5 V LVCMOS (JESD8-11) 1.2 V LVCMOS 3.3 V PCI 3.3 V PCI-X Differential LVDS LVPECL Notes: 1. PDC6 is the static power (where applicable) measured on VCCI. 2. PAC9 is the total dynamic power measured on VCCI. 3. Applicable for IGLOO V2 devices only Table 2-13 • Summary of I/O Input Buffer Power (per pin) – Default I/O Software Settings Applicable to Standard Plus I/O Banks VCCI (V) Single-Ended 3.3 V LVTTL / 3.3 V LVCMOS 2.5 V LVCMOS 1.8 V LVCMOS 1.5 V LVCMOS (JESD8-11) 1.2 V LVCMOS3 3.3 V PCI 3.3 V PCI-X Notes: 1. PDC6 is the static power (where applicable) measured on VCCI. 2. PAC9 is the total dynamic power measured on VCCI. 3. Applicable for IGLOO V2 devices only. 3.3 2.5 1.8 1.5 1.2 3.3 3.3 – – – – – – – 16.41 4.75 1.66 1.00 0.61 17.78 17.78 Static Power PDC6 (mW)1 Dynamic Power PAC9 (µW/MHz)2 2.5 3.3 2.26 5.72 0.89 1.63
3
Static Power PDC6 (mW)1
Dynamic Power PAC9 (µW/MHz)2
3.3 2.5 1.8 1.5 1.2 3.3 3.3
– – – – – – –
16.27 4.65 1.61 0.96 0.58 17.67 17.67
A dv a n c e v 0. 5
2-9
IGLOO DC and Switching Characteristics Table 2-14 • Summary of I/O Input Buffer Power (per pin) – Default I/O Software Settings Applicable to Standard I/O Banks VCCI (V) Single-Ended 3.3 V LVTTL / 3.3 V LVCMOS 2.5 V LVCMOS 1.8 V LVCMOS 1.5 V LVCMOS (JESD8-11) 1.2 V LVCMOS Notes: 1. PDC6 is the static power (where applicable) measured on VCCI. 2. PAC9 is the total dynamic power measured on VCCI. 3. Applicable for IGLOO V2 devices only. Table 2-15 • Summary of I/O Output Buffer Power (per pin) – Default I/O Software Settings1 Applicable to Advanced I/O Banks CLOAD (pF) Single-Ended 3.3 V LVTTL / 3.3 V LVCMOS 2.5 V LVCMOS 1.8 V LVCMOS 1.5 V LVCMOS (JESD8-11) 1.2 V LVCMOS 3.3 V PCI 3.3 V PCI-X Differential LVDS LVPECL Notes: 1. Dynamic power consumption is given for standard load and software default drive strength and output slew. 2. PDC7 is the static power (where applicable) measured on VCCI. 3. PAC10 is the total dynamic power measured on VCCI. 4. Applicable for IGLOO V2 devices only. – – 2.5 3.3 7.74 19.54 78.72 143.99
4 3
Static Power PDC6 (mW)1
Dynamic Power PAC9 (µW/MHz)2
3.3 2.5 1.8 1.5 1.2
– – – – –
17.24 5.64 2.63 1.97 0.57
VCCI (V) 3.3 2.5 1.8 1.5 1.2 3.3 3.3
Static Power PDC7 (mW)2 – – – – – –
Dynamic Power PAC10 (µW/MHz)3 136.95 76.84 49.31 33.36 16.24 194.05 194.05
5 5 5 5 5 10 10
2 -1 0
A d v a n c e v 0. 5
IGLOO DC and Switching Characteristics Table 2-16 • Summary of I/O Output Buffer Power (per pin) – Default I/O Software Settings1 Applicable to Standard Plus I/O Banks CLOAD (pF) Single-Ended 3.3 V LVTTL / 3.3 V LVCMOS 2.5 V LVCMOS 1.8 V LVCMOS 1.5 V LVCMOS (JESD8-11) 1.2 V LVCMOS 3.3 V PCI 3.3 V PCI-X Notes: 1. Dynamic power consumption is given for standard load and software default drive strength and output slew. 2. PDC7 is the static power (where applicable) measured on VCCI. 3. PAC10 is the total dynamic power measured on VCCI. 4. Applicable for IGLOO V2 devices only. Table 2-17 • Summary of I/O Output Buffer Power (per pin) – Default I/O Software Settings1 Applicable to Standard I/O Banks CLOAD (pF) Single-Ended 3.3 V LVTTL / 3.3 V LVCMOS 2.5 V LVCMOS 1.8 V LVCMOS 1.5 V LVCMOS (JESD8-11) 1.2 V LVCMOS Notes: 1. Dynamic power consumption is given for standard load and software default drive strength and output slew. 2. PDC7 is the static power (where applicable) measured on VCCI. 3. PAC10 is the total dynamic power measured on VCCI. 4. Applicable for IGLOO V2 devices only.
4 4
VCCI (V) 3.3 2.5 1.8 1.5 1.2 3.3 3.3
Static Power PDC7 (mW)2 – – – – – – –
Dynamic Power PAC10 (µW/MHz)3 122.16 68.37 34.53 23.66 14.90 181.06 181.06
5 5 5 5 5 10 10
VCCI (V) 3.3 2.5 1.8 1.5 1.2
Static Power PDC7 (mW)2 – – – – –
Dynamic Power PAC10 (µW/MHz)3 104.38 59.86 31.26 21.96 13.49
5 5 5 5 5
A dv a n c e v 0. 5
2 - 11
IGLOO DC and Switching Characteristics
Power Consumption of Various Internal Resources
Table 2-18 • Different Components Contributing to Dynamic Power Consumption in IGLOO Devices For IGLOO V2 or V5 Devices, 1.5 V DC Core Supply Voltage Device Specific Dynamic Power (µW/MHz) Parameter PAC1 PAC2 PAC3 PAC4 Definition Clock contribution of a Global Rib Clock contribution of a Global Spine Clock contribution of a VersaTile row Clock contribution of a VersaTile used as a sequential module First contribution of a VersaTile used as a sequential module Second contribution of a VersaTile used as a sequential module Contribution of a VersaTile used as a combinatorial module Average contribution of a routing net Contribution of an I/O input pin (standarddependent) Contribution of an I/O output pin (standarddependent) Average contribution of a RAM block during a read operation Average contribution of a RAM block during a write operation Dynamic PLL contribution AGL1000 AGL600 AGL400 AGL250 AGL125 AGL060 AGL030 AGL015 14.48 2.48 12.77 1.85 12.77 1.58 11.03 1.58 0.81 0.11 11.03 0.81 9.3 0.81 9.3 0.41 9.3 0.41
PAC5
0.057
PAC6
0.207
PAC7
0.17
PAC8 PAC9
0.7 See Table 2-12 on page 2-9 through Table 2-14 on page 2-10.
PAC10
See Table 2-15 on page 2-10 through Table 2-17 on page 2-11.
PAC11
25.00
PAC12
30.00
PAC13
2.70
* For a different output load, drive strength, or slew rate, Actel recommends using the Actel power spreadsheet calculator or SmartPower tool in Actel Libero® Integrated Design Environment (IDE).
2 -1 2
A d v a n c e v 0. 5
IGLOO DC and Switching Characteristics Table 2-19 • Different Components Contributing to the Static Power Consumption in IGLOO Devices For IGLOO V2 or V5 Devices, 1.5 V DC Core Supply Voltage Device-Specific Static Power (mW) Parameter PDC1 PDC2 PDC3 PDC4 PDC5 PDC6 Definition Array static power in Active mode Array static power in Static (Idle) mode Array static power in Flash*Freeze mode Static PLL contribution Bank quiescent power (VCCI-dependent) I/O input pin static power (standarddependent) I/O output pin static power (standarddependent) AGL1000 AGL600 AGL400 AGL250 AGL125 AGL060 AGL030 AGL015 See Table 2-11 on page 2-8. See Table 2-10 on page 2-7. See Table 2-8 on page 2-7. 1.84 See Table 2-11 on page 2-8. See Table 2-12 on page 2-9 through Table 2-14 on page 2-10.
PDC7
See Table 2-15 on page 2-10 through Table 2-17 on page 2-11.
* For a different output load, drive strength, or slew rate, Actel recommends using the Actel power spreadsheet calculator or SmartPower tool in Actel Libero® Integrated Design Environment (IDE).
A dv a n c e v 0. 5
2 - 13
IGLOO DC and Switching Characteristics Table 2-20 • Different Components Contributing to Dynamic Power Consumption in IGLOO Devices For IGLOO V2 Devices, 1.2 V DC Core Supply Voltage Device Specific Dynamic Power (µW/MHz) Parameter PAC1 PAC2 PAC3 PAC4 Definition Clock contribution of a Global Rib Clock contribution of a Global Spine Clock contribution of a VersaTile row Clock contribution of a VersaTile used as a sequential module First contribution of a VersaTile used as a sequential module Second contribution of a VersaTile used as a sequential module Contribution of a VersaTile used as a combinatorial module Average contribution of a routing net Contribution of an I/O input pin (standarddependent) Contribution of an I/O output pin (standarddependent) Average contribution of a RAM block during a read operation Average contribution of a RAM block during a write operation Dynamic PLL contribution AGL1000 AGL600 AGL400 AGL250 AGL125 AGL060 AGL030 AGL015 9.28 1.59 8.19 1.19 8.19 1.01 7.07 1.01 0.52 0.07 7.07 0.52 5.96 0.52 5.96 0.26 5.96 0.26
PAC5
0.045
PAC6
0.186
PAC7
0.11
PAC8 PAC9
0.45 See Table 2-12 on page 2-9 through Table 2-14 on page 2-10.
PAC10
See Table 2-15 on page 2-10 through Table 2-17 on page 2-11.
PAC11
25.00
PAC12
30.00
PAC13
2.10
* For a different output load, drive strength, or slew rate, Actel recommends using the Actel power spreadsheet calculator or SmartPower tool in Libero IDE.
2 -1 4
A d v a n c e v 0. 5
IGLOO DC and Switching Characteristics Table 2-21 • Different Components Contributing to the Static Power Consumption in IGLOO Device For IGLOO V2 Devices, 1.2 V DC Core Supply Voltage Device Specific Static Power (mW) Parameter PDC1 PDC2 PDC3 PDC4 PDC5 PDC6 Definition Array static power in Active mode Array static power in Static (Idle) mode Array static power in Flash*Freeze mode Static PLL contribution Bank quiescent power (VCCI-Dependent) I/O input pin static power (standarddependent) I/O output pin static power (standarddependent) AGL1000 AGL600 AGL400 AGL250 AGL125 AGL060 AGL030 AGL015 See Table 2-11 on page 2-8. See Table 2-10 on page 2-7. See Table 2-8 on page 2-7. 0.90 See Table 2-11 on page 2-8. See Table 2-12 on page 2-9 through Table 2-14 on page 2-10.
PDC7
See Table 2-15 on page 2-10 through Table 2-17 on page 2-11.
* For a different output load, drive strength, or slew rate, Actel recommends using the Actel power spreadsheet calculator or SmartPower tool in Actel Libero® Integrated Design Environment (IDE).
A dv a n c e v 0. 5
2 - 15
IGLOO DC and Switching Characteristics
Power Calculation Methodology
This section describes a simplified method to estimate power consumption of an application. For more accurate and detailed power estimations, use the SmartPower tool in Actel Libero IDE software. The power calculation methodology described below uses the following variables: • • • • • • • • The number of PLLs as well as the number and the frequency of each output clock generated The number of combinatorial and sequential cells used in the design The internal clock frequencies The number and the standard of I/O pins used in the design The number of RAM blocks used in the design Toggle rates of I/O pins as well as VersaTiles—guidelines are provided in Table 2-22 on page 2-18. Enable rates of output buffers—guidelines are provided for typical applications in Table 2-23 on page 2-18. Read rate and write rate to the memory—guidelines are provided for typical applications in Table 2-23 on page 2-18. The calculation should be repeated for each clock domain defined in the design.
Methodology
Total Power Consumption—PTOTAL
PTOTAL = PSTAT + PDYN
PSTAT is the total static power consumption. PDYN is the total dynamic power consumption.
Total Static Power Consumption—PSTAT
PSTAT = (PDC1 or PDC2 or PDC3) + NBANKS * PDC5 + NINPUTS * PDC6 + NOUTPUTS * PDC7
NINPUTS is the number of I/O input buffers used in the design. NOUTPUTS is the number of I/O output buffers used in the design. NBANKS is the number of I/O banks powered in the design.
Total Dynamic Power Consumption—PDYN
PDYN = PCLOCK + PS-CELL + PC-CELL + PNET + PINPUTS + POUTPUTS + PMEMORY + PPLL
Global Clock Contribution—PCLOCK
PCLOCK = (PAC1 + NSPINE* PAC2 + NROW * PAC3 + NS-CELL* PAC4) * FCLK
NSPINE is the number of global spines used in the user design—guidelines are provided in Table 2-22 on page 2-18. NROW is the number of VersaTile rows used in the design—guidelines are provided in Table 2-22 on page 2-18. FCLK is the global clock signal frequency. NS-CELL is the number of VersaTiles used as sequential modules in the design. PAC1, PAC2, PAC3, and PAC4 are device-dependent.
Sequential Cells Contribution—PS-CELL
PS-CELL = NS-CELL * (PAC5 + α1 / 2 * PAC6) * FCLK
NS-CELL is the number of VersaTiles used as sequential modules in the design. When a multi-tile sequential cell is used, it should be accounted for as 1.
α1 is the toggle rate of VersaTile outputs—guidelines are provided in Table 2-22 on
page 2-18. FCLK is the global clock signal frequency.
2 -1 6
A d v a n c e v 0. 5
IGLOO DC and Switching Characteristics
Combinatorial Cells Contribution—PC-CELL
PC-CELL = NC-CELL* α1 / 2 * PAC7 * FCLK
NC-CELL is the number of VersaTiles used as combinatorial modules in the design. page 2-18. FCLK is the global clock signal frequency.
α1 is the toggle rate of VersaTile outputs—guidelines are provided in Table 2-22 on
Routing Net Contribution—PNET
PNET = (NS-CELL + NC-CELL) * α1 / 2 * PAC8 * FCLK
NS-CELL is the number of VersaTiles used as sequential modules in the design. NC-CELL is the number of VersaTiles used as combinatorial modules in the design. page 2-18. FCLK is the global clock signal frequency.
α1 is the toggle rate of VersaTile outputs—guidelines are provided in Table 2-22 on
I/O Input Buffer Contribution—PINPUTS
PINPUTS = NINPUTS * α2 / 2 * PAC9 * FCLK
NINPUTS is the number of I/O input buffers used in the design. FCLK is the global clock signal frequency.
α2 is the I/O buffer toggle rate—guidelines are provided in Table 2-22 on page 2-18.
I/O Output Buffer Contribution—POUTPUTS
POUTPUTS = NOUTPUTS * α2 / 2 * β1 * PAC10 * FCLK
NOUTPUTS is the number of I/O output buffers used in the design.
α2 is the I/O buffer toggle rate—guidelines are provided in Table 2-22 on page 2-18. β1 is the I/O buffer enable rate—guidelines are provided in Table 2-23 on page 2-18.
FCLK is the global clock signal frequency.
RAM Contribution—PMEMORY
PMEMORY = PAC11 * NBLOCKS * FREAD-CLOCK * β2 + PAC12 * NBLOCK * FWRITE-CLOCK * β3
NBLOCKS is the number of RAM blocks used in the design. FREAD-CLOCK is the memory read clock frequency.
β2 is the RAM enable rate for read operations.
β3 is the RAM enable rate for write operations—guidelines are provided in Table 2-23
on page 2-18.
FWRITE-CLOCK is the memory write clock frequency.
PLL Contribution—PPLL
PPLL = PDC4 + PAC13 *FCLKOUT
FCLKOUT is the output clock frequency.1
1.
If a PLL is used to generate more than one output clock, include each output clock in the formula by adding its corresponding contribution (PAC13* FCLKOUT product) to the total PLL contribution.
A dv a n c e v 0. 5
2 - 17
IGLOO DC and Switching Characteristics
Guidelines
Toggle Rate Definition
A toggle rate defines the frequency of a net or logic element relative to a clock. It is a percentage. If the toggle rate of a net is 100%, this means that this net switches at half the clock frequency. Below are some examples: • • The average toggle rate of a shift register is 100% because all flip-flop outputs toggle at half of the clock frequency. The average toggle rate of an 8-bit counter is 25%: – – – – – – Bit 0 (LSB) = 100% Bit 1 Bit 2 … Bit 7 (MSB) = 0.78125% Average toggle rate = (100% + 50% + 25% + 12.5% + . . . + 0.78125%) / 8 = 50% = 25%
Enable Rate Definition
Output enable rate is the average percentage of time during which tristate outputs are enabled. When nontristate output buffers are used, the enable rate should be 100%. Table 2-22 • Toggle Rate Guidelines Recommended for Power Calculation Component Definition Toggle rate of VersaTile outputs I/O buffer toggle rate Guideline 10% 10%
α1 α2
Component
Table 2-23 • Enable Rate Guidelines Recommended for Power Calculation Definition I/O output buffer enable rate RAM enable rate for read operations RAM enable rate for write operations Guideline 100% 12.5% 12.5%
β1 β2 β3
2 -1 8
A d v a n c e v 0. 5
IGLOO DC and Switching Characteristics
User I/O Characteristics
Timing Model
I/O Module (Non-Registered) Combinational Cell Y tPD = 1.22 ns Combinational Cell Y tPD = 1.20 ns tDP = 1.72 ns Combinational Cell Y tPD = 1.80 ns I/O Module (Registered) tPY = 1.20 ns LVPECL (Applicable to Advanced I/O Banks only) D Q tPD = 1.49 ns Combinational Cell Y tICLKQ = 0.43 ns tISUD = 0.47 ns Input LVTTL Clock Register Cell tPY = 0.87 ns (Advanced I/O Banks) I/O Module (Non-Registered) LVDS, BLVDS, M-LVDS (Applicable for Advanced I/O Banks only) tCLKQ = 0.90 ns tSUD = 0.82 ns tPY = 1.35 ns Input LVTTL Clock tPY = 0.87 ns (Advanced I/O Banks) D Q Combinational Cell Y tPD = 0.92 ns tCLKQ = 0.90 ns tSUD = 0.82 ns Input LVTTL Clock tPY = 0.87 ns (Advanced I/O Banks) Register Cell D Q D tPD = 0.86 ns I/O Module (Non-Registered) LVTTL Output drive strength = 12 mA High slew rate tDP = 3.05 ns (Advanced I/O Banks) I/O Module (Non-Registered) LVTTL Output drive strength = 8 mA High slew rate tDP = 4.12 ns (Advanced I/O Banks) I/O Module (Non-Registered) LVCMOS 1.5 V Output drive strength = 4 mA High slew rate tDP = 4.42 ns (Advanced I/O Banks) I/O Module (Registered) Q LVTTL 3.3 V Output drive strength = 12 mA High slew rate tDP = 3.05 ns (Advanced I/O Banks) LVPECL (Applicable to Advanced I/O Banks Only)L
Combinational Cell Y
tOCLKQ = 1.02 ns tOSUD = 0.52 ns
Figure 2-3 • Timing Model Operating Conditions: Std. Speed, Commercial Temperature Range (TJ = 70°C), Worst-Case VCC = 1.425 V, for DC 1.5 V Core Voltage, Applicable to V2 and V5 Devices
A dv a n c e v 0. 5
2 - 19
IGLOO DC and Switching Characteristics
tPY
tDIN
PAD
D Y
Q DIN To Array
CLK
tPY = MAX(tPY(R), tPY(F)) tDIN = MAX(tDIN(R), tDIN(F))
I/O Interface
VIH Vtrip Vtrip VCC 50% Y GND tPY (R) tPY (F) VCC 50% DIN GND tDOUT (R)
Figure 2-4 • Input Buffer Timing Model and Delays (example)
PAD
VIL
50%
50% tDOUT (F)
2 -2 0
A d v a n c e v 0. 5
IGLOO DC and Switching Characteristics
tDOUT DQ D From Array I/O Interface CLK
tDP PAD Std Load tDP = MAX(tDP(R), tDP(F)) tDOUT = MAX(tDOUT(R), tDOUT(F)) tDOUT VCC 50% VCC (F) 0V
DOUT
tDOUT (R) 50%
D
DOUT
50%
50% VOH
0V
Vtrip PAD tDP (R)
Figure 2-5 • Output Buffer Model and Delays (example)
Vtrip VOL tDP (F)
A dv a n c e v 0. 5
2 - 21
IGLOO DC and Switching Characteristics
tEOUT D E Q tZL, tZH, tHZ, tLZ, tZLS, tZHS
CLK
EOUT D D Q DOUT CLK PAD
I/O Interface
tEOUT = MAX(tEOUT(r), tEOUT(f)) VCC
D VCC E 50% tEOUT (R) 50% EOUT tZL PAD Vtrip VOL 50% tEOUT (F) VCC 50% tHZ 90% VCCI 50% tZH VCCI Vtrip 10% VCCI 50% tLZ
VCC D VCC E 50% tEOUT (R) VCC EOUT PAD Vtrip VOL 50% tZLS 50% VOH 50% tZHS Vtrip 50% tEOUT (F)
Figure 2-6 • Tristate Output Buffer Timing Model and Delays (example)
2 -2 2
A d v a n c e v 0. 5
IGLOO DC and Switching Characteristics
Overview of I/O Performance
Summary of I/O DC Input and Output Levels – Default I/O Software Settings
Table 2-24 • Summary of Maximum and Minimum DC Input and Output Levels Applicable to Commercial and Industrial Conditions—Software Default Settings Applicable to Advanced I/O Banks I/O Standard 3.3 V LVTTL / 3.3 V LVCMOS 3.3 V LVCMOS Wide Range 2.5 V LVCMOS 1.8 V LVCMOS 1.5 V LVCMOS 1.2 V LVCMOS3 3.3 V PCI 3.3 V PCI-X Notes: 1. Currents are measured at 85°C junction temperature. 2. All LVMCOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JDEC8a specification. 3. Applicable to V2 Devices only. Table 2-25 • Summary of Maximum and Minimum DC Input and Output Levels Applicable to Commercial and Industrial Conditions—Software Default Settings Applicable to Standard Plus I/O Banks I/O Standard 3.3 V LVTTL / 3.3 V LVCMOS 3.3 V LVCMOS Wide Range 2.5 V LVCMOS 1.8 V LVCMOS 1.5 V LVCMOS 1.2 V LVCMOS3 3.3 V PCI 3.3 V PCI-X Notes: 1. Currents are measured at 85°C junction temperature. 2. All LVMCOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JDEC8a specification. 3. Applicable to V2 Devices only. VIL Drive Slew Max, V Strength Rate Min., V 12 mA Any2 12 mA 8 mA 4 mA 2 mA High High High High High High –0.3 –0.3 –0.3 –0.3 –0.3 –0.3 0.8 0.8 0.7 VIH Min, V 2 2 1.7 Max, V 3.6 3.6 2.7 1.9 1.575 1.26 VOL Max, V 0.4 0.2 0.7 0.45 0.25 * VCCI 0.25 * VCCI VOH Min, V 2.4 VCCI – 0.2 1.7 VCCI – 0.45 0.75 * VCCI 0.75 * VCCI IOL mA 12 0.1 12 8 4 2 IOH mA 12 0.1 12 8 4 2 VIL Drive Slew Strength Rate Min., V Max., V 12 mA Any2 12 mA 12 mA 12 mA 2 mA High High High High High High –0.3 –0.3 –0.3 –0.3 –0.3 –0.3 0.8 0.8 0.7 VIH Min., V 2 2 1.7 Max., V 3.6 3.6 2.7 1.9 1.575 1.26 VOL Max., V 0.4 0.2 0.7 0.45 0.25 * VCCI 0.25 * VCCI VOH Min., V 2.4 VCCI – 0.2 1.7 VCCI – 0.45 0.75 * VCCI 0.75 * VCCI IOL1 IOH1 mA mA 12 0.1 12 12 12 2 12 0.1 12 12 12 2
0.35 * VCCI 0.65 * VCCI 0.35 * VCCI 0.65 * VCCI 0.35 * VCCI 0.65 * VCCI
Per PCI specifications Per PCI-X specifications
0.35 * VCCI 0.65 * VCCI 0.35 * VCCI 0.65 * VCCI 0.35 * VCCI 0.65 * VCCI
Per PCI specifications Per PCI-X specifications
A dv a n c e v 0. 5
2 - 23
IGLOO DC and Switching Characteristics Table 2-26 • Summary of Maximum and Minimum DC Input and Output Levels Applicable to Commercial and Industrial Conditions—Software Default Settings Applicable to Standard I/O Banks I/O Standard 3.3 V LVTTL / 3.3 V LVCMOS 3.3 V LVCMOS Wide Range 2.5 V LVCMOS 1.8 V LVCMOS 1.5 V LVCMOS 1.2 V LVCMOS3 Notes: 1. Currents are measured at 85°C junction temperature. 2. All LVMCOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JDEC8a specification. 3. Applicable to V2 Devices only. Table 2-27 • Summary of Maximum and Minimum DC Input Levels Applicable to Commercial and Industrial Conditions Commercial1 IIL DC I/O Standards 3.3 V LVTTL / 3.3 V LVCMOS 3.3 V LVCMOS Wide Range 2.5 V LVCMOS 1.8 V LVCMOS 1.5 V LVCMOS 1.2 V LVCMOS 3.3 V PCI 3.3 V PCI-X Notes: 1. Commercial range (0°C < TA < 70°C) 2. Industrial range (–40°C < TA < 85°C) 3. Applicable to V2 Devices only.
3
VIL Drive Slew Strength Rate Min, V Max, V 8 mA Any2 8 mA 4 mA 2 mA 1 mA High High High High High High –0.3 –0.3 –0.3 –0.3 –0.3 –0.3 0.8 0.8 0.7
VIH Min, V 2 2 1.7 Max, V 3.6 3.6 2.7 1.9 1.575 1.26
VOL Max, V 0.4 0.2 0.7 0.45 0.25 * VCCI 0.25 * VCCI
VOH Min, V 2.4 VCCI – 0.2 1.7 VCCI – 0.45 0.75 * VCCI 0.75 * VCCI
IOL1 IOH1 mA mA 8 0.1 8 4 2 1 8 0.1 8 4 2 1
0.35 * VCCI 0.65 * VCCI 0.35 * VCCI 0.65 * VCCI 0.35 * VCCI 0.65 * VCCI
Industrial2 IIH µA 10 10 10 10 10 10 10 10 IIL µA 15 15 15 15 15 15 15 15 IIH µA 15 15 15 15 15 15 15 15
µA 10 10 10 10 10 10 10 10
2 -2 4
A d v a n c e v 0. 5
IGLOO DC and Switching Characteristics
Summary of I/O Timing Characteristics – Default I/O Software Settings
Table 2-28 • Summary of AC Measuring Points Standard 3.3 V LVTTL / 3.3 V LVCMOS 2.5 V LVCMOS 1.8 V LVCMOS 1.5 V LVCMOS 1.2 V LVCMOS 3.3 V PCI Measuring Trip Point (Vtrip) 1.4 V 1.2 V 0.90 V 0.75 V 0.60 V 0.285 * VCCI (RR) 0.615 * VCCI (FF) 3.3 V PCI-X 0.285 * VCCI (RR) 0.615 * VCCI (FF) Table 2-29 • I/O AC Parameter Definitions Parameter tDP tPY tDOUT tEOUT tDIN tHZ tZH tLZ tZL tZHS tZLS Parameter Definition Data to Pad delay through the Output Buffer Pad to Data delay through the Input Buffer Data to Output Buffer delay through the I/O interface Enable to Output Buffer Tristate Control delay through the I/O interface Input Buffer to Data delay through the I/O interface Enable to Pad delay through the Output Buffer—HIGH to Z Enable to Pad delay through the Output Buffer—Z to HIGH Enable to Pad delay through the Output Buffer—LOW to Z Enable to Pad delay through the Output Buffer—Z to LOW Enable to Pad delay through the Output Buffer with delayed enable—Z to HIGH Enable to Pad delay through the Output Buffer with delayed enable—Z to LOW
A dv a n c e v 0. 5
2 - 25
IGLOO DC and Switching Characteristics Table 2-30 • Summary of I/O Timing Characteristics—Software Default Settings, Std. Speed Grade, Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V Applicable to Advanced I/O Banks External Resistor (Ω) Capacitive Load (pF) Drive Strength (mA)
I/O Standard
tEO UT (ns)
Slew Rate
tDOUT (ns)
tPY (ns)
tZHS (ns) – –
tDIN (ns)
tDP (ns)
tZL (ns)
tZLS (ns)
tZH (ns)
tHZ (ns)
tLZ (ns)
3.3 V LVTTL / 3.3 V LVCMOS 2.5 V LVCMOS 1.8 V LVCMOS 1.5 V LVCMOS 3.3 V PCI 3.3 V PCI-X LVDS LVPECL Notes:
12 mA 12 mA 12 mA 12 mA Per PCI spec
High 5 pF High High High 5 pF 5 pF 5 pF
– – – –
0.97 2.09 0.19 0.85 0.66 2.13 1.67 2.67 3.04 5.66 5.20 ns 0.97 2.09 0.19 1.07 0.66 2.13 1.82 2.73 2.93 5.66 5.35 ns 0.97 2.24 0.19 1.01 0.66 2.28 1.99 3.02 3.39 5.81 5.52 ns 0.97 2.50 0.19 1.17 0.66 2.55 2.26 3.20 3.48 6.08 5.79 ns
High 10pF
25 2 0.97 2.32 0.19 0.73 0.66 2.36 1.77 2.67 3.04 5.89 5.30 ns 25 2 0.97 2.32 0.19 0.70 0.66 2.36 1.77 2.67 3.04 5.89 5.30 ns – – 0.97 1.67 0.19 1.31 0.97 1.67 0.19 1.16 – – – – – – – – – – – – ns ns
Per PCI-X High 10pF spec 24 mA 24 mA High High – –
1. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. 2. Resistance is used to measure I/O propagation delays as defined in PCI specifications. See Figure 2-12 on page 2-62 for connectivity. This resistor is not required during normal operation.
2 -2 6
A d v a n c e v 0. 5
Units
IGLOO DC and Switching Characteristics Table 2-31 • Summary of I/O Timing Characteristics—Software Default Settings, Std. Speed Grade, Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V Applicable to Standard Plus I/O Banks External Resistor (Ω) Capacitive Load (pF) Drive Strength (mA)
I/O Standard
tEO UT (ns)
Slew Rate
tDOUT (ns)
tPY (ns)
tZHS (ns) tHZ (ns) 2.26 2.14 2.06 2.03
tDIN (ns)
tDP (ns)
tZL (ns)
tZLS (ns)
tZH (ns)
tHZ (ns)
tLZ (ns)
3.3 V LVTTL / 3.3 V LVCMOS 2.5 V LVCMOS 1.8 V LVCMOS 1.5 V LVCMOS 3.3 V PCI 3.3 V PCI-X
12 mA 12 mA 8 mA 4 mA Per PCI spec Per PCI-X spec
High High High High
5 pF 5 pF 5 pF 5 pF
– – – –
0.97 1.75 0.19 0.85 0.66 1.78 1.39 2.36 2.79 5.31 4.92 ns 0.97 1.75 0.19 1.08 0.66 1.78 1.51 2.38 2.69 5.32 5.04 ns 0.97 1.97 0.19 1.01 0.66 2.01 1.76 2.46 2.66 5.54 5.29 ns 0.97 2.25 0.19 1.17 0.66 2.29 1.99 2.53 2.68 5.82 5.52 ns
High 10pF High 10pF
25 2 0.97 1.96 0.19 0.73 0.66 2.00 1.50 2.36 2.79 5.53 5.03 ns 25 2 0.97 1.96 0.19 0.70 0.66 2.00 1.50 2.36 2.79 5.53 5.03 ns
Notes: 1. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. 2. Resistance is used to measure I/O propagation delays as defined in PCI specifications. See Figure 2-12 on page 2-62 for connectivity. This resistor is not required during normal operation. Table 2-32 • Summary of I/O Timing Characteristics—Software Default Settings, Std. Speed Grade, Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V Applicable to Standard I/O Banks External Resistor (Ω) Capacitive Load (pF) Drive Strength (mA)
I/O Standard
tEOU T (ns)
Slew Rate
tDOUT (ns)
tDP (ns)
tDIN (ns)
tPY (ns)
tZH (ns)
tZL (ns)
tLZ (ns)
3.3 V LVTTL / 3.3 V LVCMOS 2.5 V LVCMOS 1.8 V LVCMOS 1.5 V LVCMOS Notes:
8 mA 8 mA 4 mA 2 mA
High High High High
5 pF 5 pF 5 pF 5 pF
– – – –
0.97 0.97 0.97 0.97
1.85 1.88 2.18 2.51
0.19 0.19 0.19 0.19
0.83 1.04 0.98 1.13
0.66 0.66 0.66 0.66
1.88 1.92 2.22 2.56
1.45 1.62 1.93 2.20
1.96 1.95 1.96 1.99
1. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. 2. Resistance is used to measure I/O propagation delays as defined in PCI specifications. See Figure 2-12 on page 2-62 for connectivity. This resistor is not required during normal operation.
A dv a n c e v 0. 5
2 - 27
Units ns ns ns ns
Units
IGLOO DC and Switching Characteristics Table 2-33 • Summary of I/O Timing Characteristics—Software Default Settings, Std. Speed Grade, Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 3.0 V Applicable to Advanced I/O Banks External Resistor (Ω) Capacitive Load (pF) Drive Strength (mA)
I/O Standard
tEO UT (ns)
Slew Rate
tDOUT (ns)
tPY (ns)
tZHS (ns) – –
tDIN (ns)
tDP (ns)
tZL (ns)
tZLS (ns)
tZH (ns)
tHZ (ns)
tLZ (ns)
3.3 V LVTTL / 3.3 V LVCMOS 2.5 V LVCMOS 1.8 V LVCMOS 1.5 V LVCMOS 1.2 V LVCMOS 3.3 V PCI 3.3 V PCI-X LVDS LVPECL Notes:
12 mA 12 mA 12 mA 12 mA 2 mA Per PCI spec
High 5 pF High High High High 5 pF 5 pF 5 pF 5p
– – – – –
2
1.55 2.66 0.26 0.98 1.10 2.71 2.18 3.23 3.92 8.52 7.99 ns 1.55 2.63 0.26 1.20 1.10 2.68 2.30 3.28 3.77 8.48 8.10 ns 1.55 2.71 0.26 1.11 1.10 2.76 2.44 3.56 4.17 8.57 8.24 ns 1.55 2.95 0.26 1.27 1.10 3.00 2.70 3.74 4.21 8.81 8.51 ns 1.55 3.61 0.26 1.58 1.10 3.45 3.33 3.94 3.66 9.05 8.93 ns 1.55 2.90 0.26 0.86 1.10 2.95 2.29 3.23 3.92 8.76 8.10 ns
High 10pF 25
Per PCI-X High 10pF 25 2 1.55 2.90 0.25 0.86 1.10 2.95 2.29 3.23 3.92 8.76 8.10 ns spec 24 mA 24 mA High High – – – – 1.55 2.19 0.25 1.52 1.55 2.24 0.25 1.37 – – – – – – – – – – – – ns ns
1. For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values. 2. Resistance is used to measure I/O propagation delays as defined in PCI specifications. See Figure 2-12 on page 2-62 for connectivity. This resistor is not required during normal operation.
2 -2 8
A d v a n c e v 0. 5
Units
IGLOO DC and Switching Characteristics Table 2-34 • Summary of I/O Timing Characteristics—Software Default Settings, Std. Speed Grade, Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 3.0 V Applicable to Standard Plus I/O Banks External Resistor (Ω) Capacitive Load (pF) Drive Strength (mA)
I/O Standard
tE OUT (ns)
Slew Rate
tDOUT (ns)
tDIN (ns)
tDP (ns)
tZLS (ns)
tPY (ns)
tZL (ns)
tLZ (ns)
tZHS (ns) tHZ (ns) 2.94 2.79 2.61 2.54 2.50
tZH (ns)
tHZ (ns)
3.3 V LVTTL / 3.3 V LVCMOS 2.5 V LVCMOS 1.8 V LVCMOS 1.5 V LVCMOS 1.2 V LVCMOS 3.3 V PCI 3.3 V PCI-X Notes:
12 mA 12 mA 8 mA 4 mA 2 mA Per PCI spec
High 5 pF High 5 pF High 5 pF High 5 pF High 5 pF
– – – – –
1.55 2.30 0.26 0.97 1.10 2.34 1.87 2.91 3.62 8.15 7.67 1.55 2.28 0.26 1.20 1.10 2.32 1.95 2.92 3.50 8.13 7.75 1.55 2.42 0.26 1.11 1.10 2.47 2.16 2.98 3.38 8.28 7.97 1.55 2.67 0.26 1.27 1.10 2.72 2.39 3.05 3.36 8.53 8.20 1.55 3.23 0.26 1.58 1.10 3.09 2.76 3.30 3.49 8.69 8.36
High 10pF 25 2 1.55 2.52 0.26 0.85 1.10 2.57 1.98 2.91 3.62 8.37 7.78
Per PCI-X High 10pF 25 2 1.55 2.52 0.25 0.85 1.10 2.57 1.98 2.91 3.62 8.37 7.78 spec
1. For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values. 2. Resistance is used to measure I/O propagation delays as defined in PCI specifications. See Figure 2-12 on page 2-62 for connectivity. This resistor is not required during normal operation. Table 2-35 • Summary of I/O Timing Characteristics—Software Default Settings, Std. Speed Grade, Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 3.0 V Applicable to Standard I/O Banks External Resistor (Ω) Capacitive Load (pF) Drive Strength (mA)
I/O Standard
tDP (ns)
tEOU T (ns)
Slew Rate
tDOUT (ns)
tDIN (ns)
tPY (ns)
tZH (ns)
tZL (ns)
tLZ (ns)
3.3 V LVTTL / 3.3 V LVCMOS 2.5 V LVCMOS 1.8 V LVCMOS 1.5 V LVCMOS 1.2 V LVCMOS Notes:
8 mA 8 mA 4 mA 2 mA 1 mA
High High High High High
5 pF 5 pF 5 pF 5 pF 5 pF
– – – – –
1.55 1.55 1.55 1.55 1.55
2.37 2.38 2.60 2.91 3.60
0.26 0.26 0.26 0.26 0.26
0.94 1.15 1.08 1.22 1.52
1.10 1.10 1.10 1.10 1.10
2.42 2.42 2.64 2.96 3.45
1.92 2.05 2.33 2.60 3.04
2.39 2.37 2.37 2.39 2.52
1. For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values. 2. Resistance is used to measure I/O propagation delays as defined in PCI specifications. See Figure 2-12 on page 2-62 for connectivity. This resistor is not required during normal operation.
A dv a n c e v 0. 5
2 - 29
Units ns ns ns ns ns
Units ns ns ns ns ns ns ns
IGLOO DC and Switching Characteristics
Detailed I/O DC Characteristics
Table 2-36 • Input Capacitance Symbol CIN CINCLK Input capacitance Input capacitance on the clock pin Definition Conditions VIN = 0, f = 1.0 MHz VIN = 0, f = 1.0 MHz Min. Max. 8 8 Units pF pF
Table 2-37 • I/O Output Buffer Maximum Resistances1 Applicable to Advanced I/O Banks Standard 3.3 V LVTTL / 3.3 V LVCMOS Drive Strength 2 mA 4 mA 6 mA 8 mA 12 mA 16 mA 24 mA 2.5 V LVCMOS 2 mA 4 mA 6 mA 8 mA 12 mA 16 mA 24 mA 1.8 V LVCMOS 2 mA 4 mA 6 mA 8 mA 12 mA 16 mA 1.5 V LVCMOS 2 mA 4 mA 6 mA 8 mA 12 mA 1.2 V LVCMOS 3.3 V PCI/PCI-X Notes: 1. These maximum values are provided for informational reasons only. Minimum output buffer resistance values depend on VCCI, drive strength selection, temperature, and process. For board design considerations and detailed output buffer resistances, use the corresponding IBIS models located on the Actel website at http://www.actel.com/download/ibis/default.aspx. 2. R(PULL-DOWN-MAX) = (VOLspec) / IOLspec 3. R(PULL-UP-MAX) = (VCCImax – VOHspec) / IOHs pe c 2 mA Per PCI/PCI-X specification RPULL-DOWN (Ω)2 100 100 50 50 25 17 11 100 100 50 50 25 17 11 100 100 50 50 25 20 200 100 67 33 33 TBD 25 RPULL-UP (Ω)3 300 300 150 150 75 50 33 300 300 150 150 75 50 33 200 200 100 100 50 40 224 112 75 37 37 TBD 75
2 -3 0
A d v a n c e v 0. 5
IGLOO DC and Switching Characteristics Table 2-38 • I/O Output Buffer Maximum Resistances1 Applicable to Standard Plus I/O Banks Standard 3.3 V LVTTL / 3.3 V LVCMOS Drive Strength 2 mA 4 mA 6 mA 8 mA 12 mA 16 mA 2.5 V LVCMOS 2 mA 4 mA 6 mA 8 mA 12 mA 1.8 V LVCMOS 2 mA 4 mA 6 mA 8 mA 1.5 V LVCMOS 2 mA 4 mA 1.2 V LVCMOS 3.3 V PCI/PCI-X Notes: 1. These maximum values are provided for informational reasons only. Minimum output buffer resistance values depend on VCCI, drive strength selection, temperature, and process. For board design considerations and detailed output buffer resistances, use the corresponding IBIS models located on the Actel website at http://www.actel.com/download/ibis/default.aspx. 2. R(PULL-DOWN-MAX) = (VOLspec) / IOLspec 3. R(PULL-UP-MAX) = (VCCImax – VOHspec) / IOHs pe c 2 mA Per PCI/PCI-X specification RPULL-DOWN (Ω)2 100 100 50 50 25 25 100 100 50 50 25 200 100 50 50 200 100 TBD 25 RPULL-UP (Ω)3 300 300 150 150 75 75 200 200 100 100 50 225 112 56 56 224 112 TBD 75
A dv a n c e v 0. 5
2 - 31
IGLOO DC and Switching Characteristics Table 2-39 • I/O Output Buffer Maximum Resistances1 Applicable to Standard I/O Banks Standard 3.3 V LVTTL / 3.3 V LVCMOS Drive Strength 2 mA 4 mA 6 mA 8 mA 2.5 V LVCMOS 2 mA 4 mA 6 mA 8 mA 1.8 V LVCMOS 2 mA 4 mA 1.5 V LVCMOS 1.2 V LVCMOS Notes: 1. These maximum values are provided for informational reasons only. Minimum output buffer resistance values depend on VCCI, drive strength selection, temperature, and process. For board design considerations and detailed output buffer resistances, use the corresponding IBIS models located on the Actel website at http://www.actel.com/download/ibis/default.aspx. 2. R(PULL-DOWN-MAX) = (VOLspec) / IOLspec 3. R(PULL-UP-MAX) = (VCCImax – VOHspec) / IOHs pe c Table 2-40 • I/O Weak Pull-Up/Pull-Down Resistances Minimum and Maximum Weak Pull-Up/Pull-Down Resistance Values R(WEAK PULL-UP)1 (Ω) VCCI 3.3 V 2.5 V 1.8 V 1.5 V 1.2 V Notes: 1. R(WEAK PULL-UP-MAX) = (VOLspec) / I(WEAK PULL-UP-MIN) 2. R(WEAK PULL-UP-MAX) = (VCCImax – VOHspec) / I(WEAK PULL-UP-MIN) Min. 10 k 11 k 18 k 19 k TBD Max. 45 k 55 k 70 k 90 k TBD R(WEAK PULL-DOWN)2 (Ω) Min. 10 k 12 k 17 k 19 k TBD Max. 45 k 74 k 110 k 140 k TBD 2 mA 1 mA RPULL-DOWN (Ω)2 100 100 50 50 100 100 50 50 200 100 200 TBD RPULL-UP (Ω)3 300 300 150 150 200 200 100 100 225 112 224 TBD
2 -3 2
A d v a n c e v 0. 5
IGLOO DC and Switching Characteristics Table 2-41 • I/O Short Currents IOSH/IOSL Applicable to Advanced I/O Banks Drive Strength 3.3 V LVTTL / 3.3 V LVCMOS 2 mA 4 mA 6 mA 8 mA 12 mA 16 mA 24 mA 2.5 V LVCMOS 2 mA 4 mA 6 mA 8 mA 12 mA 16 mA 24 mA 1.8 V LVCMOS 2 mA 4 mA 6 mA 8 mA 12 mA 16 mA 1.5 V LVCMOS 2 mA 4 mA 6 mA 8 mA 12 mA 1.2 V LVCMOS 3.3 V PCI/PCI-X * TJ = 100°C 2 mA Per PCI/PCI-X specification IOSL (mA)* 25 25 51 51 103 132 268 16 16 32 32 65 83 169 9 17 35 45 91 91 13 25 32 66 66 TBD 103 IOSH (mA)* 27 27 54 54 109 127 181 18 18 37 37 74 87 124 11 22 44 51 74 74 16 33 39 55 55 TBD 109
A dv a n c e v 0. 5
2 - 33
IGLOO DC and Switching Characteristics Table 2-42 • I/O Short Currents IOSH/IOSL Applicable to Standard Plus I/O Banks Drive Strength 3.3 V LVTTL / 3.3 V LVCMOS 2 mA 4 mA 6 mA 8 mA 12 mA 16 mA 2.5 V LVCMOS 2 mA 4 mA 6 mA 8 mA 12 mA 1.8 V LVCMOS 2 mA 4 mA 6 mA 8 mA 1.5 V LVCMOS 2 mA 4 mA 1.2 V LVCMOS 3.3 V PCI/PCI-X * TJ = 100°C Table 2-43 • I/O Short Currents IOSH/IOSL Applicable to Standard I/O Banks Drive Strength 3.3 V LVTTL / 3.3 V LVCMOS 2 mA 4 mA 6 mA 8 mA 2.5 V LVCMOS 2 mA 4 mA 6 mA 8 mA 1.8 V LVCMOS 1.5 V LVCMOS 1.2 V LVCMOS * TJ = 100°C 2 mA 4 mA 2 mA 1 mA IOSL (mA)* 25 25 51 51 16 16 32 32 9 17 13 TBD IOSH (mA)* 27 27 54 54 18 18 37 37 11 22 16 TBD 2 mA Per PCI/PCI-X specification IOSL (mA)* 25 25 51 51 103 103 16 16 32 32 65 9 17 35 35 13 25 TBD 103 IOSH (mA)* 27 27 54 54 109 109 18 18 37 37 74 11 22 44 44 16 33 TBD 109
2 -3 4
A d v a n c e v 0. 5
IGLOO DC and Switching Characteristics The length of time an I/O can withstand IOSH/IOSL events depends on the junction temperature. The reliability data below is based on a 3.3 V, 12 mA I/O setting, which is the worst case for this type of analysis. For example, at 110°C, the short current condition would have to be sustained for more than three months to cause a reliability concern. The I/O design does not contain any short circuit protection, but such protection would only be needed in extremely prolonged stress conditions. Table 2-44 • Duration of Short Circuit Event before Failure Temperature –40°C 0°C 25°C 70°C 85°C 100°C 110°C Time before Failure > 20 years > 20 years > 20 years 5 years 2 years 6 months 3 months
Table 2-45 • I/O Input Rise Time, Fall Time, and Related I/O Reliability Input Buffer LVTTL/LVCMOS LVDS/B-LVDS/M-LVDS/ LVPECL Input Rise/Fall Time (min.) No requirement No requirement Input Rise/Fall Time (max.) 10 ns * 10 ns * Reliability 20 years (110°C) 10 years (100°C)
* The maximum input rise/fall time is related to the noise induced into the input buffer trace. If the noise is low, then the rise time and fall time of input buffers can be increased beyond the maximum value. The longer the rise/fall times, the more susceptible the input signal is to the board noise. Actel recommends signal integrity evaluation/characterization of the system to ensure that there is no excessive noise coupling into input signals.
A dv a n c e v 0. 5
2 - 35
IGLOO DC and Switching Characteristics
Single-Ended I/O Characteristics
3.3 V LVTTL / 3.3 V LVCMOS
Low-Voltage Transistor–Transistor Logic (LVTTL) is a general-purpose standard (EIA/JESD) for 3.3 V applications. It uses an LVTTL input buffer and push-pull output buffer. Furthermore, all LVCMOS 3.3 V software macros comply with LVCMOS 3.3 V wide range as specified in the JESD8a specification. Table 2-46 • Minimum and Maximum DC Input and Output Levels Applicable to Advanced I/O Banks 3.3 V LVTTL / 3.3 V LVCMOS Drive Strength 2 mA 4 mA 6 mA 8 mA 12 mA 16 mA 24 mA Notes: 1. Currents are measured at 100°C junction temperature and maximum voltage. 2. Currents are measured at 85°C junction temperature. 3. Software default selection highlighted in gray. Table 2-47 • Minimum and Maximum DC Input and Output Levels Applicable to Standard Plus I/O Banks 3.3 V LVTTL / 3.3 V LVCMOS Drive Strength 2 mA 4 mA 6 mA 8 mA 12 mA 16 mA Notes: 1. Currents are measured at 100°C junction temperature and maximum voltage. 2. Currents are measured at 85°C junction temperature. 3. Software default selection highlighted in gray. VIL VIH VOL VOH IOL IOH IOSL IOSH IIL IIH VIL VIH VOL VOH IOL IOH IOSL IOSH IIL IIH
Min., V Max., V Min., V Max., V Max., V Min., V mA mA Max., mA1 Max., mA1 µA2 µA2 –0.3 –0.3 –0.3 –0.3 –0.3 –0.3 –0.3 0.8 0.8 0.8 0.8 0.8 0.8 0.8 2 2 2 2 2 2 2 3.6 3.6 3.6 3.6 3.6 3.6 3.6 0.4 0.4 0.4 0.4 0.4 0.4 0.4 2.4 2.4 2.4 2.4 2.4 2.4 2.4 2 4 6 8 2 4 6 8 25 25 51 51 103 132 268 27 27 54 54 109 127 181 10 10 10 10 10 10 10 10 10 10 10 10 10 10
12 12 16 16 24 24
Min., V Max., V Min., V Max., V Max., V Min., V mA mA Max., mA1 Max., mA1 µA2 µA2 –0.3 –0.3 –0.3 –0.3 –0.3 –0.3 0.8 0.8 0.8 0.8 0.8 0.8 2 2 2 2 2 2 3.6 3.6 3.6 3.6 3.6 3.6 0.4 0.4 0.4 0.4 0.4 0.4 2.4 2.4 2.4 2.4 2.4 2.4 2 4 6 8 12 16 2 4 6 8 12 16 25 25 51 51 103 103 27 27 54 54 109 109 10 10 10 10 10 10 10 10 10 10 10 10
2 -3 6
A d v a n c e v 0. 5
IGLOO DC and Switching Characteristics Table 2-48 • Minimum and Maximum DC Input and Output Levels Applicable to Standard I/O Banks 3.3 V LVTTL / 3.3 V LVCMOS Drive Strength 2 mA 4 mA 6 mA 8 mA Notes: 1. Currents are measured at 100°C junction temperature and maximum voltage. 2. Currents are measured at 85°C junction temperature. 3. Software default selection highlighted in gray. Table 2-49 • Minimum and Maximum DC Input and Output Levels for LVCMOS 3.3 V Wide Range Applicable to Advanced, Standard Plus, and Standard I/O Banks 3.3 V LVCMOS Wide Range Drive Strength All2 Notes: 1. Currents are measured at 100°C junction temperature and maximum voltage. 2. All LVMCOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JDEC8a specification. Min., V –0.3 VIL Max., V 0.8 Min., V 2 VIH Max., V 3.6 VOL Max., V 0.2 VOH Min., V VCCI – 0.2 IOL mA 0.1 IOH mA 0.1 IIL µA2 10 IIH µA2 10 VIL VIH VOL VOH IOL IOH IOSL IOSH IIL IIH
Min., V Max., V Min., V Max., V Max., V Min., V mA mA Max., mA1 Max., mA1 µA2 µA2 –0.3 –0.3 –0.3 –0.3 0.8 0.8 0.8 0.8 2 2 2 2 3.6 3.6 3.6 3.6 0.4 0.4 0.4 0.4 2.4 2.4 2.4 2.4 2 4 6 8 2 4 6 8 25 25 51 51 27 27 54 54 10 10 10 10 10 10 10 10
Test Point Datapath 5 pF
R=1k Test Point Enable Path
R to VCCI for tLZ/tZL/tZLS R to GND for tHZ/tZH/tZHS 35 pF for tZH/tZHS/tZL/tZLS 5 pF for tHZ/tLZ
Figure 2-7 • AC Loading Table 2-50 • AC Waveforms, Measuring Points, and Capacitive Loads Input LOW (V) 0 Input HIGH (V) 3.3 Measuring Point* (V) 1.4 CLOAD (pF) 5
* Measuring point = Vtrip. See Table 2-28 on page 2-25 for a complete table of trip points.
A dv a n c e v 0. 5
2 - 37
IGLOO DC and Switching Characteristics
Timing Characteristics
Applies to 1.5 V DC Core Voltage Table 2-51 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew – Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V Applicable to Advanced I/O Banks Drive Strength 4 mA 6 mA 8 mA 12 mA 16 mA 24 mA Speed Grade Std. Std. Std. Std. Std. Std. tDOUT 0.97 0.97 0.97 0.97 0.97 0.97 tDP tDIN tPY tEOUT 0.66 0.66 0.66 0.66 0.66 0.66 tZL tZH tLZ tHZ tZLS 8.08 7.34 7.34 6.82 6.66 6.58 tZHS 7.41 6.89 6.89 6.50 6.41 6.43 Units ns ns ns ns ns ns
4.46 0.19 0.85 3.74 0.19 0.85 3.74 0.19 0.85 3.23 0.19 0.85 3.08 0.19 0.85 3.00 0.19 0.85
4.55 3.88 2.24 2.19 3.81 3.36 2.49 2.63 3.81 3.36 2.49 2.63 3.29 2.97 2.66 2.91 3.13 2.88 2.70 2.99 3.05 2.90 2.74 3.27
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. Table 2-52 • 3.3 V LVTTL / 3.3 V LVCMOS High Slew – Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V Applicable to Advanced I/O Banks Drive Strength 4 mA 6 mA 8 mA 12 mA 16 mA 24 mA Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. Table 2-53 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew – Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V Applicable to Standard Plus Banks Drive Strength 4 mA 6 mA 8 mA 12 mA 16 mA Speed Grade Std. Std. Std. Std. Std. tDOUT 0.97 0.97 0.97 0.97 0.97 tDP tDIN tPY tEOUT 0.66 0.66 0.66 0.66 0.66 tZL tZH tLZ tHZ tZLS 7.54 6.83 6.83 6.35 6.35 tZHS 6.98 6.51 6.51 6.15 6.15 Units ns ns ns ns ns Speed Grade Std. Std. Std. Std. Std. Std. tDOUT 0.97 0.97 0.97 0.97 0.97 0.97 tDP tDIN tPY tEOUT 0.66 0.66 0.66 0.66 0.66 0.66 tZL tZH tLZ tHZ tZLS tZHS Units ns ns ns ns ns ns
2.73 0.19 0.85 2.31 0.19 0.85 2.31 0.19 0.85 2.09 0.19 0.85 2.05 0.19 0.85 2.07 0.19 0.85
2.78 2.21 2.25 2.31 6.31 5.74 2.36 1.84 2.50 2.76 5.89 5.37 2.36 1.84 2.50 2.76 5.89 5.37 2.13 1.67 2.67 3.04 5.66 5.20 2.09 1.63 2.70 3.12 5.62 5.16 2.11 1.59 2.75 3.41 5.64 5.12
3.94 0.19 0.85 3.24 0.19 0.85 3.24 0.19 0.85 2.76 0.19 0.85 2.76 0.19 0.85
4.01 3.45 1.98 2.02 3.30 2.98 2.20 2.42 3.30 2.98 2.20 2.42 2.81 2.62 2.36 2.68 2.81 2.62 2.36 2.68
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
2 -3 8
A d v a n c e v 0. 5
IGLOO DC and Switching Characteristics Table 2-54 • 3.3 V LVTTL / 3.3 V LVCMOS High Slew – Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V Applicable to Standard Plus Banks Drive Strength 4 mA 6 mA 8 mA 12 mA 16 mA Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. Table 2-55 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew – Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V Applicable to Standard Banks Drive Strength 2 mA 4 mA 6 mA 8 mA Speed Grade Std. Std. Std. Std. tDOUT 0.97 0.97 0.97 0.97 tDP 3.80 3.80 3.15 3.15 tDIN 0.19 0.19 0.19 0.19 tPY 0.83 0.83 0.83 0.83 tEOUT 0.66 0.66 0.66 0.66 tZL 3.87 3.87 3.20 3.20 tZH 3.40 3.40 2.93 2.93 tLZ 1.74 1.74 1.96 1.96 tHZ 1.78 1.78 2.17 2.17 Units ns ns ns ns Speed Grade Std. Std. Std. Std. Std. tDOUT 0.97 0.97 0.97 0.97 0.97 tDP tDIN tPY tEOUT 0.66 0.66 0.66 0.66 0.66 tZL tZH tLZ tHZ tZLS tZHS Units ns ns ns ns ns
2.32 0.19 0.85 1.94 0.19 0.85 1.94 0.19 0.85 1.75 0.19 0.85 1.75 0.19 0.85
2.36 1.89 1.98 2.13 5.89 5.42 1.98 1.56 2.20 2.53 5.51 5.09 1.98 1.56 2.20 2.53 5.51 5.09 1.78 1.39 2.36 2.79 5.31 4.92 1.78 1.39 2.36 2.79 5.31 4.92
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. Table 2-56 • 3.3 V LVTTL / 3.3 V LVCMOS High Slew – Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V Applicable to Standard Banks Drive Strength 2 mA 4 mA 6 mA 8 mA Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. Speed Grade Std. Std. Std. Std. tDOUT 0.97 0.97 0.97 0.97 tDP 2.19 2.19 1.85 1.85 tDIN 0.19 0.19 0.19 0.19 tPY 0.83 0.83 0.83 0.83 tEOUT 0.66 0.66 0.66 0.66 tZL 2.23 2.23 1.88 1.88 tZH 1.79 1.79 1.45 1.45 tLZ 1.74 1.74 1.96 1.96 tHZ 1.87 1.87 2.26 2.26 Units ns ns ns ns
A dv a n c e v 0. 5
2 - 39
IGLOO DC and Switching Characteristics Applies to 1.2 V DC Core Voltage Table 2-57 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew – Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 3.0 V Applicable to Advanced I/O Banks Drive Strength 4 mA 6 mA 8 mA 12 mA 16 mA 24 mA Speed Grade Std. Std. Std. Std. Std. Std. tDOUT 1.55 1.55 1.55 1.55 1.55 1.55 tDP tDIN tPY tEOUT 1.10 1.10 1.10 1.10 1.10 1.10 tZL tZH tLZ tHZ tZLS tZHS Units ns ns ns ns ns ns
5.11 0.26 0.98 4.37 0.26 0.98 4.37 0.26 0.98 3.84 0.26 0.98 3.68 0.26 0.98 3.60 0.26 0.98
5.21 4.47 2.80 3.01 11.01 10.28 4.45 3.93 3.05 3.46 10.26 4.45 3.93 3.05 3.46 10.26 3.91 3.53 3.23 3.75 3.75 3.44 3.27 3.83 3.67 3.46 3.31 4.12 9.72 9.56 9.48 9.74 9.74 9.34 9.25 9.27
Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values. Table 2-58 • 3.3 V LVTTL / 3.3 V LVCMOS High Slew – Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 3.0 V Applicable to Advanced I/O Banks Drive Strength 4 mA 6 mA 8 mA 12 mA 16 mA 24 mA Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values. Table 2-59 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew – Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 3.0 V Applicable to Standard Plus Banks Drive Strength 4 mA 6 mA 8 mA 12 mA 16 mA Speed Grade Std. Std. Std. Std. Std. tDOUT 1.55 1.55 1.55 1.55 1.55 tDP tDIN tPY tEOUT 1.10 1.10 1.10 1.10 1.10 tZL tZH tLZ tHZ tZLS tZHS 9.79 9.31 9.31 8.94 8.94 Units ns ns ns ns ns Speed Grade Std. Std. Std. Std. Std. Std. tDOUT 1.55 1.55 1.55 1.55 1.55 1.55 tDP tDIN tPY tEOUT 1.10 1.10 1.10 1.10 1.10 1.10 tZL tZH tLZ tHZ tZLS 9.19 8.76 8.76 8.52 8.48 8.50 tZHS 8.56 8.18 8.18 7.99 7.95 7.91 Units ns ns ns ns ns ns
3.32 0.26 0.98 2.90 0.26 0.98 2.90 0.26 0.98 2.66 0.26 0.98 2.62 0.26 0.98 2.64 0.26 0.98
3.38 2.75 2.80 3.16 2.95 2.37 3.06 3.62 2.95 2.37 3.06 3.62 2.71 2.18 3.23 3.92 2.67 2.15 3.27 3.99 2.69 2.10 3.32 4.29
4.55 0.26 0.97 3.83 0.26 0.97 3.83 0.26 0.97 3.34 0.26 0.97 3.34 0.26 0.97
4.64 3.98 2.52 2.81 10.44 3.90 3.50 2.75 3.22 3.90 3.50 2.75 3.22 3.40 3.13 2.92 3.49 3.40 3.13 2.92 3.49 9.71 9.71 9.21 9.21
Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values.
2 -4 0
A d v a n c e v 0. 5
IGLOO DC and Switching Characteristics Table 2-60 • 3.3 V LVTTL / 3.3 V LVCMOS High Slew – Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 3.0 V Applicable to Standard Plus Banks Drive Strength 4 mA 6 mA 8 mA 12 mA 16 mA Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values. Table 2-61 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew – Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 3.0 V Applicable to Standard Banks Drive Strength 2 mA 4 mA 6 mA 8 mA Speed Grade Std. Std. Std. Std. tDOUT 1.55 1.55 1.55 1.55 tDP 4.38 4.38 3.71 3.71 tDIN 0.26 0.26 0.26 0.26 tPY 0.94 0.94 0.94 0.94 tEOUT 1.10 1.10 1.10 1.10 tZL 4.46 4.46 3.78 3.78 tZH 3.91 3.91 3.43 3.43 tLZ 2.16 2.16 2.39 2.39 tHZ 2.43 2.43 2.83 2.83 Units ns ns ns ns Speed Grade Std. Std. Std. Std. Std. tDOUT 1.55 1.55 1.55 1.55 1.55 tDP tDIN tPY tEOUT 1.10 1.10 1.10 1.10 1.10 tZL tZH tLZ tHZ tZLS 8.74 8.35 8.35 8.15 8.15 tZHS 8.19 7.85 7.85 7.67 7.67 Units ns ns ns ns ns
2.88 0.26 0.97 2.49 0.26 0.97 2.49 0.26 0.97 2.30 0.26 0.97 2.30 0.26 0.97
2.93 2.38 2.52 2.94 2.54 2.04 2.75 3.36 2.54 2.04 2.75 3.36 2.34 1.87 2.91 3.62 2.34 1.87 2.91 3.62
Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values. Table 2-62 • 3.3 V LVTTL / 3.3 V LVCMOS High Slew – Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 3.0 V Applicable to Standard Banks Drive Strength 2 mA 4 mA 6 mA 8 mA Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values. Speed Grade Std. Std. Std. Std. tDOUT 1.55 1.55 1.55 1.55 tDP 2.73 2.73 2.37 2.37 tDIN 0.26 0.26 0.26 0.26 tPY 0.94 0.94 0.94 0.94 tEOUT 1.10 1.10 1.10 1.10 tZL 2.78 2.78 2.42 2.42 tZH 2.26 2.26 1.92 1.92 tLZ 2.16 2.16 2.39 2.39 tHZ 2.54 2.54 2.94 2.94 Units ns ns ns ns
A dv a n c e v 0. 5
2 - 41
IGLOO DC and Switching Characteristics
2.5 V LVCMOS
Low-Voltage CMOS for 2.5 V is an extension of the LVCMOS standard (JESD8-5) used for generalpurpose 2.5 V applications. It uses a 5 V–tolerant input buffer and push-pull output buffer. Table 2-63 • Minimum and Maximum DC Input and Output Levels Applicable to Advanced I/O Banks 2.5 V LVCMOS Drive Strength 2 mA 4 mA 6 mA 8 mA 12 mA 16 mA 24 mA Notes: 1. Currents are measured at 100°C junction temperature and maximum voltage. 2. Currents are measured at 85°C junction temperature. 3. Software default selection highlighted in gray. Table 2-64 • Minimum and Maximum DC Input and Output Levels Applicable to Standard Plus I/O Banks 2.5 V LVCMOS Drive Strength 2 mA 4 mA 6 mA 8 mA 12 mA Notes: 1. Currents are measured at 100°C junction temperature and maximum voltage. 2. Currents are measured at 85°C junction temperature. 3. Software default selection highlighted in gray. VIL VIH VOL VOH IOL IOH IOSH IOSL IIL IIH VIL VIH VOL VOH IOL IOH IOSH IOSL IIL IIH
Min., V Max., V Min., V Max., V Max., V Min., V mA mA Max., mA1 –0.3 –0.3 –0.3 –0.3 –0.3 –0.3 –0.3 0.7 0.7 0.7 0.7 0.7 0.7 0.7 1.7 1.7 1.7 1.7 1.7 1.7 1.7 2.7 2.7 2.7 2.7 2.7 2.7 2.7 0.7 0.7 0.7 0.7 0.7 0.7 0.7 1.7 1.7 1.7 1.7 1.7 1.7 1.7 2 4 6 8 12 16 24 2 4 6 8 12 16 24 16 16 32 32 65 83 169
Max., mA1 µA2 µA2 18 18 37 37 74 87 124 10 10 10 10 10 10 10 10 10 10 10 10 10 10
Min., V Max., V Min., V Max., V Max., V Min., V mA mA Max., mA1 –0.3 –0.3 –0.3 –0.3 –0.3 0.7 0.7 0.7 0.7 0.7 1.7 1.7 1.7 1.7 1.7 2.7 2.7 2.7 2.7 2.7 0.7 0.7 0.7 0.7 0.7 1.7 1.7 1.7 1.7 1.7 2 4 6 8 12 2 4 6 8 12 16 16 32 32 65
Max., mA1 µA2 µA2 18 18 37 37 74 10 10 10 10 10 10 10 10 10 10
2 -4 2
A d v a n c e v 0. 5
IGLOO DC and Switching Characteristics Table 2-65 • Minimum and Maximum DC Input and Output Levels Applicable to Standard I/O Banks 2.5 V LVCMOS Drive Strength 2 mA 4 mA 6 mA 8 mA Notes: 1. Currents are measured at 100°C junction temperature and maximum voltage. 2. Currents are measured at 85°C junction temperature. 3. Software default selection highlighted in gray. VIL VIH VOL VOH IOL IOH IOSH IOSL IIL IIH
Min., V Max., V Min., V Max., V Max., V Min., V mA mA Max., mA1 –0.3 –0.3 –0.3 –0.3 0.7 0.7 0.7 0.7 1.7 1.7 1.7 1.7 2.7 2.7 2.7 2.7 0.7 0.7 0.7 0.7 1.7 1.7 1.7 1.7 2 4 6 8 2 4 6 8 16 16 32 32
Max., mA1 µA2 µA2 18 18 37 37 10 10 10 10 10 10 10 10
Test Point Datapath 5 pF
R=1k Test Point Enable Path
R to VCCI for tLZ/tZL/tZLS R to GND for tHZ/tZH/tZHS 35 pF for tZH/tZHS/tZL/tZLS 5 pF for tHZ/tLZ
Figure 2-8 • AC Loading Table 2-66 • AC Waveforms, Measuring Points, and Capacitive Loads Input LOW (V) 0 Input HIGH (V) 2.5 Measuring Point* (V) 1.2 CLOAD (pF) 5
* Measuring point = Vtrip. See Table 2-28 on page 2-25 for a complete table of trip points.
A dv a n c e v 0. 5
2 - 43
IGLOO DC and Switching Characteristics
Timing Characteristics
Applies to 1.5 V DC Core Voltage Table 2-67 • 2.5 V LVCMOS Low Slew – Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V Applicable to Advanced I/O Banks Drive Strength 4 mA 6 mA 8 mA 12 mA 16 mA 24 mA Speed Grade Std. Std. Std. Std. Std. Std. tDOUT 0.97 0.97 0.97 0.97 0.97 0.97 tDP tDIN tPY tEOUT 0.66 0.66 0.66 0.66 0.66 0.66 tZL tZH tLZ tHZ tZLS 8.58 7.76 7.76 7.17 6.98 6.90 tZHS 8.11 7.46 7.46 6.99 6.88 6.90 Units ns ns ns ns ns ns
4.96 0.19 1.07 4.15 0.19 1.07 4.15 0.19 1.07 3.57 0.19 1.07 3.39 0.19 1.07 3.37 0.19 1.07
5.05 4.58 2.26 1.99 4.23 3.93 2.54 2.51 4.23 3.93 2.54 2.51 3.64 3.46 2.73 2.83 3.45 3.35 2.77 2.92 3.37 3.37 2.83 3.25
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. Table 2-68 • 2.5 V LVCMOS High Slew – Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V Applicable to Advanced I/O Banks Drive Strength 4 mA 6 mA 8 mA 12 mA 16 mA 24 mA Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. Table 2-69 • 2.5 V LVCMOS Low Slew – Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V Applicable to Standard Plus Banks Drive Strength 4 mA 6 mA 8 mA 12 mA Speed Grade Std. Std. Std. Std. tDOUT 0.97 0.97 0.97 0.97 tDP tDIN tPY tEOUT 0.66 0.66 0.66 0.66 tZL tZH tLZ tHZ tZLS 8.03 7.22 7.22 6.67 tZHS 7.62 7.04 7.04 6.61 Units ns ns ns ns Speed Grade Std. Std. Std. Std. Std. Std. tDOUT 0.97 0.97 0.97 0.97 0.97 0.97 tDP tDIN tPY tEOUT 0.66 0.66 0.66 0.66 0.66 0.66 tZL tZH tLZ tHZ tZLS 6.35 5.91 5.91 5.66 5.61 5.62 tZHS 6.12 5.60 5.60 5.35 5.31 5.24 Units ns ns ns ns ns ns
2.77 0.19 1.07 2.34 0.19 1.07 2.34 0.19 1.07 2.09 0.19 1.07 2.04 0.19 1.07 2.05 0.19 1.07
2.82 2.59 2.26 2.08 2.38 2.07 2.54 2.60 2.38 2.07 2.54 2.60 2.13 1.82 2.73 2.93 2.08 1.77 2.77 3.01 2.09 1.71 2.83 3.35
4.42 0.19 1.08 3.62 0.19 1.08 3.62 0.19 1.08 3.08 0.19 1.08
4.50 4.09 1.96 1.85 3.69 3.51 2.21 2.31 3.69 3.51 2.21 2.31 3.14 3.08 2.39 2.61
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
2 -4 4
A d v a n c e v 0. 5
IGLOO DC and Switching Characteristics Table 2-70 • 2.5 V LVCMOS High Slew – Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V Applicable to Standard Plus Banks Drive Strength 4 mA 6 mA 8 mA 12 mA Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. Table 2-71 • 2.5 V LVCMOS Low Slew – Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V Applicable to Standard Banks Drive Strength 2 mA 4 mA 6 mA 8 mA Speed Grade Std. Std. Std. Std. tDOUT 0.97 0.97 0.97 0.97 tDP 4.27 4.27 3.54 3.54 tDIN 0.19 0.19 0.19 0.19 tPY 1.04 1.04 1.04 1.04 tEOUT 0.66 0.66 0.66 0.66 tZL 4.35 4.35 3.60 3.60 tZH 4.06 4.06 3.47 3.47 tLZ 1.71 1.71 1.95 1.95 tHZ 1.62 1.62 2.07 2.07 Units ns ns ns ns Speed Grade Std. Std. Std. Std. tDOUT 0.97 0.97 0.97 0.97 tDP tDIN tPY tEOUT 0.66 0.66 0.66 0.66 tZL tZH tLZ tHZ tZLS tZHS 5.74 5.27 5.27 5.04 Units ns ns ns ns
2.36 0.19 1.08 1.97 0.19 1.08 1.97 0.19 1.08 1.75 0.19 1.08
2.40 2.21 1.96 1.92 5.93 2.00 1.74 2.21 2.39 5.53 2.00 1.74 2.21 2.39 5.53 1.78 1.51 2.38 2.69 5.32
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. Table 2-72 • 2.5 V LVCMOS High Slew – Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V Applicable to Standard Banks Drive Strength 2 mA 4 mA 6 mA 8 mA Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. Speed Grade Std. Std. Std. Std. tDOUT 0.97 0.97 0.97 0.97 tDP 2.24 2.24 1.88 1.88 tDIN 0.19 0.19 0.19 0.19 tPY 1.04 1.04 1.04 1.04 tEOUT 0.66 0.66 0.66 0.66 tZL 2.28 2.28 1.92 1.92 tZH 2.08 2.08 1.62 1.62 tLZ 1.71 1.71 1.95 1.95 tHZ 1.68 1.68 2.14 2.14 Units ns ns ns ns
A dv a n c e v 0. 5
2 - 45
IGLOO DC and Switching Characteristics Applies to 1.2 V Core Voltage Table 2-73 • 2.5 V LCMOS Low Slew – Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 2.3 V Applicable to Advanced I/O Banks Drive Strength 4 mA 6 mA 8 mA 12 mA 16 mA 24 mA Speed Grade Std. Std. Std. Std. Std. Std. tDOUT 1.55 1.55 1.55 1.55 1.55 1.55 tDP tDIN tPY tEOUT 1.10 1.10 1.10 1.10 1.10 1.10 tZL tZH tLZ tHZ tZLS tZHS Units ns ns ns ns ns ns
5.58 0.26 1.20 4.75 0.26 1.20 4.75 0.26 1.20 4.15 0.26 1.20 3.97 0.26 1.20 3.90 0.26 1.20
5.68 5.14 2.80 2.78 11.49 10.95 4.84 4.47 3.09 3.31 10.65 10.28 4.84 4.47 3.09 3.31 10.65 10.28 4.23 3.99 3.28 3.65 10.04 4.04 3.88 3.33 3.74 3.96 3.90 3.38 4.07 9.85 9.77 9.80 9.69 9.71
Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values. Table 2-74 • 2.5 V LCMOS High Slew – Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 2.3 V Applicable to Advanced I/O Banks Drive Strength 4 mA 6 mA 8 mA 12 mA 16 mA 24 mA Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values. Table 2-75 • 2.5 V LCMOS Low Slew – Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 2.3 V Applicable to Standard Plus Banks Drive Strength 4 mA 6 mA 8 mA 12 mA Speed Grade Std. Std. Std. Std. tDOUT 1.55 1.55 1.55 1.55 tDP tDIN tPY tEOUT 1.10 1.10 1.10 1.10 tZL tZH tLZ tHZ tZLS tZHS Units ns ns ns ns Speed Grade Std. Std. Std. Std. Std. Std. tDOUT 1.55 1.55 1.55 1.55 1.55 1.55 tDP tDIN tPY tEOUT 1.10 1.10 1.10 1.10 1.10 1.10 tZL tZH tLZ tHZ tZLS 9.19 8.74 8.74 8.48 8.44 8.45 tZHS 8.90 8.37 8.37 8.10 8.06 8.00 Units ns ns ns ns ns ns
3.32 0.26 1.20 2.88 0.26 1.20 2.88 0.26 1.20 2.63 0.26 1.20 2.58 0.26 1.20 2.59 0.26 1.20
3.38 3.09 2.80 2.89 2.93 2.56 3.09 3.43 2.93 2.56 3.09 3.43 2.68 2.30 3.28 3.77 2.63 2.25 3.33 3.86 2.64 2.19 3.39 4.21
5.01 0.26 1.20 4.20 0.26 1.20 4.20 0.26 1.20 3.64 0.26 1.20
5.11 4.60 2.49 2.60 10.92 10.41 4.28 4.00 2.74 3.08 10.08 4.28 4.00 2.74 3.08 10.08 3.71 3.56 2.92 3.39 9.52 9.81 9.81 9.36
Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values.
2 -4 6
A d v a n c e v 0. 5
IGLOO DC and Switching Characteristics Table 2-76 • 2.5 V LCMOS High Slew – Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 2.3 V Applicable to Standard Plus Banks Drive Strength 4 mA 6 mA 8 mA 12 mA Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values. Table 2-77 • 2.5 V LCMOS Low Slew – Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 2.3 V Applicable to Standard Banks Drive Strength 2 mA 4 mA 6 mA 8 mA Speed Grade Std. Std. Std. Std. tDOUT 1.55 1.55 1.55 1.55 tDP 4.84 4.84 4.08 4.08 tDIN 0.26 0.26 0.26 0.26 tPY 1.15 1.15 1.15 1.15 tEOUT 1.10 1.10 1.10 1.10 tZL 4.93 4.93 4.16 4.16 tZH 4.56 4.56 3.96 3.96 tLZ 2.12 2.12 2.37 2.37 tHZ 2.22 2.22 2.69 2.69 Units ns ns ns ns Speed Grade Std. Std. Std. Std. tDOUT 1.55 1.55 1.55 1.55 tDP tDIN tPY tEOUT 1.10 1.10 1.10 1.10 tZL tZH tLZ tHZ tZLS 8.76 8.35 8.35 8.13 tZHS 8.47 7.99 7.99 7.75 Units ns ns ns ns
2.90 0.26 1.20 2.50 0.26 1.20 2.50 0.26 1.20 2.28 0.26 1.20
2.95 2.66 2.48 2.70 2.54 2.18 2.74 3.19 2.54 2.18 2.74 3.19 2.32 1.95 2.92 3.50
Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values. Table 2-78 • 2.5 V LCMOS High Slew – Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 2.3 V Applicable to Standard Banks Drive Strength 2 mA 4 mA 6 mA 8 mA Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values. Speed Grade Std. Std. Std. Std. tDOUT 1.55 1.55 1.55 1.55 tDP 2.75 2.75 2.38 2.38 tDIN 0.26 0.26 0.26 0.26 tPY 1.15 1.15 1.15 1.15 tEOUT 1.10 1.10 1.10 1.10 tZL 2.80 2.80 2.42 2.42 tZH 2.53 2.53 2.05 2.05 tLZ 2.12 2.12 2.37 2.37 tHZ 2.31 2.31 2.79 2.79 Units ns ns ns ns
A dv a n c e v 0. 5
2 - 47
IGLOO DC and Switching Characteristics
1.8 V LVCMOS
Low-voltage CMOS for 1.8 V is an extension of the LVCMOS standard (JESD8-5) used for generalpurpose 1.8 V applications. It uses a 1.8 V input buffer and a push-pull output buffer. Table 2-79 • Minimum and Maximum DC Input and Output Levels Applicable to Advanced I/O Banks 1.8 V LVCMOS Drive Strength Min., V 2 mA 4 mA 6 mA 8 mA 12 mA 16 mA Notes: 1. Currents are measured at 100°C junction temperature and maximum voltage. 2. Currents are measured at 85°C junction temperature. 3. Software default selection highlighted in gray. Table 2-80 • Minimum and Maximum DC Input and Output Levels Applicable to Standard Plus I/O Banks 1.8 V LVCMOS Drive Strength Min., V 2 mA 4 mA 6 mA 8 mA Notes: 1. Currents are measured at 100°C junction temperature and maximum voltage. 2. Currents are measured at 85°C junction temperature. 3. Software default selection highlighted in gray. –0.3 –0.3 –0.3 –0.3 VIL Max., V VIH Min., V VOL Max., V Max., V 1.9 1.9 1.9 1.9 0.45 0.45 0.45 0.45 VOH Min., V VCCI – 0.45 VCCI – 0.45 VCCI – 0.45 VCCI – 0.45 IOL IOH IOSH IOSL IIL IIH –0.3 –0.3 –0.3 –0.3 –0.3 –0.3 VIL Max., V VIH Min., V VOL Max., V Max., V 1.9 1.9 1.9 1.9 1.9 1.9 0.45 0.45 0.45 0.45 0.45 0.45 VOH Min., V VCCI – 0.45 VCCI – 0.45 VCCI – 0.45 VCCI – 0.45 IOL IOH IOSH IOSL IIL IIH
mA mA Max., mA1 Max., mA1 µA2 µA2 2 4 6 8 2 4 6 8 9 17 35 45 91 91 11 22 44 51 74 74 10 10 10 10 10 10 10 10 10 10 10 10
0.35 * VCCI 0.65 * VCCI 0.35 * VCCI 0.65 * VCCI 0.35 * VCCI 0.65 * VCCI 0.35 * VCCI 0.65 * VCCI 0.35 * VCCI 0.65 * VCCI 0.35 * VCCI 0.65 * VCCI
VCCI – 0.45 12 12 VCCI – 0.45 16 16
mA mA Max., mA1 Max., mA1 µA2 µA2 2 4 6 8 2 4 6 8 9 17 35 35 11 22 44 44 10 10 10 10 10 10 10 10
0.35 * VCCI 0.65 * VCCI 0.35 * VCCI 0.65 * VCCI 0.35 * VCCI 0.65 * VCCI 0.35 * VCCI 0.65 * VCCI
2 -4 8
A d v a n c e v 0. 5
IGLOO DC and Switching Characteristics Table 2-81 • Minimum and Maximum DC Input and Output Levels Applicable to Standard I/O Banks 1.8 V LVCMOS Drive Strength Min., V 2 mA 4 mA Notes: 1. Currents are measured at 100°C junction temperature and maximum voltage. 2. Currents are measured at 85°C junction temperature. 3. Software default selection highlighted in gray. –0.3 –0.3 VIL Max., V VIH Min., V VOL Max., V Max., V 1.9 1.9 0.45 0.45 VOH Min., V VCCI – 0.45 VCCI – 0.45 IOL IOH IOSH IOSL IIL IIH
mA mA Max., mA1 Max., mA1 µA2 µA2 2 4 2 4 9 17 11 22 10 10 10 10
0.35 * VCCI 0.65 * VCCI 0.35 * VCCI 0.65 * VCCI
Test Point Datapath 5 pF
R=1k Test Point Enable Path
R to VCCI for tLZ/tZL/tZLS R to GND for tHZ/tZH/tZHS 35 pF for tZH/tZHS/tZL/tZLS 5 pF for tHZ/tLZ
Figure 2-9 • AC Loading Table 2-82 • AC Waveforms, Measuring Points, and Capacitive Loads Input LOW (V) 0 Input HIGH (V) 1.8 Measuring Point* (V) 0.9 CLOAD (pF) 5
* Measuring point = Vtrip. See Table 2-28 on page 2-25 for a complete table of trip points.
A dv a n c e v 0. 5
2 - 49
IGLOO DC and Switching Characteristics
Timing Characteristics
1.5 V DC Core Voltage Table 2-83 • 1.8 V LVCMOS Low Slew – Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.7 V Applicable to Advanced I/O Banks Drive Strength 2 mA 4 mA 6 mA 8 mA 12 mA 16 mA Speed Grade tDOUT Std. Std. Std. Std. Std. Std. 0.97 0.97 0.97 0.97 0.97 0.97 tDP 6.38 5.35 4.62 4.37 4.31 4.31 tDIN tPY tEOUT 0.66 0.66 0.66 0.66 0.66 0.66 tZL 6.49 5.45 4.70 4.45 4.37 4.37 tZH 5.92 5.04 4.43 4.30 4.31 4.31 tLZ tHZ tZLS tZHS 9.45 8.57 7.96 7.83 7.84 7.84 Units ns ns ns ns ns ns
0.19 1.01 0.19 1.01 0.19 1.01 0.19 1.01 0.19 1.01 0.19 1.01
2.33 1.56 10.03 2.67 2.38 2.90 2.78 2.95 2.89 3.03 3.29 3.03 3.29 8.98 8.23 7.98 7.90 7.90
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. Table 2-84 • 1.8 V LVCMOS High Slew – Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.7 V Applicable to Advanced I/O Banks Drive Strength 2 mA 4 mA 6 mA 8 mA 12 mA 16 mA Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. Table 2-85 • 1.8 V LVCMOS Low Slew – Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.7 V Applicable to Standard Plus Banks Drive Strength 2 mA 4 mA 6 mA 8 mA Speed Grade tDOUT Std. Std. Std. Std. 0.97 0.97 0.97 0.97 tDP 5.78 4.75 4.07 4.07 tDIN tPY tEOUT 0.66 0.66 0.66 0.66 tZL 5.89 4.84 4.14 4.14 tZH 5.31 4.53 3.97 3.97 tLZ tHZ tZLS 9.42 8.37 7.67 7.67 tZHS 8.84 8.06 7.50 7.50 Units ns ns ns ns Speed Grade Std. Std. Std. Std. Std. Std. tDOUT 0.97 0.97 0.97 0.97 0.97 0.97 tDP tDIN tPY tEOUT 0.66 0.66 0.66 0.66 0.66 0.66 tZL tZH tLZ tHZ tZLS 6.73 6.20 5.88 5.82 5.81 5.81 tZHS 6.78 6.04 5.67 5.60 5.52 5.52 Units ns ns ns ns ns ns
3.24 0.19 1.01 2.62 0.19 1.01 2.31 0.19 1.01 2.25 0.19 1.01 2.24 0.19 1.01 2.24 0.19 1.01
3.20 3.24 2.33 1.61 2.67 2.50 2.66 2.46 2.35 2.14 2.89 2.87 2.29 2.07 2.95 2.98 2.28 1.99 3.02 3.39 2.28 1.99 3.02 3.39
0.19 1.01 0.19 1.01 0.19 1.01 0.19 1.01
1.95 1.46 2.25 2.21 2.46 2.57 2.46 2.57
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
2 -5 0
A d v a n c e v 0. 5
IGLOO DC and Switching Characteristics Table 2-86 • 1.8 V LVCMOS High Slew – Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.7 V Applicable to Standard Plus Banks Drive Strength 2 mA 4 mA 6 mA 8 mA Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. Table 2-87 • 1.8 V LVCMOS Low Slew – Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.7 V Applicable to Standard Banks Drive Strength 2 mA 4 mA Speed Grade Std. Std. tDOUT 0.97 0.97 tDP 5.63 4.69 tDIN 0.19 0.19 tPY 0.98 0.98 tEOUT 0.66 0.66 tZL 5.73 4.78 tZH 5.29 4.51 tLZ 1.68 1.97 tHZ 1.24 1.98 Units ns ns Speed Grade Std. Std. Std. Std. tDOUT 0.97 0.97 0.97 0.97 tDP tDIN tPY tEOUT 0.66 0.66 0.66 0.66 tZL tZH tLZ tHZ tZLS 6.32 5.82 5.54 5.54 tZHS 6.28 5.62 5.29 5.29 Units ns ns ns ns
2.75 0.19 1.01 2.25 0.19 1.01 1.97 0.19 1.01 1.97 0.19 1.01
2.79 2.75 1.94 1.51 2.29 2.09 2.24 2.29 2.01 1.76 2.46 2.66 2.01 1.76 2.46 2.66
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. Table 2-88 • 1.8 V LVCMOS High Slew – Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.7 V Applicable to Standard Banks Drive Strength 2 mA 4 mA Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. Speed Grade Std. Std. tDOUT 0.97 0.97 tDP 2.62 2.18 tDIN 0.19 0.19 tPY 0.98 0.98 tEOUT 0.66 0.66 tZL 2.67 2.22 tZH 2.59 1.93 tLZ 1.67 1.96 tHZ 1.29 2.06 Units ns ns
A dv a n c e v 0. 5
2 - 51
IGLOO DC and Switching Characteristics 1.2 V DC Core Voltage Table 2-89 • 1.8 V LCMOS Low Slew – Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.7 V Applicable to Advanced I/O Banks Drive Strength 2 mA 4 mA 6 mA 8 mA 12 mA 16 mA Speed Grade tDOUT Std. Std. Std. Std. Std. Std. 1.55 1.55 1.55 1.55 1.55 1.55 tDP 6.96 5.90 5.15 4.89 4.83 4.83 tDIN tPY tEOUT 1.10 1.10 1.10 1.10 1.10 1.10 tZL 7.09 6.01 5.24 4.98 4.90 4.90 tZH 6.49 5.57 4.95 4.81 4.83 4.83 tLZ tHZ tZLS tZHS Units ns ns ns ns ns ns
0.26 1.11 0.26 1.11 0.26 1.11 0.26 1.11 0.26 1.11 0.26 1.11
2.85 2.27 12.89 12.29 3.20 3.12 11.82 11.38 3.44 3.54 11.05 10.76 3.49 3.65 10.79 10.62 3.57 4.06 10.71 10.64 3.57 4.06 10.71 10.64
Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values. Table 2-90 • 1.8 V LCMOS High Slew – Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.7 V Applicable to Advanced I/O Banks Drive Strength 2 mA 4 mA 6 mA 8 mA 12 mA 16 mA Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values. Table 2-91 • 1.8 V LCMOS Low Slew – Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.7 V Applicable to Standard Plus Banks Drive Strength 2 mA 4 mA 6 mA 8 mA Speed Grade tDOUT Std. Std. Std. Std. 1.55 1.55 1.55 1.55 tDP 6.31 5.26 4.55 4.55 tDIN tPY tEOUT 1.10 1.10 1.10 1.10 tZL 6.43 5.35 4.64 4.64 tZH 5.81 5.01 4.44 4.44 tLZ tHZ tZLS tZHS Units ns ns ns ns Speed Grade Std. Std. Std. Std. Std. Std. tDOUT 1.55 1.55 1.55 1.55 1.55 1.55 tDP tDIN tPY tEOUT 1.10 1.10 1.10 1.10 1.10 1.10 tZL tZH tLZ tHZ tZLS 9.52 8.97 8.64 8.58 8.57 8.57 tZHS 9.54 8.78 8.40 8.33 8.24 8.24 Units ns ns ns ns ns ns
3.73 0.26 1.11 3.11 0.26 1.11 2.78 0.26 1.11 2.72 0.26 1.11 2.71 0.26 1.11 2.71 0.26 1.11
3.71 3.73 2.85 2.32 3.16 2.97 3.19 3.21 2.84 2.60 3.43 3.63 2.77 2.52 3.49 3.74 2.76 2.44 3.56 4.17 2.76 2.44 3.56 4.17
0.26 1.11 0.26 1.11 0.26 1.11 0.26 1.11
2.46 2.14 12.24 11.62 2.77 2.91 11.16 10.82 2.98 3.29 10.45 10.25 2.98 3.29 10.45 10.25
Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values.
2 -5 2
A d v a n c e v 0. 5
IGLOO DC and Switching Characteristics Table 2-92 • 1.8 V LCMOS High Slew – Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.7 V Applicable to Standard Plus Banks Drive Strength 2 mA 4 mA 6 mA 8 mA Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values. Table 2-93 • 1.8 V LCMOS Low Slew – Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.7 V Applicable to Standard Banks Drive Strength 2 mA 4 mA Speed Grade Std. Std. tDOUT 1.55 1.55 tDP 6.13 5.16 tDIN 0.26 0.26 tPY 1.08 1.08 tEOUT 1.10 1.10 tZL 6.24 5.26 tZH 5.79 4.99 tLZ 2.07 2.37 tHZ 1.77 2.53 Units ns ns Speed Grade Std. Std. Std. Std. tDOUT 1.55 1.55 1.55 1.55 tDP tDIN tPY tEOUT 1.10 1.10 1.10 1.10 tZL tZH tLZ tHZ tZLS 9.07 8.56 8.28 8.28 tZHS 8.99 8.31 7.97 7.97 Units ns ns ns ns
3.21 0.26 1.11 2.71 0.26 1.11 2.42 0.26 1.11 2.42 0.26 1.11
3.26 3.18 2.45 2.18 2.76 2.50 2.76 2.99 2.47 2.16 2.98 3.38 2.47 2.16 2.98 3.38
Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values. Table 2-94 • 1.8 V LCMOS High Slew – Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.7 V Applicable to Standard Banks Drive Strength 2 mA 4 mA Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values. Speed Grade Std. Std. tDOUT 1.55 1.55 tDP 3.05 2.60 tDIN 0.26 0.26 tPY 1.08 1.08 tEOUT 1.10 1.10 tZL 3.11 2.64 tZH 3.01 2.33 tLZ 2.07 2.37 tHZ 1.81 2.61 Units ns ns
A dv a n c e v 0. 5
2 - 53
IGLOO DC and Switching Characteristics
1.5 V LVCMOS (JESD8-11)
Low-Voltage CMOS for 1.5 V is an extension of the LVCMOS standard (JESD8-5) used for generalpurpose 1.5 V applications. It uses a 1.5 V input buffer and a push-pull output buffer. Table 2-95 • Minimum and Maximum DC Input and Output Levels Applicable to Advanced I/O Banks 1.5 V LVCMOS Drive Strength Min., V 2 mA 4 mA 6 mA 8 mA 12 mA Notes: 1. Currents are measured at 100°C junction temperature and maximum voltage. 2. Currents are measured at 85°C junction temperature. 3. Software default selection highlighted in gray. Table 2-96 • Minimum and Maximum DC Input and Output Levels Applicable to Standard Plus I/O Banks 1.5 V LVCMOS Drive Strength Min., V 2 mA 4 mA Notes: 1. Currents are measured at 100°C junction temperature and maximum voltage. 2. Currents are measured at 85°C junction temperature. 3. Software default selection highlighted in gray. Table 2-97 • Minimum and Maximum DC Input and Output Levels Applicable to Standard I/O Banks 1.5 V LVCMOS Drive Strength Min., V 2 mA Notes: 1. Currents are measured at 100°C junction temperature and maximum voltage. 2. Currents are measured at 85°C junction temperature. 3. Software default selection highlighted in gray. –0.3 VIL Max., V VIH Min., V Max., V VOL Max., V VOH Min., V IOL IOH IOSH IOSL IIL IIH –0.3 –0.3 VIL Max., V VIH Min., V Max., V VOL Max., V VOH Min., V IOL IOH IOSH IOSL IIL IIH –0.3 –0.3 –0.3 –0.3 –0.3 VIL Max., V VIH Min., V Max., V VOL Max., V VOH Min., V IOL IOH IOSH IOSL IIL IIH
m A mA Max., mA1 Max., mA1 µA2 µA2 2 4 6 8 13 25 32 66 66 16 33 39 55 55 10 10 10 10 10 10 10 10 10 10
0.35 * VCCI 0.65 * VCCI 1.575 0.25 * VCCI 0.75 * VCCI 2 0.35 * VCCI 0.65 * VCCI 1.575 0.35 * VCCI 0.65 * VCCI 1.575 0.35 * VCCI 0.65 * VCCI 1.575 0.35 * VCCI 0.65 * VCCI 1.575 0.25 * VCCI 0.75 * VCCI 4 0.25 * VCCI 0.75 * VCCI 6 0.25 * VCCI 0.75 * VCCI 8
0.25 * VCCI 0.75 * VCCI 12 12
mA mA Max., mA1 Max., mA1 µA2 µA2 2 4 13 25 16 33 10 10 10 10
0.35 * VCCI 0.65 * VCCI 1.575 0.35 * VCCI 0.65 * VCCI 1.575
0.25 * VCCI 0.75 * VCCI 2 0.25 * VCCI 0.75 * VCCI 4
mA mA Max., mA1 Max., mA1 µA2 µA2 2 13 16 10 10
0.35 * VCCI 0.65 * VCCI 1.575
0.25 * VCCI 0.75 * VCCI 2
2 -5 4
A d v a n c e v 0. 5
IGLOO DC and Switching Characteristics
Test Point Datapath 5 pF
R=1k Test Point Enable Path
R to VCCI for tLZ/tZL/tZLS R to GND for tHZ/tZH/tZHS 35 pF for tZH/tZHS/tZL/tZLS 5 pF for tHZ/tLZ
Figure 2-10 • AC Loading Table 2-98 • AC Waveforms, Measuring Points, and Capacitive Loads Input LOW (V) 0 Input HIGH (V) 1.5 Measuring Point* (V) 0.75 CLOAD (pF) 5
* Measuring point = Vtrip. See Table 2-28 on page 2-25 for a complete table of trip points.
Timing Characteristics
1.5 V DC Core Voltage Table 2-99 • 1.5 V LVCMOS Low Slew – Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.4 V Applicable to Advanced I/O Banks Drive Strength 2 mA 4 mA 6 mA 8 mA 12 mA Speed Grade tDOUT Std. Std. Std. Std. Std. 0.97 0.97 0.97 0.97 0.97 tDP 6.62 5.74 5.43 5.35 5.35 tDIN tPY tEOUT 0.66 0.66 0.66 0.66 0.66 tZL 6.74 5.85 5.53 5.45 5.45 tZH 6.05 5.33 5.18 5.19 5.19 tLZ tHZ tZLS tZHS 9.58 8.86 8.71 8.72 8.72 Units ns ns ns ns ns
0.19 1.17 0.19 1.17 0.19 1.17 0.19 1.17 0.19 1.17
2.79 2.31 10.28 3.06 2.78 3.12 2.90 3.21 3.36 3.21 3.36 9.38 9.06 8.98 8.98
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. Table 2-100 • 1.5 V LVCMOS High Slew – Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.4 V Applicable to Advanced I/O Banks Drive Strength 2 mA 4 mA 6 mA 8 mA 12 mA Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. Speed Grade Std. Std. Std. Std. Std. tDOUT 0.97 0.97 0.97 0.97 0.97 tDP tDIN tPY tEOUT 0.66 0.66 0.66 0.66 0.66 tZL tZH tLZ tHZ tZLS tZHS 6.43 5.97 7.16 5.79 5.79 Units ns ns ns ns ns
2.97 0.19 1.17 2.60 0.19 1.17 3.63 0.19 1.17 2.50 0.19 1.17 2.50 0.19 1.17
3.03 2.89 2.78 2.40 6.56 2.64 2.44 3.05 2.88 6.18 3.62 3.63 3.06 3.00 7.15 2.55 2.26 3.20 3.48 6.08 2.55 2.26 3.20 3.48 6.08
A dv a n c e v 0. 5
2 - 55
IGLOO DC and Switching Characteristics Table 2-101 • 1.5 V LVCMOS Low Slew – Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.4 V Applicable to Standard Plus Banks Drive Strength 2 mA 4 mA Speed Grade Std. Std. tDOUT 0.97 0.97 tDP tDIN tPY tEOUT 0.66 0.66 tZL tZH tLZ tHZ tZLS 9.57 8.73 tZHS 8.99 8.32 Units ns ns
5.93 0.19 1.17 5.11 0.19 1.17
6.04 5.46 2.30 2.15 5.20 4.79 2.54 2.58
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. Table 2-102 • 1.5 V LVCMOS High Slew – Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.4 V Applicable to Standard Plus Banks Drive Strength 2 mA 4 mA Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. Table 2-103 • 1.5 V LVCMOS Low Slew – Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.4 V Applicable to Standard Banks Drive Strength 2 mA Speed Grade Std. tDOUT 0.97 tDP 5.88 tDIN 0.19 tPY 1.13 tEOUT 0.66 tZL 5.99 tZH 5.45 tLZ 1.99 tHZ 1.93 Units ns Speed Grade Std. Std. tDOUT 0.97 0.97 tDP tDIN tPY tEOUT 0.66 0.66 tZL tZH tLZ tHZ tZLS tZHS Units ns ns
2.58 0.19 1.17 2.25 0.19 1.17
2.63 2.40 2.29 2.24 6.16 5.94 2.29 1.99 2.53 2.68 5.82 5.52
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. Table 2-104 • 1.5 V LVCMOS High Slew – Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.4 V Applicable to Standard Banks Drive Strength 2 mA Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. 1.2 V DC Core Voltage Speed Grade Std. tDOUT 0.97 tDP 2.51 tDIN 0.19 tPY 1.13 tEOUT 0.66 tZL 2.56 tZH 2.20 tLZ 1.99 tHZ 2.03 Units ns
2 -5 6
A d v a n c e v 0. 5
IGLOO DC and Switching Characteristics Table 2-105 • 1.5 V LCMOS Low Slew – Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.4 V Applicable to Advanced I/O Banks Drive Strength 2 mA 4 mA 6 mA 8 mA 12 mA Speed Grade tDOUT Std. Std. Std. Std. Std. 1.55 1.55 1.55 1.55 1.55 tDP 7.16 6.26 5.93 5.85 5.85 tDIN tPY tEOUT 1.10 1.10 1.10 1.10 1.10 tZL 7.29 6.37 6.04 5.96 5.96 tZH 6.60 5.86 5.70 5.72 5.72 tLZ tHZ tZLS tZHS Units ns ns ns ns ns
0.26 1.27 0.26 1.27 0.26 1.27 0.26 1.27 0.26 1.27
3.32 3.01 13.10 12.41 3.59 3.49 12.18 11.67 3.65 3.62 11.85 11.51 3.75 4.10 11.77 11.52 3.75 4.10 11.77 11.52
Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values. Table 2-106 • 1.5 V LCMOS High Slew – Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.4 V Applicable to Advanced I/O Banks Drive Strength 2 mA 4 mA 6 mA 8 mA 12 mA Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values. Table 2-107 • 1.5 V LCMOS Low Slew – Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.4 V Applicable to Standard Plus Banks Drive Strength 2 mA 4 mA Speed Grade Std. Std. tDOUT 1.55 1.55 tDP tDIN tPY tEOUT 1.10 1.10 tZL tZH tLZ tHZ tZLS tZHS Units ns ns Speed Grade Std. Std. Std. Std. Std. tDOUT 1.55 1.55 1.55 1.55 1.55 tDP tDIN tPY tEOUT 1.10 1.10 1.10 1.10 1.10 tZL tZH tLZ tHZ tZLS 9.30 8.91 9.91 8.81 8.81 tZHS 9.16 8.70 9.92 8.51 8.51 Units ns ns ns ns ns
3.43 0.26 1.27 3.04 0.26 1.27 4.11 0.26 1.27 2.95 0.26 1.27 2.95 0.26 1.27
3.49 3.36 3.31 3.10 3.10 2.89 3.58 3.59 4.10 4.11 3.59 3.72 3.00 2.70 3.74 4.21 3.00 2.70 3.74 4.21
6.42 0.26 1.27 5.58 0.26 1.27
6.54 5.95 2.81 2.81 12.35 11.76 5.68 5.27 3.06 3.25 11.49 11.08
Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values. Table 2-108 • 1.5 V LCMOS High Slew – Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.4 V Applicable to Standard Plus Banks Drive Strength 2 mA 4 mA Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values. Speed Grade Std. Std. tDOUT 1.55 1.55 tDP tDIN tPY tEOUT 1.10 1.10 tZL tZH tLZ tHZ tZLS 8.88 8.53 tZHS 8.62 8.20 Units ns ns
3.01 0.26 1.27 2.67 0.26 1.27
3.07 2.81 2.80 2.90 2.72 2.39 3.05 3.36
A dv a n c e v 0. 5
2 - 57
IGLOO DC and Switching Characteristics Table 2-109 • 1.5 V LCMOS Low Slew – Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.4 V Applicable to Standard Banks Drive Strength 2 mA Speed Grade Std. tDOUT 1.55 tDP 6.35 tDIN 0.26 tPY 1.22 tEOUT 1.10 tZL 6.46 tZH 5.93 tLZ 2.39 tHZ 2.45 Units ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values. Table 2-110 • 1.5 V LCMOS High Slew – Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.4 V Applicable to Standard Banks Drive Strength 2 mA Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values. Speed Grade Std. tDOUT 1.55 tDP 2.91 tDIN 0.26 tPY 1.22 tEOUT 1.10 tZL 2.96 tZH 2.60 tLZ 2.39 tHZ 2.54 Units ns
2 -5 8
A d v a n c e v 0. 5
IGLOO DC and Switching Characteristics
1.2 V LVCMOS (JESD8-12A)
Low-Voltage CMOS for 1.2 V complies with the LVCMOS standard JESD8-12A for general purpose 1.2 V applications. It uses a 1.2 V input buffer and a push-pull output buffer. Table 2-111 • Minimum and Maximum DC Input and Output Levels Applicable to Advanced I/O Banks 1.2 V LVCMOS Drive Strength Min., V 2 mA Notes: 1. Currents are measured at 100°C junction temperature and maximum voltage. 2. Currents are measured at 85°C junction temperature. 3. Software default selection highlighted in gray. Table 2-112 • Minimum and Maximum DC Input and Output Levels Applicable to Standard Plus I/O Banks 1.2 V LVCMOS Drive Strength Min., V 2 mA Notes: 1. Currents are measured at 100°C junction temperature and maximum voltage. 2. Currents are measured at 85°C junction temperature. 3. Software default selection highlighted in gray. Table 2-113 • Minimum and Maximum DC Input and Output Levels Applicable to Standard I/O Banks 1.2 V LVCMOS Drive Strength Min., V 1 mA Notes: 1. Currents are measured at 100°C junction temperature and maximum voltage. 2. Currents are measured at 85°C junction temperature. 3. Software default selection highlighted in gray. –0.3 VIL Max., V VIH Min., V Max., V 1.26 VOL Max., V VOH Min., V IOL IOH IOSH1 IOSL1 IIL2 IIH2 –0.3 VIL Max., V VIH Min., V Max., V 1.26 VOL Max., V VOH Min., V IOL IOH IOSH1 IOSL1 IIL2 IIH2 –0.3 VIL Max., V VIH Min., V Max., V 1.26 VOL Max., V VOH Min., V IOL IOH IOSH1 IOSL1 IIL2 IIH2
mA mA Max., mA Max., mA µA µA 2 TBD TBD 10 10
0.35 * VCCI 0.65 * VCCI
0.25 * VCCI 0.75 * VCCI 2
mA mA Max., mA Max., mA µA µA 2 TBD TBD 10 10
0.35 * VCCI 0.65 * VCCI
0.25 * VCCI 0.75 * VCCI 2
mA mA Max., mA Max., mA µA µA 1 TBD TBD 10 10
0.35 * VCCI 0.65 * VCCI
0.25 * VCCI 0.75 * VCCI 1
Test Point Datapath 5 pF
R=1k Test Point Enable Path
R to VCCI for tLZ/tZL/tZLS R to GND for tHZ/tZH/tZHS 35 pF for tZH/tZHS/tZL/tZLS 5 pF for tHZ/tLZ
Figure 2-11 • AC Loading
A dv a n c e v 0. 5
2 - 59
IGLOO DC and Switching Characteristics Table 2-114 • AC Waveforms, Measuring Points, and Capacitive Loads Input LOW (V) 0 Input HIGH (V) 1.2 Measuring Point* (V) 0.6 CLOAD (pF) 5
* Measuring point = Vtrip. See Table 2-28 on page 2-25 for a complete table of trip points.
Timing Characteristics
1.2 V DC Core Voltage Table 2-115 • 1.2 V LVCMOS Low Slew Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.4 V Applicable to Advanced I/O Banks Drive Strength 2 mA Speed Grade tDOUT Std. 0.97 tDP 6.62 tDIN tPY tEOUT 0.66 tZL 6.74 tZH 6.05 tLZ tHZ tZLS tZHS 9.58 Units ns 0.19 1.17 2.79 2.31 10.28
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. Table 2-116 • 1.2 V LVCMOS High Slew Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.14 V Applicable to Advanced I/O Banks tZH tLZ tHZ Drive Strength Speed Grade tDOUT tDP tDIN tPY tEOUT tZL 2 mA Std. 1.55 3.61 0.26 1.58 1.10 3.45 3.33 3.94 3.66 Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. Table 2-117 • 1.2 V LVCMOS High Slew Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.14 V Applicable to Standard Plus I/O Banks Drive Strength 2 mA Speed Grade tDOUT Std. 1.55 tDP 7.60 tDIN tPY tEOUT 1.10 tZL 7.27 tZH 6.52 tLZ tHZ tZLS tZHS Units ns 0.26 1.58 3.31 3.36 12.86 12.12 tZLS 9.05 tZHS 8.93 Units ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. Table 2-118 • 1.2 V LVCMOS High Slew Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.14 V Applicable to Standard Plus I/O Banks Drive Strength 2 mA Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. Table 2-119 • 1.2 V LVCMOS High Slew Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.14 V Applicable to Standard Banks Drive Strength 1 mA Speed Grade Std. tDOUT 1.55 tDP 8.58 tDIN 0.26 tPY 1.52 tEOUT 1.10 tZL 8.21 tZH 7.36 tLZ 2.52 tHZ 2.40 Units ns Speed Grade Std. tDOUT 1.55 tDP tDIN tPY tEOUT 1.10 tZL tZH tLZ tHZ tZLS tZHS 8.36 Units ns 3.23 0.26 1.58 3.09 2.76 3.30 3.49 8.69
Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values.
2 -6 0
A d v a n c e v 0. 5
IGLOO DC and Switching Characteristics Table 2-120 • 1.2 V LCMOS High Slew – Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.14 V Applicable to Standard Banks Drive Strength 1 mA Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values. Speed Grade Std. tDOUT 1.55 tDP 3.60 tDIN 0.26 tPY 1.52 tEOUT 1.10 tZL 3.45 tZH 3.04 tLZ 2.52 tHZ 2.50 Units ns
A dv a n c e v 0. 5
2 - 61
IGLOO DC and Switching Characteristics
3.3 V PCI, 3.3 V PCI-X
Peripheral Component Interface for 3.3 V standard specifies support for 33 MHz and 66 MHz PCI Bus applications. Table 2-121 • Minimum and Maximum DC Input and Output Levels Applicable to Advanced and Standard Plus I/Os 3.3 V PCI/PCI-X Per PCI specification Notes: 1. Currents are measured at 100°C junction temperature and maximum voltage. 2. Currents are measured at 85°C junction temperature. AC loadings are defined per the PCI/PCI-X specifications for the datapath; Actel loadings for enable path characterization are described in Figure 2-12. VIL VIH VOL VOH IOL IOH IOSH
1
IOSL Max, mA
1
IIL µA
2
IIH µA2 10
Drive Strength Min, V Max, V Min, V Max, V Max, V Min, V mA mA Max, mA Per PCI curves
10
R = 25 Test Point Datapath
R to VCCI for tDP (F) R to GND for tDP (R)
R=1k Test Point Enable Path
R to VCCI for tLZ/tZL/t ZLS R to GND for tHZ /tZH /t ZHS 10 pF for tZH /tZHS /tZL /t ZLS 5 pF for tHZ /tLZ
Figure 2-12 • AC Loading AC loadings are defined per PCI/PCI-X specifications for the datapath; Actel loading for tristate is described in Table 2-122. Table 2-122 • AC Waveforms, Measuring Points, and Capacitive Loads Input LOW (V) 0 Input HIGH (V) 3.3 Measuring Point* (V) 0.285 * VCCI for tDP(R) 0.615 * VCCI for tDP(F) * Measuring point = Vtrip. See Table 2-28 on page 2-25 for a complete table of trip points. CLOAD (pF) 10
2 -6 2
A d v a n c e v 0. 5
IGLOO DC and Switching Characteristics
Timing Characteristics
1.5 V DC Core Voltage Table 2-123 • 3.3 V PCI/PCI-X Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V Applicable to Advanced I/O Banks Speed Grade Std. tDOUT 0.97 tDP 2.32 tDIN 0.19 tPY 0.70 tEOUT 0.66 tZL 2.36 tZH 1.77 tLZ 2.67 tHZ 3.04 tZLS 5.89 tZHS 5.30 Units ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. Table 2-124 • 3.3 V PCI/PCI-X Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V Applicable to Standard Plus I/O Banks Speed Grade Std. tDOUT 0.97 tDP 1.96 tDIN 0.19 tPY 0.70 tEOUT 0.66 tZL 2.00 tZH 1.50 tLZ 2.36 tHZ 2.79 tZLS 5.53 tZHS 5.03 Units ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. 1.2 V DC Core Voltage Table 2-125 • 3.3 V PCI/PCI-X Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 3.0 V Applicable to Advanced I/O Banks Speed Grade Std. tDOUT 1.55 tDP 2.90 tDIN 0.25 tPY 0.86 tEOUT 1.10 tZL 2.95 tZH 2.29 tLZ 3.23 tHZ 3.92 tZLS 8.76 tZHS 8.10 Units ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values. Table 2-126 • 3.3 V PCI/PCI-X Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 3.0 V Applicable to Standard Plus I/O Banks Speed Grade Std. tDOUT 1.55 tDP 2.52 tDIN 0.25 tPY 0.85 tEOUT 1.10 tZL 2.57 tZH 1.98 tLZ 2.91 tHZ 3.62 tZLS 8.37 tZHS 7.78 Units ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values.
A dv a n c e v 0. 5
2 - 63
IGLOO DC and Switching Characteristics
Differential I/O Characteristics
Physical Implementation
Configuration of the I/O modules as a differential pair is handled by Actel Designer software when the user instantiates a differential I/O macro in the design. Differential I/Os can also be used in conjunction with the embedded Input Register (InReg), Output Register (OutReg), Enable Register (EnReg), and Double Data Rate (DDR). However, there is no support for bidirectional I/Os or tristates with the LVPECL standards.
LVDS
Low-Voltage Differential Signaling (ANSI/TIA/EIA-644) is a high-speed, differential I/O standard. It requires that one data bit be carried through two signal lines, so two pins are needed. It also requires external resistor termination. The full implementation of the LVDS transmitter and receiver is shown in an example in Figure 2-13. The building blocks of the LVDS transmitter-receiver are one transmitter macro, one receiver macro, three board resistors at the transmitter end, and one resistor at the receiver end. The values for the three driver resistors are different from those used in the LVPECL implementation because the output standard specifications are different. Along with LVDS I/O, IGLOO also supports Bus LVDS structure and Multipoint LVDS (M-LVDS) configuration (up to 40 nodes).
Bourns Part Number: CAT16-LV4F12 OUTBUF_LVDS FPGA P 165 Ω Z0 = 50 Ω 140 Ω N 165 Ω Z0 = 50 Ω 100 Ω N P FPGA + – INBUF_LVDS
Figure 2-13 • LVDS Circuit Diagram and Board-Level Implementation
2 -6 4
A d v a n c e v 0. 5
IGLOO DC and Switching Characteristics Table 2-127 • Minimum and Maximum DC Input and Output Levels DC Parameter VCCI VOL VOH IOL IOH VI IIH IIL
3 3 4 4
Description Supply Voltage Output LOW Voltage Output HIGH Voltage Output Lower Current Output HIGH Current Input Voltage Input HIGH Leakage Current Input LOW Leakage Current Differential Output Voltage Output Common-Mode Voltage Input Common-Mode Voltage Input Differential Voltage
Min. 2.375 0.9 1.25 0.65 0.65 0
Typ. 2.5 1.075 1.425 0.91 0.91
Max. 2.625 1.25 1.6 1.16 1.16 2.925 10 10
Units V V V mA mA V µA µA mV V V mV
VODIFF VOCM VICM VIDIFF Notes: 1. ± 5%
250 1.125 0.05 100
350 1.25 1.25 350
450 1.375 2.35
2. Differential input voltage = ±350 mV. 3. Currents are measured at 85°C junction temperature. 4. IOL /IOH is defined by VODIFF /(resistor network). Table 2-128 • AC Waveforms, Measuring Points, and Capacitive Loads Input LOW (V) 1.075 Input HIGH (V) 1.325 Measuring Point* (V) Cross point
* Measuring point = Vtrip. See Table 2-28 on page 2-25 for a complete table of trip points.
Timing Characteristics
1.5 V DC Core Voltage Table 2-129 • LVDS – Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V Applicable to Standard Banks Speed Grade Std. tDOUT 0.97 tDP 1.67 tDIN 0.19 tPY 1.31 Units ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 and Table 2-7 on page 2-7 for derating values. 1.2 V DC Core Voltage Table 2-130 • LVDS – Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 2.3 V Applicable to Standard Banks Speed Grade Std. tDOUT 1.55 tDP 2.19 tDIN 0.25 tPY 1.52 Units ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 and Table 2-7 on page 2-7 for derating values.
A dv a n c e v 0. 5
2 - 65
IGLOO DC and Switching Characteristics
B-LVDS/M-LVDS
Bus LVDS (B-LVDS) and Multipoint LVDS (M-LVDS) specifications extend the existing LVDS standard to high-performance multipoint bus applications. Multidrop and multipoint bus configurations may contain any combination of drivers, receivers, and transceivers. Actel LVDS drivers provide the higher drive current required by B-LVDS and M-LVDS to accommodate the loading. The drivers require series terminations for better signal quality and to control voltage swing. Termination is also required at both ends of the bus since the driver can be located anywhere on the bus. These configurations can be implemented using the TRIBUF_LVDS and BIBUF_LVDS macros along with appropriate terminations. Multipoint designs using Actel LVDS macros can achieve up to 200 MHz with a maximum of 20 loads. A sample application is given in Figure 2-14. The input and output buffer delays are available in the LVDS section in Table 2-129 on page 2-65 and Table 2-130 on page 2-65. Example: For a bus consisting of 20 equidistant loads, the following terminations provide the required differential voltage, in worst-case Industrial operating conditions, at the farthest receiver: RS = 60 Ω and RT = 70 Ω, given Z0 = 50 Ω (2") and Zstub = 50 Ω (~1.5").
Receiver
EN
Transceiver
EN
Driver
Receiver
EN EN
Transceiver
EN
D
+
R
+
-
T
+
-
-
R
+
-
T
+
BIBUF_LVDS
-
RS Zstub Z0 RT Z 0
RS Zstub Zstub Z0 Z0
RS
RS Zstub Zstub Z0 Z0
RS
RS Zstub Zstub Z0 Z0
RS
RS Zstub ... Z0 Z0
RS
RS Z0 Z0 RT
Figure 2-14 • B-LVDS/M-LVDS Multipoint Application Using LVDS I/O Buffers
LVPECL
Low-Voltage Positive Emitter-Coupled Logic (LVPECL) is another differential I/O standard. It requires that one data bit be carried through two signal lines. Like LVDS, two pins are needed. It also requires external resistor termination. The full implementation of the LVDS transmitter and receiver is shown in an example in Figure 2-15. The building blocks of the LVPECL transmitter-receiver are one transmitter macro, one receiver macro, three board resistors at the transmitter end, and one resistor at the receiver end. The values for the three driver resistors are different from those used in the LVDS implementation because the output standard specifications are different.
Bourns Part Number: CAT16-PC4F12 OUTBUF_LVPECL FPGA P 100 Ω Z0 = 50 Ω 187 W N 100 Ω Z0 = 50 Ω 100 Ω N P FPGA
+ –
INBUF_LVPECL
Figure 2-15 • LVPECL Circuit Diagram and Board-Level Implementation
2 -6 6
A d v a n c e v 0. 5
IGLOO DC and Switching Characteristics Table 2-131 • Minimum and Maximum DC Input and Output Levels DC Parameter VCCI VOL VOH VIL, VIH VODIFF VOCM VICM VIDIFF Description Supply Voltage Output LOW Voltage Output HIGH Voltage Input LOW, Input HIGH Voltages Differential Output Voltage Output Common-Mode Voltage Input Common-Mode Voltage Input Differential Voltage 0.96 1.8 0 0.625 1.762 1.01 300 Min. Max. 3.0 1.27 2.11 3.3 0.97 1.98 2.57 1.06 1.92 0 0.625 1.762 1.01 300 Min. Max. 3.3 1.43 2.28 3.6 0.97 1.98 2.57 1.30 2.13 0 0.625 1.762 1.01 300 Min. Max. 3.6 1.57 2.41 3.9 0.97 1.98 2.57 Units V V V V V V V mV
Table 2-132 • AC Waveforms, Measuring Points, and Capacitive Loads Input LOW (V) 1.64 Input HIGH (V) 1.94 Measuring Point* (V) Cross point
* Measuring point = Vtrip. See Table 2-28 on page 2-87 for a complete table of trip points.
Timing Characteristics
1.5 V DC Core Voltage Table 2-133 • LVPECL – Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V Applicable to Standard Banks Speed Grade Std. tDOUT 0.97 tDP 1.67 tDIN 0.19 tPY 1.16 Units ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. 1.2 V DC Core Voltage Table 2-134 • LVPECL – Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 3.0 V Applicable to Standard Banks Speed Grade Std. tDOUT 1.55 tDP 2.24 tDIN 0.25 tPY 1.37 Units ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values.
A dv a n c e v 0. 5
2 - 67
IGLOO DC and Switching Characteristics
I/O Register Specifications
Fully Registered I/O Buffers with Synchronous Enable and Asynchronous Preset
INBUF
Preset
L Pad Out D DOUT Data_out
TRIBUF
Data
PRE D Q C DFN1E1P1 E B
E
Y Core Array
F G
PRE D Q DFN1E1P1 E
INBUF INBUF
Enable
EOUT H I
CLKBUF
CLK
A J K Data Input I/O Register with: Active High Enable Active High Preset Positive-Edge Triggered PRE D Q DFN1E1P1 E
CLKBUF
INBUF
INBUF
Data Output Register and Enable Output Register with: Active High Enable Active High Preset Postive-Edge Triggered
CLK
Figure 2-16 • Timing Model of Registered I/O Buffers with Synchronous Enable and Asynchronous Preset
2 -6 8
A d v a n c e v 0. 5
D_Enable
Enable
IGLOO DC and Switching Characteristics Table 2-135 • Parameter Definition and Measuring Nodes Parameter Name tOCLKQ tOSUD tOHD tOSUE tOHE tOPRE2Q tOREMPRE tORECPRE tOECLKQ tOESUD tOEHD tOESUE tOEHE tOEPRE2Q tOEREMPRE tOERECPRE tICLKQ tISUD tIHD tISUE tIHE tIPRE2Q tIREMPRE tIRECPRE Parameter Definition Clock-to-Q of the Output Data Register Data Setup Time for the Output Data Register Data Hold Time for the Output Data Register Enable Setup Time for the Output Data Register Enable Hold Time for the Output Data Register Asynchronous Preset-to-Q of the Output Data Register Asynchronous Preset Removal Time for the Output Data Register Asynchronous Preset Recovery Time for the Output Data Register Clock-to-Q of the Output Enable Register Data Setup Time for the Output Enable Register Data Hold Time for the Output Enable Register Enable Setup Time for the Output Enable Register Enable Hold Time for the Output Enable Register Asynchronous Preset-to-Q of the Output Enable Register Asynchronous Preset Removal Time for the Output Enable Register Asynchronous Preset Recovery Time for the Output Enable Register Clock-to-Q of the Input Data Register Data Setup Time for the Input Data Register Data Hold Time for the Input Data Register Enable Setup Time for the Input Data Register Enable Hold Time for the Input Data Register Asynchronous Preset-to-Q of the Input Data Register Asynchronous Preset Removal Time for the Input Data Register Asynchronous Preset Recovery Time for the Input Data Register Measuring Nodes (from, to)* H, DOUT F, H F, H G, H G, H L, DOUT L, H L, H H, EOUT J, H J, H K, H K, H I, EOUT I, H I, H A, E C, A C, A B, A B, A D, E D, A D, A
* See Figure 2-16 on page 2-68 for more information.
A dv a n c e v 0. 5
2 - 69
IGLOO DC and Switching Characteristics
Fully Registered I/O Buffers with Synchronous Enable and Asynchronous Clear
Pad Out
DOUT Y D CC Q EE DFN1E1C1 E BB CLR LL
CLKBUF
Data
Core Array
Data_out FF
TRIBUF
INBUF INBUF
D
Q
DFN1E1C1 GG E CLR
EOUT
Enable
CLK
HH AA JJ DD KK Data Input I/O Register with Active High Enable Active High Clear Positive-Edge Triggered
INBUF
CLR
D
Q
DFN1E1C1 E CLR
INBUF
INBUF
CLKBUF
Data Output Register and Enable Output Register with Active High Enable Active High Clear Positive-Edge Triggered
Enable
Figure 2-17 • Timing Model of the Registered I/O Buffers with Synchronous Enable and Asynchronous Clear
2 -7 0
A d v a n c e v 0. 5
D_Enable
CLK
IGLOO DC and Switching Characteristics Table 2-136 • Parameter Definition and Measuring Nodes Parameter Name tOCLKQ tOSUD tOHD tOSUE tOHE tOCLR2Q tOREMCLR tORECCLR tOECLKQ tOESUD tOEHD tOESUE tOEHE tOECLR2Q tOEREMCLR tOERECCLR tICLKQ tISUD tIHD tISUE tIHE tICLR2Q tIREMCLR tIRECCLR Parameter Definition Clock-to-Q of the Output Data Register Data Setup Time for the Output Data Register Data Hold Time for the Output Data Register Enable Setup Time for the Output Data Register Enable Hold Time for the Output Data Register Asynchronous Clear-to-Q of the Output Data Register Asynchronous Clear Removal Time for the Output Data Register Asynchronous Clear Recovery Time for the Output Data Register Clock-to-Q of the Output Enable Register Data Setup Time for the Output Enable Register Data Hold Time for the Output Enable Register Enable Setup Time for the Output Enable Register Enable Hold Time for the Output Enable Register Asynchronous Clear-to-Q of the Output Enable Register Asynchronous Clear Removal Time for the Output Enable Register Asynchronous Clear Recovery Time for the Output Enable Register Clock-to-Q of the Input Data Register Data Setup Time for the Input Data Register Data Hold Time for the Input Data Register Enable Setup Time for the Input Data Register Enable Hold Time for the Input Data Register Asynchronous Clear-to-Q of the Input Data Register Asynchronous Clear Removal Time for the Input Data Register Asynchronous Clear Recovery Time for the Input Data Register Measuring Nodes (from, to)* HH, DOUT FF, HH FF, HH GG, HH GG, HH LL, DOUT LL, HH LL, HH HH, EOUT JJ, HH JJ, HH KK, HH KK, HH II, EOUT II, HH II, HH AA, EE CC, AA CC, AA BB, AA BB, AA DD, EE DD, AA DD, AA
* See Figure 2-17 on page 2-70 for more information.
A dv a n c e v 0. 5
2 - 71
IGLOO DC and Switching Characteristics
Input Register
tICKMPWH tICKMPWL 50% 50% tISUD Data 1 50% 0 tIHD 50% 50% 50% 50% 50% 50%
CLK
Enable
50% tIHE 50%
tIWPRE tISUE
tIRECPRE 50% tIWCLR tIRECCLR 50%
tIREMPRE 50% tIREMCLR 50%
Preset
Clear tIPRE2Q Out_1 50% tICLKQ 50%
50%
tICLR2Q
50%
Figure 2-18 • Input Register Timing Diagram
Timing Characteristics
1.5 V DC Core Voltage Table 2-137 • Input Data Register Propagation Delays Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V Parameter tICLKQ tISUD tIHD tISUE tIHE tICLR2Q tIPRE2Q tIREMCLR tIRECCLR tIREMPRE tIRECPRE tIWCLR tIWPRE tICKMPWH tICKMPWL Description Clock-to-Q of the Input Data Register Data Setup Time for the Input Data Register Data Hold Time for the Input Data Register Enable Setup Time for the Input Data Register Enable Hold Time for the Input Data Register Asynchronous Clear-to-Q of the Input Data Register Asynchronous Preset-to-Q of the Input Data Register Asynchronous Clear Removal Time for the Input Data Register Asynchronous Clear Recovery Time for the Input Data Register Asynchronous Preset Removal Time for the Input Data Register Asynchronous Preset Recovery Time for the Input Data Register Asynchronous Clear Minimum Pulse Width for the Input Data Register Asynchronous Preset Minimum Pulse Width for the Input Data Register Clock Minimum Pulse Width HIGH for the Input Data Register Clock Minimum Pulse Width LOW for the Input Data Register Std. 0.42 0.47 0.00 0.67 0.00 0.79 0.79 0.00 0.24 0.00 0.24 0.19 0.19 0.31 0.28 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
2 -7 2
A d v a n c e v 0. 5
IGLOO DC and Switching Characteristics 1.2 V DC Core Voltage Table 2-138 • Input Data Register Propagation Delays Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V Parameter tICLKQ tISUD tIHD tISUE tIHE tICLR2Q tIPRE2Q tIREMCLR tIRECCLR tIREMPRE tIRECPRE tIWCLR tIWPRE tICKMPWH tICKMPWL Description Clock-to-Q of the Input Data Register Data Setup Time for the Input Data Register Data Hold Time for the Input Data Register Enable Setup Time for the Input Data Register Enable Hold Time for the Input Data Register Asynchronous Clear-to-Q of the Input Data Register Asynchronous Preset-to-Q of the Input Data Register Asynchronous Clear Removal Time for the Input Data Register Asynchronous Clear Recovery Time for the Input Data Register Asynchronous Preset Removal Time for the Input Data Register Asynchronous Preset Recovery Time for the Input Data Register Asynchronous Clear Minimum Pulse Width for the Input Data Register Asynchronous Preset Minimum Pulse Width for the Input Data Register Clock Minimum Pulse Width HIGH for the Input Data Register Clock Minimum Pulse Width LOW for the Input Data Register Std. 0.68 0.97 0.00 1.02 0.00 1.19 1.19 0.00 0.24 0.00 0.24 0.19 0.19 0.31 0.28 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values.
Output Register
tOCKMPWH tOCKMPWL 50% 50% tOSUD tOHD Data_out 1 50% 0 50% 50% 50% 50% 50% 50%
CLK
Enable
50% tOHE 50%
tOWPRE
tORECPRE 50% tORECCLR
tOREMPRE 50% tOREMCLR 50%
Preset
tOSUE
tOWCLR Clear tOPRE2Q DOUT 50% tOCLKQ 50% tOCLR2Q 50% 50%
50%
Figure 2-19 • Output Register Timing Diagram
A dv a n c e v 0. 5
2 - 73
IGLOO DC and Switching Characteristics
Timing Characteristics
1.5 V DC Core Voltage Table 2-139 • Output Data Register Propagation Delays Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V Parameter tOCLKQ tOSUD tOHD tOSUE tOHE tOCLR2Q tOPRE2Q tOREMCLR tORECCLR tOREMPRE tORECPRE tOWCLR tOWPRE tOCKMPWH tOCKMPWL Description Clock-to-Q of the Output Data Register Data Setup Time for the Output Data Register Data Hold Time for the Output Data Register Enable Setup Time for the Output Data Register Enable Hold Time for the Output Data Register Asynchronous Clear-to-Q of the Output Data Register Asynchronous Preset-to-Q of the Output Data Register Asynchronous Clear Removal Time for the Output Data Register Asynchronous Clear Recovery Time for the Output Data Register Asynchronous Preset Removal Time for the Output Data Register Asynchronous Preset Recovery Time for the Output Data Register Asynchronous Clear Minimum Pulse Width for the Output Data Register Asynchronous Preset Minimum Pulse Width for the Output Data Register Clock Minimum Pulse Width HIGH for the Output Data Register Clock Minimum Pulse Width LOW for the Output Data Register Std. 1.00 0.51 0.00 0.70 0.00 1.34 1.34 0.00 0.24 0.00 0.24 0.19 0.19 0.31 0.28 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. 1.2 V DC Core Voltage Table 2-140 • Output Data Register Propagation Delays Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V Parameter tOCLKQ tOSUD tOHD tOSUE tOHE tOCLR2Q tOPRE2Q tOREMCLR tORECCLR tOREMPRE tORECPRE tOWCLR tOWPRE tOCKMPWH tOCKMPWL Description Clock-to-Q of the Output Data Register Data Setup Time for the Output Data Register Data Hold Time for the Output Data Register Enable Setup Time for the Output Data Register Enable Hold Time for the Output Data Register Asynchronous Clear-to-Q of the Output Data Register Asynchronous Preset-to-Q of the Output Data Register Asynchronous Clear Removal Time for the Output Data Register Asynchronous Clear Recovery Time for the Output Data Register Asynchronous Preset Removal Time for the Output Data Register Asynchronous Preset Recovery Time for the Output Data Register Asynchronous Clear Minimum Pulse Width for the Output Data Register Asynchronous Preset Minimum Pulse Width for the Output Data Register Clock Minimum Pulse Width HIGH for the Output Data Register Clock Minimum Pulse Width LOW for the Output Data Register Std. 1.52 1.15 0.00 1.11 0.00 1.96 1.96 0.00 0.24 0.00 0.24 0.19 0.19 0.31 0.28 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values.
2 -7 4
A d v a n c e v 0. 5
IGLOO DC and Switching Characteristics
Output Enable Register
tOECKMPWH tOECKMPWL
50% CLK
50% tOESUD tOEHD
50%
50%
50%
50%
50%
D_Enable
1
50%
0 50%
Enable
50%
tOEWPRE 50%
tOERECPRE 50%
tOEREMPRE 50%
Preset
tOESUEtOEHE
tOEWCLR 50% Clear tOEPRE2Q EOUT 50% tOECLKQ 50% tOECLR2Q 50%
tOERECCLR 50%
tOEREMCLR 50%
Figure 2-20 • Output Enable Register Timing Diagram
Timing Characteristics
1.5 V DC Core Voltage Table 2-141 • Output Enable Register Propagation Delays Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V Parameter tOECLKQ tOESUD tOEHD tOESUE tOEHE tOECLR2Q tOEPRE2Q tOEREMCLR tOERECCLR tOEREMPRE tOERECPRE tOEWCLR tOEWPRE tOECKMPWH tOECKMPWL Description Clock-to-Q of the Output Enable Register Data Setup Time for the Output Enable Register Data Hold Time for the Output Enable Register Enable Setup Time for the Output Enable Register Enable Hold Time for the Output Enable Register Asynchronous Clear-to-Q of the Output Enable Register Asynchronous Preset-to-Q of the Output Enable Register Asynchronous Clear Removal Time for the Output Enable Register Asynchronous Clear Recovery Time for the Output Enable Register Asynchronous Preset Removal Time for the Output Enable Register Asynchronous Preset Recovery Time for the Output Enable Register Asynchronous Clear Minimum Pulse Width for the Output Enable Register Asynchronous Preset Minimum Pulse Width for the Output Enable Register Clock Minimum Pulse Width HIGH for the Output Enable Register Clock Minimum Pulse Width LOW for the Output Enable Register Std. 0.75 0.51 0.00 0.73 0.00 1.13 1.13 0.00 0.24 0.00 0.24 0.19 0.19 0.31 0.28 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
A dv a n c e v 0. 5
2 - 75
IGLOO DC and Switching Characteristics 1.2 V DC Core Voltage Table 2-142 • Output Enable Register Propagation Delays Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V Parameter tOECLKQ tOESUD tOEHD tOESUE tOEHE tOECLR2Q tOEPRE2Q tOEREMCLR tOERECCLR tOEREMPRE tOERECPRE tOEWCLR tOEWPRE tOECKMPWH tOECKMPWL Description Clock-to-Q of the Output Enable Register Data Setup Time for the Output Enable Register Data Hold Time for the Output Enable Register Enable Setup Time for the Output Enable Register Enable Hold Time for the Output Enable Register Asynchronous Clear-to-Q of the Output Enable Register Asynchronous Preset-to-Q of the Output Enable Register Asynchronous Clear Removal Time for the Output Enable Register Asynchronous Clear Recovery Time for the Output Enable Register Asynchronous Preset Removal Time for the Output Enable Register Asynchronous Preset Recovery Time for the Output Enable Register Asynchronous Clear Minimum Pulse Width for the Output Enable Register Asynchronous Preset Minimum Pulse Width for the Output Enable Register Clock Minimum Pulse Width HIGH for the Output Enable Register Clock Minimum Pulse Width LOW for the Output Enable Register Std. 1.10 1.15 0.00 1.22 0.00 1.65 1.65 0.00 0.24 0.00 0.24 0.19 0.19 0.31 0.28 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values.
2 -7 6
A d v a n c e v 0. 5
IGLOO DC and Switching Characteristics
DDR Module Specifications
Input DDR Module
Input DDR
INBUF Data
A FF1
D
Out_QF (to core)
CLK CLKBUF
B FF2
E
Out_QR (to core)
CLR INBUF
C
DDR_IN
Figure 2-21 • Input DDR Timing Model Table 2-143 • Parameter Definitions Parameter Name tDDRICLKQ1 tDDRICLKQ2 tDDRISUD tDDRIHD tDDRICLR2Q1 tDDRICLR2Q2 tDDRIREMCLR tDDRIRECCLR Parameter Definition Clock-to-Out Out_QR Clock-to-Out Out_QF Data Setup Time of DDR input Data Hold Time of DDR input Clear-to-Out Out_QR Clear-to-Out Out_QF Clear Removal Clear Recovery Measuring Nodes (from, to) B, D B, E A, B A, B C, D C, E C, B C, B
A dv a n c e v 0. 5
2 - 77
IGLOO DC and Switching Characteristics
CLK tDDRISUD Data 1 2 3 4 5 6 7 tDDRIHD 8 tDDRIRECCLR CLR tDDRIREMCLR tDDRICLKQ1 tDDRICLR2Q1 Out_QF tDDRICLR2Q2 Out_QR 3 2 4 tDDRICLKQ2 5 7 6 9
Figure 2-22 • Input DDR Timing Diagram
Timing Characteristics
1.5 V DC Core Voltage Table 2-144 • Input DDR Propagation Delays Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.25 V Parameter tDDRICLKQ1 tDDRICLKQ2 tDDRISUD1 tDDRISUD2 tDDRIHD1 tDDRIHD2 tDDRICLR2Q1 tDDRICLR2Q2 tDDRIREMCLR tDDRIRECCLR tDDRIWCLR tDDRICKMPWH tDDRICKMPWL FDDRIMAX Description Clock-to-Out Out_QR for Input DDR Clock-to-Out Out_QF for Input DDR Data Setup for Input DDR (negedge) Data Setup for Input DDR (posedge) Data Hold for Input DDR (negedge) Data Hold for Input DDR (posedge) Asynchronous Clear-to-Out Out_QR for Input DDR Asynchronous Clear-to-Out Out_QF for Input DDR Asynchronous Clear Removal Time for Input DDR Asynchronous Clear Recovery Time for Input DDR Asynchronous Clear Minimum Pulse Width for Input DDR Clock Minimum Pulse Width HIGH for Input DDR Clock Minimum Pulse Width LOW for Input DDR Maximum Frequency for Input DDR Std. 0.48 0.65 0.50 0.40 0.00 0.00 0.82 0.98 0.00 0.23 0.19 0.31 0.28 TBD Units ns ns ns ns ns ns ns ns ns ns ns ns ns MHz
Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values.
2 -7 8
A d v a n c e v 0. 5
IGLOO DC and Switching Characteristics 1.2 V DC Core Voltage Table 2-145 • Input DDR Propagation Delays Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V Parameter tDDRICLKQ1 tDDRICLKQ2 tDDRISUD1 tDDRISUD2 tDDRIHD1 tDDRIHD2 tDDRICLR2Q1 tDDRICLR2Q2 tDDRIREMCLR tDDRIRECCLR tDDRIWCLR tDDRICKMPWH tDDRICKMPWL FDDRIMAX Description Clock-to-Out Out_QR for Input DDR Clock-to-Out Out_QF for Input DDR Data Setup for Input DDR (negedge) Data Setup for Input DDR (posedge) Data Hold for Input DDR (negedge) Data Hold for Input DDR (posedge) Asynchronous Clear-to-Out Out_QR for Input DDR Asynchronous Clear-to-Out Out_QF for Input DDR Asynchronous Clear Removal Time for Input DDR Asynchronous Clear Recovery Time for Input DDR Asynchronous Clear Minimum Pulse Width for Input DDR Clock Minimum Pulse Width HIGH for Input DDR Clock Minimum Pulse Width LOW for Input DDR Maximum Frequency for Input DDR Std. 0.76 0.94 0.93 0.84 0.00 0.00 1.23 1.42 0.00 0.24 0.19 0.31 0.28 TBD Units ns ns ns ns ns ns ns ns ns ns ns ns ns MHz
Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values.
A dv a n c e v 0. 5
2 - 79
IGLOO DC and Switching Characteristics
Output DDR Module
Output DDR
Data_F (from core)
A X FF1 B Out X 0 E X X FF2 1 X OUTBUF
CLK CLKBUF C D
Data_R (from core)
CLR INBUF
B C
X X DDR_OUT
Figure 2-23 • Output DDR Timing Model Table 2-146 • Parameter Definitions Parameter Name tDDROCLKQ tDDROCLR2Q tDDROREMCLR tDDRORECCLR tDDROSUD1 tDDROSUD2 tDDROHD1 tDDROHD2 Parameter Definition Clock-to-Out Asynchronous Clear-to-Out Clear Removal Clear Recovery Data Setup Data_F Data Setup Data_R Data Hold Data_F Data Hold Data_R Measuring Nodes (from, to) B, E C, E C, B C, B A, B D, B A, B D, B
2 -8 0
A d v a n c e v 0. 5
IGLOO DC and Switching Characteristics
CLK tDDROSUD2 tDDROHD2 Data_F 1 2 tDDROREMCLR Data_R 6 7 tDDROHD1 8 9 10 tDDRORECCLR CLR tDDROREMCLR tDDROCLR2Q Out tDDROCLKQ 7 2 8 3 9 4 10 11 3 4 5
Figure 2-24 • Output DDR Timing Diagram
Timing Characteristics
1.5 V DC Core Voltage Table 2-147 • Output DDR Propagation Delays Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V Parameter tDDROCLKQ tDDROSUD1 tDDROSUD2 tDDROHD1 tDDROHD2 tDDROCLR2Q tDDROREMCLR tDDRORECCLR tDDROWCLR1 tDDROCKMPWH tDDROCKMPWL FDDOMAX Description Clock-to-Out of DDR for Output DDR Data_F Data Setup for Output DDR Data_R Data Setup for Output DDR Data_F Data Hold for Output DDR Data_R Data Hold for Output DDR Asynchronous Clear-to-Out for Output DDR Asynchronous Clear Removal Time for Output DDR Asynchronous Clear Recovery Time for Output DDR Asynchronous Clear Minimum Pulse Width for Output DDR Clock Minimum Pulse Width HIGH for the Output DDR Clock Minimum Pulse Width LOW for the Output DDR Maximum Frequency for the Output DDR Std. 1.07 0.67 0.67 0.00 0.00 1.38 0.00 0.23 0.19 0.31 0.28 TBD Units ns ns ns ns ns ns ns ns ns ns ns MHz
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
A dv a n c e v 0. 5
2 - 81
IGLOO DC and Switching Characteristics 1.2 V DC Core Voltage Table 2-148 • Output DDR Propagation Delays Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V Parameter tDDROCLKQ tDDROSUD1 tDDROSUD2 tDDROHD1 tDDROHD2 tDDROCLR2Q tDDROREMCLR tDDRORECCLR tDDROWCLR1 tDDROCKMPWH tDDROCKMPWL FDDOMAX Description Clock-to-Out of DDR for Output DDR Data_F Data Setup for Output DDR Data_R Data Setup for Output DDR Data_F Data Hold for Output DDR Data_R Data Hold for Output DDR Asynchronous Clear-to-Out for Output DDR Asynchronous Clear Removal Time for Output DDR Asynchronous Clear Recovery Time for Output DDR Asynchronous Clear Minimum Pulse Width for Output DDR Clock Minimum Pulse Width HIGH for the Output DDR Clock Minimum Pulse Width LOW for the Output DDR Maximum Frequency for the Output DDR Std. 1.60 1.09 1.16 0.00 0.00 1.99 0.00 0.24 0.19 0.31 0.28 TBD Units ns ns ns ns ns ns ns ns ns ns ns MHz
Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values.
2 -8 2
A d v a n c e v 0. 5
IGLOO DC and Switching Characteristics
VersaTile Characteristics
VersaTile Specifications as a Combinatorial Module
The IGLOO library offers all combinations of LUT-3 combinatorial functions. In this section, timing characteristics are presented for a sample of the library. For more details, refer to the IGLOO, Fusion, and ProASIC3 Macro Library Guide.
A
INV
Y
A OR2 B A AND2 B Y Y
A NOR2 B Y
A NAND2 B A B C Y
A B XOR2 Y
XOR3
Y
A A B C B C
MAJ3 Y
A 0 MUX2 B 1 Y
NAND3
S
Figure 2-25 • Sample of Combinatorial Cells
A dv a n c e v 0. 5
2 - 83
IGLOO DC and Switching Characteristics
tPD Fanout = 4 Net Length = 1 VersaTile B A NAND2 or Any Combinatorial Logic Y
Net Length = 1 VersaTile
A NAND2 or Any Combinatorial Logic Y
tPD = MAX(tPD(RR), tPD(RF), tPD(FF), tPD(FR)) where edges are applicable for a particular combinatorial cell
B Net Length = 1 VersaTile B A A
NAND2 or Any Combinatorial Logic
Y
Net Length = 1 VersaTile
B
VCC
NAND2 or Any Combinatorial Logic
Y
50% A, B, C
50% GND VCC
50% OUT GND VCC OUT 50% tPD (RF) GND tPD (RR) tPD (FF) tPD (FR)
50%
50%
Figure 2-26 • Timing Model and Waveforms
2 -8 4
A d v a n c e v 0. 5
IGLOO DC and Switching Characteristics
Timing Characteristics
1.5 V DC Core Voltage
Table 2-149 • Combinatorial Cell Propagation Delays Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V Combinatorial Cell INV AND2 NAND2 OR2 NOR2 XOR2 MAJ3 XOR3 MUX2 AND3 Equation Y =!A Y=A·B Y = !(A · B) Y=A+B Y = !(A + B) Y=A⊕ B Y = MAJ(A , B, C) Y=A⊕B⊕ C Y = A !S + B S Y=A·B·C Parameter tPD tPD tPD tPD tPD tPD tPD tPD tPD tPD Std. 0.80 0.84 0.90 1.19 1.10 1.37 1.33 1.79 1.48 1.21 Units ns ns ns ns ns ns ns ns ns ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
1.2 V DC Core Voltage
Table 2-150 • Combinatorial Cell Propagation Delays Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V Combinatorial Cell INV AND2 NAND2 OR2 NOR2 XOR2 MAJ3 XOR3 MUX2 AND3 Equation Y = !A Y=A·B Y = !(A · B) Y=A+B Y = !(A + B) Y=A⊕ B Y = MAJ(A , B, C) Y=A⊕B⊕ C Y = A !S + B S Y=A·B·C Parameter tPD tPD tPD tPD tPD tPD tPD tPD tPD tPD Std. 1.34 1.43 1.59 2.30 2.07 2.46 2.46 3.12 2.83 2.28 Units ns ns ns ns ns ns ns ns ns ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values.
A dv a n c e v 0. 5
2 - 85
IGLOO DC and Switching Characteristics
VersaTile Specifications as a Sequential Module
The IGLOO library offers a wide variety of sequential cells, including flip-flops and latches. Each has a data input and optional enable, clear, or preset. In this section, timing characteristics are presented for a representative sample from the library. For more details, refer to the IGLOO, Fusion, and ProASIC3 Macro Library Guide.
Data
D DFN1
Q
Out
Data D En CLK Q DFN1E1
Out
CLK
PRE
Data
D
Q DFN1C1
Out
Data En CLK
D
Q
Out
DFI1E1P1
CLK CLR
Figure 2-27 • Sample of Sequential Cells
2 -8 6
A d v a n c e v 0. 5
IGLOO DC and Switching Characteristics
tCKMPWH tCKMPWL 50% 50% tSUD Data 50% tHD 0 50% 50% 50% 50% 50% 50%
CLK
EN 50% tHE tWPRE tSUE 50% tRECPRE 50% tRECCLR 50% tREMPRE 50% tREMCLR 50%
PRE
tWCLR CLR tPRE2Q Out tCLKQ 50% 50% 50%
tCLR2Q 50%
Figure 2-28 • Timing Model and Waveforms
Timing Characteristics
1.5 V DC Core Voltage
Table 2-151 • Register Delays Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V Parameter tCLKQ tSUD tHD tSUE tHE tCLR2Q tPRE2Q tREMCLR tRECCLR tREMPRE tRECPRE tWCLR tWPRE tCKMPWH tCKMPWL Clock-to-Q of the Core Register Data Setup Time for the Core Register Data Hold Time for the Core Register Enable Setup Time for the Core Register Enable Hold Time for the Core Register Asynchronous Clear-to-Q of the Core Register Asynchronous Preset-to-Q of the Core Register Asynchronous Clear Removal Time for the Core Register Asynchronous Clear Recovery Time for the Core Register Asynchronous Preset Removal Time for the Core Register Asynchronous Preset Recovery Time for the Core Register Asynchronous Clear Minimum Pulse Width for the Core Register Asynchronous Preset Minimum Pulse Width for the Core Register Clock Minimum Pulse Width HIGH for the Core Register Clock Minimum Pulse Width LOW for the Core Register Description Std. 0.89 0.81 0.00 0.73 0.00 0.60 0.62 0.00 0.24 0.00 0.23 0.30 0.30 0.56 0.56 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
A dv a n c e v 0. 5
2 - 87
IGLOO DC and Switching Characteristics
1.2 V DC Core Voltage
Table 2-152 • Register Delays Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V Parameter tCLKQ tSUD tHD tSUE tHE tCLR2Q tPRE2Q tREMCLR tRECCLR tREMPRE tRECPRE tWCLR tWPRE tCKMPWH tCKMPWL Clock-to-Q of the Core Register Data Setup Time for the Core Register Data Hold Time for the Core Register Enable Setup Time for the Core Register Enable Hold Time for the Core Register Asynchronous Clear-to-Q of the Core Register Asynchronous Preset-to-Q of the Core Register Asynchronous Clear Removal Time for the Core Register Asynchronous Clear Recovery Time for the Core Register Asynchronous Preset Removal Time for the Core Register Asynchronous Preset Recovery Time for the Core Register Asynchronous Clear Minimum Pulse Width for the Core Register Asynchronous Preset Minimum Pulse Width for the Core Register Clock Minimum Pulse Width HIGH for the Core Register Clock Minimum Pulse Width LOW for the Core Register Description Std. 1.61 1.17 0.00 1.29 0.00 0.87 0.89 0.00 0.24 0.00 0.24 0.46 0.46 0.95 0.95 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values.
2 -8 8
A d v a n c e v 0. 5
IGLOO DC and Switching Characteristics
Global Resource Characteristics
AGL250 Clock Tree Topology
Clock delays are device-specific. Figure 2-29 is an example of a global tree used for clock routing. The global tree presented in Figure 2-29 is driven by a CCC located on the west side of the AGL250 device. It is used to drive all D-flip-flops in the device.
Central Global Rib
CCC
VersaTile Rows
Global Spine
Figure 2-29 • Example of Global Tree Use in an AGL250 Device for Clock Routing
A dv a n c e v 0. 5
2 - 89
IGLOO DC and Switching Characteristics
Global Tree Timing Characteristics
Global clock delays include the central rib delay, the spine delay, and the row delay. Delays do not include I/O input buffer clock delays, as these are I/O standard–dependent, and the clock may be driven and conditioned internally by the CCC module. For more details on clock conditioning capabilities, refer to the "Clock Conditioning Circuits" section on page 2-98. Table 2-153 to Table 2-168 on page 2-97 present minimum and maximum global clock delays within each device. Minimum and maximum delays are measured with minimum and maximum loading.
Timing Characteristics
1.5 V DC Core Voltage Table 2-153 • AGL015 Global Resource Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V Std. Parameter tRCKL tRCKH tRCKMPWH tRCKMPWL tRCKSW FRMAX Notes: 1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element, located in a lightly loaded row (single element is connected to the global net). 2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row (all available flip-flops are connected to the global net in the row). 3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. Table 2-154 • AGL030 Global Resource Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V Std. Parameter tRCKL tRCKH tRCKMPWH tRCKMPWL tRCKSW FRMAX Notes: 1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element, located in a lightly loaded row (single element is connected to the global net). 2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row (all available flip-flops are connected to the global net in the row). 3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. Description Input LOW Delay for Global Clock Input HIGH Delay for Global Clock Minimum Pulse Width HIGH for Global Clock Minimum Pulse Width LOW for Global Clock Maximum Skew for Global Clock Maximum Frequency for Global Clock 0.27 Min.
1 1
Description Input LOW Delay for Global Clock Input HIGH Delay for Global Clock Minimum Pulse Width HIGH for Global Clock Minimum Pulse Width LOW for Global Clock Maximum Skew for Global Clock Maximum Frequency for Global Clock
Min.
Max.2 1.42 1.49
Units ns ns ns ns
1.21 1.23
0.27
ns MHz
Max.2 1.42 1.49
Units ns ns ns ns ns MHz
1.21 1.23
2 -9 0
A d v a n c e v 0. 5
IGLOO DC and Switching Characteristics Table 2-155 • AGL060 Global Resource Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V Std. Parameter tRCKL tRCKH tRCKMPWH tRCKMPWL tRCKSW FRMAX Notes: 1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element, located in a lightly loaded row (single element is connected to the global net). 2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row (all available flip-flops are connected to the global net in the row). 3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. Table 2-156 • AGL125 Global Resource Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V Std. Parameter tRCKL tRCKH tRCKMPWH tRCKMPWL tRCKSW FRMAX Notes: 1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element, located in a lightly loaded row (single element is connected to the global net). 2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row (all available flip-flops are connected to the global net in the row). 3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. Description Input LOW Delay for Global Clock Input HIGH Delay for Global Clock Minimum Pulse Width HIGH for Global Clock Minimum Pulse Width LOW for Global Clock Maximum Skew for Global Clock Maximum Frequency for Global Clock 0.43 Min.
1 1
Description Input LOW Delay for Global Clock Input HIGH Delay for Global Clock Minimum Pulse Width HIGH for Global Clock Minimum Pulse Width LOW for Global Clock Maximum Skew for Global Clock Maximum Frequency for Global Clock
Min.
Max.2 1.55 1.62
Units ns ns ns ns
1.33 1.35
0.27
ns MHz
Max.2 1.71 1.82
Units ns ns ns ns ns MHz
1.36 1.39
A dv a n c e v 0. 5
2 - 91
IGLOO DC and Switching Characteristics Table 2-157 • AGL250 Global Resource Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V Std. Parameter tRCKL tRCKH tRCKMPWH tRCKMPWL tRCKSW FRMAX Notes: 1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element, located in a lightly loaded row (single element is connected to the global net). 2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row (all available flip-flops are connected to the global net in the row). 3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. Table 2-158 • AGL400 Global Resource Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V Std. Parameter tRCKL tRCKH tRCKMPWH tRCKMPWL tRCKSW FRMAX Notes: 1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element, located in a lightly loaded row (single element is connected to the global net). 2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row (all available flip-flops are connected to the global net in the row). 3. For specific junction temperature and voltage-supply levels, refer to Table 2-6 on page 2-6 for derating values. Description Input Low Delay for Global Clock Input High Delay for Global Clock Minimum Pulse Width High for Global Clock Minimum Pulse Width Low for Global Clock Maximum Skew for Global Clock Maximum Frequency for Global Clock 0.43 Min. 1.45 1.48
1 1
Description Input LOW Delay for Global Clock Input HIGH Delay for Global Clock Minimum Pulse Width HIGH for Global Clock Minimum Pulse Width LOW for Global Clock Maximum Skew for Global Clock Maximum Frequency for Global Clock
Min.
Max.2 1.73 1.84
Units ns ns ns ns
1.39 1.41
0.43
ns MHz
Max. 2 1.79 1.91
Units ns ns ns ns ns MHz
2 -9 2
A d v a n c e v 0. 5
IGLOO DC and Switching Characteristics Table 2-159 • AGL600 Global Resource Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V Std. Parameter tRCKL tRCKH tRCKMPWH tRCKMPWL tRCKSW FRMAX Notes: 1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element, located in a lightly loaded row (single element is connected to the global net). 2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row (all available flip-flops are connected to the global net in the row). 3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. Table 2-160 • AGL1000 Global Resource Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V Std. Parameter tRCKL tRCKH tRCKMPWH tRCKMPWL tRCKSW FRMAX Notes: 1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element, located in a lightly loaded row (single element is connected to the global net). 2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row (all available flip-flops are connected to the global net in the row). 3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. Description Input LOW Delay for Global Clock Input HIGH Delay for Global Clock Minimum Pulse Width HIGH for Global Clock Minimum Pulse Width LOW for Global Clock Maximum Skew for Global Clock Maximum Frequency for Global Clock 0.42 Min.
1 1
Description Input LOW Delay for Global Clock Input HIGH Delay for Global Clock Minimum Pulse Width HIGH for Global Clock Minimum Pulse Width LOW for Global Clock Maximum Skew for Global Clock Maximum Frequency for Global Clock
Min.
Max.2 1.82 1.94
Units ns ns ns ns
1.48 1.52
0.42
ns MHz
Max.2 1.89 2.02
Units ns ns ns ns ns MHz
1.55 1.60
A dv a n c e v 0. 5
2 - 93
IGLOO DC and Switching Characteristics 1.2 V DC Core Voltage Table 2-161 • AGL015 Global Resource Commercial-Case Conditions: TJ = 70°C, VCC = 1.14 V Std. Parameter tRCKL tRCKH tRCKMPWH tRCKMPWL tRCKSW FRMAX Notes: 1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element, located in a lightly loaded row (single element is connected to the global net). 2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row (all available flip-flops are connected to the global net in the row). 3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. Table 2-162 • AGL030 Global Resource Commercial-Case Conditions: TJ = 70°C, VCC = 1.14 V Std. Parameter tRCKL tRCKH tRCKMPWH tRCKMPWL tRCKSW FRMAX Notes: 1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element, located in a lightly loaded row (single element is connected to the global net). 2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row (all available flip-flops are connected to the global net in the row). 3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. Description Input LOW Delay for Global Clock Input HIGH Delay for Global Clock Minimum Pulse Width HIGH for Global Clock Minimum Pulse Width LOW for Global Clock Maximum Skew for Global Clock Maximum Frequency for Global Clock 0.39 Min.1 1.80 1.88 Max.2 2.09 2.27 Units ns ns ns ns ns MHz Description Input LOW Delay for Global Clock Input HIGH Delay for Global Clock Minimum Pulse Width HIGH for Global Clock Minimum Pulse Width LOW for Global Clock Maximum Skew for Global Clock Maximum Frequency for Global Clock 0.39 Min.1 1.79 1.87 Max.2 2.09 2.26 Units ns ns ns ns ns MHz
2 -9 4
A d v a n c e v 0. 5
IGLOO DC and Switching Characteristics Table 2-163 • AGL060 Global Resource Commercial-Case Conditions: TJ = 70°C, VCC = 1.14 V Std. Parameter tRCKL tRCKH tRCKMPWH tRCKMPWL tRCKSW FRMAX Notes: 1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element, located in a lightly loaded row (single element is connected to the global net). 2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row (all available flip-flops are connected to the global net in the row). 3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. Table 2-164 • AGL125 Global Resource Commercial-Case Conditions: TJ = 70°C, VCC = 1.14 V Std. Parameter tRCKL tRCKH tRCKMPWH tRCKMPWL tRCKSW FRMAX Notes: 1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element, located in a lightly loaded row (single element is connected to the global net). 2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row (all available flip-flops are connected to the global net in the row). 3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. Description Input LOW Delay for Global Clock Input HIGH Delay for Global Clock Minimum Pulse Width HIGH for Global Clock Minimum Pulse Width LOW for Global Clock Maximum Skew for Global Clock Maximum Frequency for Global Clock 0.62 Min.
1 1
Description Input LOW Delay for Global Clock Input HIGH Delay for Global Clock Minimum Pulse Width HIGH for Global Clock Minimum Pulse Width LOW for Global Clock Maximum Skew for Global Clock Maximum Frequency for Global Clock
Min.
Max.2 2.33 2.51
Units ns ns ns ns
2.04 2.10
0.40
ns MHz
Max.2 2.54 2.77
Units ns ns ns ns ns MHz
2.08 2.15
A dv a n c e v 0. 5
2 - 95
IGLOO DC and Switching Characteristics Table 2-165 • AGL250 Global Resource Commercial-Case Conditions: TJ = 70°C, VCC = 1.14 V Std. Parameter tRCKL tRCKH tRCKMPWH tRCKMPWL tRCKSW FRMAX Notes: 1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element, located in a lightly loaded row (single element is connected to the global net). 2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row (all available flip-flops are connected to the global net in the row). 3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. Table 2-166 • AGL400 Global Resource Commercial-Case Conditions: TJ = 70°C, VCC = 1.14 V Std. Parameter tRCKL tRCKH tRCKMPWH tRCKMPWL tRCKSW FRMAX Notes: 1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element, located in a lightly loaded row (single element is connected to the global net). 2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row (all available flip-flops are connected to the global net in the row). 3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. Description Input LOW Delay for Global Clock Input HIGH Delay for Global Clock Minimum Pulse Width HIGH for Global Clock Minimum Pulse Width LOW for Global Clock Maximum Skew for Global Clock Maximum Frequency for Global Clock 0.62 Min.
1 1
Description Input LOW Delay for Global Clock Input HIGH Delay for Global Clock Minimum Pulse Width HIGH for Global Clock Minimum Pulse Width LOW for Global Clock Maximum Skew for Global Clock Maximum Frequency for Global Clock
Min.
Max.2 2.57 2.81
Units ns ns ns ns
2.11 2.19
0.62
ns MHz
Max.2 2.64 2.89
Units ns ns ns ns ns MHz
2.18 2.27
2 -9 6
A d v a n c e v 0. 5
IGLOO DC and Switching Characteristics Table 2-167 • AGL600 Global Resource Commercial-Case Conditions: TJ = 70°C, VCC = 1.14 V Std. Parameter tRCKL tRCKH tRCKMPWH tRCKMPWL tRCKSW FRMAX Notes: 1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element, located in a lightly loaded row (single element is connected to the global net). 2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row (all available flip-flops are connected to the global net in the row). 3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. Table 2-168 • AGL1000 Global Resource Commercial-Case Conditions: TJ = 70°C, VCC = 1.14 V Std. Parameter tRCKL tRCKH tRCKMPWH tRCKMPWL tRCKSW FRMAX Notes: 1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element, located in a lightly loaded row (single element is connected to the global net). 2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row (all available flip-flops are connected to the global net in the row). 3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. Description Input LOW Delay for Global Clock Input HIGH Delay for Global Clock Minimum Pulse Width HIGH for Global Clock Minimum Pulse Width LOW for Global Clock Maximum Skew for Global Clock Maximum Frequency for Global Clock 0.61 Min.
1 1
Description Input LOW Delay for Global Clock Input HIGH Delay for Global Clock Minimum Pulse Width HIGH for Global Clock Minimum Pulse Width LOW for Global Clock Maximum Skew for Global Clock Maximum Frequency for Global Clock
Min.
Max.2 2.67 2.93
Units ns ns ns ns
2.22 2.32
0.61
ns MHz
Max.2 2.76 3.03
Units ns ns ns ns ns MHz
2.31 2.42
A dv a n c e v 0. 5
2 - 97
IGLOO DC and Switching Characteristics
Clock Conditioning Circuits
CCC Electrical Specifications
Timing Characteristics
Table 2-169 • IGLOO CCC/PLL Specification For IGLOO V2 or V5 Devices, 1.5 V DC Core Supply Voltage Parameter Clock Conditioning Circuitry Input Frequency fIN_CCC Clock Conditioning Circuitry Output Frequency fOUT_CCC Delay Increments in Programmable Delay Blocks 1, 2 Number of Programmable Values in Each Programmable Delay Block Serial Clock (SCLK) for Dynamic PLL
3
Min. 1.5 0.75
Typ.
Max. 250 250
Units MHz MHz ps
360 32 100 1
ns ns
Input Cycle-to-Cycle Jitter (peak magnitude) CCC Output Peak-to-Peak Period Jitter FCCC_OUT
Maximum Peak-to-Peak Period Jitter 1 Global Network Used External 3 Global FB Used Networks Used 0.75% 1.50% 3.75% 0.70% 1.20% 2.75%
0.75 MHz to 24 MHz 24 MHz to 100 MHz 100 MHz to 250 MHz Acquisition Time LockControl = 0 LockControl = 1 Tracking Jitter LockControl = 0 LockControl = 1 Output Duty Cycle Delay Range in Block: Programmable Delay 1 Delay Range in Block: Programmable Delay 2 Delay Range in Block: Fixed Delay 1, 2, 4 Notes:
1, 2, 4 1, 2, 4
0.50% 1.00% 2.50%
300 6.0
µs ms
2.5 1.5 48.5 1.25 0.025 3.5 51.5 15.65 15.65
ns ns % ns ns ns
1. This delay is a function of voltage and temperature. See Table 2-6 on page 2-6 and Table 2-7 on page 2-7 for deratings. 2. TJ = 25°C, VCC = 1.5 V 3. Maximum value obtained for a Std. speed grade device in Worst-Case Commercial Conditions. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. 4. For the definitions of Type 1 and Type 2, refer to the PLL Block Diagram in the Clock Conditioning Circuits in IGLOO and ProASIC3 Devices chapter of the handbook. 5. The AGL030 device does not support PLL. 6. Tracking jitter is defined as the variation in clock edge position of PLL outputs with reference to the PLL input clock edge. Tracking jitter does not measure the variation in PLL output period, which is covered by the period jitter parameter.
2 -9 8
A d v a n c e v 0. 5
IGLOO DC and Switching Characteristics Table 2-170 • IGLOO CCC/PLL Specification For IGLOO V2 Devices, 1.2 V DC Core Supply Voltage Parameter Clock Conditioning Circuitry Input Frequency fIN_CCC Clock Conditioning Circuitry Output Frequency fOUT_CCC Delay Increments in Programmable Delay Blocks 1, 2 Number of Programmable Values in Each Programmable Delay Block Serial Clock (SCLK) for Dynamic PLL
3
Min. 1.5 0.75
Typ.
Max. 160 160
Units MHz MHz ps
580 32 60 0.25
ns ns
Input Cycle-to-Cycle Jitter (peak magnitude) CCC Output Peak-to-Peak Period Jitter FCCC_OUT
Maximum Peak-to-Peak Period Jitter 1 Global Network Used External FB Used 0.75% 1.50% 3.75% 3 Global Networks Used 0.70% 1.20% 2.75%
0.75 MHz to 24 MHz 24 MHz to 100 MHz 100 MHz to 160 MHz Acquisition Time LockControl = 0 LockControl = 1 Tracking Jitter LockControl = 0 LockControl = 1 Output Duty Cycle Delay Range in Block: Programmable Delay 1 Delay Range in Block: Programmable Delay 2 Delay Range in Block: Fixed Delay 1, 2, 4 Notes:
1, 2, 4 1, 2, 4
0.50% 1.00% 2.50%
300 6.0
µs ms
4 3 48.5 2.3 0.025 5.7 51.5 20.86 20.86
ns ns % ns ns ns
1. This delay is a function of voltage and temperature. See Table 2-6 on page 2-6 and Table 2-7 on page 2-7 for deratings. 2. TJ = 25°C, VCC = 1.5 V 3. Maximum value obtained for a Std. speed grade device in Worst-Case Commercial Conditions. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. 4. For the definitions of Type 1 and Type 2, refer to the PLL Block Diagram in the Clock Conditioning Circuits in IGLOO and ProASIC3 Devices chapter of the handbook. 5. The AGL030 device does not support PLL. 6. Tracking jitter is defined as the variation in clock edge position of PLL outputs with reference to the PLL input clock edge. Tracking jitter does not measure the variation in PLL output period, which is covered by the period jitter parameter.
A dv a n c e v 0. 5
2 - 99
IGLOO DC and Switching Characteristics
Output Signal
Tperiod_max
Tperiod_min
Note: Peak-to-peak jitter measurements are defined by Tpeak-to-peak = Tperiod_max – Tperiod_min. Figure 2-30 • Peak-to-Peak Jitter Definition
2 -1 0 0
A d v a n c e v 0. 5
IGLOO DC and Switching Characteristics
Embedded SRAM and FIFO Characteristics
SRAM
RAM4K9 ADDRA11 ADDRA10 ADDRA0 DINA8 DINA7 DOUTA8 DOUTA7 DOUTA0 RAM512X18 RADDR8 RADDR7 RADDR0 RD17 RD16 RD0
DINA0
RW1 RW0
WIDTHA1 WIDTHA0 PIPEA WMODEA BLKA WENA CLKA ADDRB11 ADDRB10 ADDRB0 DINB8 DINB7 DOUTB8 DOUTB7 DOUTB0
PIPE
REN RCLK WADDR8 WADDR7
WADDR0 WD17 WD16
WD0 DINB0 WIDTHB1 WIDTHB0 PIPEB WMODEB BLKB WENB CLKB RESET WW1 WW0
WEN WCLK RESET
Figure 2-31 • RAM Models
A dv a n c e v 0. 5
2 -101
IGLOO DC and Switching Characteristics
Timing Waveforms
tCYC tCKH CLK tAS ADD A0 tBKS BLK_B tENS WEN_B tCKQ1 DO Dn D0 tDOH1
Figure 2-32 • RAM Read for Pass-Through Output
tCKL
tAH A1 A2 tBKH tENH
D1
D2
tCYC tCKH CLK t ADD tBKS BLK_B tENS WEN_B tCKQ2 DO Dn D0 tDOH2
Figure 2-33 • RAM Read for Pipelined Output
AS
tCKL
tAH A0 A1 A2 tBKH tENH
D1
2 -1 0 2
A d v a n c e v 0. 5
IGLOO DC and Switching Characteristics
tCYC tCKH CLK tAS ADD tBKS tBKH BLK_B tENS WEN_B tDS DI DI0 tDH DI1 tENH A0 tAH A1 A2 tCKL
DO
Dn
D2
Figure 2-34 • RAM Write, Output Retained (WMODE = 0)
tCYC tCKH CLK tAS ADD tBKS BLK_B tENS WEN_B tDS DI DO (pass-through) DO (pipelined) DI0 tDH DI1 DI2 tBKH A0 tAH A1 A2 tCKL
Dn
DI0
DI1
Dn
DI0
DI1
Figure 2-35 • RAM Write, Output as Write Data (WMODE = 1)
A dv a n c e v 0. 5
2 -103
IGLOO DC and Switching Characteristics
CLK1 tAS ADD1 tDS DI1 tAH A0 tDH D1 tCCKH CLK2 WEN_B1 WEN_B2 ADD2 DI2 DO2 (pass-through) DO2 (pipelined) A0 D0 tCKQ1 Dn D0 tCKQ2 Dn D0 A1 D2 A3 D3
tAS
tAH A0 A4 D4
Figure 2-36 • Write Access after Write onto Same Address
2 -1 0 4
A d v a n c e v 0. 5
IGLOO DC and Switching Characteristics
CLK1 tAS tAH ADD1 DI1 CLK2 WEN_B1 WEN_B2 tAS tAH ADD2 DO2 (pass-through) DO2 (pipelined) Dn Dn A0 tCKQ1 D0 tCKQ2 D0 D1 A1 A4 A0 tDS tDH D0 tWRO A2 D2 A3 D3
Figure 2-37 • Read Access after Write onto Same Address
A dv a n c e v 0. 5
2 -105
IGLOO DC and Switching Characteristics
CLK1 tAS ADD1 WEN_B1 tCKQ1 DO1 (pass-through) DO1 (pipelined) CLK2 tAS ADD2 A0 D1 tAH A1 D2 A3 D3 Dn D0 tCKQ2 Dn tCCKH D0 tCKQ1 D1 tAH A0 A1 A0
DI2 WEN_B2
Figure 2-38 • Write Access after Read onto Same Address
tCYC tCKH CLK tCKL
RESET_B tRSTBQ DO Dm Dn
Figure 2-39 • RAM Reset
2 -1 0 6
A d v a n c e v 0. 5
IGLOO DC and Switching Characteristics
Timing Characteristics
1.5 V DC Core Voltage
Table 2-171 • RAM4K9 Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V Parameter tAS tAH tENS tENH tBKS tBKH tDS tDH tCKQ1 tCKQ2 tWRO tCCKH tRSTBQ tREMRSTB tRECRSTB tMPWRSTB tCYC FMAX Address setup time Address hold time REN_B, WEN_B setup time REN_B, WEN_B hold time BLK_B setup time BLK_B hold time Input data (DI) setup time Input data (DI) hold time Clock HIGH to new data valid on DO (output retained, WMODE = 0) Clock HIGH to new data valid on DO (flow-through, WMODE = 1) Clock HIGH to new data valid on DO (pipelined) Address collision clk-to-clk delay for reliable read access after write on same address Description Std. Units 0.83 0.16 0.81 0.16 1.65 0.16 0.71 0.36 3.53 3.06 1.81 TBD ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHz
Address collision clk-to-clk delay for reliable write access after write/read on same TBD address RESET_B LOW to data out LOW on DO (flow-through) RESET_B LOW to data out LOW on DO (pipelined) RESET_B removal RESET_B recovery RESET_B minimum pulse width Clock cycle time Maximum frequency 2.06 2.06 0.61 3.21 0.68 6.24 160
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
A dv a n c e v 0. 5
2 -107
IGLOO DC and Switching Characteristics Table 2-172 • RAM512X18 Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V Parameter tAS tAH tENS tENH tDS tDH tCKQ1 tCKQ2 tWRO tCCKH tRSTBQ tREMRSTB tRECRSTB tMPWRSTB tCYC FMAX Address setup time Address hold time REN_B, WEN_B setup time REN_B, WEN_B hold time Input data (DI) setup time Input data (DI) hold time Clock HIGH to new data valid on DO (output retained, WMODE = 0) Clock HIGH to new data valid on DO (pipelined) Address collision clk-to-clk delay for reliable read access after write on same address Description Std. Units 0.83 0.16 0.73 0.08 0.71 0.36 4.21 1.71 TBD ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHz
Address collision clk-to-clk delay for reliable write access after write/read on same TBD address RESET_B LOW to data out LOW on DO (flow-through) RESET_B LOW to data out LOW on DO (pipelined) RESET_B removal RESET_B recovery RESET_B minimum pulse width Clock cycle time Maximum frequency 2.06 2.06 0.61 3.21 0.68 6.24 160
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
2 -1 0 8
A d v a n c e v 0. 5
IGLOO DC and Switching Characteristics
1.2 V DC Core Voltage
Table 2-173 • RAM4K9 Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V Parameter tAS tAH tENS tENH tBKS tBKH tDS tDH tCKQ1 tCKQ2 tWRO tCCKH tRSTBQ tREMRSTB tRECRSTB tMPWRSTB tCYC FMAX Address setup time Address hold time REN_B, WEN_B setup time REN_B, WEN_B hold time BLK_B setup time BLK_B hold time Input data (DI) setup time Input data (DI) hold time Clock HIGH to new data valid on DO (output retained, WMODE = 0) Clock HIGH to new data valid on DO (flow-through, WMODE = 1) Clock HIGH to new data valid on DO (pipelined) Address collision clk-to-clk delay for reliable read access after write on same address Address collision clk-to-clk delay for reliable write access after write/read on same address RESET_B LOW to data out LOW on DO (flow-through) RESET_B LOW to data out LOW on DO (pipelined) RESET_B removal RESET_B recovery RESET_B minimum pulse width Clock cycle time Maximum frequency Description Std. 1.53 0.29 1.50 0.29 3.05 0.29 1.33 0.66 6.61 5.72 3.38 TBD TBD 3.86 3.86 1.12 5.93 1.18 10.90 92 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHz
Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values.
A dv a n c e v 0. 5
2 -109
IGLOO DC and Switching Characteristics Table 2-174 • RAM512X18 Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V Parameter tAS tAH tENS tENH tDS tDH tCKQ1 tCKQ2 tWRO tCCKH tRSTBQ tREMRSTB tRECRSTB tMPWRSTB tCYC FMAX Address setup time Address hold time REN_B, WEN_B setup time REN_B, WEN_B hold time Input data (DI) setup time Input data (DI) hold time Clock HIGH to new data valid on DO (output retained, WMODE = 0) Clock HIGH to new data valid on DO (pipelined) Address collision clk-to-clk delay for reliable read access after write on same address Address collision clk-to-clk delay for reliable write access after write/read on same address RESET_B LOW to data out LOW on DO (flow through) RESET_B LOW to data out LOW on DO (pipelined) RESET_B removal RESET_B recovery RESET_B minimum pulse width Clock cycle time Maximum frequency Description Std. 1.53 0.29 1.36 0.15 1.33 0.66 7.88 3.20 TBD TBD 3.86 3.86 1.12 5.93 1.18 10.90 92 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHz
Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values.
2 -1 1 0
A d v a n c e v 0. 5
IGLOO DC and Switching Characteristics
FIFO
FIFO4K18 RW2 RW1 RW0 WW2 WW1 WW0 ESTOP FSTOP AEVAL11 AEVAL10 RD17 RD16
RD0 FULL AFULL EMPTY AEMPTY
AEVAL0 AFVAL11 AFVAL10
AFVAL0 REN RBLK RCLK WD17 WD16
WD0 WEN WBLK WCLK RPIPE
RESET
Figure 2-40 • FIFO Model
A dv a n c e v 0. 5
2 -111
IGLOO DC and Switching Characteristics
Timing Waveforms
RCLK/ WCLK tMPWRSTB RESET_B tRSTFG EMPTY tRSTAF AEMPTY tRSTFG FULL tRSTAF AFULL WA/RA (Address Counter)
Figure 2-41 • FIFO Reset
tRSTCK
MATCH (A0)
tCYC RCLK tRCKEF EMPTY tCKAF AEMPTY WA/RA (Address Counter)
NO MATCH
NO MATCH
Dist = AEF_TH
MATCH (EMPTY)
Figure 2-42 • FIFO EMPTY Flag and AEMPTY Flag Assertion
2 -1 1 2
A d v a n c e v 0. 5
IGLOO DC and Switching Characteristics
tCYC WCLK tWCKFF FULL tCKAF AFULL
WA/RA NO MATCH (Address Counter)
NO MATCH
Dist = AFF_TH
MATCH (FULL)
Figure 2-43 • FIFO FULL Flag and AFULL Flag Assertion
WCLK
WA/RA (Address Counter)
MATCH (EMPTY)
NO MATCH
NO MATCH 2nd Rising Edge After 1st Write tRCKEF
NO MATCH
NO MATCH
Dist = AEF_TH + 1
RCLK
1st Rising Edge After 1st Write
EMPTY tCKAF AEMPTY
Figure 2-44 • FIFO EMPTY Flag and AEMPTY Flag Deassertion
RCLK WA/RA MATCH (FULL) NO MATCH (Address Counter) 1st Rising Edge After 1st WCLK Read FULL tCKAF AFULL NO MATCH 1st Rising Edge After 2nd Read tWCKF NO MATCH NO MATCH Dist = AFF_TH – 1
Figure 2-45 • FIFO FULL Flag and AFULL Flag Deassertion
A dv a n c e v 0. 5
2 -113
IGLOO DC and Switching Characteristics
Timing Characteristics
1.5 V DC Core Voltage
Table 2-175 • FIFO Worst Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V Parameter tENS tENH tBKS tBKH tDS tDH tCKQ1 tCKQ2 tRCKEF tWCKFF tCKAF tRSTFG tRSTAF tRSTBQ REN_B, WEN_B Setup Time REN_B, WEN_B Hold Time BLK_B Setup Time BLK_B Hold Time Input Data (DI) Setup Time Input Data (DI) Hold Time Clock HIGH to New Data Valid on DO (flow-through) Clock HIGH to New Data Valid on DO (pipelined) RCLK HIGH to Empty Flag Valid WCLK HIGH to Full Flag Valid Clock HIGH to Almost Empty/Full Flag Valid RESET_B LOW to Empty/Full Flag Valid RESET_B LOW to Almost Empty/Full Flag Valid RESET_B LOW to Data Out LOW on DO (flow-through) RESET_B LOW to Data Out LOW on DO (pipelined) tREMRSTB tRECRSTB tMPWRSTB tCYC FMAX RESET_B Removal RESET_B Recovery RESET_B Minimum Pulse Width Clock Cycle Time Maximum Frequency for FIFO Description Std. 1.99 0.16 0.30 0.00 0.76 0.25 3.33 1.80 3.53 3.35 12.85 3.48 12.72 2.02 2.02 0.61 3.21 0.68 6.24 160 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHz
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
2 -1 1 4
A d v a n c e v 0. 5
IGLOO DC and Switching Characteristics
1.2 V DC Core Voltage
Table 2-176 • FIFO Worst Commercial-Case Conditions: TJ = 70°C, VCC = 1.14 V Parameter tENS tENH tBKS tBKH tDS tDH tCKQ1 tCKQ2 tRCKEF tWCKFF tCKAF tRSTFG tRSTAF tRSTBQ REN_B, WEN_B Setup Time REN_B, WEN_B Hold Time BLK_B Setup Time BLK_B Hold Time Input Data (DI) Setup Time Input Data (DI) Hold Time Clock HIGH to New Data Valid on DO (flow-through) Clock HIGH to New Data Valid on DO (pipelined) RCLK HIGH to Empty Flag Valid WCLK HIGH to Full Flag Valid Clock HIGH to Almost Empty/Full Flag Valid RESET_B LOW to Empty/Full Flag Valid RESET_B LOW to Almost Empty/Full Flag Valid RESET_B LOW to Data Out LOW on DO (flow-through) RESET_B LOW to Data Out LOW on DO (pipelined) tREMRSTB tRECRSTB tMPWRSTB tCYC FMAX RESET_B Removal RESET_B Recovery RESET_B Minimum Pulse Width Clock Cycle Time Maximum Frequency for FIFO Description Std. 4.13 0.31 0.47 0.00 1.56 0.49 6.80 3.62 7.23 6.85 26.61 7.12 26.33 4.09 4.09 1.23 6.58 1.18 10.90 92 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHz
Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values.
A dv a n c e v 0. 5
2 -115
IGLOO DC and Switching Characteristics
Embedded FlashROM Characteristics
tSU CLK tHOLD tSU tHOLD tSU tHOLD
Address
A0 tCKQ2
A1 tCKQ2 D0 tCKQ2 D1
Data
D0
Figure 2-46 • Timing Diagram
Timing Characteristics
1.5 V DC Core Voltage
Table 2-177 • Embedded FlashROM Access Time Worst Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V Parameter tSU tHOLD tCK2Q FMAX Address Setup Time Address Hold Time Clock to Out Maximum Clock Frequency Description Std. 0.57 0.00 34.14 15 Units ns ns ns MHz
1.2 V DC Core Voltage
Table 2-178 • Embedded FlashROM Access Time Worst Commercial-Case Conditions: TJ = 70°C, VCC = 1.14 V Parameter tSU tHOLD tCK2Q FMAX Address Setup Time Address Hold Time Clock to Out Maximum Clock Frequency Description Std. 0.59 0.00 52.90 10 Units ns ns ns MHz
2 -1 1 6
A d v a n c e v 0. 5
IGLOO DC and Switching Characteristics
JTAG 1532 Characteristics
JTAG timing delays do not include JTAG I/Os. To obtain complete JTAG timing, add I/O buffer delays to the corresponding standard selected; refer to the I/O timing characteristics in the "User I/O Characteristics" section on page 2-19 for more details.
Timing Characteristics
Table 2-179 • JTAG 1532 Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V Parameter tDISU tDIHD tTMSSU tTMDHD tTCK2Q tRSTB2Q FTCKMAX tTRSTREM tTRSTREC tTRSTMPW Description Test Data Input Setup Time Test Data Input Hold Time Test Mode Select Setup Time Test Mode Select Hold Time Clock to Q (data out) Reset to Q (data out) TCK Maximum Frequency ResetB Removal Time ResetB Recovery Time ResetB Minimum Pulse Std. 1.00 2.00 1.00 2.00 8.00 25.00 15 0.58 0.00 TBD Units ns ns ns ns ns ns MHz ns ns ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. Table 2-180 • JTAG 1532 Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V Parameter tDISU tDIHD tTMSSU tTMDHD tTCK2Q tRSTB2Q FTCKMAX tTRSTREM tTRSTREC tTRSTMPW Description Test Data Input Setup Time Test Data Input Hold Time Test Mode Select Setup Time Test Mode Select Hold Time Clock to Q (data out) Reset to Q (data out) TCK Maximum Frequency ResetB Removal Time ResetB Recovery Time ResetB Minimum Pulse Std. 1.50 3.00 1.50 3.00 11.00 30.00 9.00 1.18 0.00 TBD Units ns ns ns ns ns ns MHz ns ns ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
A dv a n c e v 0. 5
2 -117
IGLOO DC and Switching Characteristics
Part Number and Revision Date
Part Number 51700095-002-4 Revised October 2008
List of Changes
The following table lists critical changes that were made in the current version of the chapter. Previous Version Advance v0.4 (August 2008) Changes in Current Version (Advance v0.5) The tables in the "Quiescent Supply Current" section were updated with values for AGL400. The tables in the "Power Consumption of Various Internal Resources" section were updated with values for AGL400. Table 2-158 · AGL400 Global Resource is new. Advance v0.3 (July 2008) 3.0 V LVCMOS wide range support data Table 2-2 · Recommended Operating Conditions 4. was added to Page 2-7 2-12 2-92 2-2 2-23 to 2-24
3.3 V LVCMOS wide range support data was added to Table 2-24 · Summary of Maximum and Minimum DC Input and Output Levels Applicable to Commercial and Industrial Conditions—Software Default Settings to Table 2-26 · Summary of Maximum and Minimum DC Input and Output Levels Applicable to Commercial and Industrial Conditions—Software Default Settings. 3.3 V LVCMOS wide range support data was added to Table 2-27 · Summary of Maximum and Minimum DC Input Levels. 3.3 V LVCMOS wide range support text was added to Table 2-49 · Minimum and Maximum DC Input and Output Levels for LVCMOS 3.3 V Wide Range. Table 2-49 · Minimum and Maximum DC Input and Output Levels for LVCMOS 3.3 V Wide Range is new. Advance v0.2 (July 2008) Advance v0.1 (January 2008) As a result of the Libero IDE v8.4 release, Actel now offers a wide range of core voltage support. The document was updated to change 1.2 V / 1.5 V to 1.2 V to 1.5 V. Tables have been updated to reflect default values in the software. The default I/O capacitance is 5 pF. Tables have been updated to include the LVCMOS 1.2 V I/O set. DDR Tables have two additional data points added to reflect both edges for Input DDR setup and hold time. The power data table has been updated to match SmartPower data rather then simulation values. AGL015 global clock delays have been added. Table 2-1 · Absolute Maximum Ratings was updated to combine the VCCI and VMV parameters in one row. The word "output" from the parameter description for VCCI and VMV, and table note 3 was added.
2-24 2-37 2-37 N/A
N/A
2-1
2 -1 1 8
A d v a n c e v 0. 5
IGLOO DC and Switching Characteristics
Previous Version Advance v0.1 (January 2008)
Changes in Current Version (Advance v0.5) Table 2-2 · Recommended Operating Conditions was updated to add references to tables notes 4, 6, 7, and 8. VMV was added to the VCCI parameter row, and table note 9 was added. In Table 2-3 · Flash Programming Limits – Retention, Storage, and Operating Temperature1, the maximum operating junction temperature was changed from 110° to 100°. VMV was removed from Table 2-4 · Overshoot and Undershoot Limits 1. The table title was modified to remove "as measured on quiet I/Os." Table note 2 was revised to remove "estimated SSO density over cycles." Table note 3 was revised to remove "refers only to overshoot/undershoot limits for simultaneous switching I/Os." The "PLL Behavior at Brownout Condition" section is new. Figure 2-2 · V2 Devices – I/O State as a Function of VCCI and VCC Voltage Levels is new. EQ 2-2 was updated. The temperature was changed to 100°C, and therefore the end result changed. The table notes for Table 2-8 · Quiescent Supply Current (IDD) Characteristics, IGLOO Flash*Freeze Mode*, Table 2-9 · Quiescent Supply Current (IDD) Characteristics, IGLOO Sleep Mode (VCC = 0 V)*, and Table 2-10 · Quiescent Supply Current (IDD) Characteristics, IGLOO Shutdown Mode (VCC, VCCI = 0 V)* were updated to remove VMV and include PDC6 and PDC7. VCCI and VJTAG were removed from the statement about IDD in the table note for Table 2-9 · Quiescent Supply Current (IDD) Characteristics, IGLOO Sleep Mode (VCC = 0 V)*. Note 2 of Table 2-11 · Quiescent Supply Current (IDD), No IGLOO Flash*Freeze Mode1 was updated to include VCCPLL. Note 4 was updated to include PDC6 and PDC7.
4
Page 2-2
2-2
2-3
2-4 2-5 2-6 2-7
2-8
Table 2-12 · Summary of I/O Input Buffer Power (per pin) – Default I/O 2-9 Software Settings, Table 2-13 · Summary of I/O Input Buffer Power (per pin) – through Default I/O Software Settings, Table 2-14 · Summary of I/O Input Buffer Power 2-10 (per pin) – Default I/O Software Settings, and Table 2-15 · Summary of I/O Output Buffer Power (per pin) – Default I/O Software Settings1 were updated to change PDC2 to PDC6 and PDC3 to PDC7. The table notes were updated to reflect that power was measured on VCCI. Table 2-19 · Different Components Contributing to the Static Power Consumption in IGLOO Devices and Table 2-21 · Different Components Contributing to the Static Power Consumption in IGLOO Device were updated to add PDC6 and PDC7, and to change the definition for PDC5 to bank quiescent power. Subtitles were added to indicate type of devices and core supply voltage. The "Total Static Power Consumption—PSTAT" section was updated to revise the calculation of PSTAT, including PDC6 and PDC7. In Table 2-18 · Different Components Contributing to Dynamic Power Consumption in IGLOO Devices, the description for PAC13 was changed from Static to Dynamic. Footnote 1 was updated to include information about PAC13. The PLL Contribution equation was changed from: PPLL = PAC13 + PAC14 * FCLKOUT to PPLL = PDC4 + PAC13 * FCLKOUT. 2-13, 2-15
2-16 2-12
2-17
A dv a n c e v 0. 5
2 -119
IGLOO DC and Switching Characteristics
Previous Version Advance v0.6 (November 2007)
Changes in Current Version (Advance v0.5) The "Timing Model" was updated to be consistent with the revised timing numbers. In Table 2-26 · Summary of Maximum and Minimum DC Input and Output Levels Applicable to Commercial and Industrial Conditions—Software Default Settings, TJ was changed to TA in notes 1 and 2. All AC Loading figures for single-ended I/O standards were changed from Datapaths at 35 pF to 5 pF. The "1.2 V LVCMOS (JESD8-12A)" section is new. This document was previously in datasheet Advance v0.7. As a result of moving to the handbook format, Actel has restarted the version numbers. The new version number is Advance v0.1.
Page 2-19 2-24
N/A 2-59 N/A
Advance v0.6 (continued)
Table 2-4 • IGLOO CCC/PLL Specification and Table 2-5 • IGLOO CCC/PLL Specification were updated. The former Table 2-16 • Maximum I/O Frequency for Single-Ended and Differential I/Os in All Banks in IGLOO Devices (maximum drive strength and high slew selected) was removed. The "During Flash*Freeze Mode" section was updated to include information about the output of the I/O to the FPGA core. Table 2-31 • Flash*Freeze Pin Location in IGLOO Family Packages (deviceindependent) was updated to add UC81 and CS281. Flash*Freeze pins were assigned for CS81, CS121, and CS196. Figure 2-40 • Flash*Freeze Mode Type 2 – Timing Diagram was updated to modify the LSICC Signal. Information regarding calculation of the quiescent supply current was added to the "Quiescent Supply Current" section. Table 3-8 • Quiescent Supply Current Flash*Freeze Mode† was updated. (IDD) Characteristics, IGLOO
2-19, 2-20 N/A
2-57 2-61
2-55 3-6 3-6 3-6 3-7 3-58 3-104 2-51 2-61 3-2
Table 3-9 • Quiescent Supply Current (IDD) Characteristics, IGLOO Sleep Mode (VCC = 0 V)† was updated. Table 3-11 • Quiescent Supply Current (IDD), No IGLOO Flash*Freeze Mode1 was updated. Table 3-115 • Minimum and Maximum DC Input and Output Levels was updated. Table 3-156 • JTAG 1532 was updated and Table 3-155 • JTAG 1532 is new. Advance v0.3 (August 2007) Advance v0.2 (July 2007) Advance v0.1 The "Power Conservation Techniques" section was updated to recommend that unused I/O signals be left floating. The CS81 and CS121 packages were added to Table 2-31 • Flash*Freeze Pin Location in IGLOO Family Packages (device-independent). The TJ parameter in Table 3-2 • Recommended Operating Conditions was changed to TA, ambient temperature, and table notes 4–6 were added.
2 -1 2 0
A d v a n c e v 0. 5
IGLOO DC and Switching Characteristics
Actel Safety Critical, Life Support, and High-Reliability Applications Policy
The Actel products described in this advance status datasheet may not have completed Actel’s qualification process. Actel may amend or enhance products during the product introduction and qualification process, resulting in changes in device functionality or performance. It is the responsibility of each customer to ensure the fitness of any Actel product (but especially a new product) for a particular purpose, including appropriateness for safety-critical, life-support, and other high-reliability applications. Consult Actel’s Terms and Conditions for specific liability exclusions relating to life-support applications. A reliability report covering all of Actel’s products is available on the Actel website at http://www.actel.com/documents/ORT_Report.pdf. Actel also offers a variety of enhanced qualification and lot acceptance screening procedures. Contact your local Actel sales office for additional reliability information.
A dv a n c e v 0. 5
2 -121
IGLOO Packaging
3 – Package Pin Assignments
81-Pin µCSP
A1 Ball Pad Corner
987654321 A B C D E F G H J
Note: This is the bottom view of the package. Figure 3-1 •
Note
For Package Manufacturing and Environmental information, visit the Resource Center at http://www.actel.com/products/solutions/package/docs.aspx.
v 1.7
3-1
Package Pin Assignments
81-Pin µCSP Pin Number A1 A2 A3 A4 A5 A6 A7 A8 A9 B1 B2 B3 B4 B5 B6 B7 B8 B9 C1 C2 C3 C4 C5 C6 C7 C8 C9 D1 D2 D3 D4 D5 D6 D7 D8 D9 AGL030 Function IO00RSB0 IO02RSB0 IO06RSB0 IO11RSB0 IO16RSB0 IO19RSB0 IO22RSB0 IO24RSB0 IO26RSB0 IO81RSB1 IO04RSB0 IO10RSB0 IO13RSB0 IO15RSB0 IO20RSB0 IO21RSB0 IO28RSB0 IO25RSB0 IO79RSB1 IO80RSB1 IO08RSB0 IO12RSB0 IO17RSB0 IO14RSB0 IO18RSB0 IO29RSB0 IO27RSB0 IO74RSB1 IO76RSB1 IO77RSB1 VCC VCCIB0 GND IO23RSB0 IO31RSB0 IO30RSB0
81-Pin µCSP Pin Number E1 E2 E3 E4 E5 E6 E7 E8 E9 F1 F2 F3 F4 F5 F6 F7 F8 F9 G1 G2 G3 G4 G5 G6 G7 G8 G9 H1 H2 H3 H4 H5 H6 H7 H8 H9 AGL030 Function GEB0/IO71RSB1 GEA0/IO72RSB1 GEC0/IO73RSB1 VCCIB1 VCC VCCIB0 GDC0/IO32RSB0 GDA0/IO33RSB0 GDB0/IO34RSB0 IO68RSB1 IO67RSB1 IO64RSB1 GND VCCIB1 IO47RSB1 IO36RSB0 IO38RSB0 IO40RSB0 IO65RSB1 IO66RSB1 IO57RSB1 IO53RSB1 IO49RSB1 IO45RSB1 IO46RSB1 VJTAG TRST IO62RSB1 FF/IO60RSB1 IO58RSB1 IO54RSB1 IO48RSB1 IO43RSB1 IO42RSB1 TDI TDO
81-Pin µCSP Pin Number J1 J2 J3 J4 J5 J6 J7 J8 J9 AGL030 Function IO63RSB1 IO61RSB1 IO59RSB1 IO56RSB1 IO52RSB1 IO44RSB1 TCK TMS VPUMP
3 -2
v1.7
IGLOO Packaging
81-Pin CSP
A1 Ball Pad Corner
987654321 A B C D E F G H J
Note: This is the bottom view of the package. Figure 3-2 •
Note
For Package Manufacturing and Environmental information, visit the Resource Center at http://www.actel.com/products/solutions/package/docs.aspx.
v1.7
3-3
Package Pin Assignments
81-Pin CSP Pin Number A1 A2 A3 A4 A5 A6 A7 A8 A9 B1 B2 B3 B4 B5 B6 B7 B8 B9 C1 C2 C3 C4 C5 C6 C7 C8 C9 D1 D2 D3 D4 D5 D6 D7 D8 D9 AGL030 Function IO00RSB0 IO02RSB0 IO06RSB0 IO11RSB0 IO16RSB0 IO19RSB0 IO22RSB0 IO24RSB0 IO26RSB0 IO81RSB1 IO04RSB0 IO10RSB0 IO13RSB0 IO15RSB0 IO20RSB0 IO21RSB0 IO28RSB0 IO25RSB0 IO79RSB1 IO80RSB1 IO08RSB0 IO12RSB0 IO17RSB0 IO14RSB0 IO18RSB0 IO29RSB0 IO27RSB0 IO74RSB1 IO76RSB1 IO77RSB1 VCC VCCIB0 GND IO23RSB0 IO31RSB0 IO30RSB0
81-Pin CSP Pin Number E1 E2 E3 E4 E5 E6 E7 E8 E9 F1 F2 F3 F4 F5 F6 F7 F8 F9 G1 G2 G3 G4 G5 G6 G7 G8 G9 H1 H2 H3 H4 H5 H6 H7 H8 H9 AGL030 Function GEB0/IO71RSB1 GEA0/IO72RSB1 GEC0/IO73RSB1 VCCIB1 VCC VCCIB0 GDC0/IO32RSB0 GDA0/IO33RSB0 GDB0/IO34RSB0 IO68RSB1 IO67RSB1 IO64RSB1 GND VCCIB1 IO47RSB1 IO36RSB0 IO38RSB0 IO40RSB0 IO65RSB1 IO66RSB1 IO57RSB1 IO53RSB1 IO49RSB1 IO44RSB1 IO46RSB1 VJTAG TRST IO62RSB1 FF/IO60RSB1 IO58RSB1 IO54RSB1 IO48RSB1 IO43RSB1 IO42RSB1 TDI TDO
81-Pin CSP Pin Number J1 J2 J3 J4 J5 J6 J7 J8 J9 AGL030 Function IO63RSB1 IO61RSB1 IO59RSB1 IO56RSB1 IO52RSB1 IO45RSB1 TCK TMS VPUMP
3 -4
v1.7
IGLOO Packaging
121-Pin CSP
11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L
Note: This is the bottom view of the package. Figure 3-3 •
Note
For Package Manufacturing and Environmental information, visit the Resource Center at http://www.actel.com/products/solutions/package/docs.aspx.
v1.7
3-5
Package Pin Assignments
121-Pin CSP Pin Number A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 D1 D2 D3 D4 D5 D6 D7 D8 AGL060 Function GNDQ IO01RSB0 GAA1/IO03RSB0 GAC1/IO07RSB0 IO15RSB0 IO13RSB0 IO17RSB0 GBB1/IO22RSB0 GBA1/IO24RSB0 GNDQ VMV0 GAA2/IO95RSB1 IO00RSB0 GAA0/IO02RSB0 GAC0/IO06RSB0 IO08RSB0 IO12RSB0 IO16RSB0 GBC1/IO20RSB0 GBB0/IO21RSB0 GBB2/IO27RSB0 GBA2/IO25RSB0 IO89RSB1 GAC2/IO91RSB1 GAB1/IO05RSB0 GAB0/IO04RSB0 IO09RSB0 IO14RSB0 GBA0/IO23RSB0 GBC0/IO19RSB0 IO26RSB0 IO28RSB0 GBC2/IO29RSB0 IO88RSB1 IO90RSB1 GAB2/IO93RSB1 IO10RSB0 IO11RSB0 IO18RSB0 IO32RSB0 IO31RSB0 D9 D10 D11 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 H1 H2 H3 H4 H5
121-Pin CSP Pin Number AGL060 Function GCA2/IO41RSB0 IO30RSB0 IO33RSB0 IO87RSB1 GFC0/IO85RSB1 IO92RSB1 IO94RSB1 VCC VCCIB0 GND GCC0/IO36RSB0 IO34RSB0 GCB1/IO37RSB0 GCC1/IO35RSB0 VCOMPLF GFB0/IO83RSB1 GFA0/IO82RSB1 GFC1/IO86RSB1 VCCIB1 VCC VCCIB0 GCB2/IO42RSB0 GCC2/IO43RSB0 GCB0/IO38RSB0 GCA1/IO39RSB0 VCCPLF GFB2/IO79RSB1 GFA1/IO81RSB1 GFB1/IO84RSB1 GND VCCIB1 VCC GDC0/IO46RSB0 GDA1/IO49RSB0 GDB0/IO48RSB0 GCA0/IO40RSB0 IO75RSB1 IO76RSB1 GFC2/IO78RSB1 GFA2/IO80RSB1 IO77RSB1 H6 H7 H8 H9 H10 H11 J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11
121-Pin CSP Pin Number AGL060 Function GEC2/IO66RSB1 IO54RSB1 GDC2/IO53RSB1 VJTAG TRST IO44RSB0 GEC1/IO74RSB1 GEC0/IO73RSB1 GEB1/IO72RSB1 GEA0/IO69RSB1 FF/GEB2/IO67RSB1 IO62RSB1 GDA2/IO51RSB1 GDB2/IO52RSB1 TDI TDO GDC1/IO45RSB0 GEB0/IO71RSB1 GEA1/IO70RSB1 GEA2/IO68RSB1 IO64RSB1 IO60RSB1 IO59RSB1 IO56RSB1 TCK TMS VPUMP GDB1/IO47RSB0 VMV1 GNDQ IO65RSB1 IO63RSB1 IO61RSB1 IO58RSB1 IO57RSB1 IO55RSB1 GNDQ GDA0/IO50RSB0 VMV1
3 -6
v1.7
IGLOO Packaging
196-Pin CSP
A1 Ball Pad Corner
14 13 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P
Note: This is the bottom view of the package. Figure 3-4 •
Note
For Package Manufacturing and Environmental information, visit the Resource Center at http://www.actel.com/products/solutions/package/docs.aspx.
v1.7
3-7
Package Pin Assignments
196-Pin CSP Pin Number A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 C1 C2 C3 C4 C5 C6 C7 C8 AGL125 Function GND GAA0/IO00RSB0 GAC0/IO04RSB0 GAC1/IO05RSB0 IO09RSB0 IO15RSB0 IO18RSB0 IO22RSB0 IO27RSB0 GBC0/IO35RSB0 GBB0/IO37RSB0 GBB1/IO38RSB0 GBA1/IO40RSB0 GND VCCIB1 VMV0 GAA1/IO01RSB0 GAB1/IO03RSB0 GND IO16RSB0 IO20RSB0 IO24RSB0 IO28RSB0 GND GBC1/IO36RSB0 GBA0/IO39RSB0 GBA2/IO41RSB0 GBB2/IO43RSB0 GAC2/IO128RSB1 GAB2/IO130RSB1 GNDQ VCCIB0 GAB0/IO02RSB0 IO14RSB0 VCCIB0 NC
196-Pin CSP Pin Number C9 C10 C11 C12 C13 C14 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 F1 F2 AGL125 Function IO23RSB0 IO29RSB0 VCCIB0 IO42RSB0 GNDQ IO44RSB0 IO127RSB1 IO129RSB1 GAA2/IO132RSB1 IO126RSB1 IO06RSB0 IO13RSB0 IO19RSB0 IO21RSB0 IO26RSB0 IO31RSB0 IO30RSB0 VMV0 IO46RSB0 GBC2/IO45RSB0 IO125RSB1 GND IO131RSB1 VCCIB1 NC IO08RSB0 IO17RSB0 IO12RSB0 IO11RSB0 NC VCCIB0 IO32RSB0 GND IO34RSB0 IO124RSB1 IO114RSB1
196-Pin CSP Pin Number F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 G13 G14 H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 AGL125 Function IO113RSB1 IO112RSB1 IO111RSB1 NC VCC VCC NC IO07RSB0 IO25RSB0 IO10RSB0 IO33RSB0 IO47RSB0 GFB1/IO121RSB1 GFA0/IO119RSB1 GFA2/IO117RSB1 VCOMPLF GFC0/IO122RSB1 VCC GND GND VCC GCC0/IO52RSB0 GCB1/IO53RSB0 GCA0/IO56RSB0 IO48RSB0 GCC2/IO59RSB0 GFB0/IO120RSB1 GFA1/IO118RSB1 VCCPLF GFB2/IO116RSB1 GFC1/IO123RSB1 VCC GND GND VCC GCC1/IO51RSB0
3 -8
v1.7
IGLOO Packaging
196-Pin CSP Pin Number H11 H12 H13 H14 J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 J13 J14 K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 K12 K13 K14 L1 L2 L3 L4 AGL125 Function GCB0/IO54RSB0 GCA1/IO55RSB0 IO49RSB0 GCA2/IO57RSB0 GFC2/IO115RSB1 IO110RSB1 IO94RSB1 IO93RSB1 IO89RSB1 NC VCC VCC NC IO60RSB0 GCB2/IO58RSB0 IO50RSB0 GDC1/IO61RSB0 GDC0/IO62RSB0 IO99RSB1 GND IO95RSB1 VCCIB1 NC IO86RSB1 IO80RSB1 IO74RSB1 IO72RSB1 NC VCCIB0 GDA1/IO65RSB0 GND GDB1/IO63RSB0 GEB1/IO107RSB1 GEC1/IO109RSB1 GEC0/IO108RSB1 IO96RSB1
196-Pin CSP Pin Number L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 M12 M13 M14 N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 N12 AGL125 Function IO91RSB1 IO90RSB1 IO83RSB1 IO81RSB1 IO71RSB1 IO70RSB1 VPUMP VJTAG GDA0/IO66RSB0 GDB0/IO64RSB0 GEB0/IO106RSB1 GEA1/IO105RSB1 GNDQ VCCIB1 IO92RSB1 IO88RSB1 NC VCCIB1 IO76RSB1 GDB2/IO68RSB1 VCCIB1 VMV1 TRST VCCIB0 GEA0/IO104RSB1 VMV1 GEC2/IO101RSB1 IO100RSB1 GND IO87RSB1 IO82RSB1 IO78RSB1 IO73RSB1 GND TCK TDI
196-Pin CSP Pin Number N13 N14 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 AGL125 Function GNDQ TDO GND GEA2/IO103RSB1 FF/GEB2/IO102RSB1 IO98RSB1 IO97RSB1 IO85RSB1 IO84RSB1 IO79RSB1 IO77RSB1 IO75RSB1 GDC2/IO69RSB1 GDA2/IO67RSB1 TMS GND
v1.7
3-9
Package Pin Assignments
196-Pin CSP Pin Number A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 C1 C2 C3 C4 C5 C6 C7 C8 AGL250 Function GND GAA0/IO00RSB0 GAC0/IO04RSB0 GAC1/IO05RSB0 IO10RSB0 IO13RSB0 IO17RSB0 IO19RSB0 IO23RSB0 GBC0/IO35RSB0 GBB0/IO37RSB0 GBB1/IO38RSB0 GBA1/IO40RSB0 GND VCCIB3 VMV0 GAA1/IO01RSB0 GAB1/IO03RSB0 GND IO12RSB0 IO16RSB0 IO22RSB0 IO24RSB0 GND GBC1/IO36RSB0 GBA0/IO39RSB0 GBA2/IO41PPB1 GBB2/IO42PDB1 GAC2/IO116UDB3 GAB2/IO117UDB3 GNDQ VCCIB0 GAB0/IO02RSB0 IO11RSB0 VCCIB0 IO20RSB0
196-Pin CSP Pin Number C9 C10 C11 C12 C13 C14 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 F1 F2 AGL250 Function IO30RSB0 IO33RSB0 VCCIB0 IO41NPB1 GNDQ IO42NDB1 IO116VDB3 IO117VDB3 GAA2/IO118UDB3 IO113PPB3 IO08RSB0 IO14RSB0 IO15RSB0 IO18RSB0 IO25RSB0 IO32RSB0 IO44PPB1 VMV1 IO43NDB1 GBC2/IO43PDB1 IO112PDB3 GND IO118VDB3 VCCIB3 IO114USB3 IO07RSB0 IO09RSB0 IO21RSB0 IO31RSB0 IO34RSB0 VCCIB1 IO44NPB1 GND IO45PDB1 IO112NDB3 IO107NPB3
196-Pin CSP Pin Number F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 G13 G14 H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 AGL250 Function IO111PDB3 IO111NDB3 IO113NPB3 IO06RSB0 VCC VCC IO28RSB0 IO54PDB1 IO54NDB1 IO47NDB1 IO47PDB1 IO45NDB1 GFB1/IO109PDB3 GFA0/IO108NDB3 GFA2/IO107PPB3 VCOMPLF GFC0/IO110NDB3 VCC GND GND VCC GCC0/IO48NDB1 GCB1/IO49PDB1 GCA0/IO50NDB1 IO53NDB1 GCC2/IO53PDB1 GFB0/IO109NDB3 GFA1/IO108PDB3 VCCPLF GFB2/IO106PPB3 GFC1/IO110PDB3 VCC GND GND VCC GCC1/IO48PDB1
3 -1 0
v1.7
IGLOO Packaging
196-Pin CSP Pin Number H11 H12 H13 H14 J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 J13 J14 K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 K12 K13 K14 L1 L2 L3 L4 AGL250 Function GCB0/IO49NDB1 GCA1/IO50PDB1 IO51NDB1 GCA2/IO51PDB1 GFC2/IO105PDB3 IO104PPB3 IO106NPB3 IO103PDB3 IO103NDB3 IO80RSB2 VCC VCC IO64RSB2 IO56PDB1 GCB2/IO52PDB1 IO52NDB1 GDC1/IO58UDB1 GDC0/IO58VDB1 IO105NDB3 GND IO104NPB3 VCCIB3 IO101PPB3 IO91RSB2 IO81RSB2 IO73RSB2 IO77RSB2 IO56NDB1 VCCIB1 GDA1/IO60UPB1 GND GDB1/IO59UDB1 GEB1/IO99PDB3 GEC1/IO100PDB3 GEC0/IO100NDB3 IO101NPB3
196-Pin CSP Pin Number L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 M12 M13 M14 N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 N12 AGL250 Function IO89RSB2 IO92RSB2 IO75RSB2 IO66RSB2 IO65RSB2 IO71RSB2 VPUMP VJTAG GDA0/IO60VPB1 GDB0/IO59VDB1 GEB0/IO99NDB3 GEA1/IO98PPB3 GNDQ VCCIB2 IO88RSB2 IO87RSB2 IO82RSB2 VCCIB2 IO67RSB2 GDB2/IO62RSB2 VCCIB2 VMV2 TRST VCCIB1 GEA0/IO98NPB3 VMV3 GEC2/IO95RSB2 IO94RSB2 GND IO86RSB2 IO78RSB2 IO74RSB2 IO69RSB2 GND TCK TDI
196-Pin CSP Pin Number N13 N14 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 AGL250 Function GNDQ TDO GND GEA2/IO97RSB2 GEB2/IO96RSB2 IO90RSB2 IO85RSB2 IO83RSB2 IO79RSB2 IO76RSB2 IO72RSB2 IO68RSB2 GDC2/IO63RSB2 GDA2/IO61RSB2 TMS GND
v1.7
3 - 11
Package Pin Assignments
196-pin CSP Pin Number A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 B1 B2 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 C1 C2 C3 C4 C5 C6 C7 AGL400 Function GND GAA0/IO00RSB0 GAC0/IO04RSB0 GAC1/IO05RSB0 IO14RSB0 IO18RSB0 IO26RSB0 IO29RSB0 IO36RSB0 GBC0/IO54RSB0 GBB0/IO56RSB0 GBB1/IO57RSB0 GBA1/IO59RSB0 GND VCCIB3 VMV0 VMV0 GAA1/IO01RSB0 GAB1/IO03RSB0 GND IO17RSB0 IO25RSB0 IO34RSB0 IO39RSB0 GND GBC1/IO55RSB0 GBA0/IO58RSB0 GBA2/IO60PPB1 GBB2/IO61PDB1 GAC2/IO153UDB3 GAB2/IO154UDB3 GNDQ VCCIB0 GAB0/IO02RSB0 IO15RSB0 VCCIB0
196-pin CSP Pin Number C8 C9 C10 C11 C12 C13 C14 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 F1 AGL400 Function IO31RSB0 IO44RSB0 IO49RSB0 VCCIB0 IO60NPB1 GNDQ IO61NDB1 IO153VDB3 IO154VDB3 GAA2/IO155UDB3 IO150PPB3 IO11RSB0 IO20RSB0 IO23RSB0 IO28RSB0 IO41RSB0 IO47RSB0 IO63PPB1 VMV1 IO62NDB1 GBC2/IO62PDB1 IO149PDB3 GND IO155VDB3 VCCIB3 IO151USB3 IO09RSB0 IO12RSB0 IO32RSB0 IO46RSB0 IO51RSB0 VCCIB1 IO63NPB1 GND IO64PDB1 IO149NDB3
196-pin CSP Pin Number F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 G13 G14 H1 H2 H3 H4 H5 H6 H7 H8 H9 AGL400 Function IO144NPB3 IO148PDB3 IO148NDB3 IO150NPB3 IO07RSB0 VCC VCC IO43RSB0 IO73PDB1 IO73NDB1 IO66NDB1 IO66PDB1 IO64NDB1 GFB1/IO146PDB3 GFA0/IO145NDB3 GFA2/IO144PPB3 VCOMPLF GFC0/IO147NDB3 VCC GND GND VCC GCC0/IO67NDB1 GCB1/IO68PDB1 GCA0/IO69NDB1 IO72NDB1 GCC2/IO72PDB1 GFB0/IO146NDB3 GFA1/IO145PDB3 VCCPLF GFB2/IO143PPB3 GFC1/IO147PDB3 VCC GND GND VCC
3 -1 2
v1.7
IGLOO Packaging
196-pin CSP Pin Number H10 H11 H12 H13 H14 J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 J13 J14 K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 K12 K13 K14 L1 L2 L3 AGL400 Function GCC1/IO67PDB1 GCB0/IO68NDB1 GCA1/IO69PDB1 IO70NDB1 GCA2/IO70PDB1 GFC2/IO142PDB3 IO141PPB3 IO143NPB3 IO140PDB3 IO140NDB3 IO109RSB2 VCC VCC IO84RSB2 IO75PDB1 GCB2/IO71PDB1 IO71NDB1 GDC1/IO77UDB1 GDC0/IO77VDB1 IO142NDB3 GND IO141NPB3 VCCIB3 IO138PPB3 IO125RSB2 IO110RSB2 IO98RSB2 IO104RSB2 IO75NDB1 VCCIB1 GDA1/IO79UPB1 GND GDB1/IO78UDB1 GEB1/IO136PDB3 GEC1/IO137PDB3 GEC0/IO137NDB3
196-pin CSP Pin Number L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 M12 M12 M13 M14 N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 AGL400 Function IO138NPB3 IO122RSB2 IO128RSB2 IO101RSB2 IO88RSB2 IO86RSB2 IO94RSB2 VPUMP VJTAG GDA0/IO79VPB1 GDB0/IO78VDB1 GEB0/IO136NDB3 GEA1/IO135PPB3 GNDQ VCCIB2 IO120RSB2 IO119RSB2 IO112RSB2 VCCIB2 IO89RSB2 GDB2/IO81RSB2 VCCIB2 VMV2 VMV2 TRST VCCIB1 GEA0/IO135NPB3 VMV3 GEC2/IO132RSB2 IO130RSB2 GND IO117RSB2 IO106RSB2 IO100RSB2 IO92RSB2 GND
196-pin CSP Pin Number N11 N12 N13 N14 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 AGL400 Function TCK TDI GNDQ TDO GND GEA2/IO134RSB2 FF/GEB2/IO133RSB2 IO123RSB2 IO116RSB2 IO114RSB2 IO107RSB2 IO103RSB2 IO95RSB2 IO91RSB2 GDC2/IO82RSB2 GDA2/IO80RSB2 TMS GND
v1.7
3 - 13
Package Pin Assignments
281-Pin CSP
19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P R T U V W
Note: This is the bottom view of the package. Figure 3-5 •
Note
For Package Manufacturing and Environmental information, visit the Resource Center at http://www.actel.com/products/solutions/package/docs.aspx.
3 -1 4
v1.7
IGLOO Packaging
281-Pin CSP Pin Number A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 AGL600 Function GND GAB0/IO02RSB0 GAC1/IO05RSB0 IO07RSB0 IO10RSB0 IO14RSB0 IO18RSB0 IO21RSB0 IO22RSB0 VCCIB0 IO33RSB0 IO40RSB0 IO37RSB0 IO48RSB0 IO51RSB0 IO53RSB0 GBC1/IO55RSB0 GBA0/IO58RSB0 GND GAA2/IO174PPB3 VCCIB0 GAB1/IO03RSB0 GAC0/IO04RSB0 IO06RSB0 GND IO15RSB0 IO20RSB0 IO23RSB0 IO24RSB0 IO36RSB0 IO35RSB0 IO44RSB0 GND IO52RSB0 GBC0/IO54RSB0 GBA1/IO59RSB0
281-Pin CSP Pin Number B18 B19 C1 C2 C6 C14 C18 C19 D1 D2 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D18 D19 E1 E2 E4 E5 E6 E7 E8 E9 E10 E11 E12 AGL600 Function VCCIB1 IO61NDB1 GAB2/IO173PPB3 IO174NPB3 IO12RSB0 IO50RSB0 IO60NPB1 GBB2/IO61PDB1 IO170PPB3 IO172NPB3 GAA0/IO00RSB0 GAA1/IO01RSB0 IO09RSB0 IO16RSB0 IO19RSB0 IO26RSB0 GND IO34RSB0 IO45RSB0 IO49RSB0 IO47RSB0 GBB0/IO56RSB0 GBA2/IO60PPB1 GBC2/IO62PPB1 IO66NPB1 IO169NPB3 IO171PPB3 IO171NPB3 IO08RSB0 IO11RSB0 IO13RSB0 IO17RSB0 IO25RSB0 IO30RSB0 IO41RSB0 IO42RSB0
281-Pin CSP Pin Number E13 E14 E15 E16 E18 E19 F1 F2 F3 F4 F5 F15 F16 F17 F18 F19 G1 G2 G4 G5 G7 G8 G9 G10 G11 G12 G13 G15 G16 G18 G19 H1 H2 H4 H5 H7 AGL600 Function IO46RSB0 GBB1/IO57RSB0 IO62NPB1 IO63PPB1 IO64PPB1 IO65NPB1 IO168NPB3 GND IO169PPB3 IO170NPB3 IO173NPB3 IO63NPB1 IO65PPB1 IO64NPB1 GND IO68PPB1 IO167NPB3 IO165NDB3 IO168PPB3 IO167PPB3 GAC2/IO172PPB3 VCCIB0 IO28RSB0 IO32RSB0 IO43RSB0 VCCIB0 IO66PPB1 IO67NDB1 IO67PDB1 GCC0/IO69NPB1 GCB1/IO70PPB1 GFB0/IO163NPB3 IO165PDB3 GFC1/IO164PPB3 GFB1/IO163PPB3 VCCIB3
v1.7
3 - 15
Package Pin Assignments
281-Pin CSP Pin Number H8 H9 H10 H11 H12 H13 H15 H16 H18 H19 J1 J2 J4 J5 J7 J8 J9 J10 J11 J12 J13 J15 J16 J18 J19 K1 K2 K4 K5 K7 K8 K9 K10 K11 K12 K13 AGL600 Function VCC VCCIB0 VCC VCCIB0 VCC VCCIB1 IO68NPB1 GCB0/IO70NPB1 GCA1/IO71PPB1 GCA2/IO72PPB1 VCOMPLF GFA0/IO162NDB3 VCCPLF GFC0/IO164NPB3 GFA2/IO161PDB3 VCCIB3 GND GND GND VCCIB1 GCC1/IO69PPB1 GCA0/IO71NPB1 GCB2/IO73PPB1 IO72NPB1 IO75PSB1 VCCIB3 GFA1/IO162PDB3 GND IO159NPB3 IO161NDB3 VCC GND GND GND VCC GCC2/IO74PPB1
281-Pin CSP Pin Number K15 K16 K18 K19 L1 L2 L4 L5 L7 L8 L9 L10 L11 L12 L13 L15 L16 L18 L19 M1 M2 M4 M5 M7 M8 M9 M10 M11 M12 M13 M15 M16 M18 M19 N1 N2 AGL600 Function IO73NPB1 GND IO74NPB1 VCCIB1 GFB2/IO160PDB3 IO160NDB3 GFC2/IO159PPB3 IO153PPB3 IO153NPB3 VCCIB3 GND GND GND VCCIB1 IO76PPB1 IO76NPB1 IO77PPB1 IO78NPB1 IO77NPB1 IO158PDB3 IO158NDB3 IO154NPB3 IO152PPB3 VCCIB3 VCC VCCIB2 VCC VCCIB2 VCC VCCIB1 IO79NPB1 IO81NPB1 IO79PPB1 IO78PPB1 IO154PPB3 IO152NPB3
281-Pin CSP Pin Number N4 N5 N7 N8 N9 N10 N11 N12 N13 N15 N16 N18 N19 P1 P2 P3 P4 P5 P15 P16 P17 P18 P19 R1 R2 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 AGL600 Function IO150PPB3 IO148NPB3 GEA2/IO143RSB2 VCCIB2 IO117RSB2 IO115RSB2 IO114RSB2 VCCIB2 VPUMP IO82PPB1 IO85PPB1 IO82NPB1 IO81PPB1 IO151PDB3 GND IO151NDB3 IO149PPB3 GEA0/IO144NPB3 IO83NDB1 IO83PDB1 GDC1/IO86PPB1 GND IO85NPB1 IO150NPB3 IO149NPB3 GEC1/IO146PPB3 GEB1/IO145PPB3 IO138RSB2 IO127RSB2 IO123RSB2 IO118RSB2 IO111RSB2 IO106RSB2 IO103RSB2 IO97RSB2 IO95RSB2
3 -1 6
v1.7
IGLOO Packaging
281-Pin CSP Pin Number R15 R16 R18 R19 T1 T2 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T18 T19 U1 U2 U6 U14 U18 U19 V1 V2 V3 V4 V5 V6 V7 V8 V9 AGL600 Function IO94RSB2 GDA1/IO88PPB1 GDB0/IO87NPB1 GDC0/IO86NPB1 IO148PPB3 GEC0/IO146NPB3 GEB0/IO145NPB3 IO132RSB2 IO136RSB2 IO130RSB2 IO126RSB2 IO120RSB2 GND IO113RSB2 IO104RSB2 IO101RSB2 IO98RSB2 GDC2/IO91RSB2 TMS VJTAG GDB1/IO87PPB1 IO147PDB3 GEA1/IO144PPB3 IO131RSB2 IO99RSB2 TRST GDA0/IO88NPB1 IO147NDB3 VCCIB3 GEC2/IO141RSB2 IO140RSB2 IO135RSB2 GND IO125RSB2 IO122RSB2 IO116RSB2
281-Pin CSP Pin Number V10 V11 V12 V13 V14 V15 V16 V17 V18 V19 W1 W2 W3 W4 W5 W6 W7 W8 W9 W10 W11 W12 W13 W14 W15 W16 W17 W18 W19 AGL600 Function IO112RSB2 IO110RSB2 IO108RSB2 IO102RSB2 GND IO93RSB2 GDA2/IO89RSB2 TDI VCCIB2 TDO GND FF/GEB2/IO142RSB2 IO139RSB2 IO137RSB2 IO134RSB2 IO133RSB2 IO128RSB2 IO124RSB2 IO119RSB2 VCCIB2 IO109RSB2 IO107RSB2 IO105RSB2 IO100RSB2 IO96RSB2 IO92RSB2 GDB2/IO90RSB2 TCK GND
v1.7
3 - 17
Package Pin Assignments
281-Pin CSP Pin Number A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 AGL1000 Function GND GAB0/IO02RSB0 GAC1/IO05RSB0 IO13RSB0 IO11RSB0 IO16RSB0 IO20RSB0 IO24RSB0 IO29RSB0 VCCIB0 IO39RSB0 IO45RSB0 IO48RSB0 IO58RSB0 IO61RSB0 IO62RSB0 GBC1/IO73RSB0 GBA0/IO76RSB0 GND GAA2/IO225PPB3 VCCIB0 GAB1/IO03RSB0 GAC0/IO04RSB0 IO12RSB0 GND IO21RSB0 IO26RSB0 IO34RSB0 IO35RSB0 IO36RSB0 IO46RSB0 IO52RSB0 GND IO59RSB0 GBC0/IO72RSB0 GBA1/IO77RSB0
281-Pin CSP Pin Number B18 B19 C1 C2 C6 C14 C18 C19 D1 D2 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D18 D19 E1 E2 E4 E5 E6 E7 E8 E9 E10 E11 E12 AGL1000 Function VCCIB1 IO79NDB1 GAB2/IO224PPB3 IO225NPB3 IO18RSB0 IO63RSB0 IO78NPB1 GBB2/IO79PDB1 IO219PPB3 IO223NPB3 GAA0/IO00RSB0 GAA1/IO01RSB0 IO15RSB0 IO19RSB0 IO27RSB0 IO32RSB0 GND IO38RSB0 IO44RSB0 IO47RSB0 IO60RSB0 GBB0/IO74RSB0 GBA2/IO78PPB1 GBC2/IO80PPB1 IO88NPB1 IO217NPB3 IO221PPB3 IO221NPB3 IO10RSB0 IO14RSB0 IO25RSB0 IO28RSB0 IO31RSB0 IO33RSB0 IO42RSB0 IO49RSB0
281-Pin CSP Pin Number E13 E14 E15 E16 E18 E19 F1 F2 F3 F4 F5 F15 F16 F17 F18 F19 G1 G2 G4 G5 G7 G8 G9 G10 G11 G12 G13 G15 G16 G18 G19 H1 H2 H4 H5 H7 AGL1000 Function IO53RSB0 GBB1/IO75RSB0 IO80NPB1 IO85PPB1 IO83PPB1 IO84NPB1 IO214NPB3 GND IO217PPB3 IO219NPB3 IO224NPB3 IO85NPB1 IO84PPB1 IO83NPB1 GND IO90PPB1 IO212NPB3 IO211NDB3 IO214PPB3 IO212PPB3 GAC2/IO223PPB3 VCCIB0 IO30RSB0 IO37RSB0 IO43RSB0 VCCIB0 IO88PPB1 IO89NDB1 IO89PDB1 GCC0/IO91NPB1 GCB1/IO92PPB1 GFB0/IO208NPB3 IO211PDB3 GFC1/IO209PPB3 GFB1/IO208PPB3 VCCIB3
3 -1 8
v1.7
IGLOO Packaging
281-Pin CSP Pin Number H8 H9 H10 H11 H12 H13 H15 H16 H18 H19 J1 J2 J4 J5 J7 J8 J9 J10 J11 J12 J13 J15 J16 J18 J19 K1 K2 K4 K5 K7 K8 K9 K10 K11 K12 K13 AGL1000 Function VCC VCCIB0 VCC VCCIB0 VCC VCCIB1 IO90NPB1 GCB0/IO92NPB1 GCA1/IO93PPB1 GCA2/IO94PPB1 VCOMPLF GFA0/IO207NDB3 VCCPLF GFC0/IO209NPB3 GFA2/IO206PDB3 VCCIB3 GND GND GND VCCIB1 GCC1/IO91PPB1 GCA0/IO93NPB1 GCB2/IO95PPB1 IO94NPB1 IO102PSB1 VCCIB3 GFA1/IO207PDB3 GND IO204NPB3 IO206NDB3 VCC GND GND GND VCC GCC2/IO96PPB1
281-Pin CSP Pin Number K15 K16 K18 K19 L1 L2 L4 L5 L7 L8 L9 L10 L11 L12 L13 L15 L16 L18 L19 M1 M2 M4 M5 M7 M8 M9 M10 M11 M12 M13 M15 M16 M18 M19 N1 N2 AGL1000 Function IO95NPB1 GND IO96NPB1 VCCIB1 GFB2/IO205PDB3 IO205NDB3 GFC2/IO204PPB3 IO203PPB3 IO203NPB3 VCCIB3 GND GND GND VCCIB1 IO103PPB1 IO103NPB1 IO97PPB1 IO98NPB1 IO97NPB1 IO202PDB3 IO202NDB3 IO201NPB3 IO198PPB3 VCCIB3 VCC VCCIB2 VCC VCCIB2 VCC VCCIB1 IO104NPB1 IO100NPB1 IO104PPB1 IO98PPB1 IO201PPB3 IO198NPB3
281-Pin CSP Pin Number N4 N5 N7 N8 N9 N10 N11 N12 N13 N15 N16 N18 N19 P1 P2 P3 P4 P5 P15 P16 P17 P18 P19 R1 R2 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 AGL1000 Function IO196PPB3 IO197NPB3 GEA2/IO187RSB2 VCCIB2 IO155RSB2 IO154RSB2 IO150RSB2 VCCIB2 VPUMP IO107PPB1 IO105PPB1 IO107NPB1 IO100PPB1 IO195PDB3 GND IO195NDB3 IO194PPB3 GEA0/IO188NPB3 IO108NDB1 IO108PDB1 GDC1/IO111PPB1 GND IO105NPB1 IO196NPB3 IO194NPB3 GEC1/IO190PPB3 GEB1/IO189PPB3 IO184RSB2 IO173RSB2 IO168RSB2 IO160RSB2 IO151RSB2 IO141RSB2 IO136RSB2 IO127RSB2 IO124RSB2
v1.7
3 - 19
Package Pin Assignments
281-Pin CSP Pin Number R15 R16 R18 R19 T1 T2 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T18 T19 U1 U2 U6 U14 U18 U19 V1 V2 V3 V4 V5 V6 V7 V8 V9 AGL1000 Function IO122RSB2 GDA1/IO113PPB1 GDB0/IO112NPB1 GDC0/IO111NPB1 IO197PPB3 GEC0/IO190NPB3 GEB0/IO189NPB3 IO181RSB2 IO172RSB2 IO171RSB2 IO156RSB2 IO159RSB2 GND IO139RSB2 IO138RSB2 IO129RSB2 IO123RSB2 GDC2/IO116RSB2 TMS VJTAG GDB1/IO112PPB1 IO193PDB3 GEA1/IO188PPB3 IO167RSB2 IO128RSB2 TRST GDA0/IO113NPB1 IO193NDB3 VCCIB3 GEC2/IO185RSB2 IO182RSB2 IO175RSB2 GND IO161RSB2 IO143RSB2 IO146RSB2
281-Pin CSP Pin Number V10 V11 V12 V13 V14 V15 V16 V17 V18 V19 W1 W2 W3 W4 W5 W6 W7 W8 W9 W10 W11 W12 W13 W14 W15 W16 W17 W18 W19 AGL1000 Function IO145RSB2 IO144RSB2 IO134RSB2 IO133RSB2 GND IO119RSB2 GDA2/IO114RSB2 TDI VCCIB2 TDO GND FF/GEB2/IO186RSB2 IO183RSB2 IO176RSB2 IO170RSB2 IO162RSB2 IO157RSB2 IO152RSB2 IO149RSB2 VCCIB2 IO140RSB2 IO135RSB2 IO130RSB2 IO125RSB2 IO120RSB2 IO118RSB2 GDB2/IO115RSB2 TCK GND
3 -2 0
v1.7
IGLOO Packaging
48-Pin QFN
Pin 1 48 1
Notes: 1. This is the bottom view of the package. 2. The die attach paddle center of the package is tied to ground (GND). Figure 3-6 •
Note
For Package Manufacturing and Environmental information, visit the Resource Center at http://www.actel.com/products/solutions/package/docs.aspx.
v1.7
3 - 21
Package Pin Assignments
48-Pin QFP Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 AGL030 Function IO82RSB1 GEC0/IO73RSB1 GEA0/IO72RSB1 GEB0/IO71RSB1 GND VCCIB1 IO68RSB1 IO67RSB1 IO66RSB1 IO65RSB1 IO64RSB1 IO62RSB1 IO61RSB1 FF/IO60RSB1 IO57RSB1 IO55RSB1 IO53RSB1 VCC VCCIB1 IO46RSB1 IO42RSB1 TCK TDI TMS VPUMP TDO TRST VJTAG IO38RSB0 GDB0/IO34RSB0 GDA0/IO33RSB0 GDC0/IO32RSB0 VCCIB0 GND VCC IO25RSB0
48-Pin QFP Pin Number 37 38 39 40 41 42 43 44 45 46 47 48 AGL030 Function IO24RSB0 IO22RSB0 IO20RSB0 IO18RSB0 IO16RSB0 IO14RSB0 IO10RSB0 IO08RSB0 IO06RSB0 IO04RSB0 IO02RSB0 IO00RSB0
3 -2 2
v1.7
IGLOO Packaging
68-Pin QFN
Pin A1 Mark
68 1
Notes: 1. This is the bottom view of the package. 2. The die attach paddle center of the package is tied to ground (GND). Figure 3-7 •
Note
For Package Manufacturing and Environmental information, visit the Resource Center at http://www.actel.com/products/solutions/package/docs.aspx.
v1.7
3 - 23
Package Pin Assignments
68-Pin QFN Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 AGL015 Function IO82RSB1 IO80RSB1 IO78RSB1 IO76RSB1 GEC0/IO73RSB1 GEA0/IO72RSB1 GEB0/IO71RSB1 VCC GND VCCIB1 IO68RSB1 IO67RSB1 IO66RSB1 IO65RSB1 IO64RSB1 IO63RSB1 IO62RSB1 FF/IO60RSB1 IO58RSB1 IO56RSB1 IO54RSB1 IO52RSB1 IO51RSB1 VCC GND VCCIB1 IO50RSB1 IO48RSB1 IO46RSB1 IO44RSB1 IO42RSB1 TCK TDI TMS VPUMP TDO
68-Pin QFN Pin Number 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 AGL015 Function TRST VJTAG IO40RSB0 IO37RSB0 GDB0/IO34RSB0 GDA0/IO33RSB0 GDC0/IO32RSB0 VCCIB0 GND VCC IO31RSB0 IO29RSB0 IO28RSB0 IO27RSB0 IO25RSB0 IO24RSB0 IO22RSB0 IO21RSB0 IO19RSB0 IO17RSB0 IO15RSB0 IO14RSB0 VCCIB0 GND VCC IO12RSB0 IO10RSB0 IO08RSB0 IO06RSB0 IO04RSB0 IO02RSB0 IO00RSB0
3 -2 4
v1.7
IGLOO Packaging
68-Pin QFN Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 AGL030 Function IO82RSB1 IO80RSB1 IO78RSB1 IO76RSB1 GEC0/IO73RSB1 GEA0/IO72RSB1 GEB0/IO71RSB1 VCC GND VCCIB1 IO68RSB1 IO67RSB1 IO66RSB1 IO65RSB1 IO64RSB1 IO63RSB1 IO62RSB1 FF/IO60RSB1 IO58RSB1 IO56RSB1 IO54RSB1 IO52RSB1 IO51RSB1 VCC GND VCCIB1 IO50RSB1 IO48RSB1 IO46RSB1 IO44RSB1 IO42RSB1 TCK TDI TMS VPUMP TDO
68-Pin QFN Pin Number 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 AGL030 Function TRST VJTAG IO40RSB0 IO37RSB0 GDB0/IO34RSB0 GDA0/IO33RSB0 GDC0/IO32RSB0 VCCIB0 GND VCC IO31RSB0 IO29RSB0 IO28RSB0 IO27RSB0 IO25RSB0 IO24RSB0 IO22RSB0 IO21RSB0 IO19RSB0 IO17RSB0 IO15RSB0 IO14RSB0 VCCIB0 GND VCC IO12RSB0 IO10RSB0 IO08RSB0 IO06RSB0 IO04RSB0 IO02RSB0 IO00RSB0
v1.7
3 - 25
Package Pin Assignments
132-Pin QFN
A37 B34 C31 D4 A36 B33 C30 A48 B44 C40 Pin A1Mark D1 A1 B1
C1
C21 B23 A25 D3
C10 B11 A12 D2 Optional Corner Pad (4x)
C20 B22 A24
Notes: 1. This is the bottom view of the package.
C11 B12 A13
2. The die attach paddle center of the package is tied to ground (GND). Figure 3-8 •
Note
For Package Manufacturing and Environmental information, visit the Resource Center at http://www.actel.com/products/solutions/package/docs.aspx.
3 -2 6
v1.7
IGLOO Packaging
132-Pin QFN Pin Number A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 A33 A34 A35 A36 AGL030 Function IO80RSB1 IO77RSB1 NC IO76RSB1 GEC0/IO73RSB1 NC GEB0/IO71RSB1 IO69RSB1 NC VCC IO67RSB1 IO64RSB1 IO59RSB1 IO56RSB1 NC IO55RSB1 IO53RSB1 VCC IO50RSB1 IO48RSB1 IO45RSB1 IO44RSB1 IO43RSB1 TDI TRST IO40RSB0 NC IO39RSB0 IO38RSB0 IO36RSB0 IO35RSB0 GDC0/IO32RSB0 NC VCC IO30RSB0 IO27RSB0
132-Pin QFN Pin Number A37 A38 A39 A40 A41 A42 A43 A44 A45 A46 A47 A48 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 AGL030 Function IO22RSB0 IO19RSB0 NC IO18RSB0 IO16RSB0 IO14RSB0 VCC IO11RSB0 IO08RSB0 IO06RSB0 IO05RSB0 IO02RSB0 IO81RSB1 IO78RSB1 GND IO75RSB1 NC GND IO70RSB1 NC GND IO66RSB1 IO63RSB1 FF/IO60RSB1 IO57RSB1 GND IO54RSB1 IO52RSB1 GND IO49RSB1 IO46RSB1 GND IO42RSB1 TMS TDO IO41RSB0
132-Pin QFN Pin Number B25 B26 B27 B28 B29 B30 B31 B32 B33 B34 B35 B36 B37 B38 B39 B40 B41 B42 B43 B44 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 AGL030 Function GND NC IO37RSB0 GND GDA0/IO33RSB0 NC GND IO29RSB0 IO26RSB0 IO23RSB0 IO20RSB0 GND IO17RSB0 IO15RSB0 GND IO12RSB0 IO09RSB0 GND IO04RSB0 IO01RSB0 IO82RSB1 IO79RSB1 NC IO74RSB1 GEA0/IO72RSB1 NC NC VCCIB1 IO65RSB1 IO62RSB1 IO61RSB1 IO58RSB1 NC NC IO51RSB1 VCCIB1
v1.7
3 - 27
Package Pin Assignments
132-Pin QFN Pin Number C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 C27 C28 C29 C30 C31 C32 C33 C34 C35 C36 C37 C38 C39 C40 D1 D2 D3 D4 AGL030 Function IO47RSB1 NC TCK NC VPUMP VJTAG NC NC NC GDB0/IO34RSB0 NC VCCIB0 IO28RSB0 IO25RSB0 IO24RSB0 IO21RSB0 NC NC VCCIB0 IO13RSB0 IO10RSB0 IO07RSB0 IO03RSB0 IO00RSB0 GND GND GND GND
3 -2 8
v1.7
IGLOO Packaging
132-Pin QFN Pin Number A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 A33 A34 A35 A36 AGL125 Function GAB2/IO69RSB1 IO130RSB1 VCCIB1 GFC1/IO126RSB1 GFB0/IO123RSB1 VCCPLF GFA1/IO121RSB1 GFC2/IO118RSB1 IO115RSB1 VCC GEB1/IO110RSB1 GEA0/IO107RSB1 GEC2/IO104RSB1 IO100RSB1 VCC IO99RSB1 IO96RSB1 IO94RSB1 IO91RSB1 IO85RSB1 IO79RSB1 VCC GDB2/IO71RSB1 TDI TRST GDC1/IO61RSB0 VCC IO60RSB0 GCC2/IO59RSB0 GCA2/IO57RSB0 GCA0/IO56RSB0 GCB1/IO53RSB0 IO49RSB0 VCC IO44RSB0 GBA2/IO41RSB0
132-Pin QFN Pin Number A37 A38 A39 A40 A41 A42 A43 A44 A45 A46 A47 A48 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 AGL125 Function GBB1/IO38RSB0 GBC0/IO35RSB0 VCCIB0 IO28RSB0 IO22RSB0 IO18RSB0 IO14RSB0 IO11RSB0 IO07RSB0 VCC GAC1/IO05RSB0 GAB0/IO02RSB0 IO68RSB1 GAC2/IO131RSB1 GND GFC0/IO125RSB1 VCOMPLF GND GFB2/IO119RSB1 IO116RSB1 GND GEB0/IO109RSB1 VMV1 FF/GEB2/IO105RSB1 IO101RSB1 GND IO98RSB1 IO95RSB1 GND IO87RSB1 IO81RSB1 GND GNDQ TMS TDO GDC0/IO62RSB0
132-Pin QFN Pin Number B25 B26 B27 B28 B29 B30 B31 B32 B33 B34 B35 B36 B37 B38 B39 B40 B41 B42 B43 B44 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 AGL125 Function GND NC GCB2/IO58RSB0 GND GCB0/IO54RSB0 GCC1/IO51RSB0 GND GBB2/IO43RSB0 VMV0 GBA0/IO39RSB0 GBC1/IO36RSB0 GND IO26RSB0 IO21RSB0 GND IO13RSB0 IO08RSB0 GND GAC0/IO04RSB0 GNDQ GAA2/IO67RSB1 IO132RSB1 VCC GFB1/IO124RSB1 GFA0/IO122RSB1 GFA2/IO120RSB1 IO117RSB1 VCCIB1 GEA1/IO108RSB1 GNDQ GEA2/IO106RSB1 IO103RSB1 VCCIB1 IO97RSB1 IO93RSB1 IO89RSB1
v1.7
3 - 29
Package Pin Assignments
132-Pin QFN Pin Number C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 C27 C28 C29 C30 C31 C32 C33 C34 C35 C36 C37 C38 C39 C40 D1 D2 D3 D4 AGL125 Function IO83RSB1 VCCIB1 TCK VMV1 VPUMP VJTAG VCCIB0 NC NC GCA1/IO55RSB0 GCC0/IO52RSB0 VCCIB0 IO42RSB0 GNDQ GBA1/IO40RSB0 GBB0/IO37RSB0 VCC IO24RSB0 IO19RSB0 IO16RSB0 IO10RSB0 VCCIB0 GAB1/IO03RSB0 VMV0 GND GND GND GND
3 -3 0
v1.7
IGLOO Packaging
100-Pin VQFP
100
1
Note: This is the top view of the package. Figure 3-9 •
Note
For Package Manufacturing and Environmental information, visit the Resource Center at http://www.actel.com/products/solutions/package/docs.aspx.
v1.7
3 - 31
Package Pin Assignments
100-Pin VQFP Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 AGL030 Function GND IO82RSB1 IO81RSB1 IO80RSB1 IO79RSB1 IO78RSB1 IO77RSB1 IO76RSB1 GND IO75RSB1 IO74RSB1 GEC0/IO73RSB1 GEA0/IO72RSB1 GEB0/IO71RSB1 IO70RSB1 IO69RSB1 VCC VCCIB1 IO68RSB1 IO67RSB1 IO66RSB1 IO65RSB1 IO64RSB1 IO63RSB1 IO62RSB1 IO61RSB1 FF/IO60RSB1 IO59RSB1 IO58RSB1 IO57RSB1 IO56RSB1 IO55RSB1 IO54RSB1 IO53RSB1 IO52RSB1 IO51RSB1
100-Pin VQFP Pin Number 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 AGL030 Function VCC GND VCCIB1 IO49RSB1 IO47RSB1 IO46RSB1 IO45RSB1 IO44RSB1 IO43RSB1 IO42RSB1 TCK TDI TMS NC GND VPUMP NC TDO TRST VJTAG IO41RSB0 IO40RSB0 IO39RSB0 IO38RSB0 IO37RSB0 IO36RSB0 GDB0/IO34RSB0 GDA0/IO33RSB0 GDC0/IO32RSB0 VCCIB0 GND VCC IO31RSB0 IO30RSB0 IO29RSB0 IO28RSB0
100-Pin VQFP Pin Number 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 AGL030 Function IO27RSB0 IO26RSB0 IO25RSB0 IO24RSB0 IO23RSB0 IO22RSB0 IO21RSB0 IO20RSB0 IO19RSB0 IO18RSB0 IO17RSB0 IO16RSB0 IO15RSB0 IO14RSB0 VCCIB0 GND VCC IO12RSB0 IO10RSB0 IO08RSB0 IO07RSB0 IO06RSB0 IO05RSB0 IO04RSB0 IO03RSB0 IO02RSB0 IO01RSB0 IO00RSB0
3 -3 2
v1.7
IGLOO Packaging
100-Pin VQFP Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 AGL060 Function GND GAA2/IO51RSB1 IO52RSB1 GAB2/IO53RSB1 IO95RSB1 GAC2/IO94RSB1 IO93RSB1 IO92RSB1 GND GFB1/IO87RSB1 GFB0/IO86RSB1 VCOMPLF GFA0/IO85RSB1 VCCPLF GFA1/IO84RSB1 GFA2/IO83RSB1 VCC VCCIB1 GEC1/IO77RSB1 GEB1/IO75RSB1 GEB0/IO74RSB1 GEA1/IO73RSB1 GEA0/IO72RSB1 VMV1 GNDQ GEA2/IO71RSB1 FF/GEB2/IO70RSB1 GEC2/IO69RSB1 IO68RSB1 IO67RSB1 IO66RSB1 IO65RSB1 IO64RSB1 IO63RSB1 IO62RSB1 IO61RSB1
100-Pin VQFP Pin Number 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 AGL060 Function VCC GND VCCIB1 IO60RSB1 IO59RSB1 IO58RSB1 IO57RSB1 GDC2/IO56RSB1 GDB2/IO55RSB1 GDA2/IO54RSB1 TCK TDI TMS VMV1 GND VPUMP NC TDO TRST VJTAG GDA1/IO49RSB0 GDC0/IO46RSB0 GDC1/IO45RSB0 GCC2/IO43RSB0 GCB2/IO42RSB0 GCA0/IO40RSB0 GCA1/IO39RSB0 GCC0/IO36RSB0 GCC1/IO35RSB0 VCCIB0 GND VCC IO31RSB0 GBC2/IO29RSB0 GBB2/IO27RSB0 IO26RSB0
100-Pin VQFP Pin Number 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 AGL060 Function GBA2/IO25RSB0 VMV0 GNDQ GBA1/IO24RSB0 GBA0/IO23RSB0 GBB1/IO22RSB0 GBB0/IO21RSB0 GBC1/IO20RSB0 GBC0/IO19RSB0 IO18RSB0 IO17RSB0 IO15RSB0 IO13RSB0 IO11RSB0 VCCIB0 GND VCC IO10RSB0 IO09RSB0 IO08RSB0 GAC1/IO07RSB0 GAC0/IO06RSB0 GAB1/IO05RSB0 GAB0/IO04RSB0 GAA1/IO03RSB0 GAA0/IO02RSB0 IO01RSB0 IO00RSB0
v1.7
3 - 33
Package Pin Assignments
100-Pin VQFP Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 AGL125 Function GND GAA2/IO67RSB1 IO68RSB1 GAB2/IO69RSB1 IO132RSB1 GAC2/IO131RSB1 IO130RSB1 IO129RSB1 GND GFB1/IO124RSB1 GFB0/IO123RSB1 VCOMPLF GFA0/IO122RSB1 VCCPLF GFA1/IO121RSB1 GFA2/IO120RSB1 VCC VCCIB1 GEC0/IO111RSB1 GEB1/IO110RSB1 GEB0/IO109RSB1 GEA1/IO108RSB1 GEA0/IO107RSB1 VMV1 GNDQ GEA2/IO106RSB1 FF/GEB2/IO105RSB1 GEC2/IO104RSB1 IO102RSB1 IO100RSB1 IO99RSB1 IO97RSB1 IO96RSB1 IO95RSB1 IO94RSB1 IO93RSB1
100-Pin VQFP Pin Number 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 AGL125 Function VCC GND VCCIB1 IO87RSB1 IO84RSB1 IO81RSB1 IO75RSB1 GDC2/IO72RSB1 GDB2/IO71RSB1 GDA2/IO70RSB1 TCK TDI TMS VMV1 GND VPUMP NC TDO TRST VJTAG GDA1/IO65RSB0 GDC0/IO62RSB0 GDC1/IO61RSB0 GCC2/IO59RSB0 GCB2/IO58RSB0 GCA0/IO56RSB0 GCA1/IO55RSB0 GCC0/IO52RSB0 GCC1/IO51RSB0 VCCIB0 GND VCC IO47RSB0 GBC2/IO45RSB0 GBB2/IO43RSB0 IO42RSB0
100-Pin VQFP Pin Number 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 AGL125 Function GBA2/IO41RSB0 VMV0 GNDQ GBA1/IO40RSB0 GBA0/IO39RSB0 GBB1/IO38RSB0 GBB0/IO37RSB0 GBC1/IO36RSB0 GBC0/IO35RSB0 IO32RSB0 IO28RSB0 IO25RSB0 IO22RSB0 IO19RSB0 VCCIB0 GND VCC IO15RSB0 IO13RSB0 IO11RSB0 IO09RSB0 IO07RSB0 GAC1/IO05RSB0 GAC0/IO04RSB0 GAB1/IO03RSB0 GAB0/IO02RSB0 GAA1/IO01RSB0 GAA0/IO00RSB0
3 -3 4
v1.7
IGLOO Packaging
100-Pin VQFP Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 AGL250 Function GND GAA2/IO118UDB3 IO118VDB3 GAB2/IO117UDB3 IO117VDB3 GAC2/IO116UDB3 IO116VDB3 IO112PSB3 GND GFB1/IO109PDB3 GFB0/IO109NDB3 VCOMPLF GFA0/IO108NPB3 VCCPLF GFA1/IO108PPB3 GFA2/IO107PSB3 VCC VCCIB3 GFC2/IO105PSB3 GEC1/IO100PDB3 GEC0/IO100NDB3 GEA1/IO98PDB3 GEA0/IO98NDB3 VMV3 GNDQ GEA2/IO97RSB2 FF/GEB2/IO96RSB2 GEC2/IO95RSB2 IO93RSB2 IO92RSB2 IO91RSB2 IO90RSB2 IO88RSB2 IO86RSB2 IO85RSB2 IO84RSB2
100-Pin VQFP Pin Number 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 AGL250 Function VCC GND VCCIB2 IO77RSB2 IO74RSB2 IO71RSB2 GDC2/IO63RSB2 GDB2/IO62RSB2 GDA2/IO61RSB2 GNDQ TCK TDI TMS VMV2 GND VPUMP NC TDO TRST VJTAG GDA1/IO60USB1 GDC0/IO58VDB1 GDC1/IO58UDB1 IO52NDB1 GCB2/IO52PDB1 GCA1/IO50PDB1 GCA0/IO50NDB1 GCC0/IO48NDB1 GCC1/IO48PDB1 VCCIB1 GND VCC IO43NDB1 GBC2/IO43PDB1 GBB2/IO42PSB1 IO41NDB1
100-Pin VQFP Pin Number 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 AGL250 Function GBA2/IO41PDB1 VMV1 GNDQ GBA1/IO40RSB0 GBA0/IO39RSB0 GBB1/IO38RSB0 GBB0/IO37RSB0 GBC1/IO36RSB0 GBC0/IO35RSB0 IO29RSB0 IO27RSB0 IO25RSB0 IO23RSB0 IO21RSB0 VCCIB0 GND VCC IO15RSB0 IO13RSB0 IO11RSB0 GAC1/IO05RSB0 GAC0/IO04RSB0 GAB1/IO03RSB0 GAB0/IO02RSB0 GAA1/IO01RSB0 GAA0/IO00RSB0 GNDQ VMV0
v1.7
3 - 35
Package Pin Assignments
144-Pin FBGA
A1 Ball Pad Corner
12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M
Note: This is the bottom view of the package. Figure 3-10 •
Note
For Package Manufacturing and Environmental information, visit the Resource Center at http://www.actel.com/products/solutions/package/docs.aspx.
3 -3 6
v1.7
IGLOO Packaging
144-Pin FBGA Pin Number A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 AGL125 Function GNDQ VMV0 GAB0/IO02RSB0 GAB1/IO03RSB0 IO11RSB0 GND IO18RSB0 VCC IO25RSB0 GBA0/IO39RSB0 GBA1/IO40RSB0 GNDQ GAB2/IO69RSB1 GND GAA0/IO00RSB0 GAA1/IO01RSB0 IO08RSB0 IO14RSB0 IO19RSB0 IO22RSB0 GBB0/IO37RSB0 GBB1/IO38RSB0 GND VMV0 IO132RSB1 GFA2/IO120RSB1 GAC2/IO131RSB1 VCC IO10RSB0 IO12RSB0 IO21RSB0 IO24RSB0 IO27RSB0 GBA2/IO41RSB0 IO42RSB0 GBC2/IO45RSB0
144-Pin FBGA Pin Number D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 AGL125 Function IO128RSB1 IO129RSB1 IO130RSB1 GAA2/IO67RSB1 GAC0/IO04RSB0 GAC1/IO05RSB0 GBC0/IO35RSB0 GBC1/IO36RSB0 GBB2/IO43RSB0 IO28RSB0 IO44RSB0 GCB1/IO53RSB0 VCC GFC0/IO125RSB1 GFC1/IO126RSB1 VCCIB1 IO68RSB1 VCCIB0 VCCIB0 GCC1/IO51RSB0 VCCIB0 VCC GCA0/IO56RSB0 IO46RSB0 GFB0/IO123RSB1 VCOMPLF GFB1/IO124RSB1 IO127RSB1 GND GND GND GCC0/IO52RSB0 GCB0/IO54RSB0 GND GCA1/IO55RSB0 GCA2/IO57RSB0
144-Pin FBGA Pin Number G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 AGL125 Function GFA1/IO121RSB1 GND VCCPLF GFA0/IO122RSB1 GND GND GND GDC1/IO61RSB0 IO48RSB0 GCC2/IO59RSB0 IO47RSB0 GCB2/IO58RSB0 VCC GFB2/IO119RSB1 GFC2/IO118RSB1 GEC1/IO112RSB1 VCC IO50RSB0 IO60RSB0 GDB2/IO71RSB1 GDC0/IO62RSB0 VCCIB0 IO49RSB0 VCC GEB1/IO110RSB1 IO115RSB1 VCCIB1 GEC0/IO111RSB1 IO116RSB1 IO117RSB1 VCC TCK GDA2/IO70RSB1 TDO GDA1/IO65RSB0 GDB1/IO63RSB0
v1.7
3 - 37
Package Pin Assignments
144-Pin FBGA Pin Number K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 K12 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 M12 AGL125 Function GEB0/IO109RSB1 GEA1/IO108RSB1 GEA0/IO107RSB1 GEA2/IO106RSB1 IO100RSB1 IO98RSB1 GND IO73RSB1 GDC2/IO72RSB1 GND GDA0/IO66RSB0 GDB0/IO64RSB0 GND VMV1 FF/GEB2/IO105RSB1 IO102RSB1 VCCIB1 IO95RSB1 IO85RSB1 IO74RSB1 TMS VJTAG VMV1 TRST GNDQ GEC2/IO104RSB1 IO103RSB1 IO101RSB1 IO97RSB1 IO94RSB1 IO86RSB1 IO75RSB1 TDI VCCIB1 VPUMP GNDQ
3 -3 8
v1.7
IGLOO Packaging
144-Pin FBGA Pin Number A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 AGL250 Function GNDQ VMV0 GAB0/IO02RSB0 GAB1/IO03RSB0 IO16RSB0 GND IO29RSB0 VCC IO33RSB0 GBA0/IO39RSB0 GBA1/IO40RSB0 GNDQ GAB2/IO117UDB3 GND GAA0/IO00RSB0 GAA1/IO01RSB0 IO14RSB0 IO19RSB0 IO22RSB0 IO30RSB0 GBB0/IO37RSB0 GBB1/IO38RSB0 GND VMV1 IO117VDB3 GFA2/IO107PPB3 GAC2/IO116UDB3 VCC IO12RSB0 IO17RSB0 IO24RSB0 IO31RSB0 IO34RSB0 GBA2/IO41PDB1 IO41NDB1 GBC2/IO43PPB1
144-Pin FBGA Pin Number D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 AGL250 Function IO112NDB3 IO112PDB3 IO116VDB3 GAA2/IO118UPB3 GAC0/IO04RSB0 GAC1/IO05RSB0 GBC0/IO35RSB0 GBC1/IO36RSB0 GBB2/IO42PDB1 IO42NDB1 IO43NPB1 GCB1/IO49PPB1 VCC GFC0/IO110NDB3 GFC1/IO110PDB3 VCCIB3 IO118VPB3 VCCIB0 VCCIB0 GCC1/IO48PDB1 VCCIB1 VCC GCA0/IO50NDB1 IO51NDB1 GFB0/IO109NPB3 VCOMPLF GFB1/IO109PPB3 IO107NPB3 GND GND GND GCC0/IO48NDB1 GCB0/IO49NPB1 GND GCA1/IO50PDB1 GCA2/IO51PDB1
144-Pin FBGA Pin Number G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 AGL250 Function GFA1/IO108PPB3 GND VCCPLF GFA0/IO108NPB3 GND GND GND GDC1/IO58UPB1 IO53NDB1 GCC2/IO53PDB1 IO52NDB1 GCB2/IO52PDB1 VCC GFB2/IO106PDB3 GFC2/IO105PSB3 GEC1/IO100PDB3 VCC IO79RSB2 IO65RSB2 GDB2/IO62RSB2 GDC0/IO58VPB1 VCCIB1 IO54PSB1 VCC GEB1/IO99PDB3 IO106NDB3 VCCIB3 GEC0/IO100NDB3 IO88RSB2 IO81RSB2 VCC TCK GDA2/IO61RSB2 TDO GDA1/IO60UDB1 GDB1/IO59UDB1
v1.7
3 - 39
Package Pin Assignments
144-Pin FBGA Pin Number K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 K12 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 M12 AGL250 Function GEB0/IO99NDB3 GEA1/IO98PDB3 GEA0/IO98NDB3 GEA2/IO97RSB2 IO90RSB2 IO84RSB2 GND IO66RSB2 GDC2/IO63RSB2 GND GDA0/IO60VDB1 GDB0/IO59VDB1 GND VMV3 FF/GEB2/IO96RSB2 IO91RSB2 VCCIB2 IO82RSB2 IO80RSB2 IO72RSB2 TMS VJTAG VMV2 TRST GNDQ GEC2/IO95RSB2 IO92RSB2 IO89RSB2 IO87RSB2 IO85RSB2 IO78RSB2 IO76RSB2 TDI VCCIB2 VPUMP GNDQ
3 -4 0
v1.7
IGLOO Packaging
144-pin FBGA Pin Number A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 AGL400 Function GNDQ VMV0 GAB0/IO02RSB0 GAB1/IO03RSB0 IO16RSB0 GND IO30RSB0 VCC IO34RSB0 GBA0/IO58RSB0 GBA1/IO59RSB0 GNDQ GAB2/IO154UDB3 GND GAA0/IO00RSB0 GAA1/IO01RSB0 IO14RSB0 IO19RSB0 IO23RSB0 IO31RSB0 GBB0/IO56RSB0 GBB1/IO57RSB0 GND VMV1 IO154VDB3 GFA2/IO144PPB3 GAC2/IO153UDB3 VCC IO12RSB0 IO17RSB0 IO25RSB0 IO32RSB0 IO53RSB0 GBA2/IO60PDB1 IO60NDB1 GBC2/IO62PPB1
144-pin FBGA Pin Number D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 AGL400 Function IO149NDB3 IO149PDB3 IO153VDB3 GAA2/IO155UPB3 GAC0/IO04RSB0 GAC1/IO05RSB0 GBC0/IO54RSB0 GBC1/IO55RSB0 GBB2/IO61PDB1 IO61NDB1 IO62NPB1 GCB1/IO68PPB1 VCC GFC0/IO147NDB3 GFC1/IO147PDB3 VCCIB3 IO155VPB3 VCCIB0 VCCIB0 GCC1/IO67PDB1 VCCIB1 VCC GCA0/IO69NDB1 IO70NDB1 GFB0/IO146NPB3 VCOMPLF GFB1/IO146PPB3 IO144NPB3 GND GND GND GCC0/IO67NDB1 GCB0/IO68NPB1 GND GCA1/IO69PDB1 GCA2/IO70PDB1
144-pin FBGA Pin Number G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 AGL400 Function GFA1/IO145PPB3 GND VCCPLF GFA0/IO145NPB3 GND GND GND GDC1/IO77UPB1 IO72NDB1 GCC2/IO72PDB1 IO71NDB1 GCB2/IO71PDB1 VCC GFB2/IO143PDB3 GFC2/IO142PSB3 GEC1/IO137PDB3 VCC IO75PDB1 IO75NDB1 GDB2/IO81RSB2 GDC0/IO77VPB1 VCCIB1 IO73PSB1 VCC GEB1/IO136PDB3 IO143NDB3 VCCIB3 GEC0/IO137NDB3 IO125RSB2 IO116RSB2 VCC TCK GDA2/IO80RSB2 TDO GDA1/IO79UDB1 GDB1/IO78UDB1
v1.7
3 - 41
Package Pin Assignments
144-pin FBGA Pin Number K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 K12 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 M12 AGL400 Function GEB0/IO136NDB3 GEA1/IO135PDB3 GEA0/IO135NDB3 GEA2/IO134RSB2 IO127RSB2 IO121RSB2 GND IO104RSB2 GDC2/IO82RSB2 GND GDA0/IO79VDB1 GDB0/IO78VDB1 GND VMV3 FF/GEB2/IO133RSB2 IO128RSB2 VCCIB2 IO119RSB2 IO114RSB2 IO110RSB2 TMS VJTAG VMV2 TRST GNDQ GEC2/IO132RSB2 IO129RSB2 IO126RSB2 IO124RSB2 IO122RSB2 IO117RSB2 IO115RSB2 TDI VCCIB2 VPUMP GNDQ
3 -4 2
v1.7
IGLOO Packaging
144-Pin FBGA Pin Number A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 AGL600 Function GNDQ VMV0 GAB0/IO02RSB0 GAB1/IO03RSB0 IO10RSB0 GND IO34RSB0 VCC IO50RSB0 GBA0/IO58RSB0 GBA1/IO59RSB0 GNDQ GAB2/IO173PDB3 GND GAA0/IO00RSB0 GAA1/IO01RSB0 IO13RSB0 IO19RSB0 IO31RSB0 IO39RSB0 GBB0/IO56RSB0 GBB1/IO57RSB0 GND VMV1 IO173NDB3 GFA2/IO161PPB3 GAC2/IO172PDB3 VCC IO16RSB0 IO25RSB0 IO28RSB0 IO42RSB0 IO45RSB0 GBA2/IO60PDB1 IO60NDB1 GBC2/IO62PPB1
144-Pin FBGA Pin Number D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 AGL600 Function IO169PDB3 IO169NDB3 IO172NDB3 GAA2/IO174PPB3 GAC0/IO04RSB0 GAC1/IO05RSB0 GBC0/IO54RSB0 GBC1/IO55RSB0 GBB2/IO61PDB1 IO61NDB1 IO62NPB1 GCB1/IO70PPB1 VCC GFC0/IO164NDB3 GFC1/IO164PDB3 VCCIB3 IO174NPB3 VCCIB0 VCCIB0 GCC1/IO69PDB1 VCCIB1 VCC GCA0/IO71NDB1 IO72NDB1 GFB0/IO163NPB3 VCOMPLF GFB1/IO163PPB3 IO161NPB3 GND GND GND GCC0/IO69NDB1 GCB0/IO70NPB1 GND GCA1/IO71PDB1 GCA2/IO72PDB1
144-Pin FBGA Pin Number G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 AGL600 Function GFA1/IO162PPB3 GND VCCPLF GFA0/IO162NPB3 GND GND GND GDC1/IO86PPB1 IO74NDB1 GCC2/IO74PDB1 IO73NDB1 GCB2/IO73PDB1 VCC GFB2/IO160PDB3 GFC2/IO159PSB3 GEC1/IO146PDB3 VCC IO80PDB1 IO80NDB1 GDB2/IO90RSB2 GDC0/IO86NPB1 VCCIB1 IO84PSB1 VCC GEB1/IO145PDB3 IO160NDB3 VCCIB3 GEC0/IO146NDB3 IO129RSB2 IO131RSB2 VCC TCK GDA2/IO89RSB2 TDO GDA1/IO88PDB1 GDB1/IO87PDB1
v1.7
3 - 43
Package Pin Assignments
144-Pin FBGA Pin Number K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 K12 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 M12 AGL600 Function GEB0/IO145NDB3 GEA1/IO144PDB3 GEA0/IO144NDB3 GEA2/IO143RSB2 IO119RSB2 IO111RSB2 GND IO94RSB2 GDC2/IO91RSB2 GND GDA0/IO88NDB1 GDB0/IO87NDB1 GND VMV3 FF/GEB2/IO142RSB2 IO136RSB2 VCCIB2 IO115RSB2 IO103RSB2 IO97RSB2 TMS VJTAG VMV2 TRST GNDQ GEC2/IO141RSB2 IO138RSB2 IO123RSB2 IO126RSB2 IO134RSB2 IO108RSB2 IO99RSB2 TDI VCCIB2 VPUMP GNDQ
3 -4 4
v1.7
IGLOO Packaging
144-Pin FBGA Pin Number A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 AGL1000 Function GNDQ VMV0 GAB0/IO02RSB0 GAB1/IO03RSB0 IO10RSB0 GND IO44RSB0 VCC IO69RSB0 GBA0/IO76RSB0 GBA1/IO77RSB0 GNDQ GAB2/IO224PDB3 GND GAA0/IO00RSB0 GAA1/IO01RSB0 IO13RSB0 IO26RSB0 IO35RSB0 IO60RSB0 GBB0/IO74RSB0 GBB1/IO75RSB0 GND VMV1 IO224NDB3 GFA2/IO206PPB3 GAC2/IO223PDB3 VCC IO16RSB0 IO29RSB0 IO32RSB0 IO63RSB0 IO66RSB0 GBA2/IO78PDB1 IO78NDB1 GBC2/IO80PPB1
144-Pin FBGA Pin Number D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 AGL1000 Function IO213PDB3 IO213NDB3 IO223NDB3 GAA2/IO225PPB3 GAC0/IO04RSB0 GAC1/IO05RSB0 GBC0/IO72RSB0 GBC1/IO73RSB0 GBB2/IO79PDB1 IO79NDB1 IO80NPB1 GCB1/IO92PPB1 VCC GFC0/IO209NDB3 GFC1/IO209PDB3 VCCIB3 IO225NPB3 VCCIB0 VCCIB0 GCC1/IO91PDB1 VCCIB1 VCC GCA0/IO93NDB1 IO94NDB1 GFB0/IO208NPB3 VCOMPLF GFB1/IO208PPB3 IO206NPB3 GND GND GND GCC0/IO91NDB1 GCB0/IO92NPB1 GND GCA1/IO93PDB1 GCA2/IO94PDB1
144-Pin FBGA Pin Number G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 AGL1000 Function GFA1/IO207PPB3 GND VCCPLF GFA0/IO207NPB3 GND GND GND GDC1/IO111PPB1 IO96NDB1 GCC2/IO96PDB1 IO95NDB1 GCB2/IO95PDB1 VCC GFB2/IO205PDB3 GFC2/IO204PSB3 GEC1/IO190PDB3 VCC IO105PDB1 IO105NDB1 GDB2/IO115RSB2 GDC0/IO111NPB1 VCCIB1 IO101PSB1 VCC GEB1/IO189PDB3 IO205NDB3 VCCIB3 GEC0/IO190NDB3 IO160RSB2 IO157RSB2 VCC TCK GDA2/IO114RSB2 TDO GDA1/IO113PDB1 GDB1/IO112PDB1
v1.7
3 - 45
Package Pin Assignments
144-Pin FBGA Pin Number K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 K12 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 M12 AGL1000 Function GEB0/IO189NDB3 GEA1/IO188PDB3 GEA0/IO188NDB3 GEA2/IO187RSB2 IO169RSB2 IO152RSB2 GND IO117RSB2 GDC2/IO116RSB2 GND GDA0/IO113NDB1 GDB0/IO112NDB1 GND VMV3 FF/GEB2/IO186RSB2 IO172RSB2 VCCIB2 IO153RSB2 IO144RSB2 IO140RSB2 TMS VJTAG VMV2 TRST GNDQ GEC2/IO185RSB2 IO173RSB2 IO168RSB2 IO161RSB2 IO156RSB2 IO145RSB2 IO141RSB2 TDI VCCIB2 VPUMP GNDQ
3 -4 6
v1.7
IGLOO Packaging
256-Pin FBGA
A1 Ball Pad Corner 16 15 14 13 12 11 10 9 8 7 654 321 A B C D E F G H J K L M N P R T
Note: This is the bottom view of the package. Figure 3-11 •
Note
For Package Manufacturing and Environmental information, visit the Resource Center at http://www.actel.com/products/solutions/package/docs.aspx.
v1.7
3 - 47
Package Pin Assignments
256-Pin FBGA Pin Number A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 C1 C2 C3 C4 AGL400 Function GND GAA0/IO00RSB0 GAA1/IO01RSB0 GAB0/IO02RSB0 IO16RSB0 IO17RSB0 IO22RSB0 IO28RSB0 IO34RSB0 IO37RSB0 IO41RSB0 IO43RSB0 GBB1/IO57RSB0 GBA0/IO58RSB0 GBA1/IO59RSB0 GND GAB2/IO154UDB3 GAA2/IO155UDB3 IO12RSB0 GAB1/IO03RSB0 IO13RSB0 IO14RSB0 IO21RSB0 IO27RSB0 IO32RSB0 IO38RSB0 IO42RSB0 GBC1/IO55RSB0 GBB0/IO56RSB0 IO44RSB0 GBA2/IO60PDB1 IO60NDB1 IO154VDB3 IO155VDB3 IO11RSB0 IO07RSB0
256-Pin FBGA Pin Number C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 E1 E2 E3 E4 E5 E6 E7 E8 AGL400 Function GAC0/IO04RSB0 GAC1/IO05RSB0 IO20RSB0 IO24RSB0 IO33RSB0 IO39RSB0 IO45RSB0 GBC0/IO54RSB0 IO48RSB0 VMV0 IO61NPB1 IO63PDB1 IO151VDB3 IO151UDB3 GAC2/IO153UDB3 IO06RSB0 GNDQ IO10RSB0 IO19RSB0 IO26RSB0 IO30RSB0 IO40RSB0 IO46RSB0 GNDQ IO47RSB0 GBB2/IO61PPB1 IO53RSB0 IO63NDB1 IO150PDB3 IO08RSB0 IO153VDB3 IO152VDB3 VMV0 VCCIB0 VCCIB0 IO25RSB0
256-Pin FBGA Pin Number E9 E10 E11 E12 E13 E14 E15 E16 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 AGL400 Function IO31RSB0 VCCIB0 VCCIB0 VMV1 GBC2/IO62PDB1 IO65RSB1 IO52RSB0 IO66PDB1 IO150NDB3 IO149NPB3 IO09RSB0 IO152UDB3 VCCIB3 GND VCC VCC VCC VCC GND VCCIB1 IO62NDB1 IO49RSB0 IO64PPB1 IO66NDB1 IO148NDB3 IO148PDB3 IO149PPB3 GFC1/IO147PPB3 VCCIB3 VCC GND GND GND GND VCC VCCIB1
3 -4 8
v1.7
IGLOO Packaging
256-Pin FBGA Pin Number G13 G14 G15 G16 H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 H13 H14 H15 H16 J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 J13 J14 J15 J16 AGL400 Function GCC1/IO67PPB1 IO64NPB1 IO73PDB1 IO73NDB1 GFB0/IO146NPB3 GFA0/IO145NDB3 GFB1/IO146PPB3 VCOMPLF GFC0/IO147NPB3 VCC GND GND GND GND VCC GCC0/IO67NPB1 GCB1/IO68PPB1 GCA0/IO69NPB1 NC GCB0/IO68NPB1 GFA2/IO144PPB3 GFA1/IO145PDB3 VCCPLF IO143NDB3 GFB2/IO143PDB3 VCC GND GND GND GND VCC GCB2/IO71PPB1 GCA1/IO69PPB1 GCC2/IO72PPB1 NC GCA2/IO70PDB1
256-Pin FBGA Pin Number K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 K12 K13 K14 K15 K16 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 L15 L16 M1 M2 M3 M4 AGL400 Function GFC2/IO142PDB3 IO144NPB3 IO141PPB3 IO120RSB2 VCCIB3 VCC GND GND GND GND VCC VCCIB1 IO71NPB1 IO74RSB1 IO72NPB1 IO70NDB1 IO142NDB3 IO141NPB3 IO125RSB2 IO139RSB3 VCCIB3 GND VCC VCC VCC VCC GND VCCIB1 GDB0/IO78VPB1 IO76VDB1 IO76UDB1 IO75PDB1 IO140PDB3 IO130RSB2 IO138NPB3 GEC0/IO137NPB3
256-Pin FBGA Pin Number M5 M6 M7 M8 M9 M10 M11 M12 M13 M14 M15 M16 N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 N12 N13 N14 N15 N16 P1 P2 P3 P4 P5 P6 P7 P8 AGL400 Function VMV3 VCCIB2 VCCIB2 IO108RSB2 IO101RSB2 VCCIB2 VCCIB2 VMV2 IO83RSB2 GDB1/IO78UPB1 GDC1/IO77UDB1 IO75NDB1 IO140NDB3 IO138PPB3 GEC1/IO137PPB3 IO131RSB2 GNDQ GEA2/IO134RSB2 IO117RSB2 IO111RSB2 IO99RSB2 IO94RSB2 IO87RSB2 GNDQ IO93RSB2 VJTAG GDC0/IO77VDB1 GDA1/IO79UDB1 GEB1/IO136PDB3 GEB0/IO136NDB3 VMV2 IO129RSB2 IO128RSB2 IO122RSB2 IO115RSB2 IO110RSB2
v1.7
3 - 49
Package Pin Assignments
256-Pin FBGA Pin Number P9 P10 P11 P12 P13 P14 P15 P16 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 AGL400 Function IO98RSB2 IO95RSB2 IO88RSB2 IO84RSB2 TCK VPUMP TRST GDA0/IO79VDB1 GEA1/IO135PDB3 GEA0/IO135NDB3 IO127RSB2 GEC2/IO132RSB2 IO123RSB2 IO118RSB2 IO112RSB2 IO106RSB2 IO100RSB2 IO96RSB2 IO89RSB2 IO85RSB2 GDB2/IO81RSB2 TDI NC TDO GND IO126RSB2 FF/GEB2/IO133RSB 2 IO124RSB2 IO116RSB2 IO113RSB2 IO107RSB2 IO105RSB2 IO102RSB2 IO97RSB2 IO92RSB2
256-Pin FBGA Pin Number T12 T13 T14 T15 T16 AGL400 Function GDC2/IO82RSB2 IO86RSB2 GDA2/IO80RSB2 TMS GND
3 -5 0
v1.7
IGLOO Packaging
256-Pin FBGA Pin Number A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 C1 C2 C3 C4 C5 C6 AGL600 Function GND GAA0/IO00RSB0 GAA1/IO01RSB0 GAB0/IO02RSB0 IO11RSB0 IO16RSB0 IO18RSB0 IO28RSB0 IO34RSB0 IO37RSB0 IO41RSB0 IO43RSB0 GBB1/IO57RSB0 GBA0/IO58RSB0 GBA1/IO59RSB0 GND GAB2/IO173PDB3 GAA2/IO174PDB3 GNDQ GAB1/IO03RSB0 IO13RSB0 IO14RSB0 IO21RSB0 IO27RSB0 IO32RSB0 IO38RSB0 IO42RSB0 GBC1/IO55RSB0 GBB0/IO56RSB0 IO52RSB0 GBA2/IO60PDB1 IO60NDB1 IO173NDB3 IO174NDB3 VMV3 IO07RSB0 GAC0/IO04RSB0 GAC1/IO05RSB0
256-Pin FBGA Pin Number C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 AGL600 Function IO20RSB0 IO24RSB0 IO33RSB0 IO39RSB0 IO44RSB0 GBC0/IO54RSB0 IO51RSB0 VMV0 IO61NPB1 IO63PDB1 IO171NDB3 IO171PDB3 GAC2/IO172PDB3 IO06RSB0 GNDQ IO10RSB0 IO19RSB0 IO26RSB0 IO30RSB0 IO40RSB0 IO45RSB0 GNDQ IO50RSB0 GBB2/IO61PPB1 IO53RSB0 IO63NDB1 IO166PDB3 IO167NPB3 IO172NDB3 IO169NDB3 VMV0 VCCIB0 VCCIB0 IO25RSB0 IO31RSB0 VCCIB0 VCCIB0 VMV1
256-Pin FBGA Pin Number E13 E14 E15 E16 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 G13 G14 G15 G16 H1 H2 AGL600 Function GBC2/IO62PDB1 IO67PPB1 IO64PPB1 IO66PDB1 IO166NDB3 IO168NPB3 IO167PPB3 IO169PDB3 VCCIB3 GND VCC VCC VCC VCC GND VCCIB1 IO62NDB1 IO64NPB1 IO65PPB1 IO66NDB1 IO165NDB3 IO165PDB3 IO168PPB3 GFC1/IO164PPB3 VCCIB3 VCC GND GND GND GND VCC VCCIB1 GCC1/IO69PPB1 IO65NPB1 IO75PDB1 IO75NDB1 GFB0/IO163NPB3 GFA0/IO162NDB3
v1.7
3 - 51
Package Pin Assignments
256-Pin FBGA Pin Number H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 H13 H14 H15 H16 J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 J13 J14 J15 J16 K1 K2 K3 K4 K5 K6 K7 K8 AGL600 Function GFB1/IO163PPB3 VCOMPLF GFC0/IO164NPB3 VCC GND GND GND GND VCC GCC0/IO69NPB1 GCB1/IO70PPB1 GCA0/IO71NPB1 IO67NPB1 GCB0/IO70NPB1 GFA2/IO161PPB3 GFA1/IO162PDB3 VCCPLF IO160NDB3 GFB2/IO160PDB3 VCC GND GND GND GND VCC GCB2/IO73PPB1 GCA1/IO71PPB1 GCC2/IO74PPB1 IO80PPB1 GCA2/IO72PDB1 GFC2/IO159PDB3 IO161NPB3 IO156PPB3 IO129RSB2 VCCIB3 VCC GND GND
256-Pin FBGA Pin Number K9 K10 K11 K12 K13 K14 K15 K16 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 L15 L16 M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 M12 M13 M14 AGL600 Function GND GND VCC VCCIB1 IO73NPB1 IO80NPB1 IO74NPB1 IO72NDB1 IO159NDB3 IO156NPB3 IO151PPB3 IO158PSB3 VCCIB3 GND VCC VCC VCC VCC GND VCCIB1 GDB0/IO87NPB1 IO85NDB1 IO85PDB1 IO84PDB1 IO150PDB3 IO151NPB3 IO147NPB3 GEC0/IO146NPB3 VMV3 VCCIB2 VCCIB2 IO117RSB2 IO110RSB2 VCCIB2 VCCIB2 VMV2 IO94RSB2 GDB1/IO87PPB1
256-Pin FBGA Pin Number M15 M16 N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 N12 N13 N14 N15 N16 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 R1 R2 R3 R4 AGL600 Function GDC1/IO86PDB1 IO84NDB1 IO150NDB3 IO147PPB3 GEC1/IO146PPB3 IO140RSB2 GNDQ GEA2/IO143RSB2 IO126RSB2 IO120RSB2 IO108RSB2 IO103RSB2 IO99RSB2 GNDQ IO92RSB2 VJTAG GDC0/IO86NDB1 GDA1/IO88PDB1 GEB1/IO145PDB3 GEB0/IO145NDB3 VMV2 IO138RSB2 IO136RSB2 IO131RSB2 IO124RSB2 IO119RSB2 IO107RSB2 IO104RSB2 IO97RSB2 VMV1 TCK VPUMP TRST GDA0/IO88NDB1 GEA1/IO144PDB3 GEA0/IO144NDB3 IO139RSB2 GEC2/IO141RSB2
3 -5 2
v1.7
IGLOO Packaging
256-Pin FBGA Pin Number R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 AGL600 Function IO132RSB2 IO127RSB2 IO121RSB2 IO114RSB2 IO109RSB2 IO105RSB2 IO98RSB2 IO96RSB2 GDB2/IO90RSB2 TDI GNDQ TDO GND IO137RSB2 FF/GEB2/IO142RSB2 IO134RSB2 IO125RSB2 IO123RSB2 IO118RSB2 IO115RSB2 IO111RSB2 IO106RSB2 IO102RSB2 GDC2/IO91RSB2 IO93RSB2 GDA2/IO89RSB2 TMS GND
v1.7
3 - 53
Package Pin Assignments
256-Pin FBGA Pin Number A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 C1 C2 C3 C4 C5 C6 AGL1000 Function GND GAA0/IO00RSB0 GAA1/IO01RSB0 GAB0/IO02RSB0 IO16RSB0 IO22RSB0 IO28RSB0 IO35RSB0 IO45RSB0 IO50RSB0 IO55RSB0 IO61RSB0 GBB1/IO75RSB0 GBA0/IO76RSB0 GBA1/IO77RSB0 GND GAB2/IO224PDB3 GAA2/IO225PDB3 GNDQ GAB1/IO03RSB0 IO17RSB0 IO21RSB0 IO27RSB0 IO34RSB0 IO44RSB0 IO51RSB0 IO57RSB0 GBC1/IO73RSB0 GBB0/IO74RSB0 IO71RSB0 GBA2/IO78PDB1 IO81PDB1 IO224NDB3 IO225NDB3 VMV3 IO11RSB0 GAC0/IO04RSB0 GAC1/IO05RSB0
256-Pin FBGA Pin Number C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 AGL1000 Function IO25RSB0 IO36RSB0 IO42RSB0 IO49RSB0 IO56RSB0 GBC0/IO72RSB0 IO62RSB0 VMV0 IO78NDB1 IO81NDB1 IO222NDB3 IO222PDB3 GAC2/IO223PDB3 IO223NDB3 GNDQ IO23RSB0 IO29RSB0 IO33RSB0 IO46RSB0 IO52RSB0 IO60RSB0 GNDQ IO80NDB1 GBB2/IO79PDB1 IO79NDB1 IO82NSB1 IO217PDB3 IO218PDB3 IO221NDB3 IO221PDB3 VMV0 VCCIB0 VCCIB0 IO38RSB0 IO47RSB0 VCCIB0 VCCIB0 VMV1
256-Pin FBGA Pin Number E13 E14 E15 E16 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 G13 G14 G15 G16 H1 H2 AGL1000 Function GBC2/IO80PDB1 IO83PPB1 IO86PPB1 IO87PDB1 IO217NDB3 IO218NDB3 IO216PDB3 IO216NDB3 VCCIB3 GND VCC VCC VCC VCC GND VCCIB1 IO83NPB1 IO86NPB1 IO90PPB1 IO87NDB1 IO210PSB3 IO213NDB3 IO213PDB3 GFC1/IO209PPB3 VCCIB3 VCC GND GND GND GND VCC VCCIB1 GCC1/IO91PPB1 IO90NPB1 IO88PDB1 IO88NDB1 GFB0/IO208NPB3 GFA0/IO207NDB3
3 -5 4
v1.7
IGLOO Packaging
256-Pin FBGA Pin Number H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 H13 H14 H15 H16 J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 J13 J14 J15 J16 K1 K2 K3 K4 K5 K6 K7 K8 AGL1000 Function GFB1/IO208PPB3 VCOMPLF GFC0/IO209NPB3 VCC GND GND GND GND VCC GCC0/IO91NPB1 GCB1/IO92PPB1 GCA0/IO93NPB1 IO96NPB1 GCB0/IO92NPB1 GFA2/IO206PSB3 GFA1/IO207PDB3 VCCPLF IO205NDB3 GFB2/IO205PDB3 VCC GND GND GND GND VCC GCB2/IO95PPB1 GCA1/IO93PPB1 GCC2/IO96PPB1 IO100PPB1 GCA2/IO94PSB1 GFC2/IO204PDB3 IO204NDB3 IO203NDB3 IO203PDB3 VCCIB3 VCC GND GND
256-Pin FBGA Pin Number K9 K10 K11 K12 K13 K14 K15 K16 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 L15 L16 M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 M12 M13 M14 AGL1000 Function GND GND VCC VCCIB1 IO95NPB1 IO100NPB1 IO102NDB1 IO102PDB1 IO202NDB3 IO202PDB3 IO196PPB3 IO193PPB3 VCCIB3 GND VCC VCC VCC VCC GND VCCIB1 GDB0/IO112NPB1 IO106NDB1 IO106PDB1 IO107PDB1 IO197NSB3 IO196NPB3 IO193NPB3 GEC0/IO190NPB3 VMV3 VCCIB2 VCCIB2 IO147RSB2 IO136RSB2 VCCIB2 VCCIB2 VMV2 IO110NDB1 GDB1/IO112PPB1
256-Pin FBGA Pin Number M15 M16 N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 N12 N13 N14 N15 N16 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 R1 R2 R3 R4 AGL1000 Function GDC1/IO111PDB1 IO107NDB1 IO194PSB3 IO192PPB3 GEC1/IO190PPB3 IO192NPB3 GNDQ GEA2/IO187RSB2 IO161RSB2 IO155RSB2 IO141RSB2 IO129RSB2 IO124RSB2 GNDQ IO110PDB1 VJTAG GDC0/IO111NDB1 GDA1/IO113PDB1 GEB1/IO189PDB3 GEB0/IO189NDB3 VMV2 IO179RSB2 IO171RSB2 IO165RSB2 IO159RSB2 IO151RSB2 IO137RSB2 IO134RSB2 IO128RSB2 VMV1 TCK VPUMP TRST GDA0/IO113NDB1 GEA1/IO188PDB3 GEA0/IO188NDB3 IO184RSB2 GEC2/IO185RSB2
v1.7
3 - 55
Package Pin Assignments
256-Pin FBGA Pin Number R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 AGL1000 Function IO168RSB2 IO163RSB2 IO157RSB2 IO149RSB2 IO143RSB2 IO138RSB2 IO131RSB2 IO125RSB2 GDB2/IO115RSB2 TDI GNDQ TDO GND IO183RSB2 FF/GEB2/IO186RSB2 IO172RSB2 IO170RSB2 IO164RSB2 IO158RSB2 IO153RSB2 IO142RSB2 IO135RSB2 IO130RSB2 GDC2/IO116RSB2 IO120RSB2 GDA2/IO114RSB2 TMS GND
3 -5 6
v1.7
IGLOO Packaging
484-Pin FBGA
A1 Ball Pad Corner
22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
A B C D E F G H J K L M N P R T U V W Y AA AB
Note: This is the bottom view of the package. Figure 3-12 •
Note
For Package Manufacturing and Environmental information, visit the Resource Center at http://www.actel.com/products/solutions/package/docs.aspx.
v1.7
3 - 57
Package Pin Assignments
484-Pin FBGA Pin Number A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 AA1 AA2 AA3 AA4 AA5 AA6 AA7 AA8 AA9 AA10 AA11 AA12 AA13 AA14 AGL400 Function GND GND VCCIB0 NC NC IO15RSB0 IO18RSB0 NC NC IO23RSB0 IO29RSB0 IO35RSB0 IO36RSB0 NC NC IO50RSB0 IO51RSB0 NC NC VCCIB0 GND GND GND VCCIB3 NC NC NC NC NC NC NC NC NC NC NC NC
484-Pin FBGA Pin Number AA15 AA16 AA17 AA18 AA19 AA20 AA21 AA22 AB1 AB2 AB3 AB4 AB5 AB6 AB7 AB8 AB9 AB10 AB11 AB12 AB13 AB14 AB15 AB16 AB17 AB18 AB19 AB20 AB21 AB22 B1 B2 B3 B4 B5 B6 AGL400 Function NC NC NC NC NC NC VCCIB1 GND GND GND VCCIB2 NC NC IO121RSB2 IO119RSB2 IO114RSB2 IO109RSB2 NC NC IO104RSB2 IO103RSB2 NC NC IO91RSB2 IO90RSB2 NC NC VCCIB2 GND GND GND VCCIB3 NC NC NC NC
484-Pin FBGA Pin Number B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 AGL400 Function NC NC NC NC NC NC NC NC NC NC NC NC NC NC VCCIB1 GND VCCIB3 NC NC NC GND NC NC VCC VCC NC NC NC NC VCC VCC NC NC GND NC NC
3 -5 8
v1.7
IGLOO Packaging
484-Pin FBGA Pin Number C21 C22 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 AGL400 Function NC VCCIB1 NC NC NC GND GAA0/IO00RSB0 GAA1/IO01RSB0 GAB0/IO02RSB0 IO16RSB0 IO17RSB0 IO22RSB0 IO28RSB0 IO34RSB0 IO37RSB0 IO41RSB0 IO43RSB0 GBB1/IO57RSB0 GBA0/IO58RSB0 GBA1/IO59RSB0 GND NC NC NC NC NC GND GAB2/IO154UDB3 GAA2/IO155UDB3 IO12RSB0 GAB1/IO03RSB0 IO13RSB0 IO14RSB0 IO21RSB0 IO27RSB0 IO32RSB0
484-Pin FBGA Pin Number E13 E14 E15 E16 E17 E18 E19 E20 E21 E22 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 G1 G2 G3 G4 AGL400 Function IO38RSB0 IO42RSB0 GBC1/IO55RSB0 GBB0/IO56RSB0 IO44RSB0 GBA2/IO60PDB1 IO60NDB1 GND NC NC NC NC NC IO154VDB3 IO155VDB3 IO11RSB0 IO07RSB0 GAC0/IO04RSB0 GAC1/IO05RSB0 IO20RSB0 IO24RSB0 IO33RSB0 IO39RSB0 IO45RSB0 GBC0/IO54RSB0 IO48RSB0 VMV0 IO61NPB1 IO63PDB1 NC NC NC NC NC NC IO151VDB3
484-Pin FBGA Pin Number G5 G6 G7 G8 G9 G10 G11 G12 G13 G14 G15 G16 G17 G18 G19 G20 G21 G22 H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 H13 H14 H15 H16 H17 H18 AGL400 Function IO151UDB3 GAC2/IO153UDB3 IO06RSB0 GNDQ IO10RSB0 IO19RSB0 IO26RSB0 IO30RSB0 IO40RSB0 IO46RSB0 GNDQ IO47RSB0 GBB2/IO61PPB1 IO53RSB0 IO63NDB1 NC NC NC NC NC VCC IO150PDB3 IO08RSB0 IO153VDB3 IO152VDB3 VMV0 VCCIB0 VCCIB0 IO25RSB0 IO31RSB0 VCCIB0 VCCIB0 VMV1 GBC2/IO62PDB1 IO65RSB1 IO52RSB0
v1.7
3 - 59
Package Pin Assignments
484-Pin FBGA Pin Number H19 H20 H21 H22 J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 J13 J14 J15 J16 J17 J18 J19 J20 J21 J22 K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 AGL400 Function IO66PDB1 VCC NC NC NC NC NC IO150NDB3 IO149NPB3 IO09RSB0 IO152UDB3 VCCIB3 GND VCC VCC VCC VCC GND VCCIB1 IO62NDB1 IO49RSB0 IO64PPB1 IO66NDB1 NC NC NC NC NC NC IO148NDB3 IO148PDB3 IO149PPB3 GFC1/IO147PPB3 VCCIB3 VCC GND
484-Pin FBGA Pin Number K11 K12 K13 K14 K15 K16 K17 K18 K19 K20 K21 K22 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 L15 L16 L17 L18 L19 L20 L21 L22 M1 M2 AGL400 Function GND GND GND VCC VCCIB1 GCC1/IO67PPB1 IO64NPB1 IO73PDB1 IO73NDB1 NC NC NC NC NC NC GFB0/IO146NPB3 GFA0/IO145NDB3 GFB1/IO146PPB3 VCOMPLF GFC0/IO147NPB3 VCC GND GND GND GND VCC GCC0/IO67NPB1 GCB1/IO68PPB1 GCA0/IO69NPB1 NC GCB0/IO68NPB1 NC NC NC NC NC
484-Pin FBGA Pin Number M3 M4 M5 M6 M7 M8 M9 M10 M11 M12 M13 M14 M15 M16 M17 M18 M19 M20 M21 M22 N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 N12 N13 N14 N15 N16 AGL400 Function NC GFA2/IO144PPB3 GFA1/IO145PDB3 VCCPLF IO143NDB3 GFB2/IO143PDB3 VCC GND GND GND GND VCC GCB2/IO71PPB1 GCA1/IO69PPB1 GCC2/IO72PPB1 NC GCA2/IO70PDB1 NC NC NC NC NC NC GFC2/IO142PDB3 IO144NPB3 IO141PPB3 IO120RSB2 VCCIB3 VCC GND GND GND GND VCC VCCIB1 IO71NPB1
3 -6 0
v1.7
IGLOO Packaging
484-Pin FBGA Pin Number N17 N18 N19 N20 N21 N22 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 R1 R2 R3 R4 R5 R6 R7 R8 AGL400 Function IO74RSB1 IO72NPB1 IO70NDB1 NC NC NC NC NC NC IO142NDB3 IO141NPB3 IO125RSB2 IO139RSB3 VCCIB3 GND VCC VCC VCC VCC GND VCCIB1 GDB0/IO78VPB1 IO76VDB1 IO76UDB1 IO75PDB1 NC NC NC NC NC VCC IO140PDB3 IO130RSB2 IO138NPB3 GEC0/IO137NPB3 VMV3
484-Pin FBGA Pin Number R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 AGL400 Function VCCIB2 VCCIB2 IO108RSB2 IO101RSB2 VCCIB2 VCCIB2 VMV2 IO83RSB2 GDB1/IO78UPB1 GDC1/IO77UDB1 IO75NDB1 VCC NC NC NC NC NC IO140NDB3 IO138PPB3 GEC1/IO137PPB3 IO131RSB2 GNDQ GEA2/IO134RSB2 IO117RSB2 IO111RSB2 IO99RSB2 IO94RSB2 IO87RSB2 GNDQ IO93RSB2 VJTAG GDC0/IO77VDB1 GDA1/IO79UDB1 NC NC NC
484-Pin FBGA Pin Number U1 U2 U3 U4 U5 U6 U7 U8 U9 U10 U11 U12 U13 U14 U15 U16 U17 U18 U19 U20 U21 U22 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 AGL400 Function NC NC NC GEB1/IO136PDB3 GEB0/IO136NDB3 VMV2 IO129RSB2 IO128RSB2 IO122RSB2 IO115RSB2 IO110RSB2 IO98RSB2 IO95RSB2 IO88RSB2 IO84RSB2 TCK VPUMP TRST GDA0/IO79VDB1 NC NC NC NC NC GND GEA1/IO135PDB3 GEA0/IO135NDB3 IO127RSB2 GEC2/IO132RSB2 IO123RSB2 IO118RSB2 IO112RSB2 IO106RSB2 IO100RSB2 IO96RSB2 IO89RSB2
v1.7
3 - 61
Package Pin Assignments
484-Pin FBGA Pin Number V15 V16 V17 V18 V19 V20 V21 V22 W1 W2 W3 W4 W5 W6 W7 W8 W9 W10 W11 W12 W13 W14 W15 W16 W17 W18 W19 W20 W21 W22 Y1 Y2 Y3 Y4 Y5 Y6 AGL400 Function IO85RSB2 GDB2/IO81RSB2 TDI NC TDO GND NC NC NC NC NC GND IO126RSB2 FF/GEB2/IO133RSB2 IO124RSB2 IO116RSB2 IO113RSB2 IO107RSB2 IO105RSB2 IO102RSB2 IO97RSB2 IO92RSB2 GDC2/IO82RSB2 IO86RSB2 GDA2/IO80RSB2 TMS GND NC NC NC VCCIB3 NC NC NC GND NC
484-Pin FBGA Pin Number Y7 Y8 Y9 Y10 Y11 Y12 Y13 Y14 Y15 Y16 Y17 Y18 Y19 Y20 Y21 Y22 AGL400 Function NC VCC VCC NC NC NC NC VCC VCC NC NC GND NC NC NC VCCIB1
3 -6 2
v1.7
IGLOO Packaging
484-Pin FBGA Pin Number A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 AA1 AA2 AA3 AA4 AA5 AA6 AA7 AA8 AA9 AA10 AA11 AA12 AA13 AA14 AGL600 Function GND GND VCCIB0 NC NC IO09RSB0 IO15RSB0 NC NC IO22RSB0 IO23RSB0 IO29RSB0 IO35RSB0 NC NC IO46RSB0 IO48RSB0 NC NC VCCIB0 GND GND GND VCCIB3 NC NC NC IO135RSB2 IO133RSB2 NC NC NC NC NC NC NC
484-Pin FBGA Pin Number AA15 AA16 AA17 AA18 AA19 AA20 AA21 AA22 AB1 AB2 AB3 AB4 AB5 AB6 AB7 AB8 AB9 AB10 AB11 AB12 AB13 AB14 AB15 AB16 AB17 AB18 AB19 AB20 AB21 AB22 B1 B2 B3 B4 B5 B6 AGL600 Function NC IO101RSB2 NC NC NC NC VCCIB1 GND GND GND VCCIB2 NC NC IO130RSB2 IO128RSB2 IO122RSB2 IO116RSB2 NC NC IO113RSB2 IO112RSB2 NC NC IO100RSB2 IO95RSB2 NC NC VCCIB2 GND GND GND VCCIB3 NC NC NC IO08RSB0
484-Pin FBGA Pin Number B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 AGL600 Function IO12RSB0 NC NC IO17RSB0 NC NC IO36RSB0 NC NC IO47RSB0 IO49RSB0 NC NC NC VCCIB1 GND VCCIB3 NC NC NC GND NC NC VCC VCC NC NC NC NC VCC VCC NC NC GND NC NC
v1.7
3 - 63
Package Pin Assignments
484-Pin FBGA Pin Number C21 C22 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 AGL600 Function NC VCCIB1 NC NC NC GND GAA0/IO00RSB0 GAA1/IO01RSB0 GAB0/IO02RSB0 IO11RSB0 IO16RSB0 IO18RSB0 IO28RSB0 IO34RSB0 IO37RSB0 IO41RSB0 IO43RSB0 GBB1/IO57RSB0 GBA0/IO58RSB0 GBA1/IO59RSB0 GND NC NC NC NC NC GND GAB2/IO173PDB3 GAA2/IO174PDB3 GNDQ GAB1/IO03RSB0 IO13RSB0 IO14RSB0 IO21RSB0 IO27RSB0 IO32RSB0
484-Pin FBGA Pin Number E13 E14 E15 E16 E17 E18 E19 E20 E21 E22 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 G1 G2 G3 G4 AGL600 Function IO38RSB0 IO42RSB0 GBC1/IO55RSB0 GBB0/IO56RSB0 IO52RSB0 GBA2/IO60PDB1 IO60NDB1 GND NC NC NC NC NC IO173NDB3 IO174NDB3 VMV3 IO07RSB0 GAC0/IO04RSB0 GAC1/IO05RSB0 IO20RSB0 IO24RSB0 IO33RSB0 IO39RSB0 IO44RSB0 GBC0/IO54RSB0 IO51RSB0 VMV0 IO61NPB1 IO63PDB1 NC NC NC IO170NDB3 IO170PDB3 NC IO171NDB3
484-Pin FBGA Pin Number G5 G6 G7 G8 G9 G10 G11 G12 G13 G14 G15 G16 G17 G18 G19 G20 G21 G22 H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 H13 H14 H15 H16 H17 H18 AGL600 Function IO171PDB3 GAC2/IO172PDB3 IO06RSB0 GNDQ IO10RSB0 IO19RSB0 IO26RSB0 IO30RSB0 IO40RSB0 IO45RSB0 GNDQ IO50RSB0 GBB2/IO61PPB1 IO53RSB0 IO63NDB1 NC NC NC NC NC VCC IO166PDB3 IO167NPB3 IO172NDB3 IO169NDB3 VMV0 VCCIB0 VCCIB0 IO25RSB0 IO31RSB0 VCCIB0 VCCIB0 VMV1 GBC2/IO62PDB1 IO67PPB1 IO64PPB1
3 -6 4
v1.7
IGLOO Packaging
484-Pin FBGA Pin Number H19 H20 H21 H22 J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 J13 J14 J15 J16 J17 J18 J19 J20 J21 J22 K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 AGL600 Function IO66PDB1 VCC NC NC NC NC NC IO166NDB3 IO168NPB3 IO167PPB3 IO169PDB3 VCCIB3 GND VCC VCC VCC VCC GND VCCIB1 IO62NDB1 IO64NPB1 IO65PPB1 IO66NDB1 NC IO68PDB1 IO68NDB1 IO157PDB3 IO157NDB3 NC IO165NDB3 IO165PDB3 IO168PPB3 GFC1/IO164PPB3 VCCIB3 VCC GND
484-Pin FBGA Pin Number K11 K12 K13 K14 K15 K16 K17 K18 K19 K20 K21 K22 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 L15 L16 L17 L18 L19 L20 L21 L22 M1 M2 AGL600 Function GND GND GND VCC VCCIB1 GCC1/IO69PPB1 IO65NPB1 IO75PDB1 IO75NDB1 NC IO76NDB1 IO76PDB1 NC IO155PDB3 NC GFB0/IO163NPB3 GFA0/IO162NDB3 GFB1/IO163PPB3 VCOMPLF GFC0/IO164NPB3 VCC GND GND GND GND VCC GCC0/IO69NPB1 GCB1/IO70PPB1 GCA0/IO71NPB1 IO67NPB1 GCB0/IO70NPB1 IO77PDB1 IO77NDB1 IO78NPB1 NC IO155NDB3
484-Pin FBGA Pin Number M3 M4 M5 M6 M7 M8 M9 M10 M11 M12 M13 M14 M15 M16 M17 M18 M19 M20 M21 M22 N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 N12 N13 N14 N15 N16 AGL600 Function IO158NPB3 GFA2/IO161PPB3 GFA1/IO162PDB3 VCCPLF IO160NDB3 GFB2/IO160PDB3 VCC GND GND GND GND VCC GCB2/IO73PPB1 GCA1/IO71PPB1 GCC2/IO74PPB1 IO80PPB1 GCA2/IO72PDB1 IO79PPB1 IO78PPB1 NC IO154NDB3 IO154PDB3 NC GFC2/IO159PDB3 IO161NPB3 IO156PPB3 IO129RSB2 VCCIB3 VCC GND GND GND GND VCC VCCIB1 IO73NPB1
v1.7
3 - 65
Package Pin Assignments
484-Pin FBGA Pin Number N17 N18 N19 N20 N21 N22 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 R1 R2 R3 R4 R5 R6 R7 R8 AGL600 Function IO80NPB1 IO74NPB1 IO72NDB1 NC IO79NPB1 NC NC IO153PDB3 IO153NDB3 IO159NDB3 IO156NPB3 IO151PPB3 IO158PPB3 VCCIB3 GND VCC VCC VCC VCC GND VCCIB1 GDB0/IO87NPB1 IO85NDB1 IO85PDB1 IO84PDB1 NC IO81PDB1 NC NC NC VCC IO150PDB3 IO151NPB3 IO147NPB3 GEC0/IO146NPB3 VMV3
484-Pin FBGA Pin Number R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 AGL600 Function VCCIB2 VCCIB2 IO117RSB2 IO110RSB2 VCCIB2 VCCIB2 VMV2 IO94RSB2 GDB1/IO87PPB1 GDC1/IO86PDB1 IO84NDB1 VCC IO81NDB1 IO82PDB1 IO152PDB3 IO152NDB3 NC IO150NDB3 IO147PPB3 GEC1/IO146PPB3 IO140RSB2 GNDQ GEA2/IO143RSB2 IO126RSB2 IO120RSB2 IO108RSB2 IO103RSB2 IO99RSB2 GNDQ IO92RSB2 VJTAG GDC0/IO86NDB1 GDA1/IO88PDB1 NC IO83PDB1 IO82NDB1
484-Pin FBGA Pin Number U1 U2 U3 U4 U5 U6 U7 U8 U9 U10 U11 U12 U13 U14 U15 U16 U17 U18 U19 U20 U21 U22 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 AGL600 Function IO149PDB3 IO149NDB3 NC GEB1/IO145PDB3 GEB0/IO145NDB3 VMV2 IO138RSB2 IO136RSB2 IO131RSB2 IO124RSB2 IO119RSB2 IO107RSB2 IO104RSB2 IO97RSB2 VMV1 TCK VPUMP TRST GDA0/IO88NDB1 NC IO83NDB1 NC NC NC GND GEA1/IO144PDB3 GEA0/IO144NDB3 IO139RSB2 GEC2/IO141RSB2 IO132RSB2 IO127RSB2 IO121RSB2 IO114RSB2 IO109RSB2 IO105RSB2 IO98RSB2
3 -6 6
v1.7
IGLOO Packaging
484-Pin FBGA Pin Number V15 V16 V17 V18 V19 V20 V21 V22 W1 W2 W3 W4 W5 W6 W7 W8 W9 W10 W11 W12 W13 W14 W15 W16 W17 W18 W19 W20 W21 W22 Y1 Y2 Y3 Y4 Y5 Y6 AGL600 Function IO96RSB2 GDB2/IO90RSB2 TDI GNDQ TDO GND NC NC NC IO148PDB3 NC GND IO137RSB2 FF/GEB2/IO142RSB2 IO134RSB2 IO125RSB2 IO123RSB2 IO118RSB2 IO115RSB2 IO111RSB2 IO106RSB2 IO102RSB2 GDC2/IO91RSB2 IO93RSB2 GDA2/IO89RSB2 TMS GND NC NC NC VCCIB3 IO148NDB3 NC NC GND NC
484-Pin FBGA Pin Number Y7 Y8 Y9 Y10 Y11 Y12 Y13 Y14 Y15 Y16 Y17 Y18 Y19 Y20 Y21 Y22 AGL600 Function NC VCC VCC NC NC NC NC VCC VCC NC NC GND NC NC NC VCCIB1
v1.7
3 - 67
Package Pin Assignments
484-Pin FBGA Pin Number A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 AA1 AA2 AA3 AA4 AA5 AA6 AA7 AA8 AA9 AA10 AA11 AA12 AA13 AA14 AGL1000 Function GND GND VCCIB0 IO07RSB0 IO09RSB0 IO13RSB0 IO18RSB0 IO20RSB0 IO26RSB0 IO32RSB0 IO40RSB0 IO41RSB0 IO53RSB0 IO59RSB0 IO64RSB0 IO65RSB0 IO67RSB0 IO69RSB0 NC VCCIB0 GND GND GND VCCIB3 NC IO181RSB2 IO178RSB2 IO175RSB2 IO169RSB2 IO166RSB2 IO160RSB2 IO152RSB2 IO146RSB2 IO139RSB2 IO133RSB2 NC
484-Pin FBGA Pin Number AA15 AA16 AA17 AA18 AA19 AA20 AA21 AA22 AB1 AB2 AB3 AB4 AB5 AB6 AB7 AB8 AB9 AB10 AB11 AB12 AB13 AB14 AB15 AB16 AB17 AB18 AB19 AB20 AB21 AB22 B1 B2 B3 B4 B5 B6 AGL1000 Function NC IO122RSB2 IO119RSB2 IO117RSB2 NC NC VCCIB1 GND GND GND VCCIB2 IO180RSB2 IO176RSB2 IO173RSB2 IO167RSB2 IO162RSB2 IO156RSB2 IO150RSB2 IO145RSB2 IO144RSB2 IO132RSB2 IO127RSB2 IO126RSB2 IO123RSB2 IO121RSB2 IO118RSB2 NC VCCIB2 GND GND GND VCCIB3 NC IO06RSB0 IO08RSB0 IO12RSB0
484-Pin FBGA Pin Number B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 AGL1000 Function IO15RSB0 IO19RSB0 IO24RSB0 IO31RSB0 IO39RSB0 IO48RSB0 IO54RSB0 IO58RSB0 IO63RSB0 IO66RSB0 IO68RSB0 IO70RSB0 NC NC VCCIB1 GND VCCIB3 IO220PDB3 NC NC GND IO10RSB0 IO14RSB0 VCC VCC IO30RSB0 IO37RSB0 IO43RSB0 NC VCC VCC NC NC GND NC NC
3 -6 8
v1.7
IGLOO Packaging
484-Pin FBGA Pin Number C21 C22 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 AGL1000 Function NC VCCIB1 IO219PDB3 IO220NDB3 NC GND GAA0/IO00RSB0 GAA1/IO01RSB0 GAB0/IO02RSB0 IO16RSB0 IO22RSB0 IO28RSB0 IO35RSB0 IO45RSB0 IO50RSB0 IO55RSB0 IO61RSB0 GBB1/IO75RSB0 GBA0/IO76RSB0 GBA1/IO77RSB0 GND NC NC NC IO219NDB3 NC GND GAB2/IO224PDB3 GAA2/IO225PDB3 GNDQ GAB1/IO03RSB0 IO17RSB0 IO21RSB0 IO27RSB0 IO34RSB0 IO44RSB0
484-Pin FBGA Pin Number E13 E14 E15 E16 E17 E18 E19 E20 E21 E22 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 G1 G2 G3 G4 AGL1000 Function IO51RSB0 IO57RSB0 GBC1/IO73RSB0 GBB0/IO74RSB0 IO71RSB0 GBA2/IO78PDB1 IO81PDB1 GND NC IO84PDB1 NC IO215PDB3 IO215NDB3 IO224NDB3 IO225NDB3 VMV3 IO11RSB0 GAC0/IO04RSB0 GAC1/IO05RSB0 IO25RSB0 IO36RSB0 IO42RSB0 IO49RSB0 IO56RSB0 GBC0/IO72RSB0 IO62RSB0 VMV0 IO78NDB1 IO81NDB1 IO82PPB1 NC IO84NDB1 IO214NDB3 IO214PDB3 NC IO222NDB3
484-Pin FBGA Pin Number G5 G6 G7 G8 G9 G10 G11 G12 G13 G14 G15 G16 G17 G18 G19 G20 G21 G22 H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 H13 H14 H15 H16 H17 H18 AGL1000 Function IO222PDB3 GAC2/IO223PDB3 IO223NDB3 GNDQ IO23RSB0 IO29RSB0 IO33RSB0 IO46RSB0 IO52RSB0 IO60RSB0 GNDQ IO80NDB1 GBB2/IO79PDB1 IO79NDB1 IO82NPB1 IO85PDB1 IO85NDB1 NC NC NC VCC IO217PDB3 IO218PDB3 IO221NDB3 IO221PDB3 VMV0 VCCIB0 VCCIB0 IO38RSB0 IO47RSB0 VCCIB0 VCCIB0 VMV1 GBC2/IO80PDB1 IO83PPB1 IO86PPB1
v1.7
3 - 69
Package Pin Assignments
484-Pin FBGA Pin Number H19 H20 H21 H22 J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 J13 J14 J15 J16 J17 J18 J19 J20 J21 J22 K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 AGL1000 Function IO87PDB1 VCC NC NC IO212NDB3 IO212PDB3 NC IO217NDB3 IO218NDB3 IO216PDB3 IO216NDB3 VCCIB3 GND VCC VCC VCC VCC GND VCCIB1 IO83NPB1 IO86NPB1 IO90PPB1 IO87NDB1 NC IO89PDB1 IO89NDB1 IO211PDB3 IO211NDB3 NC IO210PPB3 IO213NDB3 IO213PDB3 GFC1/IO209PPB3 VCCIB3 VCC GND
484-Pin FBGA Pin Number K11 K12 K13 K14 K15 K16 K17 K18 K19 K20 K21 K22 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 L15 L16 L17 L18 L19 L20 L21 L22 M1 M2 AGL1000 Function GND GND GND VCC VCCIB1 GCC1/IO91PPB1 IO90NPB1 IO88PDB1 IO88NDB1 IO94NPB1 IO98NDB1 IO98PDB1 NC IO200PDB3 IO210NPB3 GFB0/IO208NPB3 GFA0/IO207NDB3 GFB1/IO208PPB3 VCOMPLF GFC0/IO209NPB3 VCC GND GND GND GND VCC GCC0/IO91NPB1 GCB1/IO92PPB1 GCA0/IO93NPB1 IO96NPB1 GCB0/IO92NPB1 IO97PDB1 IO97NDB1 IO99NPB1 NC IO200NDB3
484-Pin FBGA Pin Number M3 M4 M5 M6 M7 M8 M9 M10 M11 M12 M13 M14 M15 M16 M17 M18 M19 M20 M21 M22 N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 N12 N13 N14 N15 N16 AGL1000 Function IO206NDB3 GFA2/IO206PDB3 GFA1/IO207PDB3 VCCPLF IO205NDB3 GFB2/IO205PDB3 VCC GND GND GND GND VCC GCB2/IO95PPB1 GCA1/IO93PPB1 GCC2/IO96PPB1 IO100PPB1 GCA2/IO94PPB1 IO101PPB1 IO99PPB1 NC IO201NDB3 IO201PDB3 NC GFC2/IO204PDB3 IO204NDB3 IO203NDB3 IO203PDB3 VCCIB3 VCC GND GND GND GND VCC VCCIB1 IO95NPB1
3 -7 0
v1.7
IGLOO Packaging
484-Pin FBGA Pin Number N17 N18 N19 N20 N21 N22 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 R1 R2 R3 R4 R5 R6 R7 R8 AGL1000 Function IO100NPB1 IO102NDB1 IO102PDB1 NC IO101NPB1 IO103PDB1 NC IO199PDB3 IO199NDB3 IO202NDB3 IO202PDB3 IO196PPB3 IO193PPB3 VCCIB3 GND VCC VCC VCC VCC GND VCCIB1 GDB0/IO112NPB1 IO106NDB1 IO106PDB1 IO107PDB1 NC IO104PDB1 IO103NDB1 NC IO197PPB3 VCC IO197NPB3 IO196NPB3 IO193NPB3 GEC0/IO190NPB3 VMV3
484-Pin FBGA Pin Number R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 AGL1000 Function VCCIB2 VCCIB2 IO147RSB2 IO136RSB2 VCCIB2 VCCIB2 VMV2 IO110NDB1 GDB1/IO112PPB1 GDC1/IO111PDB1 IO107NDB1 VCC IO104NDB1 IO105PDB1 IO198PDB3 IO198NDB3 NC IO194PPB3 IO192PPB3 GEC1/IO190PPB3 IO192NPB3 GNDQ GEA2/IO187RSB2 IO161RSB2 IO155RSB2 IO141RSB2 IO129RSB2 IO124RSB2 GNDQ IO110PDB1 VJTAG GDC0/IO111NDB1 GDA1/IO113PDB1 NC IO108PDB1 IO105NDB1
484-Pin FBGA Pin Number U1 U2 U3 U4 U5 U6 U7 U8 U9 U10 U11 U12 U13 U14 U15 U16 U17 U18 U19 U20 U21 U22 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 AGL1000 Function IO195PDB3 IO195NDB3 IO194NPB3 GEB1/IO189PDB3 GEB0/IO189NDB3 VMV2 IO179RSB2 IO171RSB2 IO165RSB2 IO159RSB2 IO151RSB2 IO137RSB2 IO134RSB2 IO128RSB2 VMV1 TCK VPUMP TRST GDA0/IO113NDB1 NC IO108NDB1 IO109PDB1 NC NC GND GEA1/IO188PDB3 GEA0/IO188NDB3 IO184RSB2 GEC2/IO185RSB2 IO168RSB2 IO163RSB2 IO157RSB2 IO149RSB2 IO143RSB2 IO138RSB2 IO131RSB2
v1.7
3 - 71
Package Pin Assignments
484-Pin FBGA Pin Number V15 V16 V17 V18 V19 V20 V21 V22 W1 W2 W3 W4 W5 W6 W7 W8 W9 W10 W11 W12 W13 W14 W15 W16 W17 W18 W19 W20 W21 W22 Y1 Y2 Y3 Y4 Y5 Y6 AGL1000 Function IO125RSB2 GDB2/IO115RSB2 TDI GNDQ TDO GND NC IO109NDB1 NC IO191PDB3 NC GND IO183RSB2 FF/GEB2/IO186RSB2 IO172RSB2 IO170RSB2 IO164RSB2 IO158RSB2 IO153RSB2 IO142RSB2 IO135RSB2 IO130RSB2 GDC2/IO116RSB2 IO120RSB2 GDA2/IO114RSB2 TMS GND NC NC NC VCCIB3 IO191NDB3 NC IO182RSB2 GND IO177RSB2
484-Pin FBGA Pin Number Y7 Y8 Y9 Y10 Y11 Y12 Y13 Y14 Y15 Y16 Y17 Y18 Y19 Y20 Y21 Y22 AGL1000 Function IO174RSB2 VCC VCC IO154RSB2 IO148RSB2 IO140RSB2 NC VCC VCC NC NC GND NC NC NC VCCIB1
3 -7 2
v1.7
IGLOO Packaging
Part Number and Revision Date
Part Number 51700095-003-7 Revised December 2008
List of Changes
The following table lists critical changes that were made in the current version of the chapter. Previous Version v1.6 (October 2008) Changes in Current Version (v1.7) The "48-Pin QFP" pin table is new. The "68-Pin QFN" pin table is new. The AGL600 Function for pin K15 in the "484-Pin FBGA" table was changed to VCCIB1. v1.5 (June 2008) The "196-pin CSP" table for the AGL400 device is new. The "144-Pin FBGA" table for the AGL400 device is new. The "256-Pin FBGA" table for the AGL400 device is new. The "484-Pin FBGA" table for the AGL400 device is new. v1.4 (June 2008) Pin numbers were added to the "68-Pin QFN" package diagram. Note 2 was added below the diagram. The "132-Pin QFN" package diagram was updated to include D1 to D4. In addition, note 1 was changed from top view to bottom view, and note 2 is new. v1.3 (February 2008) v1.2 (February 2008) v1.1 (January 2008) v1.0 (January 2008) Advance v0.7 (November 2007) Advance v0.6 (November 2007) The "68-Pin QFN" package drawing was updated to include numbers on pins 1 and 68. The "281-Pin CSP" package and pin table was added for AGL1000. The "196-Pin CSP" package and pin table was added for AGL250. The "68-Pin QFN" section is new. The "196-Pin CSP" package and pin table was added for AGL125. This document was previously in datasheet Advance v0.7. As a result of moving to the handbook format, Actel has restarted the version numbers. The new version number is v1.0. The "121-Pin CSP" and "281-Pin CSP" packages are new. The "81-Pin CSP" table for the AGL030 device was updated to change the G6 pin function to IO44RSB1 and the JG pin function to IO45RSB1. The "121-Pin CSP" table for the AGL060 device is new. The "256-Pin FBGA" table for the AGL1000 device is new. The "281-Pin CSP" table for the AGL 600 device is new. The "100-Pin VQFP" table for the AGL060 device is new. The "144-Pin FBGA" table for the AGL250 device is new. The "144-Pin FBGA" table for the AGL1000 device is new. The "484-Pin FBGA" table for the AGL600 device is new. The "484-Pin FBGA" table for the AGL1000 device is new. Advance v0.5 (September 2007) The "81-Pin µCSP" table for the AGL030 device is new. The "81-Pin CSP" table for the AGL030 device is new. Page 3-22 3-25 3-64 3-12 3-44 3-55 3-64 3-23 3-26
3-23 3-18 3-10 3-23 3-7 N/A
4-5, 4-7 4-4 4-6 4-34 4-8 4-18 4-24 4-28 4-38 4-43 4-3 4-1
v1.7
3 - 73
Package Pin Assignments
Datasheet Categories
Categories
In order to provide the latest information to designers, some datasheets are published before data has been fully characterized. Datasheets are designated as "Product Brief," "Advance," "Preliminary," and "Production." The definitions of these categories are as follows:
Product Brief
The product brief is a summarized version of a datasheet (advance or production) and contains general product information. This document gives an overview of specific device and family information.
Advance
This version contains initial estimated information based on simulation, other products, devices, or speed grades. This information can be used as estimates, but not for production. This label only applies to the DC and Switching Characteristics chapter of the datasheet and will only be used when the data has not been fully characterized.
Preliminary
The datasheet contains information based on simulation and/or initial characterization. The information is believed to be correct, but changes are possible.
Unmarked (production)
This version contains information that is considered to be final.
Export Administration Regulations (EAR)
The products described in this document are subject to the Export Administration Regulations (EAR). They could require an approved export license prior to export from the United States. An export includes release of product or disclosure of technology to a foreign national inside or outside the United States.
Actel Safety Critical, Life Support, and High-Reliability Applications Policy
The Actel products described in this advance status document may not have completed Actel’s qualification process. Actel may amend or enhance products during the product introduction and qualification process, resulting in changes in device functionality or performance. It is the responsibility of each customer to ensure the fitness of any Actel product (but especially a new product) for a particular purpose, including appropriateness for safety-critical, life-support, and other high-reliability applications. Consult Actel’s Terms and Conditions for specific liability exclusions relating to life-support applications. A reliability report covering all of Actel’s products is available on the Actel website at http://www.actel.com/documents/ORT_Report.pdf. Actel also offers a variety of enhanced qualification and lot acceptance screening procedures. Contact your local Actel sales office for additional reliability information.
3 -7 4
v1.7
IGLOO Packaging
v1.7
3 - 75
Actel and the Actel logo are registered trademarks of Actel Corporation. All other trademarks are the property of their owners.
www.actel.com
Actel is the leader in low-power and mixed-signal FPGAs and offers the most comprehensive portfolio of system and power management solutions. Power Matters. Learn more at www.actel.com. Actel Corporation 2061 Stierlin Court Mountain View, CA 94043-4655 USA Phone 650.318.4200 Fax 650.318.4600 Actel Europe Ltd. River Court,Meadows Business Park Station Approach, Blackwater Camberley Surrey GU17 9AB United Kingdom Phone +44 (0) 1276 609 300 Fax +44 (0) 1276 607 540 Actel Japan EXOS Ebisu Buillding 4F 1-24-14 Ebisu Shibuya-ku Tokyo 150 Japan Phone +81.03.3445.7671 Fax +81.03.3445.7668 http://jp.actel.com Actel Hong Kong Room 2107, China Resources Building 26 Harbour Road Wanchai, Hong Kong Phone +852 2185 6460 Fax +852 2185 6488 www.actel.com.cn
51700095-005-12/12.08
工商网监
湘ICP备2023018690号
