APA150-PQ896A

Automotive Supplement Automotive-Grade ProASIC Features and Benefits High Capacity • • • • • • • 75,000 to 1 Million System Gates 27k to 198kbits of Two-Port SRAM 66 to 642 User I/Os 0.22µ 4LM Flash-based CMOS Process Live at Power-Up, Single-Chip Solution No Configuration Device Required Retains Programmed Design during Power-Down/Power-Up Cycles PLUS TM Flash Family FPGAs High-Speed, Very Long-Line Network High Performance, Low-Skew, Splittable Global Network 100% Utilization and >95% Routability Schmitt-Trigger Option on Every Input 2.5V/3.3V Support with Individually-Selectable Voltage and Slew Rate Bidirectional Global I/Os Compliance with PCI Specification Revision 2.2 Boundary-Scan Test IEEE Std. 1149.1 (JTAG) Compliant Pin Compatible Packages across ProASICPLUS Family PLLs with Flexible Phase, Multiply/Divide and Delay Capabilities Internal and/or External Dynamic PLL Configuration Two LVPECL Differential Pairs for Clock or Data Inputs Flexibility with Choice of Industry-Standard Frontend Tools Efficient Design through Front-End Timing and Gate Optimization In-System Programming (ISP) via JTAG Port ACTgen Netlist Generation Ensures Optimal Usage of Embedded Memory Blocks 24 SRAM and FIFO Configurations with Synchronous and Asynchronous Operation up to 150 MHz (typical) • • • • • • • • • • • • • • I/O Reprogrammable Flash Technology Unique Clock Conditioning Circuitry Extended Temperature Range • • • • • Supports Automotive Temperature Range -40 to 125°C (Junction) 3.3V, 32-Bit PCI (up to 50 MHz) Two Integrated PLLs External System Performance up to 150 MHz Industry’s Most Effective Security Key (FlashLock™) Prevents Read Back of Programming Bitstream Low Impedance Flash Switches Segmented Hierarchical Routing Structure Small, Efficient, Configurable (Combinatorial or Sequential) Logic Cells Ultra-Fast Local and Long-Line Network APA075 75,000 3,072 27k 12 2 2 4 24 158 Yes Yes 100 208 144 APA150 150,000 6,144 36k 16 2 2 4 32 186 Yes Yes 100 208 144, 256 Performance Standard FPGA and ASIC Design Flow Secure Programming Low Power • • • ISP Support • • • SRAMs and FIFOs High Performance Routing Hierarchy • Table 1 • Automotive-Grade ProASICPLUS Product Profile Device Maximum System Gates Maximum Tiles (Registers) Embedded RAM Bits (k=1,024 bits) Embedded RAM Blocks (256x9) LVPECL PLL Global Networks Maximum Clocks Maximum User I/Os JTAG ISP PCI Package (by pin count) TQFP PQFP FBGA APA300 300,000 8,192 72k 32 2 2 4 32 186 Yes Yes – 208 144, 256 APA450 450,000 12,288 108k 48 2 2 4 48 344 Yes Yes – 208 144, 256, 484 APA600 600,000 21,504 126k 56 2 2 4 56 370 Yes Yes – 208 256, 484 APA750 750,000 32,768 144k 64 2 2 4 64 562 Yes Yes – 208 896 APA1000 1,000,000 56,320 198k 88 2 2 4 88 642 Yes Yes – 208 896 February 2004 © 2004 Actel Corporation 1 Automotive-Grade ProASICPLUS Flash Family FPGAs Ordering Information APA1000 FG 896 A Application A = Automotive (-40 to 125˚C) Package Lead Count Package Type TQ = Thin Quad Flat Pack (1.4mm pitch) PQ = Plastic Quad Flat Pack (0.5mm pitch) FG = Fine Pitch Ball Grid Array (1.0mm pitch) Part Number APA075 APA150 APA300 APA450 APA600 APA750 APA1000 = = = = = = = 75,000 Equivalent System Gates 150,000 Equivalent System Gates 300,000 Equivalent System Gates 450,000 Equivalent System Gates 600,000 Equivalent System Gates 750,000 Equivalent System Gates 1,000,000 Equivalent System Gates Plastic Device Resources User I/Os* Device APA075 APA150 APA300 APA450 APA600 APA750 APA1000 TQFP 100-Pin 66 66 PQFP 208-Pin 158 158 158 158 158 158 158 FBGA 144-Pin 100 100 100 100 186 186 186 186 344 370 562 642 FBGA 256-Pin FBGA 484-Pin FBGA 896-Pin Package Definitions TQFP = Thin Quad Flat Pack, PQFP = Plastic Quad Flat Pack, FBGA = Fine Pitch Ball Grid Array *Each pair of PECL I/Os were counted as one user I/O. Speed Grade Matrix Std Automotive-Grade ✔ Contact your local Actel sales representative for device availability. 2 A u t o m o t i v e S u pp l e m e n t Automotive-Grade ProASICPLUS Flash Family FPGAs General Description ProASICPLUS devices offer a reprogrammable design integration solution at the automotive temperature range (-40°C to +125°C) through the use of nonvolatile Flash technology. ProASICPLUS devices have a fine-grain architecture, similar to ASICs, and enable engineers to design high-density systems using existing ASIC or FPGA design flows and tools. Automotive-grade ProASICPLUS devices offer up to 1 million system gates, support up to 198kbits of two-port SRAM and 642 user I/Os and provide 50 MHz PCI performance. The nonvolatile and reprogrammable Flash technology enables ProASICPLUS devices to be live at power-up, and no external boot PROM is required to support device programming. While on-board security mechanisms prevent any access to the programmed information, reprogramming can be performed in-system to support future design iterations and field upgrades. The ProASICPLUS device architecture mitigates the complexity of ASIC migration at higher user volume, making the automotive-grade ProASICPLUS a cost-effective solution for in-cabin telematics and automobile interconnect applications. The ProASICPLUS family is built on an advanced Flashbased 0.22µm LVCMOS process with four layers of metal. Standard CMOS design techniques are used to implement logic and control functions, including the PLLs and LVPECL inputs, resulting in predictable performance fully compatible with gate arrays. The ProASICPLUS architecture provides granularity comparable to gate arrays. The device core consists of a Sea-of-Tiles. Each tile can be configured as a flip-flop, latch, or three-input/one-output logic function by programming the appropriate Flash switches. The combination of fine granularity, flexible routing resources, and abundant Flash switches allows 100% utilization and over 95% routability for highly congested designs. Tiles and larger functions are interconnected through a four-level routing hierarchy. devices feature Automotive-grade ProASICPLUS embedded two-port SRAM blocks with built-in FIFO/RAM control logic and user-defined depth and width. Users can select programming for synchronous or asynchronous operation, as well as parity generation or checking. The automotive-grade ProASICPLUS devices offer a unique clock conditioning circuit (CCC), with two clock conditioning blocks in each device. Each block provides a phase-locked loop (PLL) core, delay lines, phase shifts (0°, 90°, 180°, 270°), and clock multipliers/dividers, as well as the circuitry required to provide bidirectional access to the PLL. The PLL block contains four programmable frequency dividers, which allow the incoming clock signal to be divided by a wide range of factors from 1 to 64. The clock conditioning circuit can perform a positive/ negative clock delay operation in increments of 0.25 ns by up to 8 ns. The PLL can be configured internally or externally during operation without redesigning or reprogramming the part. In addition to the PLL, there are two LVPECL differential input pairs to accommodate high speed clock and data inputs. The automotive-grade ProASICPLUS devices are available in a variety of high-performance plastic packages to simplify the system board design. To support for comprehensive, lower cost board-level testing, Actel’s ProASICPLUS devices are fully compatible with IEEE Standard 1149.1 for test access port and boundary-scan test architecture. A u t om ot i v e S u p pl e m e n t 3 Automotive-Grade ProASICPLUS Flash Family FPGAs Operating Conditions Table 1 • Absolute Maximum Ratings* Parameter Supply Voltage Core (VDD) Supply Voltage I/O Ring (VDDP) DC Input Voltage PCI DC Input Voltage PCI DC Input Clamp Current (absolute) LVPECL Input Voltage GND VIN < –1V or VIN = VDDP + 1V Condition Minimum –0.3 –0.3 –0.3 –1.0 10 –0.3 0 VDDP + 0.5 0 Maximum 3.0 4.0 VDDP + 0.3 VDDP + 1.0 Units V V V V mA V V Note: *Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. Performance Retention Actel guarantees the performance numbers presented in the Actel Designer timing analysis software and in this datasheet, as long as the specified device performance retention period is not exceeded. For devices operated and stored at 110°C or less, the performance retention period is 20 years after programming. For devices operated and stored at temperatures greater than 110°C, refer to Table 2 on page 5 to determine the performance retention period. Actel does not guarantee performance if the performance retention period is exceeded. Evaluate the percentage of time spent at the highest temperature, then determine the next highest temperature to which the device will be exposed. In Table 2 on page 5, find the temperature profile that most closely matches the application. For example, the ambient temperature of a system cycles between 100°C (25% of the time) and 50°C (75% of the time). No forced ventilation cooling system is in use. An APA600-PQ208A FPGA operates in the system, dissipating 1W. The package thermal resistance (junction-to-ambient) in still air is 20°C/W, indicating that the junction temperature of the FPGA will be 120°C (25% of the time) and 70°C (75% of the time). The entry in Table 2 on page 5, which most closely matches the application, is 25% at 125°C with 75% at 110°C. Performance retention in this example is at least 16.0 years. Note that exceeding the stated retention period may result in a performance degradation in the FPGA below the worst-case performance indicated in the Actel Timer. To ensure that performance does not degrade below the worstcase values in the Actel Timer, the FPGA must be reprogrammed within the performance retention period. In addition, note that performance retention is independent of whether or not the FPGA is operating. The retention period of a device in storage at a given temperature will be the same as the retention period of a device operating at that junction temperature. 4 A u t o m o t i v e S u pp l e m e n t Automotive-Grade ProASICPLUS Flash Family FPGAs Table 2 • Performance Retention Time at TJ 110°C or below 100% 99% 98% 95% 90% 85% 80% 75% 70% 60% 50% 25% 0% Time at TJ 125°C or below 0% 1% 2% 5% 10% 15% 20% 25% 30% 40% 50% 75% 100% Minimum Program Retention (Years) 20.0 19.8 19.6 19.0 18.2 17.4 16.7 16.0 15.4 14.3 13.3 11.4 10.0 Table 3 • Nominal Supply Voltages Mode VDD 2.5V Output 2.5V 3.3V Output* 2.5V Note: *Automotive-grade ProASICPLUS devices do not support mixed-mode I/Os. Table 4 • Recommended Maximum Operating Conditions for Programming and PLL Supplies* Automotive Parameter VPP VPN IPP IPN AVDD AGND VDDP 2.5V 3.3V Condition During Programming Normal Operation During Programming Normal Operation During Programming During Programming Minimum 15.8 0 –13.8 –13.8 Maximum 16.5 16.5 –13.2 0 25 10 Units V V V V mA mA V V VDD GND VDD GND Note: *Devices should not be operated outside the Recommended Operating Conditions. A u t om ot i v e S u p pl e m e n t 5 Automotive-Grade ProASICPLUS Flash Family FPGAs Table 5 • Recommended Operating Conditions* Limits Parameter DC Supply Voltage (2.5V I/Os) DC Supply Voltage (3.3V I/Os) Operating Junction Temperature Range Symbol VDD & VDDP VDDP VDD TJ Automotive 2.5V ± 5% 3.3V ± 5% 2.5V ± 5% -40°C to125°C Note: *Devices should not be operated outside the Recommended Operating Conditions. Table 6 • DC Electrical Specifications (VDD and VDDP = 2.5V ±5%) Automotive1 Symbol VOH Parameter Output High Voltage High Drive (OB25LPH) Conditions IOH = –6 mA IOH = –12 mA IOH = –24 mA IOH = –3 mA IOH = –6 mA IOH = –8 mA IOL = 8 mA IOL = 15 mA IOL = 24 mA IOL = 4 mA IOL = 8 mA IOL = 15 mA 1.7 –0.3 VIN ≥ 1.25V 6 0.3 with pull up (VIN = GND) without pull up (VIN = GND or VDD) IDDQ IOZ IOSH Quiescent Supply Current (standby) VIN = GND2 or VDD –50 –120 –100 100 30 10 10 –240 –50 5.0 0.35 Min. 2.1 2.0 1.7 2.1 1.9 1.7 0.2 0.4 0.7 0.2 0.4 0.7 VDDP + 0.3 0.7 56 0.45 – 20 50 20 50 V V kΩ V µA µA mA µA mA V Typ. Max. Units V Low Drive (OB25LPL) VOL Output Low Voltage High Drive (OB25LPH) Low Drive (OB25LPL) VIH VIL Input High Voltage Input Low Voltage RWEAKPULLUP Weak Pull-up Resistance (OTB25LPU) HYST IIN Input Hysteresis Schmitt Input Current Tristate Output Leakage Current VOH = GND or VDD Output Short Circuit Current High High Drive (OB25LPH) VIN = VSS Low Drive (OB25LPL) VIN = VSS Output Short Circuit Current Low High Drive (OB25LPH) VIN = VDDP Low Drive (OB25LPL) VIN = VDDP I/O Pad Capacitance Clock Input Pad Capacitance IOSL mA pF pF CI/O CCLK Notes: 1. All process conditions. Junction Temperature: –40 to +125°C. 2. No pull-up resistor. 6 A u t o m o t i v e S u pp l e m e n t Automotive-Grade ProASICPLUS Flash Family FPGAs Table 7 • DC Electrical Specifications (VDDP = 3.3V ±5% and VDD 2.5V ±5%) Automotive1 Symbol VOH Parameter Conditions Min. 0.9∗VDDP 2.4 V 3.3V I/O, Low Drive (OB33L) VOL IOH = –6 mA IOH = –12 mA 0.9∗VDDP 2.4 0.1VDDP 0.4 0.7 V 3.3V I/O, Low Drive (OB33L) IOL = 7 mA IOL = 10 mA IOL = 15 mA 2 –0.3 Resistance VIN ≥ 1.5V Resistance VIN ≥ 1.5V with pull up (VIN = GND) without pull up (VIN = GND or VDD) IDDQ IOZ IOSH Quiescent Supply Current (standby) Tristate Current Output VIN = GND or VDD –10 2 Typ. Max. Units Output High Voltage IOH = –14 mA 3.3V I/O, High Drive (OB33P) IOH = –24 mA Output Low Voltage IOL = 15 mA 3.3V I/O, High Drive (OB33P) IOL = 20 mA IOL = 28 mA 0.1VDDP 0.4 0.7 VDDP + 0.3 0.8 43 43 –40 50 5.0 20 10 V VIH VIL Input High Voltage 3.3V LVTTL/LVCMOS Input Low Voltage 3.3V LVTTL/LVCMOS V kΩ kΩ µA µA mA µA RWEAKPULLUP Weak Pull-up (IOB33U) RWEAKPULLUP Weak Pull-up (IOB25U) IIN Input Current 7 7 –300 –50 Leakage VOH = GND or VDD Output Short Circuit Current High 3.3V High Drive (OB33P) VIN = GND 3.3V Low Drive (OB33L) VIN = GND Output Short Circuit Current Low 3.3V High Drive VIN = VDD 3.3V Low Drive VIN = VDD I/O Pad Capacitance Clock Input Pad Capacitance –200 –100 mA IOSL 200 100 10 10 mA pF pF CI/O CCLK Notes: 1. All process conditions. Junction Temperature: –40 to +125°C. 2. No pull-up resistor. A u t om ot i v e S u p pl e m e n t 7 Automotive-Grade ProASICPLUS Flash Family FPGAs Table 8 • DC Specifications (3.3V PCI Revision 2.2 Operation)1 Automotive2 Symbol VDD VDDP VIH VIL IIPU IIL VOH VOL CIN CCLK Notes: 1. For PCI operation, use OTB33PH, OB33PH, IOB33PH, IB33, or IB33S macro library cells only. 2. All process conditions. Junction Temperature: –40 to +125°C. 3. This specification is guaranteed by design. It is the minimum voltage to which pull-up resistors are calculated to pull a floated network. Designers with applications sensitive to static power utilization should ensure that the input buffer is conducting minimum current at this input voltage. 4. Input leakage currents include hi-Z output leakage for all bidirectional buffers with tristate outputs. Parameter Supply Voltage for Core Supply Voltage for I/O Ring Input High Voltage Input Low Voltage Input Pull-up Voltage3 Input Leakage Current Output High Voltage Output Low Voltage Input Pin Capacitance (except CLK) CLK Pin Capacitance 5 4 Condition Min. 2.375 3.135 0.5VDDP –0.5 0.7VDDP Max. 2.625 3.465 VDDP + 0.5 0.3VDDP Units V V V V V 0 < VIN < VCCI IOUT = –500 µA IOUT = 1500 µA –50 0.9VDDP 50 µA V 0.1VDDP 10 12 V pF pF 8 A u t o m o t i v e S u pp l e m e n t Automotive-Grade ProASICPLUS Flash Family FPGAs Table 9 • AC Specifications (3.3V PCI Revision 2.2 Operation) Automotive Symbol Parameter IOH(AC) Switching Current High Condition 0 < VOUT ≤ 0.3VCCI* 0.3VCCI ≤ VOUT < 0.9VCCI 0.7VCCI < VOUT < VCCI * * Min. –12VCCI (–17.1 + (VDDP – VOUT)) Max. Units mA mA See equation C – page 124 of the PCI Specification document rev. 2.2 –32VCCI 16VDDP 1 (Test Point) IOL(AC) Switching Current Low VOUT = 0.7VCC* VCCI > VOUT ≥ 0.6VCCI* mA mA mA 0.6VCCI > VOUT > 0.1VCCI 0.18VCCI > VOUT > 0* (26.7VOUT) See equation D – page 124 of the PCI Specification document rev. 2.2 38VCCI –25 + (VIN + 1)/0.015 25 + (VIN – VDDP – 1)/0.015 1 1 4 4 (Test Point) ICL ICH slewR slewF Low Clamp Current High Clamp Current Output Rise Slew Rate Output Fall Slew Rate VOUT = 0.18VCC –3 < VIN ≤ –1 VCCI + 4 > VIN ≥ VCCI + 1 0.2VCCI to 0.6VCCI load 0.6VCCI to 0.2VCCI load * * mA mA mA V/ns V/ns Note: * Refer to the PCI Specification document rev. 2.2. Pad Loading Applicable to the Rising Edge PCI pin 1/2 in. max output buffer 1kΩ 10 pF Pad Loading Applicable to the Falling Edge PCI pin output buffer 1kΩ 10 pF A u t om ot i v e S u p pl e m e n t 9 Actel and the Actel logo are registered trademarks of Actel Corporation. All other trademarks are the property of their owners. http://www.actel.com Actel Corporation 2061 Stierlin Court Mountain View, CA 94043-4655 USA Phone 650.318.4200 Fax 650.318.4600 Actel Europe Ltd. Dunlop House, Riverside Way Camberley, Surrey GU15 3YL United Kingdom Phone +44 (0)1276.401450 Fax +44 (0)1276.401490 Actel Japan EXOS Ebisu Bldg. 4F 1-24-14 Ebisu Shibuya-ku Tokyo 150 Japan Phone +81.03.3445.7671 Fax +81.03.3445.7668 Actel Hong Kong 39th Floor, One Pacific Place 88 Queensway, Admiralty Hong Kong Phone 852.227.35712 Fax 852.227.35999 51700051-0/2.04