APT14M100B

APT14M100B APT14M100S 1000V, 14A, 0.88Ω Max N-Channel MOSFET Power MOS 8™ is a high speed, high voltage N-channel switch-mode power MOSFET. A proprietary planar stripe design yields excellent reliability and manufacturability. Low switching loss is achieved with low input capacitance and ultra low Crss "Miller" capacitance. The intrinsic gate resistance and capacitance of the poly-silicon gate structure help control slew rates during switching, resulting in low EMI and reliable paralleling, even when switching at very high frequency. Reliability in flyback, boost, forward, and other circuits is enhanced by the high avalanche energy capability. TO -24 7 D 3 PAK APT14M100B APT14M100S D Single die MOSFET G S TYPICAL APPLICATIONS FEATURES • Fast switching with low EMI/RFI • PFC and other boost converter • Low RDS(on) • Buck converter • Ultra low Crss for improved noise immunity • Two switch forward (asymmetrical bridge) • Low gate charge • Single switch forward • Avalanche energy rated • Flyback • RoHS compliant • Inverters Absolute Maximum Ratings Symbol ID Parameter Unit Ratings Continuous Drain Current @ TC = 25°C 14 Continuous Drain Current @ TC = 100°C 9 A IDM Pulsed Drain Current VGS Gate-Source Voltage ±30 V EAS Single Pulse Avalanche Energy 2 875 mJ IAR Avalanche Current, Repetitive or Non-Repetitive 7 A 1 55 Thermal and Mechanical Characteristics Typ Max Unit W PD Total Power Dissipation @ TC = 25°C 500 RθJC Junction to Case Thermal Resistance 0.25 RθCS Case to Sink Thermal Resistance, Flat, Greased Surface TJ,TSTG Operating and Storage Junction Temperature Range TL Soldering Temperature for 10 Seconds (1.6mm from case) WT Package Weight Torque Mounting Torque ( TO-247 Package), 6-32 or M3 screw Microsemi Website - http://www.microsemi.com 0.11 -55 150 300 °C/W °C 0.22 oz 5.9 g 10 in·lbf 1.1 N·m Rev C 7-2011 Min Characteristic 050-8105 Symbol Static Characteristics TJ = 25°C unless otherwise specified Symbol Parameter Test Conditions Min VBR(DSS) Drain-Source Breakdown Voltage VGS = 0V, ID = 250μA 1000 ∆VBR(DSS)/∆TJ Drain-Source On Resistance VGS(th) Gate-Source Threshold Voltage ∆VGS(th)/∆TJ VGS = 10V, ID = 7A 3 Zero Gate Voltage Drain Current IGSS Gate-Source Leakage Current Dynamic Characteristics VDS = 1000V VGS = 0V Forward Transconductance Ciss Input Capacitance Crss Reverse Transfer Capacitance Coss Output Capacitance Typ Max 1.15 0.71 4 -10 0.88 5 TJ = 25°C 100 500 ±100 TJ = 125°C VGS = ±30V Unit V V/°C Ω V mV/°C μA nA TJ = 25°C unless otherwise specified Parameter gfs 3 VGS = VDS, ID = 1mA Threshold Voltage Temperature Coefficient IDSS Symbol Reference to 25°C, ID = 250μA Breakdown Voltage Temperature Coefficient RDS(on) APT14M100B_S Min Test Conditions VDS = 50V, ID = 7A 4 Effective Output Capacitance, Charge Related Co(er) 5 Effective Output Capacitance, Energy Related Max 16 3965 55 335 VGS = 0V, VDS = 25V f = 1MHz Co(cr) Typ Unit S pF 135 VGS = 0V, VDS = 0V to 667V 70 Qg Total Gate Charge Qgs Gate-Source Charge Qgd Gate-Drain Charge td(on) Turn-On Delay Time Resistive Switching Current Rise Time VDD = 667V, ID = 7A tr td(off) tf Turn-Off Delay Time 120 21 60 28 29 95 26 VGS = 0 to 10V, ID = 7A, VDS = 500V RG = 4.7Ω 6 , VGG = 15V Current Fall Time nC ns Source-Drain Diode Characteristics Symbol IS ISM Parameter Continuous Source Current (Body Diode) Pulsed Source Current (Body Diode) 1 Test Conditions MOSFET symbol showing the integral reverse p-n junction diode (body diode) Diode Forward Voltage ISD = 7A, TJ = 25°C, VGS = 0V trr Reverse Recovery Time ISD = 7A, VDD = 100V 3 Qrr Reverse Recovery Charge Peak Recovery dv/dt Typ Max Unit 14 A G VSD dv/dt Min D 56 S diSD/dt = 100A/μs, TJ = 25°C ISD ≤ 7A, di/dt ≤1000A/μs, VDD = 667V, TJ = 125°C 1 1065 22 V ns μC 10 V/ns 1 Repetitive Rating: Pulse width and case temperature limited by maximum junction temperature. 2 Starting at TJ = 25°C, L = 35.71mH, RG = 4.7Ω, IAS = 7A. 3 Pulse test: Pulse Width < 380μs, duty cycle < 2%. 050-8105 Rev C 7-2011 4 Co(cr) is defined as a fixed capacitance with the same stored charge as COSS with VDS = 67% of V(BR)DSS. 5 Co(er) is defined as a fixed capacitance with the same stored energy as COSS with VDS = 67% of V(BR)DSS. To calculate Co(er) for any value of VDS less than V(BR)DSS, use this equation: Co(er) = -1.15E-7/VDS^2 + 2.03E-8/VDS + 3.93E-11. 6 RG is external gate resistance, not including internal gate resistance or gate driver impedance. (MIC4452) Microsemi reserves the right to change, without notice, the specifications and information contained herein. APT14M100B_S 45 V GS 16 = 10V T = 125°C J 40 14 TJ = -55°C 30 25 TJ = 25°C 20 15 10 TJ = 125°C 5 0 12 10 8 5V 6 4 2 TJ = 150°C 0 0 5 10 15 20 25 30 VDS(ON), DRAIN-TO-SOURCE VOLTAGE (V) 4.5V 0 Figure 1, Output Characteristics 3.0 NORMALIZED TO VGS = 10V @ 7A 2.5 VDS> ID(ON) x RDS(ON) MAX. 250μSEC. PULSE TEST @