APT75M50L

APT75M50B2 APT75M50L 500V, 75A, 0.075Ω Max N-Channel MOSFET Power MOS 8™ is a high speed, high voltage N-channel switch-mode power MOSFET. A proprietary planar stripe design yields excellent reliability and manufacturability. Low switching loss is achieved with low input capacitance and ultra low Crss "Miller" capacitance. The intrinsic gate resistance and capacitance of the poly-silicon gate structure help control slew rates during switching, resulting in low EMI and reliable paralleling, even when switching at very high frequency. Reliability in flyback, boost, forward, and other circuits is enhanced by the high avalanche energy capability. T-Ma x TM TO-264 APT75M50B2 APT75M50L D Single die MOSFET G S TYPICAL APPLICATIONS FEATURES • Fast switching with low EMI/RFI • PFC and other boost converter • Low RDS(on) • Buck converter • Ultra low Crss for improved noise immunity • Two switch forward (asymmetrical bridge) • Low gate charge • Single switch forward • Avalanche energy rated • Flyback • RoHS compliant • Inverters Absolute Maximum Ratings Symbol ID Parameter Unit Ratings Continuous Drain Current @ TC = 25°C 75 Continuous Drain Current @ TC = 100°C 47 A IDM Pulsed Drain Current VGS Gate-Source Voltage ±30 V EAS Single Pulse Avalanche Energy 2 1580 mJ IAR Avalanche Current, Repetitive or Non-Repetitive 37 A 1 230 Thermal and Mechanical Characteristics Typ Max Unit W PD Total Power Dissipation @ TC = 25°C 1040 RθJC Junction to Case Thermal Resistance 0.12 RθCS Case to Sink Thermal Resistance, Flat, Greased Surface TJ,TSTG Operating and Storage Junction Temperature Range TL Soldering Temperature for 10 Seconds (1.6mm from case) WT Package Weight Torque Mounting Torque ( TO-264Package), 4.40 or M3 screw Microsemi Website - http://www.microsemi.com 0.11 -55 150 300 °C/W °C 0.22 oz 6.2 g 10 in·lbf 1.1 N·m Rev E 8-2011 Min Characteristic 050-8082 Symbol Static Characteristics TJ = 25°C unless otherwise specified Symbol Parameter Test Conditions Min VBR(DSS) Drain-Source Breakdown Voltage VGS = 0V, ID = 250μA 500 ∆VBR(DSS)/∆TJ Drain-Source On Resistance VGS(th) Gate-Source Threshold Voltage ∆VGS(th)/∆TJ VGS = 10V, ID = 37A 3 Zero Gate Voltage Drain Current IGSS Gate-Source Leakage Current Dynamic Characteristics Forward Transconductance Ciss Input Capacitance Crss Reverse Transfer Capacitance Coss Output Capacitance VDS = 500V TJ = 25°C VGS = 0V TJ = 125°C Typ Max 0.60 0.064 4 -10 0.075 5 100 500 ±100 VGS = ±30V Unit V V/°C Ω V mV/°C μA nA TJ = 25°C unless otherwise specified Parameter gfs 3 VGS = VDS, ID = 2.5mA Threshold Voltage Temperature Coefficient IDSS Symbol Reference to 25°C, ID = 250μA Breakdown Voltage Temperature Coefficient RDS(on) APT75M50B2_L Min Test Conditions VDS = 50V, ID = 37A 4 Effective Output Capacitance, Charge Related Co(er) 5 Effective Output Capacitance, Energy Related Max 55 11600 160 1250 VGS = 0V, VDS = 25V f = 1MHz Co(cr) Typ Unit S pF 725 VGS = 0V, VDS = 0V to 333V 365 Qg Total Gate Charge Qgs Gate-Source Charge Qgd Gate-Drain Charge td(on) Turn-On Delay Time Resistive Switching Current Rise Time VDD = 333V, ID = 37A tr td(off) tf Turn-Off Delay Time 290 65 130 45 55 120 39 VGS = 0 to 10V, ID = 37A, VDS = 250V RG = 2.2Ω 6 , VGG = 15V Current Fall Time nC ns Source-Drain Diode Characteristics Symbol IS ISM Parameter Continuous Source Current (Body Diode) Pulsed Source Current (Body Diode) 1 Test Conditions MOSFET symbol showing the integral reverse p-n junction diode (body diode) Diode Forward Voltage ISD = 37A, TJ = 25°C, VGS = 0V trr Reverse Recovery Time ISD = 37A 3 Qrr Reverse Recovery Charge Peak Recovery dv/dt Typ Max Unit 75 A G VSD dv/dt Min D 230 S diSD/dt = 100A/μs, TJ = 25°C ISD ≤ 37A, di/dt ≤1000A/μs, VDD = 333V, TJ = 125°C 1 695 17 V ns μC 8 V/ns 1 Repetitive Rating: Pulse width and case temperature limited by maximum junction temperature. 2 Starting at TJ = 25°C, L = 2.31mH, RG = 25Ω, IAS = 37A. 3 Pulse test: Pulse Width < 380μs, duty cycle < 2%. 050-8082 Rev E 8-2011 4 Co(cr) is defined as a fixed capacitance with the same stored charge as COSS with VDS = 67% of V(BR)DSS. 5 Co(er) is defined as a fixed capacitance with the same stored energy as COSS with VDS = 67% of V(BR)DSS. To calculate Co(er) for any value of VDS less than V(BR)DSS, use this equation: Co(er) = -1.65E-7/VDS^2 + 5.51E-8/VDS + 2.03E-10. 6 RG is external gate resistance, not including internal gate resistance or gate driver impedance. (MIC4452) Microsemi reserves the right to change, without notice, the specifications and information contained herein. APT75M50B2_L 300 V GS 140 = 10V T = 125°C J TJ = -55°C 200 TJ = 25°C 150 100 TJ = 150°C 50 ID, DRIAN CURRENT (A) 100 6V 80 60 40 5V 20 4.5V TJ = 125°C 0 0 5 10 15 20 25 VDS(ON), DRAIN-TO-SOURCE VOLTAGE (V) 0 2.5 NORMALIZED TO VDS> ID(ON) x RDS(ON) MAX. 250μSEC. PULSE TEST @