AT17N256-10SI

Features • EE Programmable 262,144 x 1-, 524,288 x 1-, 1,048,576 x 1-, 2,097,152 x 1-, and • • • • • • • • 4,194,304 x 1-bit Serial Memories Designed to Store Configuration Programs for Field Programmable Gate Arrays (FPGAs) Available as a 3.3V (±10%) Commercial and Industrial Version Simple Interface to SRAM FPGAs Pin Compatible with Xilinx® XC17SXXXA and XC17SXXXXL PROMs Compatible with Xilinx Spartan®-II, Spartan-IIE and Spartan XL FPGAs in Master Serial Mode Very Low-power CMOS EEPROM Process Available in 8-lead PDIP, 8-lead SOIC, 20-lead SOIC and 44-lead TQFP Packages for a Specific Density Low-power Standby Mode High-reliability – Endurance: Minimum 10 Write Cycles – Data Retention: 20 Years at 85°C Description The AT17N series FPGA Configuration EEPROM (Configurators) provide an easy-touse, cost-effective configuration memory for Field Programmable Gate Arrays. The AT17N series device is packaged in the 8-lead PDIP, 8-lead SOIC, 20-lead SOIC and 44-lead TQFP, see Table 1. The AT17N series Configurators uses a simple serialaccess procedure to configure one or more FPGA devices. The AT17N series configurators can be programmed with industry-standard programmers, Atmel’s ATDH2200E Programming Kit or Atmel’s ATDH2225 ISP Cable and factory programming. FPGA Configuration Memory AT17N256 AT17N512 AT17N010 AT17N002 AT17N040 Table 1. AT17N Series Packages AT17N256 AT17N512/ AT17N010 AT17N002 AT17N040 8-lead PDIP Yes Yes – – 8-lead SOIC Yes – – – 20-lead SOIC Yes Yes Yes – 44-lead TQFP – – Yes Yes Package 3.3V System Support Not Recommended For New Design AT17N256 replaced by AT17LV256 AT17N512 replaced by AT17LV512 AT17N010 replaced by AT17LV010 AT17N002 replaced by AT17LV002 AT17N040 replaced by AT17LV040 3020C–CNFG–08/07 1 Pin Configuration 8-lead SOIC DATA CLK RESET/OE CE 1 2 3 4 8 7 6 5 VCC VCC (SER_EN) DC GND 8-lead PDIP DATA CLK RESET/OE CE 8 7 6 5 1 2 3 4 VCC VCC (SER_EN) DC GND 20-lead SOIC DATA NC CLK NC NC NC NC RESET/OE NC CE 2 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VCC NC VCC (SER_EN) NC NC NC NC DC NC GND AT17N256/512/010/002/040 3020C–CNFG–08/07 AT17N256/512/010/002/040 44 43 42 41 40 39 38 37 36 35 34 NC CLK NC NC DATA NC VCC NC NC VCC (SER_EN) NC 44 TQFP 33 32 31 30 29 28 27 26 25 24 23 1 2 3 4 5 6 7 8 9 10 11 NC NC NC NC NC NC NC NC NC NC DC NC RESET/OE NC CE NC NC GND NC NC DC NC 12 13 14 15 16 17 18 19 20 21 22 NC NC NC NC NC NC DC NC NC NC NC 3 3020C–CNFG–08/07 Block Diagram SER_EN POWER ON RESET Device Description The control signals for the configuration EEPROM (CE, RESET/OE and CCLK) interface directly with the FPGA device control signals. All FPGA devices can control the entire configuration process and retrieve data from the configuration EEPROM without requiring an external intelligent controller. The configuration EEPROM RESET/OE and CE pins control the tri-state buffer on the DATA output pin and enable the address counter. When RESET/OE is driven High, the configuration EEPROM resets its address counter and tri-states its DATA pin. The CE pin also controls the output of the AT17N series configurator. If CE is held High after the RESET/OE reset pulse, the counter is disabled and the DATA output pin is tri-stated. When OE is subsequently driven Low, the counter and the DATA output pin are enabled. When RESET/OE is driven High again, the address counter is reset and the DATA output pin is tri-stated, regardless of the state of CE. Upon power-up, the address counter is automatically reset. 4 AT17N256/512/010/002/040 3020C–CNFG–08/07 AT17N256/512/010/002/040 Pin Description AT17N512/ AT17N010 AT17N256 AT17N040 AT17N002 Name I/O 8 DIP/ SOIC DATA I/O 1 1 1 1 1 40 40 CLK I 2 3 2 3 3 43 43 RESET/OE I 3 8 3 8 8 13 13 CE I 4 10 4 10 10 15 15 5 11 5 11 11 18 18 GND 20 SOIC 8 DIP 20 SOIC 20 SOIC 44 TQFP 44 TQFP DC O 6 13 6 13 13 21 21 DC O – – – – – 23 23 VCC(SER_EN) I 7 18 7 18 18 35 35 8 20 8 20 20 38 38 VCC DATA Three-state DATA output for configuration. Open-collector bi-directional pin for programming. CLK Clock input. Used to increment the internal address and bit counter for reading and programming. RESET/OE Output Enable (active High) and RESET (active Low) when SER_EN is High. A Low level on RESET/OE resets both the address and bit counters. A High level (with CE Low) enables the data output driver. The logic polarity of this input is programmable as either RESET/OE or RESET/OE. For most applications, RESET should be programmed active Low. This document describes the pin as RESET/OE. CE Chip Enable input (active Low). A Low level (with OE High) allows CLK to increment the address counter and enables the data output driver. A High level on CE disables both the address and bit counters and forces the device into a low-power standby mode. Note that this pin will not enable/disable the device in the Two-Wire Serial Programming mode (SER_EN Low). GND Ground pin. A 0.2 µF decoupling capacitor between VCC and GND is recommended. VCC(SER_EN) Serial enable must be held High during FPGA loading operations. Bringing SER_EN Low enables the Two-Wire Serial Programming Mode. For non-ISP applications, SER_EN should be tied to VCC. VCC 3.3V (±10%) Commercial and Industrial power supply pin. NC NC pins are No Connect pins, which are not internally bonded out to the die. DC DC pins are No Connect pins internally connected to the die. It is not recommended to connect these pins to any external signal. 5 3020C–CNFG–08/07 FPGA Master Serial Mode Summary The I/O and logic functions of any SRAM-based FPGA are established by a configuration program. The program is loaded either automatically upon power-up, or on command, depending on the state of the FPGA mode pins. In Master mode, the FPGA automatically loads the configuration program from an external memory. The AT17N Serial Configuration EEPROM has been designed for compatibility with the Master Serial mode. This document discusses the master serial mode configuration of Atmel AT17N series configuration memories, pin compatible with Spartan-II, Spartan-IIE and Spartan XL OTP PROMs. Control of Configuration Most connections between the FPGA device and the AT17N Serial EEPROM are simple and self-explanatory. • The DATA output of the AT17N series configurator drives DIN of the FPGA devices. • The master FPGA CCLK output drives the CLK input of the AT17N series configurator. • SER_EN must be connected to VCC (except during ISP). • The CE and OE/Reset are driven by the FPGA to enable output data buffer of the EEPROM. Programming Mode The programming mode is entered by bringing SER_EN Low. In this mode the chip can be programmed by the Two-Wire serial bus. The programming is done at VCC supply only. Programming super voltages are generated inside the chip. Standby Mode The AT17N series configurators enter a low-power standby mode whenever CE is asserted High. In this mode, the AT17N256 configurator consumes less than 50 µA of current at 3.3V (100 µA for the AT17N512/010 and 200 µA for the AT17N002/040). 6 AT17N256/512/010/002/040 3020C–CNFG–08/07 AT17N256/512/010/002/040 Absolute Maximum Ratings* Operating Temperature.................................... -40°C to +85 °C Storage Temperature ..................................... -65°C to +150°C Voltage on Any Pin with Respect to Ground ..............................-0.1V to VCC +0.5V Supply Voltage (VCC) .......................................... 3.0V to +3.6V *NOTICE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those listed under operating conditions is not implied. Exposure to Absolute Maximum Rating conditions for extended periods of time may affect device reliability. Maximum Soldering Temp. (10 sec. @ 1/16 in.).............260°C ESD (RZAP = 1.5K, CZAP = 100 pF)................................. 2000V Operating Conditions 3.3V Symbol Description Min Max Units Commercial Supply voltage relative to GND -0°C to +70°C 3.0 3.6 V Industrial Supply voltage relative to GND -40°C to +85°C 3.0 3.6 V VCC 7 3020C–CNFG–08/07 DC Characteristics VCC = 3.3V ± 10% AT17N512/ AT17N010 AT17N256 AT17N002/ AT17N040 Symbol Description Min Max Min Max Min Max Units VIH High-level Input Voltage 2.0 VCC 2.0 VCC 2.0 VCC V VIL Low-level Input Voltage 0 0.8 0 0.8 0 0.8 V VOH High-level Output Voltage (IOH = -2.5 mA) VOL Low-level Output Voltage (IOL = +3 mA) VOH High-level Output Voltage (IOH = -2 mA) VOL Low-level Output Voltage (IOL = +3 mA) ICCA Supply Current, Active Mode IL Input or Output Leakage Current (VIN = VCC or GND) ICCS Supply Current, Standby Mode 2.4 2.4 Commercial 2.4 0.4 0.4 2.4 2.4 Industrial -10 V 0.4 2.4 V V 0.4 0.4 0.4 V 5 5 5 mA 10 µA 10 -10 10 -10 Commercial 50 100 150 µA Industrial 100 100 150 µA AC Characteristics VCC = 3.3V ± 10% AT17N256 Commercial Description TOE(1) OE to Data Delay 50 55 TCE(1) CE to Data Delay 60 CLK to Data Delay 75 TCAC Max Industrial Symbol (1) Min AT17N512/010/002/040 Min Max Commercial Min Max Industrial Min Max Units 50 55 ns 60 55 60 ns 80 55 60 ns TOH Data Hold from CE, OE, or CLK TDF(2) CE or OE to Data Float Delay TLC CLK Low Time 25 25 25 25 ns THC CLK High Time 25 25 25 25 ns TSCE CE Setup Time to CLK (to guarantee proper counting) 35 60 30 35 ns THCE CE Hold Time from CLK (to guarantee proper counting) 0 0 0 0 ns THOE OE High Time (guarantees counter is reset) 25 25 25 25 ns FMAX Maximum Clock Frequency Notes: 8 0 0 55 10 0 55 10 0 50 15 ns 50 10 ns MHz 1. AC test lead = 50 pF. 2. Float delays are measured with 5 pF AC loads. Transition is measured ± 200 mV from steady-state active levels. AT17N256/512/010/002/040 3020C–CNFG–08/07 AT17N256/512/010/002/040 AC Characteristics CE TSCE TSCE THCE RESET/OE TLC THOE THC CLK TOE TCE TCAC TOH TDF DATA TOH 9 3020C–CNFG–08/07 Thermal Resistance Coefficients(1) AT17N256 AT17N512/ AT17N010 AT17N002 AT17N040 θJC [°C/W] 37 37 – – θJA [°C/W](2) 107 107 – – θJC [°C/W] 45 – – – θJA [°C/W](2) 150 – – – Package Type 8P3 8S1 20S2 44A Notes: 10 Plastic Dual Inline Package (PDIP) Plastic Gull Wing Small Outline (SOIC) Plastic Gull Wing Small Outline (SOIC) Thin Plastic Quad Flat Package (TQFP) θJC [°C/W] – θJA [°C/W](2) – θJC [°C/W] – – 17 17 θJA [°C/W](2) – – 62 62 1. For more information refer to the “Thermal Characteristics of Atmel’s Packages”, available on the Atmel web site. 2. Airflow = 0 ft/min. AT17N256/512/010/002/040 3020C–CNFG–08/07 AT17N256/512/010/002/040 Figure 1. Ordering Code AT17N256-10PC Voltage +- 3.3V 10% Size (Bits) Package 256 = 256K Temperature C = Commercial 512 = 512K P = 8P3 010 = 1M N = 8S1 002 = 2M S = 20S2 040 = 4M TQ = 44A I = Industrial Package Type 8P3 8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP) 8S1 8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC) 20S2 20-lead, 0.300" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC) 44A 44-lead, Thin (1.0 mm) Plastic Quad Flat Package Carrier (TQFP) 11 3020C–CNFG–08/07 Ordering Information Memory Size 256-Kbit Ordering Code Package AT17N256-10PC 8P3 AT17N256-10NC 8S1 AT17N256-10SC 20S2 AT17N256-10PI 8P3 AT17N256-10NI 8S1 AT17N256-10SI 20S2 AT17N512-10SC 20S2 Commercial (0°C to 70°C) AT17N512-10SI 20S2 Industrial (-40°C to 85°C) AT17N010-10SC 20S2 Commercial (0°C to 70°C) AT17N010-10SI 20S2 Industrial (-40°C to 85°C) AT17N002-10SC 20S2 AT17N002-10TQC 44A AT17N002-10SI 20S2 AT17N002-10TQI 44A AT17N040-10TQC 44A Commercial (0°C to 70°C) AT17N040-10TQI 44A Industrial (-40°C to 85°C) 512-Kbit 1-Mbit 2-Mbit 4-Mbit Notes: 12 Operation Range Commercial (0°C to 70°C) Industrial (-40°C to 85°C) Commercial (0°C to 70°C) Industrial (-40°C to 85°C) 1. For the -10CC and -10CI packages, customers may migrate to AT17LVXXX-10CU. AT17N256/512/010/002/040 3020C–CNFG–08/07 AT17N256/512/010/002/040 Packaging Information 8P3 – PDIP E 1 E1 N Top View c eA End View COMMON DIMENSIONS (Unit of Measure = inches) D e D1 A2 A MIN NOM A2 0.115 0.130 0.195 b 0.014 0.018 0.022 5 b2 0.045 0.060 0.070 6 b3 0.030 0.039 0.045 6 c 0.008 0.010 0.014 D 0.355 0.365 0.400 D1 0.005 E 0.300 0.310 0.325 4 E1 0.240 0.250 0.280 3 SYMBOL A b2 b3 b 4 PLCS Side View L Notes: 0.210 0.100 BSC eA 0.300 BSC 0.115 NOTE 2 3 3 e L MAX 0.130 4 0.150 2 1. This drawing is for general information only; refer to JEDEC Drawing MS-001, Variation BA for additional information. 2. Dimensions A and L are measured with the package seated in JEDEC seating plane Gauge GS-3. 3. D, D1 and E1 dimensions do not include mold Flash or protrusions. Mold Flash or protrusions shall not exceed 0.010 inch. 4. E and eA measured with the leads constrained to be perpendicular to datum. 5. Pointed or rounded lead tips are preferred to ease insertion. 6. b2 and b3 maximum dimensions do not include Dambar protrusions. Dambar protrusions shall not exceed 0.010 (0.25 mm). 01/09/02 R 2325 Orchard Parkway San Jose, CA 95131 TITLE 8P3, 8-lead, 0.300" Wide Body, Plastic Dual In-line Package (PDIP) DRAWING NO. REV. 8P3 B 13 3020C–CNFG–08/07 8S1 – SOIC C 1 E E1 L N Ø TOP VIEW END VIEW e b COMMON DIMENSIONS (Unit of Measure = mm) A A1 SYMBOL MIN NOM MAX A1 0.10 – 0.25 NOTE D SIDE VIEW Note: These drawings are for general information only. Refer to JEDEC Drawing MS-012, Variation AA for proper dimensions, tolerances, datums, etc. 3/17/05 R 14 1150 E. Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 TITLE 8S1, 8-lead (0.150" Wide Body), Plastic Gull Wing Small Outline (JEDEC SOIC) DRAWING NO. REV. 8S1 C AT17N256/512/010/002/040 3020C–CNFG–08/07 AT17N256/512/010/002/040 20S2 – SOIC 15 3020C–CNFG–08/07 44A – TQFP PIN 1 B PIN 1 IDENTIFIER E1 e E D1 D C 0˚~7˚ A1 A2 A L COMMON DIMENSIONS (Unit of Measure = mm) Notes: 1. This package conforms to JEDEC reference MS-026, Variation ACB. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum plastic body size dimensions including mold mismatch. 3. Lead coplanarity is 0.10 mm maximum. SYMBOL MIN NOM MAX A – – 1.20 A1 0.05 – 0.15 A2 0.95 1.00 1.05 D 11.75 12.00 12.25 D1 9.90 10.00 10.10 E 11.75 12.00 12.25 E1 9.90 10.00 10.10 B 0.30 – 0.45 C 0.09 – 0.20 L 0.45 – 0.75 e NOTE Note 2 Note 2 0.80 TYP 10/5/2001 R 16 2325 Orchard Parkway San Jose, CA 95131 TITLE 44A, 44-lead, 10 x 10 mm Body Size, 1.0 mm Body Thickness, 0.8 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP) DRAWING NO. REV. 44A B AT17N256/512/010/002/040 3020C–CNFG–08/07 AT17N256/512/010/002/040 Revision History Revision Level – Release Date History B – March 2006 Added last-time buy for AT17NXXX-10CC and AT17NXXX-10CI. C – August 2007 Removed 8CN4 8-lead LAP package. 17 3020C–CNFG–08/07 Headquarters International Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Atmel Asia Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong Kong Tel: (852) 2721-9778 Fax: (852) 2722-1369 Atmel Europe Le Krebs 8, Rue Jean-Pierre Timbaud BP 309 78054 Saint-Quentin-enYvelines Cedex France Tel: (33) 1-30-60-70-00 Fax: (33) 1-30-60-71-11 Atmel Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581 Technical Support configurator@atmel.com Sales Contact www.atmel.com/contacts Product Contact Web Site www.atmel.com Literature Requests www.atmel.com/literature Disclaimer: The information in this document is provided in connection with Atmel products. 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FLEX™ is the trademark of Altera Corporation; ORCA ™ is the trademark of Lattice Semiconductors; SPARTAN ® and Virtex ® are the registered trademarks of Xilinx, Inc.; XC3000 ™, XC4000™ and XC5200™ are the trademarks of Xilinx, Inc.; APEX ™ is the trademark of MIPS Technologies; Other terms and product names may be the trademarks of others. 3020C–CNFG–08/07