AT24C512B-PU

Features • Low-voltage and Standard-voltage Operation • • • • • • • • • • • • – 1.8v (VCC = 1.8V to 3.6V) – 2.5v (VCC = 2.5V to 5.5V) Internally Organized 65,536 x 8 Two-wire Serial Interface Schmitt Triggers, Filtered Inputs for Noise Suppression Bidirectional Data Transfer Protocol 1 MHz (2.5V, 5.5V), 400 kHz (1.8V) Compatibility Write Protect Pin for Hardware and Software Data Protection 128-byte Page Write Mode (Partial Page Writes Allowed) Self-timed Write Cycle (5 ms Max) High Reliability – Endurance: 1,000,000 Write Cycles – Data Retention: 40 Years Lead-free/Halogen-free Devices 8-lead PDIP, 8-lead JEDEC SOIC, 8-lead EIAJ SOIC, 8-lead TSSOP, 8-ball dBGA2, and 8-lead Ultra Thin Small Array (SAP) Packages Die Sales: Wafer Form, Waffle Pack and Bumped Die Two-wire Serial EEPROM 512K (65,536 x 8) AT24C512B with Three Device Address Inputs Description The AT24C512B provides 524,288 bits of serial electrically erasable and programmable read only memory (EEPROM) organized as 65,536 words of 8 bits each. The device’s cascadable feature allows up to eight devices to share a common two-wire bus. The device is optimized for use in many industrial and commercial applications where low-power and low-voltage operation are essential. The devices are available in space-saving 8-pin PDIP, 8-lead JEDEC SOIC, 8-lead EIAJ SOIC, 8-lead TSSOP, 8-ball dBGA2 and 8-lead Ultra Thin SAP packages. In addition, the entire family is available in 1.8V (1.8V to 3.6V) and 2.5V (2.5V to 5.5V) versions. Table 0-1. Pin Configurations Pin Name Function A0–A2 Address Inputs SDA Serial Data SCL Serial Clock Input WP Write Protect 8-ball dBGA2 VCC WP SCL SDA 8 7 6 5 Not Recommended for New Design. Replaced by AT24C512C. 1 2 3 4 A0 A1 A2 GND 8-lead TSSOP A0 A1 A2 GND 8 7 6 5 1 2 3 4 8-lead PDIP VCC WP SCL SDA A0 A1 A2 GND 8 7 6 5 1 2 3 4 A0 A1 A2 GND VCC WP SCL SDA 8-lead SOIC 8-lead Ultra Thin SAP VCC WP SCL SDA 8 7 6 5 1 2 3 4 A0 A1 A2 GND 1 2 3 4 8 7 6 5 VCC WP SCL SDA Bottom View Bottom View Rev. 5297A–SEEPR–1/08 Absolute Maximum Ratings* Operating Temperature ................................ –55C to +125C *NOTICE: Storage Temperature.................................... –65C to +150C Voltage on Any Pin with Respect to Ground ....................................–1.0V to +7.0V Maximum Operating Voltage .......................................... 6.25V Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC Output Current........................................................ 5.0 mA Figure 0-1. Block Diagram VCC GND WP START STOP LOGIC SERIAL CONTROL LOGIC LOAD DEVICE ADDRESS COMPARATOR A2 A1 A0 R/W EN H.V. PUMP/TIMING COMP LOAD DATA RECOVERY INC DATA WORD ADDR/COUNTER Y DEC X DEC SCL SDA EEPROM SERIAL MUX DOUT/ACK LOGIC DIN DOUT 2 AT24C512B 5297A–SEEPR–1/08 AT24C512B 1. Pin Description SERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into each EEPROM device and negative edge clock data out of each device. SERIAL DATA (SDA): The SDA pin is bidirectional for serial data transfer. This pin is opendrain driven and may be wire-ORed with any number of other open-drain or open collector devices. DEVICE/PAGE ADDRESSES (A2, A1, A0): The A2, A1, and A0 pins are device address inputs that are hardwired (directly to GND or to Vcc) for compatibility with other AT24Cxx devices. When the pins are hardwired, as many as eight 512K devices may be addressed on a single bus system. (Device addressing is discussed in detail under “Device Addressing,” page 8.) A device is selected when a corresponding hardware and software match is true. If these pins are left floating, the A2, A1, and A0 pins will be internally pulled down to GND. However, due to capacitive coupling that may appear during customer applications, Atmel ® recommends always connecting the address pins to a known state. When using a pull-up resistor, Atmel recommends using 10k or less. WRITE PROTECT (WP): The write protect input, when connected to GND, allows normal write operations. When WP is connected directly to Vcc, all write operations to the memory are inhibited. If the pin is left floating, the WP pin will be internally pulled down to GND. However, due to capacitive coupling that may appear during customer applications, Atmel recommends always connecting the WP pins to a known state. When using a pull-up resistor, Atmel recommends using 10k or less. 3 5297A–SEEPR–1/08 2. Memory Organization AT24C512B, 512K SERIAL EEPROM: The 512K is internally organized as 512 pages of 128-bytes each. Random word addressing requires a 16-bit data word address. Table 2-1. Pin Capacitance(1) Applicable over recommended operating range from: TA = 25C, f = 1.0 MHz, VCC = +1.8V to +5.5V Symbol Test Condition CI/O CIN Note: Max Units Conditions Input/Output Capacitance (SDA) 8 pF VI/O = 0V Input Capacitance (A0, A1, SCL) 6 pF VIN = 0V 1. This parameter is characterized and is not 100% tested. Table 2-2. DC Characteristics Applicable over recommended operating range from: TAI = –40C to +85C, VCC = +1.8V to +5.5V (unless otherwise noted) Symbol Parameter VCC1 Supply Voltage VCC2 Supply Voltage ICC Supply Current VCC = 5.0V ICC Supply Current VCC = 5.0V ISB1 Standby Current ISB2 Standby Current ILI Input Leakage Current VIN = VCC or VSS ILO Output Leakage Current VOUT = VCC or VSS VIL Input Low Level(1) VIH Input High Level (1) VOL1 Output Low Level VCC = 1.8V Output Low Level VCC = 3.0V VOL2 Note: 4 Test Condition VCC = 1.8V VCC = 3.6V VCC = 2.5V VCC = 5.5V Min Typ Max Units 1.8 3.6 V 2.5 5.5 V READ at 400 kHz 2.0 mA WRITE at 400 kHz 3.0 mA 1.0 µA 3.0 µA 2.0 µA 6.0 µA 0.10 3.0 µA 0.05 3.0 µA –0.6 VCC x 0.3 V VCC x 0.7 VCC + 0.5 V IOL = 0.15 mA 0.2 V IOL = 2.1 mA 0.4 V VIN = VCC or VSS VIN = VCC or VSS 1. VIL min and VIH max are reference only and are not tested. AT24C512B 5297A–SEEPR–1/08 AT24C512B Table 2-3. AC Characteristics (Industrial Temperature) Applicable over recommended operating range from TAI = 40C to +85C, VCC = +1.8V to +5.5V, CL = 100 pF (unless otherwise noted). Test conditions are listed in Note 2. 1.8-volt Symbol Parameter Min fSCL Clock Frequency, SCL tLOW Clock Pulse Width Low tHIGH Clock Pulse Width High 2.5, 5.0-volt Max Min 400 Max Units 1000 kHz 1.3 0.4 µs 0.6 0.4 µs (1) ti Noise Suppression Time 100 tAA Clock Low to Data Out Valid 0.05 tBUF Time the bus must be free before a new transmission can start(1) 1.3 0.5 µs tHD.STA Start Hold Time 0.6 0.25 µs tSU.STA Start Set-up Time 0.6 0.25 µs tHD.DAT Data In Hold Time 0 0 µs tSU.DAT Data In Set-up Time 100 100 ns tR Inputs Rise Time(1) (1) 0.9 0.05 50 ns 0.55 µs 0.3 0.3 µs 300 100 ns tF Inputs Fall Time tSU.STO Stop Set-up Time 0.6 0.25 µs tDH Data Out Hold Time 50 50 ns tWR Write Cycle Time Endurance(1) 25°C, Page Mode, 3.3V Notes: 5 1,000,000 5 ms Write Cycles 1. This parameter is ensured by characterization only. 2. AC measurement conditions: RL (connects to VCC): 1.3 k (2.5V, 5V), 10 k (1.8V) Input pulse voltages: 0.3 VCC to 0.7 VCC Input rise and fall times:  50 ns Input and output timing reference voltages: 0.5 VCC 5 5297A–SEEPR–1/08 3. Device Operation CLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an external device. Data on the SDA pin may change only during SCL low time periods (see Figure 3-4 on page 8). Data changes during SCL high periods will indicate a start or stop condition as defined below. START CONDITION: A high-to-low transition of SDA with SCL high is a start condition which must precede any other command (see Figure 3-5 on page 8). STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition. After a read sequence, the stop command will place the EEPROM in a standby power mode (see Figure 3-5 on page 8). ACKNOWLEDGE: All addresses and data words are serially transmitted to and from the EEPROM in 8-bit words. The EEPROM sends a zero during the ninth clock cycle to acknowledge that it has received each word. STANDBY MODE: The AT24C512B features a low power standby mode which is enabled: a) upon power-up and b) after the receipt of the STOP bit and the completion of any internal operations. Software Reset: After an interruption in protocol, power loss or system reset, any 2-wire part can be protocol reset by following these steps: (a) Create a start bit condition, (b) clock 9 cycles, (c) create another start bit followed by stop bit condition as shown below. The device is ready for next communication after above steps have been completed. Figure 3-1. Protocol Reset Condition Dummy Clock Cycles Start bit SCL 1 2 3 Start bit 8 Stop bit 9 SDA 6 AT24C512B 5297A–SEEPR–1/08 AT24C512B Figure 3-2. Bus Timing (SCL: Serial Clock, SDA: Serial Data I/O) tHIGH tF tR tLOW SCL tSU.STA tLOW tHD.STA tHD.DAT tSU.DAT tSU.STO SDA IN tAA tDH tBUF SDA OUT Figure 3-3. Write Cycle Timing (SCL: Serial Clock, SDA: Serial Data I/O) SCL SDA 8th BIT ACK WORDn (1) twr STOP CONDITION Note: START CONDITION 1. The write cycle time tWR is the time from a valid stop condition of a write sequence to the end of the internal clear/write cycle. 7 5297A–SEEPR–1/08 Figure 3-4. Data Validity SDA SCL DATA STABLE DATA STABLE DATA CHANGE Figure 3-5. Start and Stop Definition SDA SCL START Figure 3-6. STOP Output Acknowledge 1 SCL 8 9 DATA IN DATA OUT START 8 ACKNOWLEDGE AT24C512B 5297A–SEEPR–1/08 AT24C512B 4. Device Addressing The 512K EEPROM requires an 8-bit device address word following a start condition to enable the chip for a read or write operation (see Figure 6-1 on page 10). The device address word consists of a mandatory “1”, “0” sequence for the first four most significant bits as shown. This is common to all two-wire EEPROM devices. The 512K uses the three device address bits A2, A1, A0 to allow as many as eight devices on the same bus. These bits must compare to their corresponding hardwired input pins. The A2, A1 and A0 pins use an internal proprietary circuit that biases them to a logic low condition if the pins are allowed to float. The eighth bit of the device address is the read/write operation select bit. A read operation is initiated if this bit is high and a write operation is initiated if this bit is low. Upon a compare of the device address, the EEPROM will output a “0”. If a compare is not made, the device will return to a standby state. DATA SECURITY: The AT24C512B has a hardware data protection scheme that allows the user to Write Protect the whole memory when the WP pin is at VCC. 5. Write Operations BYTE WRITE: A write operation requires two 8-bit data word addresses following the device address word and acknowledgment. Upon receipt of this address, the EEPROM will again respond with a “0” and then clock in the first 8-bit data word. Following receipt of the 8-bit data word, the EEPROM will output a “0”. The addressing device, such as a microcontroller, then must terminate the write sequence with a stop condition. At this time the EEPROM enters an internally-timed write cycle, tWR, to the nonvolatile memory. All inputs are disabled during this write cycle and the EEPROM will not respond until the write is complete (see Figure 6-2 on page 10). PAGE WRITE: The 512K EEPROM is capable of 128-byte page writes. A page write is initiated the same way as a byte write, but the microcontroller does not send a stop condition after the first data word is clocked in. Instead, after the EEPROM acknowledges receipt of the first data word, the microcontroller can transmit up to 127 more data words. The EEPROM will respond with a “0” after each data word received. The microcontroller must terminate the page write sequence with a stop condition (see Figure 6-3 on page 11). The data word address lower 7 bits are internally incremented following the receipt of each data word. The higher data word address bits are not incremented, retaining the memory page row location. When the word address, internally generated, reaches the page boundary, the following byte is placed at the beginning of the same page. If more than 128 data words are transmitted to the EEPROM, the data word address will “roll over” and previous data will be overwritten. The address roll over during write is from the last byte of the current page to the first byte of the same page. ACKNOWLEDGE POLLING: Once the internally-timed write cycle has started and the EEPROM inputs are disabled, acknowledge polling can be initiated. This involves sending a start condition followed by the device address word. The Read/Write bit is representative of the operation desired. Only if the internal write cycle has completed will the EEPROM respond with a “0”, allowing the read or write sequence to continue. 9 5297A–SEEPR–1/08 6. Read Operations Read operations are initiated the same way as write operations with the exception that the Read/Write select bit in the device address word is set to “1”. There are three read operations: current address read, random address read and sequential read. CURRENT ADDRESS READ: The internal data word address counter maintains the last address accessed during the last read or write operation, incremented by “1”. This address stays valid between operations as long as the chip power is maintained. The address roll over during read is from the last byte of the last memory page, to the first byte of the first page. Once the device address with the Read/Write select bit set to “1” is clocked in and acknowledged by the EEPROM, the current address data word is serially clocked out. The microcontroller does not respond with an input “0” but does generate a following stop condition (see Figure 6-4 on page 11). RANDOM READ: A random read requires a “dummy” byte write sequence to load in the data word address. Once the device address word and data word address are clocked in and acknowledged by the EEPROM, the microcontroller must generate another start condition. The microcontroller now initiates a current address read by sending a device address with the Read/Write select bit high. The EEPROM acknowledges the device address and serially clocks out the data word. The microcontroller does not respond with a “0” but does generate a following stop condition (see Figure 6-5 on page 11). SEQUENTIAL READ: Sequential reads are initiated by either a current address read or a random address read. After the microcontroller receives a data word, it responds with an acknowledge. As long as the EEPROM receives an acknowledge, it will continue to increment the data word address and serially clock out sequential data words. When the memory address limit is reached, the data word address will roll over and the sequential read will continue. The sequential read operation is terminated when the microcontroller does not respond with a “0” but does generate a following stop condition (see Figure 6-6 on page 11). Figure 6-1. Device Address 1 MSB Figure 6-2. 10 0 1 0 A2 A1 A0 R/W LSB Byte Write AT24C512B 5297A–SEEPR–1/08 AT24C512B Figure 6-3. Page Write Figure 6-4. Current Address Read Figure 6-5. Random Read Figure 6-6. Sequential Read 11 5297A–SEEPR–1/08 Ordering Information Ordering Code Voltage Package AT24C512B-PU (Bulk form only) 1.8 8P3 AT24C512B-PU25 (Bulk form only) 2.5 8P3 AT24C512BN-SH-B(1) (NiPdAu Lead Finish) 1.8 8S1 (NiPdAu Lead Finish) 1.8 8S1 (1) (NiPdAu Lead Finish) 2.5 8S1 (2) (NiPdAu Lead Finish) (2) AT24C512BN-SH-T AT24C512BN-SH25-B 2.5 8S1 AT24C512BW-SH-B(1) (NiPdAu Lead Finish) 1.8 8S2 AT24C512BW-SH-T(2) (NiPdAu Lead Finish) 1.8 8S2 2.5 8S2 AT24C512BN-SH25-T (1) AT24C512BW-SH25-B (NiPdAu Lead Finish) AT24C512BW-SH25-T(2) (NiPdAu Lead Finish) 2.5 8S2 AT24C512B-TH-B(1) (NiPdAu Lead Finish) 1.8 8A2 AT24C512B-TH-T(2) (NiPdAu Lead Finish) 1.8 8A2 (1) (NiPdAu Lead Finish) 2.5 8A2 (2) (NiPdAu Lead Finish) 2.5 8A2 AT24C512BY7-YH-T(2) (NiPdAu Lead Finish) 1.8 8Y7 2.5 8Y7 1.8 8U2-1 1.8 Die Sale AT24C512B-TH25-B AT24C512B-TH25-T (2) AT24C512BY7-YH25-T (NiPdAu Lead Finish) (2) AT24C512BU2-UU-T AT24C512B-W-11 Notes: (3) Operation Range Lead-free/Halogen-free/ Industrial Temperature (–40C to 85C) Industrial Temperature (–40C to 85C) 1. “-B” denotes bulk 2. “-T” denotes tape and reel. SOIC = 4K per reel. TSSOP and dBGA2 = 5K per reel. SAP = 3K per reel. EIAJ = 2K per reel. 3. Available in tape and reel, and wafer form; order as SL788 for inkless wafer form. Bumped die available upon request. Please contact Serial Interface Marketing. Package Type 8P3 8-lead, 0.300" Wide, Plastic Dual In-line Package (PDIP) 8S1 8-lead, 0.150” Wide, Plastic Gull Wing Small Outline Package (JEDEC SOIC) 8S2 8-lead, 0.200” Wide Plastic Gull Wing Small Outline Package (EIAJ SOIC) 8A2 8-lead, 4.4 mm Body, Plastic Thin Shrink Small Outline Package (TSSOP) 8Y7 8-lead, 6.00 mm x 4.90 mm Body, Ultra Thin, Dual Footprint, Non-leaded, Small Array Package (SAP) 8U2-1 8-ball, die Ball Grid Array Package (dBGA2) Options –1.8 Low-voltage (1.8V to 3.6V) –2.5 Low-voltage (2.5V to 5.5V) 12 AT24C512B 5297A–SEEPR–1/08 AT24C512B 7. Part marking scheme: 7.1 8-PDIP(1.8V) TOP MARK Seal Year | Seal Week | | | |---|---|---|---|---|---|---|---| A T M L U Y W W Y = SEAL YEAR 6: 2006 0: 2010 7: 2007 8: 2008 9: 2009 1: 2011 2: 2012 3: 2013 |---|---|---|---|---|---|---|---| 2 F B 04 = Week 4 :: : :::: : :: : :::: :: 50 = Week 50 1 52 = Week 52 |---|---|---|---|---|---|---|---| * Lot Number |---|---|---|---|---|---|---|---| | Pin 1 Indicator (Dot) 7.2 WW = SEAL WEEK 02 = Week 2 Lot Number to Use ALL Characters in Marking BOTTOM MARK No Bottom Mark 8-PDIP(2.5V) TOP MARK Seal Year | Seal Week | | | |---|---|---|---|---|---|---|---| A T M L U Y W W Y = SEAL YEAR 6: 2006 0: 2010 7: 2007 8: 2008 9: 2009 1: 2011 2: 2012 3: 2013 |---|---|---|---|---|---|---|---| 2 F B | Pin 1 Indicator (Dot) 04 = Week 4 :: : :::: : :: : :::: :: 50 = Week 50 2 |---|---|---|---|---|---|---|---| * Lot Number |---|---|---|---|---|---|---|---| WW = SEAL WEEK 02 = Week 2 52 = Week 52 Lot Number to Use ALL Characters in Marking BOTTOM MARK No Bottom Mark 13 5297A–SEEPR–1/08 7.3 8-SOIC(1.8V) TOP MARK Seal Year | Seal Week | | | |---|---|---|---|---|---|---|---| A T M L H Y W W Y = SEAL YEAR 6: 2006 0: 2010 7: 2007 8: 2008 9: 2009 1: 2011 2: 2012 3: 2013 |---|---|---|---|---|---|---|---| 2 F B 52 = Week 52 Lot Number to Use ALL Characters in Marking BOTTOM MARK No Bottom Mark 8-SOIC(2.5V) TOP MARK Seal Year | Seal Week | | | |---|---|---|---|---|---|---|---| A T M L H Y W W Y = SEAL YEAR 6: 2006 0: 2010 7: 2007 8: 2008 9: 2009 1: 2011 2: 2012 3: 2013 |---|---|---|---|---|---|---|---| 2 F B WW = SEAL WEEK 02 = Week 2 04 = Week 4 :: : :::: : :: : :::: :: 50 = Week 50 2 |---|---|---|---|---|---|---|---| * Lot Number |---|---|---|---|---|---|---|---| | Pin 1 Indicator (Dot) 14 04 = Week 4 :: : :::: : :: : :::: :: 50 = Week 50 1 |---|---|---|---|---|---|---|---| * Lot Number |---|---|---|---|---|---|---|---| | Pin 1 Indicator (Dot) 7.4 WW = SEAL WEEK 02 = Week 2 52 = Week 52 Lot Number to Use ALL Characters in Marking BOTTOM MARK No Bottom Mark AT24C512B 5297A–SEEPR–1/08 AT24C512B 7.5 8-TSSOP(1.8V) TOP MARK Pin 1 Indicator (Dot) | |---|---|---|---| * H Y W W |---|---|---|---|---| 2 F B 1 Y = SEAL YEAR 6: 7: 8: 9: 2006 2007 2008 2009 0: 1: 2: 3: WW = SEAL WEEK 2010 2011 2012 2013 * 02 04 :: :: = = : : Week Week :::: :::: 2 4 : :: 50 = Week 50 |---|---|---|---|---| 52 = Week 52 BOTTOM MARK |---|---|---|---|---|---|---| Country of origin C 0 0 |---|---|---|---|---|---|---| A A A A A A A |---|---|---|---|---|---|---| 2FBU YMTC |