AT24C64B
2-Wire Automotive Serial EEPROM
64-Kbit (8,192 x 8)
DATASHEET
Features
Standard-Voltage Operation
̶
2.7 (VCC = 2.7V to 5.5V)
Internally Organized 8,192 x 8 (64K)
Automotive Temperature Range –40C to +125C
2-Wire Serial Interface
Schmitt Trigger, Filtered Inputs for Noise Suppression
Bidirectional Data Transfer Protocol
400kHz Clock Rate
Write Protect Pin for Hardware Data Protection
32-byte Page Write Mode (Partial Page Writes Allowed)
Self-timed Write Cycle (5ms Max)
High Reliability
̶
̶
Endurance: 1,000,000 Write Cycles
Data Retention: 100 Years
Lead-free/Halogen-free Devices Available
8-lead JEDEC SOIC and 8-lead TSSOP Packages
Description
The Atmel® AT24C64B provides 65,536 bits of Serial Electrically Erasable and
Programmable Read-Only Memory (EEPROM) organized as 8,192 words of 8 bits
each. The device’s cascadable feature allows up to eight devices to share a
common 2-wire bus. The device is optimized for use in many automotive
applications where low power and low voltage operation are essential. The
AT24C64B is available in space saving 8-lead JEDEC SOIC and 8-lead TSSOP
packages and is accessed via a 2-wire serial interface and is available in a 2.7V
(2.7V to 5.5V) version.
Atmel-8778B-SEEPROM-AT24C64B-Auto-Datasheet_082014
1.
Pin Configurations and Pinouts
Figure 1.
Pin Name
2.
Pin Configurations
Function
A0 – A2
Address Inputs
GND
Ground
VCC
Power Supply
WP
Write Protect
SCL
Serial Clock Input
SDA
Serial Data
8-lead TSSOP
(Top View)
(Top View)
A0
1
8
VCC
A1
2
7
WP
A0
A1
A2
GND
A2
3
6
SCL
GND
4
5
SDA
Note:
Drawings are not to scale.
1
2
3
4
8
7
6
5
VCC
WP
SCL
SDA
Absolute Maximum Ratings*
Operating Temperature . . . . . . . . . . –55C to +125C
Storage Temperature . . . . . . . . . . . . –65C to +150C
Voltage on Any Pin
with Respect to Ground . . . . . . . . . . . . –1.0V to +7.0V
Maximum Operating Voltage . . . . . . . . . . . . . . . 6.25V
DC Output Current . . . . . . . . . . . . . . . . . . . . . . .5.0mA
2
8-lead SOIC
AT24C64B Automotive [DATASHEET]
Atmel-8778B-SEEPROM-AT24C64B-Auto-Datasheet_082014
*Notice: Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent damage
to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
3.
Block Diagram
Figure 3-1.
Block Diagram
VCC
GND
WP
Start
Stop
Logic
Serial
Control
Logic
LOAD
Device
Address
Comparator
A2
A1
A0
R/W
EN
H.V. Pump/Timing
COMP
LOAD
Data Word
ADDR/Counter
Y DEC
Data Recovery
INC
X DEC
SCL
SDA
EEPROM
Serial MUX
DOUT/ACK
Logic
DIN
DOUT
4.
Pin Description
Serial Clock (SCL): The SCL input is used to positive edge clock data into each EEPROM device and negative
edge clock data out of each device.
Serial Data (SDA): The SDA pin is bidirectional for serial data transfer. This pin is open-drain driven and may
be wire-ORed with any number of other open-drain or open collector devices.
Device Address (A2, A1, and A0): The A2, A1, and A0 pins are device address inputs that are hardwired or left
not connected for hardware compatibility with other AT24Cxx devices. When the pins are hardwired, as many
as eight 64K devices may be addressed on a single bus system (see Section 7., “Device Addressing”). If the
pins are left floating, the A2, A1, and A0 pins will internally be pulled down to Ground (GND) if the capacitive
coupling to the circuit board VCC plane is less than 3pF. If coupling is greater than 3pF, Atmel recommends
connecting the address pins to GND.
Write Protect (WP): The Write Protect input, when connected to GND, allows normal write operations. When
WP is connected high to VCC, all write operations to upper quadrant of the memory are inhibited. If the pin is left
floating, the WP pin will be internally pulled down to GND if the capacitive coupling to the circuit board VCC plane
is less than 3pF. If coupling is greater than 3pF, Atmel recommends connecting the pin to GND. Switching WP
to VCC prior to a write operation creates a software write protect function.
AT24C64B Automotive [DATASHEET]
Atmel-8778B-SEEPROM-AT24C64B-Auto-Datasheet_082014
3
5.
Memory Organization
AT24C64B, 64K Serial EEPROM: The 64K is internally organized as 256 pages of 32 bytes each. Random
word addressing requires a 13-bit data word address.
5.1
Pin Capacitance
Table 5-1.
Pin Capacitance(1)
Applicable over recommended operating range from TA = 25C, f = 1.0MHz, VCC = 5.5V.
Symbol
Test Condition
CI/O
CIN
Note:
5.2
1.
Max]
Units
Conditions
Input/Output Capacitance (SDA)
8
pF
VI/O = 0V
Input Capacitance (A0, A1, A2, SCL)
6
pF
VIN = 0V
This parameter is characterized and is not 100% tested.
DC Characteristics
Table 5-2.
DC Characteristics
Applicable over recommended operating range from: TA = -40C to +125C, VCC = +2.7V to +5.5V (unless otherwise noted).
Symbol
Parameter
VCC3
Supply Voltage
ICC1
Supply Current
VCC = 5.0V
Read at 400kHz
ICC2
Supply Current
VCC = 5.0V
Write at 400kHz
ISB
Standby Current
ILI
Input Leakage Current
ILO
Output Leakage Current
VIL(1)
Input Low Level
VIH(1)
Input High Level
VOL2
Output Low Level
VCC = 3.0V
VOL1
Output Low Level
VCC = 1.8V
Note:
4
1.
Test Condition
Min
Max
Units
5.5
V
0.4
1.0
mA
2.0
3.0
mA
1.0
3.0
3.0
5.0
VIN = VCC or VSS
0.10
3.0
μA
VOUT = VCC or VSS
0.05
3.0
μA
-0.6
VCC x 0.3
V
VCC x 0.7
VCC + 0.5
V
IOL = 2.1mA
0.4
V
IOL = 0.15mA
0.2
V
2.7
VCC = 2.7V
VCC = 5.0V
VIN = VCC or VSS
VIL min and VIH max are reference only and are not tested.
AT24C64B Automotive [DATASHEET]
Atmel-8778B-SEEPROM-AT24C64B-Auto-Datasheet_082014
Typ
μA
5.3
AC Characteristics
Table 5-3.
AC Characteristics
Applicable over recommended operating range from TA = -40C to +125C, VCC = +2.7V to +5.5V, CL = 1 TTL Gate and
100pF (unless otherwise noted).
Symbol
Parameter
Min
fSCL
Clock Frequency, SCL
tLOW
Clock Pulse Width Low
1.2
μs
tHIGH
Clock Pulse Width High
0.6
μs
tI
Noise Suppression Time(1)
tAA
Clock Low to Data Out Valid
0.1
(1)
Max
Units
400
kHz
50
ns
0.9
μs
tBUF
Time the bus must be free before a new transmission can start
1.2
μs
tHD.STA
Start Hold Time
0.6
μs
tSU.STA
Start Set-up Time
0.6
μs
tHD.DAT
Data In Hold Time
0
μs
tSU.DAT
Data In Set-up Time
100
ns
tR(1)
Inputs Rise Time
0.3
μs
tF(1)
Inputs Fall Time
300
ns
tSU.STO
Stop Set-up Time
0.6
μs
tDH
Data Out Hold Time
50
ns
tWR
Write Cycle Time
Endurance(1)
5.0V, 25C, Page Mode
Note:
1.
5
1,000,000
ms
Write Cycles
This parameter is ensured by characterization only.
AT24C64B Automotive [DATASHEET]
Atmel-8778B-SEEPROM-AT24C64B-Auto-Datasheet_082014
5
6.
Device Operation
Clock and Data Transitions: The SDA pin is normally pulled high with an external device. Data on the SDA pin
may change only during SCL low time periods (see to Data Validity timing diagram). Data changes during SCL
high periods will indicate a Start or Stop condition as defined below.
Figure 6-1.
Data Validity
SDA
SCL
Data Stable
Data Stable
Data
Change
Start Condition: A high-to-low transition of SDA with SCL high is a Start condition which must precede any
other command.
Stop Condition: A low-to-high transition of SDA with SCL high is a Stop condition. After a read sequence, the
Stop condition will place the EEPROM in a standby power mode.
Figure 6-2.
Start and Stop Definition
SDA
SCL
Start
6
AT24C64B Automotive [DATASHEET]
Atmel-8778B-SEEPROM-AT24C64B-Auto-Datasheet_082014
Stop
Acknowledge: All addresses and data words are serially transmitted to and from the EEPROM in 8-bit words.
The EEPROM sends a zero during the ninth clock cycle to acknowledge that it has received each word.
Figure 6-3.
Output Acknowledge
1
SCL
8
9
Data In
Data Out
Acknowledge
Start
Standby Mode: The AT24C64B features a low power standby mode which is enabled:
Upon power-up.
After the receipt of the Stop condition and the completion of any internal operations.
Memory Reset: After an interruption in protocol, power loss or system reset, any 2-wire part can be reset by
following these steps:
Clock up to nine cycles,
Look for SDA high in each cycle while SCL is high, and
Create a Start condition as SDA is high.
The device is ready for the next communication after above steps have been completed.
Figure 6-4.
Memory Reset
Dummy Clock Cycles
SCL
1
Start
Condition
2
3
8
9
Start
Condition
Stop
Condition
SDA
AT24C64B Automotive [DATASHEET]
Atmel-8778B-SEEPROM-AT24C64B-Auto-Datasheet_082014
7
Figure 6-5.
Bus Timing — SCL: Serial Clock, SDA: Serial Data I/O
tHIGH
tF
tR
tLOW
tLOW
SCL
tSU.STA
tHD.STA
tHD.DAT
tSU.DAT
tSU.STO
SDA In
tAA
tDH
tBUF
SDA Out
Figure 6-6.
Write Cycle Timing — SCL: Serial Clock, SDA: Serial Data I/O
SCL
8th bit
SDA
ACK
WORDn
tWR(1)
Stop
Condition
Note:
8
1.
Start
Condition
The write cycle time tWR is the time from a valid stop condition of a write sequence to the end of the internal
clear/write cycle.
AT24C64B Automotive [DATASHEET]
Atmel-8778B-SEEPROM-AT24C64B-Auto-Datasheet_082014
7.
Device Addressing
The 64K EEPROM requires an 8-bit device address word following a Start condition to enable the device for a
Read or Write operation. The device address word consists of a mandatory one, zero sequence for the first four
most significant bits as shown. This is common to all 2-wire EEPROM devices.
The 64K uses the three device address bits A2, A1, and A0 to allow as many as eight devices on the same bus.
These bits must compare to their corresponding hardwired input pins. The A2, A1, and A0 pins use an internal
proprietary circuit that biases them to a logic low condition if the pins are allowed to float.
The eighth bit of the device address is the Read/Write operation select bit. A Read operation is initiated if this bit
is high, and a Write operation is initiated if this bit is low.
Upon a compare of the device address, the EEPROM will output a zero. If a compare is not made, the device
will return to standby state.
Noise Protection: Special internal circuitry placed on the SDA and SCL pins prevent small noise spikes from
activating the device.
Data Security: The AT24C64B has a hardware data protection scheme that allows the user to write protect the
upper quadrant of memory when the WP pin is at VCC.
Figure 7-1.
64K
1
MSB
Device Address
0
1
0
A2
A1
A0
R/W
LSB
AT24C64B Automotive [DATASHEET]
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9
8.
Write Operations
Byte Write: A Write operation requires two 8-bit data word addresses following the device address word and
acknowledgment. Upon receipt of this address, the EEPROM will again respond with a zero and then clock in
the first 8-bit data word. Following receipt of the 8-bit data word, the EEPROM will output a zero and the
addressing device, such as a microcontroller, must terminate the write sequence with a Stop condition. At this
time the EEPROM enters an internally-timed write cycle, tWR, to the nonvolatile memory. All inputs are disabled
during this write cycle and the EEPROM will not respond until the write is complete.
Figure 8-1.
Byte Write
S
T
A
R
T
W
R
I
T
E
Device
Address
First
Word Address
Second
Word Address
S
T
O
P
Data
SDA LINE
M
S
B
Note:
1.
L R A
S / C
BW K
A
C
K
A
C
K
L A
S C
B K
* = Don’t care bit.
Page Write: The 64K EEPROM is capable of 32-byte Page Writes.
A Page Write is initiated the same way as a byte write, but the microcontroller does not send a Stop condition
after the first data word is clocked in. Instead, after the EEPROM acknowledges receipt of the first data word,
the microcontroller can transmit up to 31 more data words. The EEPROM will respond with a zero after each
data word received. The microcontroller must terminate the Page Write sequence with a Stop condition.
The data word address lower five bits are internally incremented following the receipt of each data word. The
higher data word address bits are not incremented, retaining the memory page row location. When the word
address, internally generated, reaches the page boundary, the following byte is placed at the beginning of the
same page. If more than 32 data words are transmitted to the EEPROM, the data word address will roll-over
and previous data will be overwritten.
Figure 8-2.
Page Write
S
T
A
R
T
Device
Address
W
R
I
T
E
First
Word Address (n)
Second
Word Address (n)
Data (n)
S
T
O
P
Data (n + x)
SDA Line
M
S
B
Note:
1.
L R A
S / C
BWK
A
C
K
A
C
K
A
C
K
A
C
K
* = Don’t care bit.
Acknowledge Polling: Once the internally-timed write cycle has started and the EEPROM inputs are disabled,
Acknowledge Polling can be initiated. This involves sending a Start condition followed by the device address
word. The Read/Write bit is representative of the operation desired. Only if the internal write cycle has
completed will the EEPROM respond with a zero, allowing the read or write sequence to continue.
10
AT24C64B Automotive [DATASHEET]
Atmel-8778B-SEEPROM-AT24C64B-Auto-Datasheet_082014
9.
Read Operations
Read operations are initiated the same way as write operations with the exception that the Read/write select bit
in the device address word is set to one. There are three read operations:
Current Address Read
Random Address Read
Sequential Read
Current Address Read: The internal data word address counter maintains the last address accessed during
the last Read or Write operation, incremented by one. This address stays valid between operations as long as
the device power is maintained. The address roll-over during read is from the last byte of the last memory page,
to the first byte of the first page. The address roll-over during write is from the last byte of the current page to the
first byte of the same page.
Once the device address with the Read/write select bit set to one is clocked in and acknowledged by the
EEPROM, the current address data word is serially clocked out. The microcontroller does not respond with an
input zero but does generate a following Stop condition.
Figure 9-1.
Current Address Read
S
T
A
R
T
Device
Address
R
E
A
D
S
T
O
P
Data
SDA Line
M
S
B
N
O
L R A
S / C
B WK
A
C
K
Random Read: A Random Read requires a dummy byte write sequence to load in the data word address. Once
the device address word and data word address are clocked in and acknowledged by the EEPROM, the
microcontroller must generate another Start condition. The microcontroller now initiates a Current Address
Read by sending a device address with the Read/Write select bit high. The EEPROM acknowledges the device
address and serially clocks out the data word. The microcontroller does not respond with a zero but does
generate a following Stop condition.
Figure 9-2.
Random Read
S
T
A
R
T
Device
Address
W
R
I
T
E
S
T
A
R
T
1st, 2nd Word
Address (n)
Device
Address
R
E
A
D
S
T
O
P
Data (n)
SDA Line
M
S
B
LR A
S / C
BW K
Dummy Write
Note:
1.
A
C
K
A
C
K
N
O
A
C
K
* = Don’t care bit.
AT24C64B Automotive [DATASHEET]
Atmel-8778B-SEEPROM-AT24C64B-Auto-Datasheet_082014
11
Sequential Read: Sequential Reads are initiated by either a Current Address Read or a Random Address
Read. After the microcontroller receives a data word, it responds with an acknowledge. As long as the EEPROM
receives an acknowledge, it will continue to increment the data word address and serially clock out sequential
data words. When the memory address limit is reached, the data word address will roll-over and the Sequential
Read will continue. The Sequential Read operation is terminated when the microcontroller does not respond
with a zero but does generate a following Stop condition.
Figure 9-3.
Sequential Read
Device
Address
R
E
A
D
Data (n)
A
C
K
Data (n + 1)
A
C
K
Data (n + 2)
A
C
K
S
T
O
P
Data (n + x)
SDA Line
R A
/ C
WK
10.
N
O
A
C
K
Power Recommendation
The device internal POR (Power-On Reset) threshold is just below the minimum operating voltage of the device.
Power shall rise monotonically from 0.0Vdc to full VCC in less than 1ms. Hold at full VCC for at least 100μs before
the first operation. Power shall drop from full VCC to 0.0Vdc in less than 1ms. Power dropping to a non-zero level
and then slowly going to zero is not recommended. Power shall remain off (0.0Vdc) for 0.5s minimum. Please
consult Atmel if your power conditions do not meet the above recommendations.
12
AT24C64B Automotive [DATASHEET]
Atmel-8778B-SEEPROM-AT24C64B-Auto-Datasheet_082014
11.
Ordering Code Detail
A T 2 4 C 6 4 B N - 1 0 S Q - 2.7
Atmel Designator
Operating Voltage
M = 2.7V to 5.5V
Product Family
24C = 2-Wire Compatible
Serial EEPROM
Device Density
Package Device Grade
Q = Lead-free/Halogen-free
Automotive Temperature Range
(-40°C to +125°C)
64 = 64 kilobit
Package Option
Device Revision
Package Variation
(Package Type Dependant)
N = 0.150” width SOIC
S = JEDEC SOIC
T = TSSOP
Speed Type
10 = Default Value
Note: This field is not used for
Serial EEPROM products.
AT24C64B Automotive [DATASHEET]
Atmel-8778B-SEEPROM-AT24C64B-Auto-Datasheet_082014
13
12.
Product Markings
AT24C64B Automotive Package Marking Information
8-lead TSSOP
8-lead SOIC
ATMELYWW
24C64BN
SQ%%
D
Q% D
AT###
Note: Lot Number, location of assembly and
YWW date code on the bottom side of
the package.
Note: Lot Number and location of assembly
on the bottom side of the package.
Note 1:
designates pin 1
Note 2: Package drawings are not to scale
Catalog Number Truncation
AT24C64B
Truncation Code ###: 64B
Date Codes
Y = Year
4: 2014
5: 2015
6: 2016
7: 2017
Voltages
8: 2018
9: 2019
0: 2020
1: 2021
M = Month
A: January
B: February
...
L: December
WW = Work Week of Assembly
02: Week 2
04: Week 4
...
52: Week 52
% = Minimum Voltage
3 or 27: 2.7V min
Country of Assembly
Lot Number
Grade/Lead Finish Material
@ = Country of Assembly
AAA...A = Atmel Wafer Lot Number
Q:
Trace Code
Automotive /Matte Tin/SnAgCu
Atmel Truncation
XX = Trace Code (Atmel Lot Numbers Correspond to Code)
Example: AA, AB.... YZ, ZZ
AT: Atmel
ATM: Atmel
ATML: Atmel
6/12/14
TITLE
Package Mark Contact:
DL-CSO-Assy_eng@atmel.com
14
24C64BAM, AT24C64B Automotive Package Marking
Information
AT24C64B Automotive [DATASHEET]
Atmel-8778B-SEEPROM-AT24C64B-Auto-Datasheet_082014
DRAWING NO.
REV.
24C64BAM
C
13.
Ordering Information(1)
Atmel Ordering Code
AT24C64BN-10SQ-2.7(2)
AT24C64B-10TQ-2.7
Notes:
1.
2.
(2)
Lead Finish
Package
Matte Tin
(Lead-free/Halogen-free)
8S1
8X
Voltage
Operation Range
2.7V to 5.5V
Automotive Temperature
(-40C to +125C)
For 2.7V devices used in the 4.5V to 5.5V range, please refer to performance values in the AC and DC
characteristics tables.
“Q” designates green package and RoHS compliant.
Package Type
8S1
8-lead, 0.150" wide body, Plastic Gull Wing Small Outline (JEDEC SOIC)
8X
8-lead, 4.4mm body, Plastic Thin Shrink Small Outline Package (TSSOP)
AT24C64B Automotive [DATASHEET]
Atmel-8778B-SEEPROM-AT24C64B-Auto-Datasheet_082014
15
14.
Package Drawings
14.1
8S1 — 8-lead JEDEC SOIC
C
1
E
E1
L
N
Ø
TOP VIEW
END VIEW
e
b
COMMON DIMENSIONS
(Unit of Measure = mm)
A
A1
D
SIDE VIEW
Notes: This drawing is for general information only.
Refer to JEDEC Drawing MS-012, Variation AA
for proper dimensions, tolerances, datums, etc.
SYMBOL MIN
A
1.35
NOM
MAX
–
1.75
A1
0.10
–
0.25
b
0.31
–
0.51
C
0.17
–
0.25
D
4.80
–
5.05
E1
3.81
–
3.99
E
5.79
–
6.20
e
NOTE
1.27 BSC
L
0.40
–
1.27
Ø
0°
–
8°
6/22/11
Package Drawing Contact:
packagedrawings@atmel.com
16
TITLE
8S1, 8-lead (0.150” Wide Body), Plastic Gull Wing
Small Outline (JEDEC SOIC)
AT24C64B Automotive [DATASHEET]
Atmel-8778B-SEEPROM-AT24C64B-Auto-Datasheet_082014
GPC
SWB
DRAWING NO.
REV.
8S1
G
14.2
8X — 8-lead TSSOP
C
1
Pin 1 indicator
this corner
E1
E
L1
N
L
Top View
End View
A
b
A1
e
COMMON DIMENSIONS
(Unit of Measure = mm)
A2
D
SYMBOL
Side View
Notes:
1. This drawing is for general information only.
Refer to JEDEC Drawing MO-153, Variation AA, for proper
dimensions, tolerances, datums, etc.
2. Dimension D does not include mold Flash, protrusions or gate
burrs. Mold Flash, protrusions and gate burrs shall not exceed
0.15mm (0.006in) per side.
3. Dimension E1 does not include inter-lead Flash or protrusions.
Inter-lead Flash and protrusions shall not exceed 0.25mm
(0.010in) per side.
4. Dimension b does not include Dambar protrusion.
Allowable Dambar protrusion shall be 0.08mm total in excess
of the b dimension at maximum material condition. Dambar
cannot be located on the lower radius of the foot. Minimum
space between protrusion and adjacent lead is 0.07mm.
5. Dimension D and E1 to be determined at Datum Plane H.
MIN
NOM
MAX
A
-
-
1.20
A1
0.05
-
0.15
A2
0.80
1.00
1.05
D
2.90
3.00
3.10
2, 5
E
NOTE
6.40 BSC
E1
4.30
4.40
4.50
3, 5
b
0.19
0.25
0.30
4
e
L
0.65 BSC
0.45
L1
C
0.60
0.75
1.00 REF
0.09
-
0.20
2/27/14
TITLE
Package Drawing Contact:
packagedrawings@atmel.com
GPC
8X, 8-lead 4.4mm Body, Plastic Thin
Shrink Small Outline Package (TSSOP)
TNR
DRAWING NO.
8X
AT24C64B Automotive [DATASHEET]
Atmel-8778B-SEEPROM-AT24C64B-Auto-Datasheet_082014
REV.
E
17
15.
18
Revision History
Revision
Date
Comments
8778B
08/2014
Add the sections, power recommendation and ordering code detail. Updated part markings,
template, logos, and disclaimer page. No changes to functional specification.
8778A
09/2011
Initial document release.
AT24C64B Automotive [DATASHEET]
Atmel-8778B-SEEPROM-AT24C64B-Auto-Datasheet_082014
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