AT24C32D/AT24C64D
I²C Automotive Temperature Serial EEPROM
32‑Kbit (4,096 x 8), 64‑Kbit (8,192 x 8)
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Low-Voltage, Medium-Voltage Operation:
– Grade 1, VCC = 2.5V to 5.5V
– Grade 3, VCC = 1.7V to 5.5V
Internally Organized as 4,094 x 8 (32K) or 8,192 x 8 (64K)
Extended Temperature Range (Grade 1 and Grade 3 as defined in AEC-Q100):
– Grade 1 Temperature Range: -40°C to +125°C
– Grade 3 Temperature Range: -40°C to +85°C
I2C-Compatible (Two-Wire) Serial Interface:
– 100 kHz Standard mode
– 400 kHz Fast mode
Schmitt Triggers, Filtered Inputs for Noise Suppression
Bidirectional Data Transfer Protocol
Write-Protect Pin for Hardware Data Protection
Ultra Low Active Current (3 mA maximum) and Standby Current (6 μA maximum)
32-Byte Page Write Mode:
– Partial page writes allowed
Random and Sequential Read Modes
Self-Timed Write Cycle within 5 ms Maximum
Automotive AEC-Q100 Qualified
High Reliability:
– Endurance: 1,000,000 write cycles
– Data retention: 100 years
Green Package Options (Lead-free/Halide-free/RoHS compliant)
Packages
•
8-Lead SOIC, 8-Lead TSSOP, 8-Pad UDFN and 5-Lead SOT23 (AT24C32D only)
© 2019 Microchip Technology Inc.
Datasheet
DS20006271A-page 1
AT24C32D/AT24C64D
Table of Contents
Features......................................................................................................................................................... 1
Packages........................................................................................................................................................1
1.
Package Types (not to scale)..................................................................................................................4
2.
Pin Descriptions...................................................................................................................................... 5
2.1.
2.2.
2.3.
2.4.
2.5.
2.6.
3.
Description.............................................................................................................................................. 7
3.1.
3.2.
4.
Byte Write...................................................................................................................................18
Page Write..................................................................................................................................18
Acknowledge Polling.................................................................................................................. 19
Write Cycle Timing..................................................................................................................... 19
Write Protection..........................................................................................................................20
Read Operations................................................................................................................................... 21
8.1.
8.2.
8.3.
9.
Device Addressing..................................................................................................................... 16
Write Operations................................................................................................................................... 18
7.1.
7.2.
7.3.
7.4.
7.5.
8.
Clock and Data Transition Requirements...................................................................................13
Start and Stop Conditions.......................................................................................................... 13
Acknowledge and No-Acknowledge...........................................................................................14
Standby Mode............................................................................................................................ 14
Software Reset...........................................................................................................................14
Memory Organization............................................................................................................................16
6.1.
7.
Absolute Maximum Ratings..........................................................................................................9
DC and AC Operating Range.......................................................................................................9
DC Characteristics....................................................................................................................... 9
AC Characteristics......................................................................................................................10
Electrical Specifications..............................................................................................................11
Device Operation and Communication................................................................................................. 13
5.1.
5.2.
5.3.
5.4.
5.5.
6.
System Configuration Using Two-Wire Serial EEPROMs ........................................................... 7
Block Diagram.............................................................................................................................. 8
Electrical Characteristics.........................................................................................................................9
4.1.
4.2.
4.3.
4.4.
4.5.
5.
Device Address Inputs (A0, A1, A2).............................................................................................5
Ground......................................................................................................................................... 5
Serial Data (SDA).........................................................................................................................5
Serial Clock (SCL)........................................................................................................................5
Write-Protect (WP)....................................................................................................................... 6
Device Power Supply (VCC)......................................................................................................... 6
Current Address Read................................................................................................................21
Random Read............................................................................................................................ 21
Sequential Read.........................................................................................................................22
Device Default Condition from Microchip.............................................................................................. 23
© 2019 Microchip Technology Inc.
Datasheet
DS20006271A-page 2
AT24C32D/AT24C64D
10. Packaging Information.......................................................................................................................... 24
10.1. Package Marking Information.....................................................................................................24
11. Revision History.................................................................................................................................... 36
The Microchip Website.................................................................................................................................37
Product Change Notification Service............................................................................................................37
Customer Support........................................................................................................................................ 37
Product Identification System.......................................................................................................................38
Microchip Devices Code Protection Feature................................................................................................ 38
Legal Notice................................................................................................................................................. 39
Trademarks.................................................................................................................................................. 39
Quality Management System....................................................................................................................... 40
Worldwide Sales and Service.......................................................................................................................41
© 2019 Microchip Technology Inc.
Datasheet
DS20006271A-page 3
AT24C32D/AT24C64D
Package Types (not to scale)
1.
Package Types (not to scale)
8-Lead SOIC/TSSOP
(Top View)
A0
1
8
Vcc
A1
2
7
WP
A2
3
6
SCL
GND
4
5
SDA
8-Pad UDFN
(Top View)
A0
1
8
Vcc
A1
2
7
WP
A2
3
6
GND
4
5
5-Lead SOT23 (1,2)
(Top View)
SCL
1
SCL
GND
2
SDA
SDA
3
5
WP
4
Vcc
Note:
1. AT24C32D only.
2. Refer to Device Addressing for details about addressing the SOT23 version of the device.
© 2019 Microchip Technology Inc.
Datasheet
DS20006271A-page 4
AT24C32D/AT24C64D
Pin Descriptions
2.
Pin Descriptions
The descriptions of the pins are listed in Table 2-1.
Table 2-1. Pin Function Table
Name
A0(3)
A1(3)
A2(3)
GND
SDA
SCL
WP(3)
VCC
8-Lead SOIC
1
2
3
4
5
6
7
8
8-Lead TSSOP
1
2
3
4
5
6
7
8
8-Pad UDFN(1) 5-Lead SOT23(2)
1
—
2
—
3
—
4
2
5
3
6
1
7
5
8
4
Function
Device Address Input
Device Address Input
Device Address Input
Ground
Serial Data
Serial Clock
Write-Protect
Device Power Supply
Note:
1. The exposed pad on this package can be connected to GND or left floating.
2. AT24C32D only.
3. If the A0, A1, A2 or WP pins are not driven, they are internally pulled down to GND. In order to operate in a
wide variety of application environments, the pull-down mechanism is intentionally designed to be somewhat
strong. Once this pin is biased above the CMOS input buffer’s trip point (~0.5 x VCC), the pull‑down
mechanism disengages. Microchip recommends connecting this pin to a known state whenever possible.
2.1
Device Address Inputs (A0, A1, A2)
The A0, A1 and A2 pins are device address inputs that are hard-wired (directly to GND or to VCC) for compatibility
with other two-wire Serial EEPROM devices. When the pins are hard-wired, as many as eight devices may be
addressed on a single bus system. A device is selected when a corresponding hardware and software match is true.
If these pins are left floating, the A0, A1 and A2 pins will be internally pulled down to GND. However, due to
capacitive coupling that may appear in customer applications, Microchip recommends always connecting the address
pins to a known state. When using a pull‑up resistor, Microchip recommends using 10 kΩ or less.
2.2
Ground
The ground reference for the power supply. GND should be connected to the system ground.
2.3
Serial Data (SDA)
The SDA pin is an open-drain bidirectional input/output pin used to serially transfer data to and from the device. The
SDA pin must be pulled high using an external pull-up resistor (not to exceed 10 kΩ in value) and may be wire-ORed
with any number of other open-drain or open-collector pins from other devices on the same bus.
2.4
Serial Clock (SCL)
The SCL pin is used to provide a clock to the device and to control the flow of data to and from the device. Command
and input data present on the SDA pin is always latched in on the rising edge of SCL, while output data on the SDA
pin is clocked out on the falling edge of SCL. The SCL pin must either be forced high when the serial bus is idle or
pulled high using an external pull-up resistor.
© 2019 Microchip Technology Inc.
Datasheet
DS20006271A-page 5
AT24C32D/AT24C64D
Pin Descriptions
2.5
Write-Protect (WP)
The write-protect input, when connected to GND, allows normal write operations. When the WP pin is connected
directly to VCC, all write operations to the protected memory are inhibited.
If the pin is left floating, the WP pin will be internally pulled down to GND. However, due to capacitive coupling that
may appear in customer applications, Microchip recommends always connecting the WP pin to a known state. When
using a pull‑up resistor, Microchip recommends using 10 kΩ or less.
Table 2-2. Write-Protect
2.6
WP Pin Status
Part of the Array Protected
At VCC
Full (32K/64K) Array
At GND
Normal Write Operations
Device Power Supply (VCC)
The Device Power Supply (VCC) pin is used to supply the source voltage to the device. Operations at invalid VCC
voltages may produce spurious results and should not be attempted.
© 2019 Microchip Technology Inc.
Datasheet
DS20006271A-page 6
AT24C32D/AT24C64D
Description
3.
Description
The AT24C32D/AT24C64D provides 32,768/65,536 bits of Serial Electrically Erasable and Programmable Read-Only
Memory (EEPROM) organized as 4,096/8,192 words of 8 bits each. This device is optimized for use in many
automotive applications where low-power and low-voltage operations are essential. The device is available
in space‑saving 8‑lead SOIC, 8‑lead TSSOP, 8‑pad UDFN and 5‑lead SOT23 (AT24C32D only) packages. All
packages operate from 1.7V to 5.5V for Grade 3 and 2.5V to 5.5V for Grade 1.
3.1
System Configuration Using Two-Wire Serial EEPROMs
VCC
RPUP(max) =
tR(max)
0.8473 x CL
V - VOL(max)
RPUP(min) = CC
IOL
VCC
SCL
SDA
WP
I2C Bus Master:
Microcontroller
A0
A1
A2
GND
© 2019 Microchip Technology Inc.
GND
VCC
A0
WP
A1
AT24CXXX SDA
A2
Slave 0
SCL
VCC
A0
WP
A1
AT24CXXX SDA
A2
Slave 1
GND
Datasheet
SCL
VCC
Slave 7
WP
AT24CXXX SDA
GND
SCL
DS20006271A-page 7
AT24C32D/AT24C64D
Description
Block Diagram
A0
Hardware
Address
Comparator
Memory
System Control
Module
Power-on
Reset
Generator
VCC
High-Voltage
Generation Circuit
A1
Row Decoder
3.2
EEPROM Array
1 page
A2
© 2019 Microchip Technology Inc.
WP
Address Register
and Counter
Column Decoder
SCL
Data Register
DOUT
GND
Write
Protection
Control
Data & ACK
Input/Output Control
DIN
Start
Stop
Detector
SDA
Datasheet
DS20006271A-page 8
AT24C32D/AT24C64D
Electrical Characteristics
4.
Electrical Characteristics
4.1
Absolute Maximum Ratings
Temperature under bias
-55°C to +125°C
Storage temperature
-65°C to +150°C
VCC
6.25V
Voltage on any pin with respect to ground
-1.0V to +7.0V
DC output current
5.0 mA
AT24C32D ESD protection
>3 kV
AT24C64D ESD protection
>4 kV
Note: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
This is a stress rating only and functional operation of the device at these or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.
4.2
DC and AC Operating Range
Table 4-1. DC and AC Operating Range
AT24C32D/AT24C64D
4.3
Automotive Grade 1
Automotive Grade 3
Operating Temperature (Case)
-40°C to +125°C
-40°C to +85°C
VCC Power Supply
2.5V to 5.5V
1.7V to 5.5V
DC Characteristics
Table 4-2. DC Characteristics
Symbol
Minimum
Typical(1)
Maximum
Units
VCC1
2.5
—
5.5
V
Grade 1
VCC2
1.7
—
5.5
V
Grade 3
Supply
Current
ICC1
—
0.4
1.0
mA
VCC = 5.0V, Read at 400 kHz
Supply
Current
ICC2
—
2.0
3.0
mA
VCC = 5.0V, Write at 400 kHz
Standby
Current
ISB
—
0.1
3.0
μA
VCC = 1.7V, VIN = VCC or GND
—
1.6
4.0
μA
VCC = 2.5V, VIN = VCC or GND
—
4.0
6.0
μA
VCC = 5.0V, VIN = VCC or GND
—
0.10
3.0
μA
VIN = VCC or GND
Parameter
Supply
Voltage
Input
Leakage
Current
ILI
© 2019 Microchip Technology Inc.
Datasheet
Test Conditions
DS20006271A-page 9
AT24C32D/AT24C64D
Electrical Characteristics
...........continued
Symbol
Minimum
Typical(1)
Maximum
Units
Output
Leakage
Current
ILO
—
0.05
3.0
μA
VOUT = VCC or GND
Input Low
Level
VIL
-0.6
—
VCC x 0.3
V
Note 2
Input High
Level
VIH
VCC x 0.7
—
VCC + 0.5
V
Note 2
Output Low
Level
VOL1
—
—
0.2
V
VCC = 1.7V, IOL = 0.15 mA
Output Low
Level
VOL2
—
—
0.4
V
VCC = 2.5V, IOL = 2.1 mA
Parameter
Test Conditions
Note:
1.
2.
4.4
Typical values characterized at TA = +25°C unless otherwise noted.
This parameter is characterized but is not 100% tested in production.
AC Characteristics
Table 4-3. AC Characteristics(1)
Parameter
Clock Frequency, SCL
Clock Pulse Width Low
Clock Pulse Width High
Noise Suppression Time(2)
Clock Low to Data Out Valid
Bus Free Time between Stop and Start
Start Hold Time
Start Set-Up Time
Data In Hold Time
Data In Set-up Time
Inputs Rise Time(3)
Inputs Fall Time(3)
Stop Set-Up Time
Data Out Hold Time
Write Cycle Time
Symbol
fSCL
tLOW
tHIGH
tI
tAA
tBUF
tHD.STA
tSU.STA
tHD.DAT
tSU.DAT
tR
tF
tSU.STO
tDH
tWR
Min.
—
4,700
4,000
—
—
4,700
4,000
4,700
0
200
—
—
4,700
100
—
Max.
100
—
—
100
4,500
—
—
—
—
—
1,000
300
—
—
5
Min.
—
1,200
600
—
100
1,200
600
600
0
100
—
—
600
50
—
Max.
400
—
—
50
900
—
—
—
—
—
300
300
—
—
5
Units
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
Note:
1. AC measurement conditions:
– CL: 100 pF
– RPUP (SDA bus line pull-up resistor to VCC): 1.3 kΩ (400 kHz)
– Input pulse voltages: 0.3 x VCC to 0.7 x VCC
– Input rise and fall times: ≤50 ns
– Input and output timing reference voltages: 0.5 x VCC
2. This parameter is characterized and is not 100% tested (TA = +25°C).
3. These parameters are determined through product characterization and are not 100% tested in production.
© 2019 Microchip Technology Inc.
Datasheet
DS20006271A-page 10
AT24C32D/AT24C64D
Electrical Characteristics
Figure 4-1. Bus Timing
tF
tHIGH
tR
tLOW
SCL
tSU.STA
tHD.STA
tHD.DAT
tSU.DAT
tSU.STO
SDA In
tBUF
tAA
tDH
SDA Out
4.5
4.5.1
Electrical Specifications
Power-Up Requirements and Reset Behavior
During a power-up sequence, the VCC supplied to the AT24C32D/AT24C64D should monotonically rise from GND to
the minimum VCC level, as specified in Table 4-1, with a slew rate no faster than 0.1 V/µs.
4.5.2
Device Reset
To prevent inadvertent write operations or any other spurious events from occurring during a power-up sequence, the
AT24C32D/AT24C64D includes a Power-on Reset (POR) circuit. Upon power-up, the device will not respond to any
commands until the VCC level crosses the internal voltage threshold (VPOR) that brings the device out of Reset and
into Standby mode.
The system designer must ensure the instructions are not sent to the device until the VCC supply has reached a
stable value greater than or equal to the minimum VCC level. Additionally, once the VCC is greater than or equal to the
minimum VCC level, the bus master must wait at least tPUP before sending the first command to the device. See Table
4-4 for the values associated with these power-up parameters.
Table 4-4. Power-Up Conditions(1)
Symbol
Parameter
tPUP
Time required after VCC is stable before the device can accept commands
VPOR
Power-on Reset Threshold Voltage
tPOFF
Minimum time at VCC = 0V between power cycles
Min.
Max.
Units
100
－
µs
－
1.5
V
500
－
ms
Note:
1. These parameters are characterized but they are not 100% tested in production.
If an event occurs in the system where the VCC level supplied to the AT24C32D/AT24C64D drops below the
maximum VPOR level specified, it is recommended that a full-power cycle sequence be performed by first driving the
VCC pin to GND, waiting at least the minimum tPOFF time and then performing a new power-up sequence in
compliance with the requirements defined in this section.
© 2019 Microchip Technology Inc.
Datasheet
DS20006271A-page 11
AT24C32D/AT24C64D
Electrical Characteristics
4.5.3
Pin Capacitance
Table 4-5. Pin Capacitance(1)
Symbol
Test Condition
Max.
Units
Conditions
CI/O
Input/Output Capacitance (SDA)
8
pF
VI/O = 0V
CIN
Input Capacitance (A0, A1, A2, WP and SCL)
6
pF
VIN = 0V
Note:
1. This parameter is characterized but is not 100% tested in production.
4.5.4
EEPROM Cell Performance Characteristics
Table 4-6. EEPROM Cell Performance Characteristics
Operation
Test Condition
Write Endurance(1)
TA = 25°C, VCC = 5.0V,
Page Write mode
Data Retention(1)
TA = 55°C
Min.
Max.
Units
1,000,000
—
Write Cycles
100
—
Years
Note:
1. Performance is determined through characterization and the qualification process.
© 2019 Microchip Technology Inc.
Datasheet
DS20006271A-page 12
AT24C32D/AT24C64D
Device Operation and Communication
5.
Device Operation and Communication
The AT24C32D/AT24C64D operates as a slave device and utilizes a simple I2C-compatible two-wire digital serial
interface to communicate with a host controller, commonly referred to as the bus master. The master initiates and
controls all read and write operations to the slave devices on the serial bus, and both the master and the slave
devices can transmit and receive data on the bus.
The serial interface is comprised of just two signal lines: Serial Clock (SCL) and Serial Data (SDA). The SCL pin is
used to receive the clock signal from the master, while the bidirectional SDA pin is used to receive command and
data information from the master as well as to send data back to the master. Data is always latched into the
AT24C32D/AT24C64D on the rising edge of SCL and always output from the device on the falling edge of SCL. Both
the SCL and SDA pins incorporate integrated spike suppression filters and Schmitt Triggers to minimize the effects of
input spikes and bus noise.
All command and data information is transferred with the Most Significant bit (MSb) first. During bus communication,
one data bit is transmitted every clock cycle, and after eight bits (one byte) of data have been transferred, the
receiving device must respond with either an Acknowledge (ACK) or a No-Acknowledge (NACK) response bit during
a ninth clock cycle (ACK/NACK clock cycle) generated by the master. Therefore, nine clock cycles are required for
every one byte of data transferred. There are no unused clock cycles during any read or write operation, so there
must not be any interruptions or breaks in the data stream during each data byte transfer and ACK or NACK clock
cycle.
During data transfers, data on the SDA pin must only change while SCL is low, and the data must remain stable while
SCL is high. If data on the SDA pin changes while SCL is high, then either a Start or a Stop condition will occur. Start
and Stop conditions are used to initiate and end all serial bus communication between the master and the slave
devices. The number of data bytes transferred between a Start and a Stop condition is not limited and is determined
by the master. In order for the serial bus to be idle, both the SCL and SDA pins must be in the logic high state at the
same time.
5.1
Clock and Data Transition Requirements
The SDA pin is an open-drain terminal and therefore must be pulled high with an external pull‑up resistor. SCL is an
input pin that can either be driven high or pulled high using an external pull‑up resistor. Data on the SDA pin may
change only during SCL low time periods. Data changes during SCL high periods will indicate a Start or Stop
condition as defined below. The relationship of the AC timing parameters with respect to SCL and SDA for the
AT24C32D/AT24C64D are shown in the timing waveform in Figure 4-1. The AC timing characteristics and
specifications are outlined in AC Characteristics.
5.2
Start and Stop Conditions
5.2.1
Start Condition
A Start condition occurs when there is a high-to-low transition on the SDA pin while the SCL pin is at a stable logic ‘1’
state and will bring the device out of Standby mode. The master uses a Start condition to initiate any data transfer
sequence; therefore, every command must begin with a Start condition. The device will continuously monitor the SDA
and SCL pins for a Start condition but will not respond unless one is detected. Refer to Figure 5-1 for more details.
5.2.2
Stop Condition
A Stop condition occurs when there is a low-to-high transition on the SDA pin while the SCL pin is stable in the logic
‘1’ state.
The master can use the Stop condition to end a data transfer sequence with the AT24C32D/AT24C64D, which will
subsequently return to Standby mode. The master can also utilize a repeated Start condition instead of a Stop
condition to end the current data transfer if the master will perform another operation. Refer to Figure 5-1 for more
details.
© 2019 Microchip Technology Inc.
Datasheet
DS20006271A-page 13
AT24C32D/AT24C64D
Device Operation and Communication
5.3
Acknowledge and No-Acknowledge
After every byte of data is received, the receiving device must confirm to the transmitting device that it has
successfully received the data byte by responding with what is known as an Acknowledge (ACK).
An ACK is accomplished by the transmitting device first releasing the SDA line at the falling edge of the eighth clock
cycle followed by the receiving device responding with a logic ‘0’ during the entire high period of the ninth clock cycle.
When the AT24C32D/AT24C64D is transmitting data to the master, the master can indicate that it is done receiving
data and wants to end the operation by sending a logic ‘1’ response to the AT24C32D/AT24C64D instead of an ACK
response during the ninth clock cycle. This is known as a No-Acknowledge (NACK) and is accomplished by the
master sending a logic ‘1’ during the ninth clock cycle, at which point the AT24C32D/AT24C64D will release the SDA
line so the master can then generate a Stop condition.
The transmitting device, which can be the bus master or the Serial EEPROM, must release the SDA line at the falling
edge of the eighth clock cycle to allow the receiving device to drive the SDA line to a logic ‘0’ to ACK the previous 8bit word. The receiving device must release the SDA line at the end of the ninth clock cycle to allow the transmitter to
continue sending new data. A timing diagram has been provided in Figure 5-1 to better illustrate these requirements.
Figure 5-1. Start Condition, Data Transitions, Stop Condition and Acknowledge
SCL
SDA
Must Be
Stable
SDA
Must Be
Stable
1
2
Acknowledge Window
8
9
SDA
Start
Condition
5.4
Acknowledge
Valid
SDA
Change
Allowed
SDA
Change
Allowed
The transmitting device (Master or Slave)
must release the SDA line at this point to allow
the receiving device (Master or Slave) to drive the
SDA line low to ACK the previous 8-bit word.
Stop
Condition
The receiver (Master or Slave)
must release the SDA line at
this point to allow the transmitter
to continue sending new data.
Standby Mode
The AT24C32D/AT24C64D features a low-power Standby mode that is enabled when any one of the following
occurs:
•
•
•
5.5
A valid power-up sequence is performed (see Power-Up Requirements and Reset Behavior).
A Stop condition is received by the device unless it initiates an internal write cycle (see ).
At the completion of an internal write cycle (see Write Operations ).
Software Reset
After an interruption in protocol, power loss or system Reset, any two‑wire device can be protocol reset by clocking
SCL until SDA is released by the EEPROM and goes high. The number of clock cycles until SDA is released by the
EEPROM will vary. The software Reset sequence should not take more than nine dummy clock cycles. Once the
software Reset sequence is complete, new protocol can be sent to the device by sending a Start condition followed
by the protocol. Refer to Figure 5-2 for an illustration.
© 2019 Microchip Technology Inc.
Datasheet
DS20006271A-page 14
AT24C32D/AT24C64D
Device Operation and Communication
Figure 5-2. Software Reset
Dummy Clock Cycles
SCL
1
2
3
8
SDA Released
by EEPROM
9
Device is
Software Reset
SDA
In the event that the device is still non-responsive or remains active on the SDA bus, a power cycle must be used to
reset the device (see Power-Up Requirements and Reset Behavior).
© 2019 Microchip Technology Inc.
Datasheet
DS20006271A-page 15
AT24C32D/AT24C64D
Memory Organization
6.
Memory Organization
The AT24C32D is internally organized as 128 pages of 32 bytes each. The AT24C64D is internally organized as 256
pages of 32 bytes each.
6.1
Device Addressing
Accessing the device requires an 8-bit device address byte following a Start condition to enable the device for a read
or write operation.
The Most Significant four bits of the device address byte is referred to as the device type identifier. The device type
identifier ‘1010’ (Ah) is required in bits 7 through 4 of the device address byte (see Table 6‑1).
Following the 4-bit device type identifier are the hardware slave address bits, A2, A1 and A0. These bits can be used
to expand the address space by allowing up to eight Serial EEPROM devices on the same bus. These hardware
slave address bits must correlate with the voltage level on the corresponding hardwired device address input pins A0,
A1 and A2. The A0, A1 and A2 pins use an internal proprietary circuit that automatically biases the pin to a logic ‘0’
state if the pin is allowed to float. In order to operate in a wide variety of application environments, the pull‑down
mechanism is intentionally designed to be somewhat strong. Once the pin is biased above the CMOS input buffer's
trip point (~0.5 x VCC), the pull‑down mechanism disengages. Microchip recommends connecting the A0, A1 and A2
pins to a known state whenever possible
The eighth bit (bit 0) of the device address byte is the Read/Write Select bit. A read operation is initiated if this bit is
high and a write operation is initiated if this bit is low.
Upon the successful comparison of the device address byte, the AT24C32D/AT24C64D will return an ACK. If a valid
comparison is not made, the device will NACK.
Table 6-1. Device Address Byte
Package
Device Type Identifier
All Package Types
Hardware Slave Address Bits
R/W
Select
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
1
0
1
0
A2
A1
A0
R/W
For all operations except the current address read, two 8-bit word address bytes must be transmitted to the device
immediately following the device address byte. The word address bytes consist of the 12/13‑bit memory array word
address, and are used to specify which byte location in the EEPROM to start reading or writing. Refer to Table 6-2 to
review these bit positions.
The first word address byte contains the four Most Significant bits of the word address (A11 through A8) in bit
positions three through zero (AT24C32D case) or the five Most Significant bits of the word address (A12 through A8)
in bit positions four through zero (AT24C64D case), as seen in Table 6-2. The remainder of the first word address
byte are “don’t care” bits (in bit positions seven through four for the AT24C32D, in bit positions seven through five for
the AT24C64D) as they are outside of the addressable 32/64‑Kbit range. Upon completion of the first word address
byte, the AT24C32D/AT24C64D will return an ACK.
Table 6-2. First Word Address Byte
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
X
X
X
A12(1)
A11
A10
A9
A8
Note:
1. A12 bit for the AT24C64D, “don't care” bit for the AT24C32D.
© 2019 Microchip Technology Inc.
Datasheet
DS20006271A-page 16
AT24C32D/AT24C64D
Memory Organization
Next, the second word address byte is sent to the device which provides the remaining eight bits of the word address
(A7 through A0). Upon completion of the second word address byte, the AT24C32D/AT24C64D will return an ACK.
See Table 6-3 to review these bit positions.
Table 6-3. Second Word Address Byte
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
A7
A6
A5
A4
A3
A2
A1
A0
© 2019 Microchip Technology Inc.
Datasheet
DS20006271A-page 17
AT24C32D/AT24C64D
Write Operations
7.
Write Operations
All write operations for the AT24C32D/AT24C64D begin with the master sending a Start condition, followed by a
device address byte with the R/W bit set to logic ‘0’, and then by the word address bytes. The data value(s) to be
written to the device immediately follow the word address bytes.
7.1
Byte Write
The AT24C32D/AT24C64D supports the writing of a single 8-bit byte. Selecting a data word in the AT24C32D
requires a 12-bit word address, while selecting a data word in the AT24C64D requires a 13-bit word address.
Upon receipt of the proper device address and the word address bytes, the EEPROM will send an Acknowledge. The
device will then be ready to receive the 8-bit data word. Following receipt of the 8‑bit data word, the EEPROM will
respond with an ACK. The addressing device, such as a bus master, must then terminate the write operation with a
Stop condition. At that time, the EEPROM will enter an internally self-timed write cycle, which will be completed within
tWR, while the data word is being programmed into the nonvolatile EEPROM. All inputs are disabled during this write
cycle, and the EEPROM will not respond until the write is complete.
Figure 7-1. Byte Write
1
SCL
2
3
4
5
6
7
8
9
1
1
0
1
0
A2
A1
3
4
5
6
7
8
9
A9
A8
0
First Word Address Byte
Device Address Byte
SDA
2
A0
0
0
MSB
X
X
X
(1)
A12 A11 A10
MSB
Start Condition
by Master
ACK
from Slave
1
2
3
4
5
ACK
from Slave
6
7
8
9
1
2
3
A6
A5
A4
A3
A2
A1
5
6
7
8
9
D2
D1
D0
0
Data Word
Second Word Address Byte
A7
4
A0
0
MSB
D7
D6
D5
D4
D3
MSB
ACK
from Slave
Stop Condition
ACK
from Slave by Master
Note: A12 bit for the AT24C64D, "don't care" bit for the AT24C32D.
7.2
Page Write
A page write operation allows up to 32 bytes to be written in the same write cycle, provided all bytes are in the same
row of the memory array (where address bits A11 to A5 are the same on the AT24C32D and where address bits A12
to A5 are the same on the AT24C64D). Partial page writes of less than 32 bytes are also allowed.
A page write is initiated the same way as a byte write, but the bus master does not send a Stop condition after the
first data word is clocked in. Instead, after the EEPROM acknowledges receipt of the first data word, the bus master
can transmit up to 31 additional data words. The EEPROM will respond with an ACK after each data word is
received. Once all data to be written has been sent to the device, the bus master must issue a Stop condition (see
Figure 7-2) at which time the internally self-timed write cycle will begin.
The lower five bits of the word address are internally incremented following the receipt of each data word. The higher
order address bits are not incremented and retain the memory page row location. Page write operations are limited to
writing bytes within a single physical page, regardless of the number of bytes actually being written. When the
incremented word address reaches the page boundary, the address counter will rollover to the beginning of the same
page. Nevertheless, creating a rollover event should be avoided as previously loaded data in the page could become
unintentionally altered.
© 2019 Microchip Technology Inc.
Datasheet
DS20006271A-page 18
AT24C32D/AT24C64D
Write Operations
Figure 7-2. Page Write
1
SCL
2
3
4
5
6
7
8
9
1
2
Device Address Byte
SDA
1
0
1
0
A2
A1
A0
0
0
X
A6
6
7
X
(1)
X
A12 A11 A10
A9
ACK
from Slave
3
4
5
6
7
8
9
1
2
Second Word Address Byte
A7
5
8
9
A8
0
MSB
Start Condition
by Master
2
4
First Word Address Byte
MSB
1
3
A5
A4
A3
A2
A1
ACK
from Slave
3
4
5
6
7
8
9
Data Word (n)
A0
MSB
0
D7
D6
D5
D4
D3
D2
1
2
3
4
5
6
7
8
9
Data Word (n+x), max of 32 without rollover
D1
D0
MSB
0
D7
D6
D5
D4
D3
D2
D1
D0
0
MSB
ACK
from Slave
Stop Condition
ACK by Master
from Slave
ACK
from Slave
Note: A12 bit for the AT24C64D, “don't care” bit for the AT24C32D.
7.3
Acknowledge Polling
An Acknowledge Polling routine can be implemented to optimize time-sensitive applications that would prefer not to
wait the fixed maximum write cycle time (tWR). This method allows the application to know immediately when the
Serial EEPROM write cycle has completed, so a subsequent operation can be started.
Once the internally self-timed write cycle has started, an Acknowledge Polling routine can be initiated. This involves
repeatedly sending a Start condition followed by a valid device address byte with the R/W bit set at logic ‘0’. The
device will not respond with an ACK while the write cycle is ongoing. Once the internal write cycle has completed, the
EEPROM will respond with an ACK, allowing a new read or write operation to be immediately initiated. A flowchart
has been included below in Figure 7-3 to better illustrate this technique.
Figure 7-3. Acknowledge Polling Flowchart
Send any
Write
protocol.
Send
Stop
condition
to initiate the
Write cycle.
Send Start
condition followed
by a valid
Device Address
byte with R/W = 0.
Did
the device
ACK?
YES
Proceed to
next Read or
Write operation.
NO
7.4
Write Cycle Timing
The length of the self-timed write cycle (tWR) is defined as the amount of time from the Stop condition that begins the
internal write cycle to the Start condition of the first device address byte sent to the AT24C32D/AT24C64D that it
subsequently responds to with an ACK. Figure 7-4 has been included to show this measurement. During the
internally self-timed write cycle, any attempts to read from or write to the memory array will not be processed.
© 2019 Microchip Technology Inc.
Datasheet
DS20006271A-page 19
AT24C32D/AT24C64D
Write Operations
Figure 7-4. Write Cycle Timing
SCL
8
9
9
ACK
ACK
Data Word n
SDA
D0
tWR
Stop
Condition
7.5
Start
Condition
First Acknowledge from the device
to a valid device address sequence after
write cycle is initiated. The minimum tWR
can only be determined through
the use of an ACK Polling routine.
Stop
Condition
Write Protection
The AT24C32D/AT24C64D utilizes a hardware data protection scheme that allows the user to write-protect the entire
memory array contents when the WP pin is at VCC (or a valid VIH). No write protection will be set if the WP pin is at
GND or left floating.
Table 7-1. Write-Protect Behavior
WP Pin Voltage
Part of the Array Protected
VCC
Full (32K/64K) Array
GND
None － Write Protection Not Enabled
The status of the WP pin is sampled at the Stop condition for every byte write or page write operation prior to the start
of an internally self-timed write cycle. Changing the WP pin state after the Stop condition has been sent will not alter
or interrupt the execution of the write cycle.
If an attempt is made to write to the device while the WP pin has been asserted, the device will acknowledge the
device address, word address and data bytes, but no write cycle will occur when the Stop condition is issued. The
device will immediately be ready to accept a new read or write operation.
© 2019 Microchip Technology Inc.
Datasheet
DS20006271A-page 20
AT24C32D/AT24C64D
Read Operations
8.
Read Operations
Read operations are initiated the same way as write operations with the exception that the Read/Write Select bit in
the device address byte must be a logic ‘1’. There are three read operations:
•
•
•
8.1
Current Address Read
Random Address Read
Sequential Read
Current Address Read
The internal data word address counter maintains the last address accessed during the last read or write operation,
incremented by one. This address stays valid between operations as long as the VCC is maintained to the part. The
address roll-over during a read is from the last byte of the last page to the first byte of the first page of the memory.
A current address read operation will output data according to the location of the internal data word address counter.
This is initiated with a Start condition, followed by a valid device address byte with the R/W bit set to logic ‘1’. The
device will ACK this sequence and the current address data word is serially clocked out on the SDA line. All types of
read operations will be terminated if the bus master does not respond with an ACK (it NACKs) during the ninth clock
cycle. After the NACK response, the master may send a Stop condition to complete the protocol, or it can send a
Start condition to begin the next sequence.
Figure 8-1. Current Address Read
SCL
1
2
3
4
5
6
7
8
9
1
2
Device Address Byte
SDA
1
MSB
Start Condition
by Master
8.2
0
1
0
A2
A1
3
4
5
6
7
8
9
D2
D1
D0
1
Data Word (n)
A0
1
0
D7
D6
D5
D4
D3
MSB
ACK
from Slave
Stop Condition
NACK
by Master
from Master
Random Read
A random read begins in the same way as a byte write operation does to load in a new data word address. This is
known as a “dummy write” sequence; however, the data byte and the Stop condition of the byte write must be omitted
to prevent the part from entering an internal write cycle. Once the device address and word address are clocked in
and acknowledged by the EEPROM, the bus master must generate another Start condition. The bus master now
initiates a current address read by sending a Start condition, followed by a valid device address byte with the R/W bit
set to logic ‘1’. The EEPROM will ACK the device address and serially clock out the data word on the SDA line. All
types of read operations will be terminated if the bus master does not respond with an ACK (it NACKs) during the
ninth clock cycle. After the NACK response, the master may send a Stop condition to complete the protocol, or it can
send a Start condition to begin the next sequence.
© 2019 Microchip Technology Inc.
Datasheet
DS20006271A-page 21
AT24C32D/AT24C64D
Read Operations
Figure 8-2. Random Read
1
SCL
2
3
4
5
6
7
8
9
1
2
Device Address Byte
SDA
1
0
1
0
A2
3
4
5
6
7
8
9
1
2
First Word Address Byte
A1
A0
0
X
0
MSB
X
(1)
A12 A11 A10
X
4
5
6
7
8
9
A0
0
Second Word Address Byte
A9
A8
0
A7
MSB
Start Condition
by Master
3
A6
A5
A4
A3
A2
A1
MSB
ACK
from Slave
ACK
from Slave
ACK
from Slave
Dummy Write
1
2
3
4
5
6
7
8
9
1
2
3
0
1
0
A2
A1
5
6
7
8
9
D2
D1
D0
1
Data Word (n)
Device Address Byte
1
4
A0
1
0
D7
MSB
D6
D5
D4
D3
MSB
Start Condition
by Master
Stop Condition
NACK
from Master by Master
ACK
from Slave
Note: A12 bit for the AT24C64D, “don't care” bit for the AT24C32D.
8.3
Sequential Read
Sequential reads are initiated by either a current address read or a random read. After the bus master receives a
data word, it responds with an Acknowledge. As long as the EEPROM receives an ACK, it will continue to increment
the word address and serially clock out sequential data words. When the maximum memory address is reached, the
data word address will roll-over and the sequential read will continue from the beginning of the memory array. All
types of read operations will be terminated if the bus master does not respond with an ACK (it NACKs) during the
ninth clock cycle. After the NACK response, the master may send a Stop condition to complete the protocol, or it can
send a Start condition to begin the next sequence.
Figure 8-3. Sequential Read
1
SCL
2
3
4
5
6
7
8
9
1
2
3
Device Address Byte
SDA
1
0
1
0
A2
A1
A0
1
0
D7
D6
7
8
9
D6
D5
D4
D3
D2
D1
D0
0
ACK
from Slave
3
4
5
6
7
8
9
1
2
Data Word (n+1)
D7
6
MSB
Start Condition
by Master
2
5
Data Word (n)
MSB
1
4
D5
D4
D3
D2
MSB
ACK
from Master
3
4
5
6
7
8
1
2
Data Word (n+2)
D1
D0
0
D7
D6
D5
D4
D3
D2
3
4
5
6
7
8
9
D1
D0
1
Data Word (n+x)
D1
D0
MSB
0
D7
D6
D5
D4
D3
D2
MSB
ACK
from Master
© 2019 Microchip Technology Inc.
9
ACK
from Master
Datasheet
Stop Condition
NACK by Master
from Master
DS20006271A-page 22
AT24C32D/AT24C64D
Device Default Condition from Microchip
9.
Device Default Condition from Microchip
The AT24C32D/AT24C64D is delivered with the EEPROM array set to logic ‘1’, resulting in FFh data in all locations.
© 2019 Microchip Technology Inc.
Datasheet
DS20006271A-page 23
AT24C32D/AT24C64D
Packaging Information
10.
Packaging Information
10.1
Package Marking Information
AT24C32D/AT24C64D: Package Marking Information
8-lead TSSOP
8-lead SOIC
AT$YWW
###%CO
YYWWNNN
ATML$YWW
###% CO
YYWWNNN
8-pad UDFN
5-lead SOT23(3)
2.0 x 3.0 mm Body
###
$%
NNN
Note 1:
##%$YY
WWNNN
designates pin 1.
Note 2: Package drawings are not to scale.
Note 3: AT24C32D only.
Catalog Number Truncation
AT24C32D
AT24C64D
Date Codes
YY = Year
16: 2016
17: 2017
18: 2018
19: 2019
Truncation Code ###: 32D/ ##: BD
Truncation Code ###: 64D/ ##: CD
Voltages
20: 2020
21: 2021
22: 2022
23: 2023
Y = Year
6: 2016
7: 2017
8: 2018
9: 2019
0: 2020
1: 2021
2: 2022
3: 2023
WW = Work Week of Assembly
02: Week 2
04: Week 4
...
52: Week 52
Country of Origin
$ = Device Grade
CO = Country of Origin
P:
9:
% = Minimum Voltage
M: 1.7V min
D: 2.5V min
Atmel Truncation
Automotive Grade 1
Automotive Grade 3
AT: Atmel
ATM: Atmel
ATML: Atmel
Trace Code
NNN = Alphanumeric Trace Code (2 Characters for Small Packages)
© 2019 Microchip Technology Inc.
Datasheet
DS20006271A-page 24
AT24C32D/AT24C64D
Packaging Information
8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm (.150 In.) Body [SOIC]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2X
0.10 C A–B
D
A
D
NOTE 5
N
E
2
E1
2
E1
E
NOTE 1
2
1
e
B
NX b
0.25
C A–B D
NOTE 5
TOP VIEW
0.10 C
C
A A2
SEATING
PLANE
8X
A1
SIDE VIEW
0.10 C
h
R0.13
h
R0.13
H
0.23
L
SEE VIEW C
(L1)
VIEW A–A
VIEW C
Microchip Technology Drawing No. C04-057-SN Rev D Sheet 1 of 2
© 2017 Microchip Technology Incorporated
© 2019 Microchip Technology Inc.
Datasheet
DS20006271A-page 25
AT24C32D/AT24C64D
Packaging Information
8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm (.150 In.) Body [SOIC]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Units
Dimension Limits
Number of Pins
N
e
Pitch
Overall Height
A
Molded Package Thickness
A2
§
Standoff
A1
Overall Width
E
Molded Package Width
E1
Overall Length
D
Chamfer (Optional)
h
Foot Length
L
L1
Footprint
Foot Angle
c
Lead Thickness
b
Lead Width
Mold Draft Angle Top
Mold Draft Angle Bottom
MIN
1.25
0.10
0.25
0.40
0°
0.17
0.31
5°
5°
MILLIMETERS
NOM
8
1.27 BSC
6.00 BSC
3.90 BSC
4.90 BSC
1.04 REF
-
MAX
1.75
0.25
0.50
1.27
8°
0.25
0.51
15°
15°
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. § Significant Characteristic
3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or
protrusions shall not exceed 0.15mm per side.
4. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
5. Datums A & B to be determined at Datum H.
Microchip Technology Drawing No. C04-057-SN Rev D Sheet 2 of 2
© 2017 Microchip Technology Incorporated
© 2019 Microchip Technology Inc.
Datasheet
DS20006271A-page 26
AT24C32D/AT24C64D
Packaging Information
8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm Body [SOIC]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
SILK SCREEN
C
Y1
X1
E
RECOMMENDED LAND PATTERN
Units
Dimension Limits
E
Contact Pitch
Contact Pad Spacing
C
Contact Pad Width (X8)
X1
Contact Pad Length (X8)
Y1
MIN
MILLIMETERS
NOM
1.27 BSC
5.40
MAX
0.60
1.55
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Microchip Technology Drawing C04-2057-SN Rev B
© 2017 Microchip Technology Incorporated
© 2019 Microchip Technology Inc.
Datasheet
DS20006271A-page 27
AT24C32D/AT24C64D
Packaging Information
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