AT24CS16
I²C-Compatible (Two-Wire) Serial EEPROM with a Unique,
Factory-Programmed 128-Bit Serial Number
16‑Kbit (2,048 x 8)
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Low-Voltage Operation:
– VCC = 1.7V to 5.5V
Internally Organized as 2,048 x 8 (16K)
128-Bit Unique Factory-Programmed Serial Number
– Permanent read-only value
– Unique across entire CS Series of Serial EEPROMs
Industrial Temperature Range: -40°C to +85°C
I2C-Compatible (Two-Wire) Serial Interface:
– 100 kHz Standard Mode, 1.7V to 5.5V
– 400 kHz Fast Mode, 1.7V to 5.5V
– 1 MHz Fast Mode Plus (FM+), 2.5V to 5.5V
Schmitt Triggers, Filtered Inputs for Noise Suppression
Bidirectional Data Transfer Protocol
Write-Protect Pin for Full Array Hardware Data Protection
Ultra Low Active Current (3 mA maximum) and Standby Current (6 µA maximum)
16-Byte Page Write Mode:
– Partial page writes allowed
Random and Sequential Read Modes
Self-Timed Write Cycle within 5 ms Maximum
ESD Protection > 4,000V
High Reliability:
– Endurance: 1,000,000 write cycles
– Data retention: 100 years
Green Package Options (Lead-free/Halide-free/RoHS compliant)
Die Sale Options: Wafer Form and Tape and Reel Available
Packages
•
8-Lead SOIC, 8-Lead TSSOP, 8-Pad UDFN and 5-Lead SOT23
© 2020 Microchip Technology Inc.
Datasheet
DS20006342A-page 1
AT24CS16
Table of Contents
Features......................................................................................................................................................... 1
Packages........................................................................................................................................................1
1.
Package Types (not to scale)..................................................................................................................4
2.
Pin Descriptions...................................................................................................................................... 5
2.1.
2.2.
2.3.
2.4.
2.5.
3.
Description.............................................................................................................................................. 7
3.1.
3.2.
4.
Byte Write...................................................................................................................................17
Page Write..................................................................................................................................17
Acknowledge Polling.................................................................................................................. 18
Write Cycle Timing..................................................................................................................... 18
Write Protection..........................................................................................................................19
Read Operations................................................................................................................................... 20
8.1.
8.2.
8.3.
8.4.
9.
Device Addressing..................................................................................................................... 16
Write Operations................................................................................................................................... 17
7.1.
7.2.
7.3.
7.4.
7.5.
8.
Clock and Data Transition Requirements...................................................................................13
Start and Stop Conditions.......................................................................................................... 13
Acknowledge and No-Acknowledge...........................................................................................14
Standby Mode............................................................................................................................ 14
Software Reset...........................................................................................................................14
Memory Organization............................................................................................................................16
6.1.
7.
Absolute Maximum Ratings..........................................................................................................9
DC and AC Operating Range.......................................................................................................9
DC Characteristics....................................................................................................................... 9
AC Characteristics......................................................................................................................10
Electrical Specifications..............................................................................................................11
Device Operation and Communication................................................................................................. 13
5.1.
5.2.
5.3.
5.4.
5.5.
6.
System Configuration Using Two-Wire Serial EEPROMs ........................................................... 7
Block Diagram.............................................................................................................................. 8
Electrical Characteristics.........................................................................................................................9
4.1.
4.2.
4.3.
4.4.
4.5.
5.
Ground......................................................................................................................................... 5
Serial Data (SDA).........................................................................................................................5
Serial Clock (SCL)........................................................................................................................5
Write-Protect (WP)....................................................................................................................... 5
Device Power Supply (VCC)......................................................................................................... 6
Current Address Read................................................................................................................20
Random Read............................................................................................................................ 20
Sequential Read.........................................................................................................................21
Serial Number Read...................................................................................................................21
Device Default Condition from Microchip.............................................................................................. 23
© 2020 Microchip Technology Inc.
Datasheet
DS20006342A-page 2
AT24CS16
10. Packaging Information.......................................................................................................................... 24
10.1. Package Marking Information.....................................................................................................24
11. Revision History.................................................................................................................................... 36
The Microchip Website.................................................................................................................................37
Product Change Notification Service............................................................................................................37
Customer Support........................................................................................................................................ 37
Product Identification System.......................................................................................................................38
Microchip Devices Code Protection Feature................................................................................................ 38
Legal Notice................................................................................................................................................. 39
Trademarks.................................................................................................................................................. 39
Quality Management System....................................................................................................................... 40
Worldwide Sales and Service.......................................................................................................................41
© 2020 Microchip Technology Inc.
Datasheet
DS20006342A-page 3
AT24CS16
Package Types (not to scale)
1.
Package Types (not to scale)
8-Lead SOIC/TSSOP
(Top View)
NC
1
8
Vcc
NC
2
7
WP
NC
3
6
SCL
GND
4
5
SDA
8-Pad UDFN
(Top View)
NC
1
8
Vcc
NC
2
7
WP
NC
3
6
GND
4
5
© 2020 Microchip Technology Inc.
5-Lead SOT23
(Top View)
SCL
1
SCL
GND
2
SDA
SDA
3
Datasheet
5
WP
4
Vcc
DS20006342A-page 4
AT24CS16
Pin Descriptions
2.
Pin Descriptions
The descriptions of the pins are listed in Table 2-1.
Table 2-1. Pin Function Table
Name
NC
NC
NC
GND
SDA
SCL
WP(2)
VCC
8‑Lead SOIC
1
2
3
4
5
6
7
8
8‑Lead TSSOP
1
2
3
4
5
6
7
8
8‑Pad UDFN(1)
1
2
3
4
5
6
7
8
5-Lead SOT23
—
—
—
2
3
1
5
4
Function
No Connect
No Connect
No Connect
Ground
Serial Data
Serial Clock
Write-Protect
Device Power Supply
Note:
1. The exposed pad on this package can be connected to GND or left floating.
2. If the WP pin is not driven, it is internally pulled down to GND. In order to operate in a wide variety of
application environments, the pull‑down mechanism is intentionally designed to be somewhat strong. Once
this pin is biased above the CMOS input buffer’s trip point (~0.5 x VCC), the pull‑down mechanism disengages.
Microchip recommends connecting these pins to a known state whenever possible.
2.1
Ground
The ground reference for the power supply. GND should be connected to the system ground.
2.2
Serial Data (SDA)
The SDA pin is an open-drain bidirectional input/output pin used to serially transfer data to and from the device. The
SDA pin must be pulled high using an external pull-up resistor (not to exceed 10 kΩ in value) and may be wire-ORed
with any number of other open-drain or open-collector pins from other devices on the same bus.
2.3
Serial Clock (SCL)
The SCL pin is used to provide a clock to the device and to control the flow of data to and from the device. Command
and input data present on the SDA pin is always latched in on the rising edge of SCL, while output data on the SDA
pin is clocked out on the falling edge of SCL. The SCL pin must either be forced high when the serial bus is idle or
pulled high using an external pull-up resistor.
2.4
Write-Protect (WP)
The write-protect input, when connected to GND, allows normal write operations. When the WP pin is connected
directly to VCC, all write operations to the protected memory are inhibited.
If the pin is left floating, the WP pin will be internally pulled down to GND. However, due to capacitive coupling that
may appear in customer applications, Microchip recommends always connecting the WP pin to a known state. When
using a pull‑up resistor, Microchip recommends using 10 kΩ or less.
Table 2-2. Write-Protect
WP Pin Status
Part of the Array Protected
At VCC
Full Array
© 2020 Microchip Technology Inc.
Datasheet
DS20006342A-page 5
AT24CS16
Pin Descriptions
...........continued
2.5
WP Pin Status
Part of the Array Protected
At GND
Normal Write Operations
Device Power Supply (VCC)
The Device Power Supply (VCC) pin is used to supply the source voltage to the device. Operations at invalid VCC
voltages may produce spurious results and should not be attempted.
© 2020 Microchip Technology Inc.
Datasheet
DS20006342A-page 6
AT24CS16
Description
3.
Description
The AT24CS16 provides 16,384 bits of Serial Electrically Erasable and Programmable Read-Only Memory
(EEPROM) organized as 2,048 words of 8 bits each. This device is optimized for use in many industrial and
commercial applications where low‑power and low‑voltage operation are essential. The device is available in
space‑saving 8‑lead SOIC, 8‑lead TSSOP, 8‑pad UDFN and 5-lead SOT23 packages. All packages operate from
1.7V to 5.5V.
The AT24CS16 provides the additional feature of a factory programmed, ensured unique 128-bit serial number, while
maintaining all of the traditional features available in the 16‑Kbit Serial EEPROM. The time consuming step of
performing and ensuring true serialization of product on a manufacturing line can be removed from the production
flow by employing the CS Series Serial EEPROM. The 128-bit serial number is programmed and permanently locked
from future writing during the Microchip production process. Further, this 128-bit location does not consume any of
the user read/write area of the 16‑Kbit Serial EEPROM. The uniqueness of the serial number is ensured across the
entire CS Series of Serial EEPROMs, regardless of the size of the memory array or the type of interface protocol.
This means that as an application’s needs for memory size or interface protocol evolve in future generations, any
previously deployed serial number from any Microchip CS Series Serial EEPROM part will remain valid.
3.1
System Configuration Using Two-Wire Serial EEPROMs
VCC
RPUP(max) =
tR(max)
0.8473 x CL
V - VOL(max)
RPUP(min) = CC
IOL
VCC
SCL
SDA
WP
I2C Bus Master:
Microcontroller
NC
VCC
NC
WP
Slave
AT24CS16
NC
SDA
GND
GND
© 2020 Microchip Technology Inc.
Datasheet
SCL
DS20006342A-page 7
AT24CS16
Description
Block Diagram
Memory
System Control
Module
POR
Generator
VCC
High-Voltage
Generation Circuit
Row Decoder
3.2
EEPROM Array
1 page
128-Bit Serial Number
Write
Protection
Control
Address Register
and Counter
Column Decoder
SCL
Data Register
DOUT
GND
© 2020 Microchip Technology Inc.
WP
Data & ACK
Input/Output Control
DIN
Start
Stop
Detector
SDA
Datasheet
DS20006342A-page 8
AT24CS16
Electrical Characteristics
4.
Electrical Characteristics
4.1
Absolute Maximum Ratings
Temperature under bias
-55°C to +125°C
Storage temperature
-65°C to +150°C
VCC
6.25V
Voltage on any pin with respect to ground
-1.0V to +7.0V
DC output current
5.0 mA
ESD protection
>4 kV
Note: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
This is a stress rating only and functional operation of the device at these or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.
4.2
DC and AC Operating Range
Table 4-1. DC and AC Operating Range
AT24CS16
4.3
Operating Temperature (Case)
Industrial Temperature Range
-40°C to +85°C
VCC Power Supply
Low-Voltage Grade
1.7V to 5.5V
DC Characteristics
Table 4-2. DC Characteristics
Symbol
Minimum
Typical(1)
Maximum
Units
Supply Voltage
VCC
1.7
—
5.5
V
Supply Current
ICC1
—
0.4
1.0
mA
VCC = 5.0V,
Read at 400 kHz
Supply Current
ICC2
—
2.0
3.0
mA
VCC = 5.0V,
Write at 400 kHz
Standby Current
ISB
—
—
1.0
μA
VCC = 1.7V,
VIN = VCC or GND
—
—
6.0
μA
VCC = 5.5V,
VIN = VCC or GND
Parameter
Test Conditions
Input Leakage Current
ILI
—
0.10
3.0
μA
VIN = VCC or GND
Output Leakage Current
ILO
—
0.05
3.0
μA
VOUT = VCC or
GND
Input Low Level
VIL
-0.6
—
VCC x 0.3
V
Note 2
Input High Level
VIH
VCC x 0.7
—
VCC + 0.5
V
Note 2
© 2020 Microchip Technology Inc.
Datasheet
DS20006342A-page 9
AT24CS16
Electrical Characteristics
...........continued
Symbol
Minimum
Typical(1)
Maximum
Units
Output Low Level
VOL1
—
—
0.2
V
VCC = 1.7V,
IOL = 0.15 mA
Output Low Level
VOL2
—
—
0.4
V
VCC = 3.0V,
IOL = 2.1 mA
Parameter
Test Conditions
Note:
1. Typical values characterized at TA = +25°C unless otherwise noted.
2. This parameter is characterized but is not 100% tested in production.
4.4
AC Characteristics
Table 4-3. AC Characteristics(1)
Parameter
Symbol
Fast Mode
Fast Mode Plus
Vcc = 1.7V to 2.5V
Vcc = 2.5V to 5.5V
Min.
Max.
Min.
Max.
Units
Clock Frequency, SCL
fSCL
—
400
—
1000
kHz
Clock Pulse Width Low
tLOW
1200
—
500
—
ns
Clock Pulse Width High
tHIGH
600
—
400
—
ns
tI
—
100
—
50
ns
Clock Low to Data Out Valid
tAA
100
900
50
450
ns
Bus Free Time between Stop and Start
tBUF
1300
—
500
—
ns
Start Hold Time
tHD.STA
600
—
250
—
ns
Start Set‑Up Time
tSU.STA
600
—
250
—
ns
Data In Hold Time
tHD.DAT
0
—
0
—
ns
Data In Set‑Up Time
tSU.DAT
100
—
100
—
ns
tR
—
300
—
300
ns
Inputs Fall Time(2)
tF
—
300
—
100
ns
Stop Set-Up Time
tSU.STO
600
—
250
—
ns
Data Out Hold Time
tDH
50
—
50
—
ns
Write Cycle Time
tWR
—
5
—
5
ms
Input Filter Spike Suppression
Inputs Rise
Time(2)
Note:
1. AC measurement conditions:
– CL: 100 pF
– RPUP (SDA bus line pull-up resistor to VCC): 1.3 kΩ (1000 kHz), 4 kΩ (400 kHz), 10 kΩ (100 kHz)
– Input rise and fall times: ≤ 50 ns
– Input and output timing reference voltages: 0.5 x VCC
2. This parameter is characterized but is not 100% tested in production.
© 2020 Microchip Technology Inc.
Datasheet
DS20006342A-page 10
AT24CS16
Electrical Characteristics
Figure 4-1. Bus Timing
tF
tHIGH
tR
tLOW
SCL
tSU.STA
tHD.STA
tHD.DAT
tSU.DAT
tSU.STO
SDA In
tBUF
tAA
tDH
SDA Out
4.5
4.5.1
Electrical Specifications
Power-Up Requirements and Reset Behavior
During a power-up sequence, the VCC supplied to the AT24CS16 should monotonically rise from GND to the
minimum VCC level, as specified in Table 4-1, with a slew rate no faster than 0.1 V/µs.
4.5.1.1
Device Reset
To prevent inadvertent write operations or any other spurious events from occurring during a power-up sequence, the
AT24CS16 includes a Power-on Reset (POR) circuit. Upon power-up, the device will not respond to any commands
until the VCC level crosses the internal voltage threshold (VPOR) that brings the device out of Reset and into Standby
mode.
The system designer must ensure the instructions are not sent to the device until the VCC supply has reached a
stable value greater than or equal to the minimum VCC level. Additionally, once the VCC is greater than or equal to the
minimum VCC level, the bus master must wait at least tPUP before sending the first command to the device. See Table
4-4 for the values associated with these power-up parameters.
Table 4-4. Power-up Conditions(1)
Symbol
Parameter
tPUP
Time required after VCC is stable before the device can accept commands
VPOR
Power-on Reset Threshold Voltage
tPOFF
Minimum time at VCC = 0V between power cycles
Min.
Max.
Units
100
-
µs
-
1.5
V
500
-
ms
Note:
1. These parameters are characterized but they are not 100% tested in production.
If an event occurs in the system where the VCC level supplied to the AT24CS16 drops below the maximum VPOR level
specified, it is recommended that a full power cycle sequence be performed by first driving the VCC pin to GND,
waiting at least the minimum tPOFF time and then performing a new power-up sequence in compliance with the
requirements defined in this section.
© 2020 Microchip Technology Inc.
Datasheet
DS20006342A-page 11
AT24CS16
Electrical Characteristics
4.5.2
Pin Capacitance
Table 4-5. Pin Capacitance(1)
Symbol
Test Condition
Max.
Units
Conditions
CI/O
Input/Output Capacitance (SDA)
8
pF
VI/O = 0V
CIN
Input Capacitance (SCL)
6
pF
VIN = 0V
Note:
1. This parameter is characterized but is not 100% tested in production.
4.5.3
EEPROM Cell Performance Characteristics
Table 4-6. EEPROM Cell Performance Characteristics
Operation
Test Condition
Write Endurance(1)
TA = 25°C, VCC = 3.3V,
Page Write mode
Data Retention(1)
TA = 55°C
Min.
Max.
Units
1,000,000
—
Write Cycles
100
—
Years
Note:
1. Performance is determined through characterization and the qualification process.
© 2020 Microchip Technology Inc.
Datasheet
DS20006342A-page 12
AT24CS16
Device Operation and Communication
5.
Device Operation and Communication
The AT24CS16 operates as a slave device and utilizes a simple I2C-compatible two-wire digital serial interface to
communicate with a host controller, commonly referred to as the bus master. The master initiates and controls all
read and write operations to the slave devices on the serial bus, and both the master and the slave devices can
transmit and receive data on the bus.
The serial interface is comprised of just two signal lines: Serial Clock (SCL) and Serial Data (SDA). The SCL pin is
used to receive the clock signal from the master, while the bidirectional SDA pin is used to receive command and
data information from the master as well as to send data back to the master. Data is always latched into the
AT24CS16 on the rising edge of SCL and always output from the device on the falling edge of SCL. Both the SCL
and SDA pins incorporate integrated spike suppression filters and Schmitt Triggers to minimize the effects of input
spikes and bus noise.
All command and data information is transferred with the Most Significant bit (MSb) first. During bus communication,
one data bit is transmitted every clock cycle, and after eight bits (one byte) of data have been transferred, the
receiving device must respond with either an Acknowledge (ACK) or a No-Acknowledge (NACK) response bit during
a ninth clock cycle (ACK/NACK clock cycle) generated by the master. Therefore, nine clock cycles are required for
every one byte of data transferred. There are no unused clock cycles during any read or write operation, so there
must not be any interruptions or breaks in the data stream during each data byte transfer and ACK or NACK clock
cycle.
During data transfers, data on the SDA pin must only change while SCL is low, and the data must remain stable while
SCL is high. If data on the SDA pin changes while SCL is high, then either a Start or a Stop condition will occur. Start
and Stop conditions are used to initiate and end all serial bus communication between the master and the slave
devices. The number of data bytes transferred between a Start and a Stop condition is not limited and is determined
by the master. In order for the serial bus to be idle, both the SCL and SDA pins must be in the logic high state at the
same time.
5.1
Clock and Data Transition Requirements
The SDA pin is an open-drain terminal and therefore must be pulled high with an external pull‑up resistor. SCL is an
input pin that can either be driven high or pulled high using an external pull‑up resistor. Data on the SDA pin may
change only during SCL low time periods. Data changes during SCL high periods will indicate a Start or Stop
condition as defined below. The relationship of the AC timing parameters with respect to SCL and SDA for the
AT24CS16 are shown in the timing waveform in Figure 4-1. The AC timing characteristics and specifications are
outlined in AC Characteristics.
5.2
Start and Stop Conditions
5.2.1
Start Condition
A Start condition occurs when there is a high-to-low transition on the SDA pin while the SCL pin is at a stable logic ‘1’
state and will bring the device out of Standby mode. The master uses a Start condition to initiate any data transfer
sequence; therefore, every command must begin with a Start condition. The device will continuously monitor the SDA
and SCL pins for a Start condition but will not respond unless one is detected. Refer to Figure 5-1 for more details.
5.2.2
Stop Condition
A Stop condition occurs when there is a low-to-high transition on the SDA pin while the SCL pin is stable in the logic
‘1’ state.
The master can use the Stop condition to end a data transfer sequence with the AT24CS16, which will subsequently
return to Standby mode. The master can also utilize a repeated Start condition instead of a Stop condition to end the
current data transfer if the master will perform another operation. Refer to Figure 5-1 for more details.
© 2020 Microchip Technology Inc.
Datasheet
DS20006342A-page 13
AT24CS16
Device Operation and Communication
5.3
Acknowledge and No-Acknowledge
After every byte of data is received, the receiving device must confirm to the transmitting device that it has
successfully received the data byte by responding with what is known as an Acknowledge (ACK).
An ACK is accomplished by the transmitting device first releasing the SDA line at the falling edge of the eighth clock
cycle followed by the receiving device responding with a logic ‘0’ during the entire high period of the ninth clock cycle.
When the AT24CS16 is transmitting data to the master, the master can indicate that it is done receiving data and
wants to end the operation by sending a logic ‘1’ response to the AT24CS16 instead of an ACK response during the
ninth clock cycle. This is known as a No-Acknowledge (NACK) and is accomplished by the master sending a logic ‘1’
during the ninth clock cycle, at which point the AT24CS16 will release the SDA line so the master can then generate
a Stop condition.
The transmitting device, which can be the bus master or the Serial EEPROM, must release the SDA line at the falling
edge of the eighth clock cycle to allow the receiving device to drive the SDA line to a logic ‘0’ to ACK the previous 8bit word. The receiving device must release the SDA line at the end of the ninth clock cycle to allow the transmitter to
continue sending new data. A timing diagram has been provided in Figure 5-1 to better illustrate these requirements.
Figure 5-1. Start Condition, Data Transitions, Stop Condition and Acknowledge
SCL
SDA
Must Be
Stable
SDA
Must Be
Stable
1
2
Acknowledge Window
8
9
SDA
Start
Condition
5.4
Acknowledge
Valid
SDA
Change
Allowed
SDA
Change
Allowed
The transmitting device (Master or Slave)
must release the SDA line at this point to allow
the receiving device (Master or Slave) to drive the
SDA line low to ACK the previous 8-bit word.
Stop
Condition
The receiver (Master or Slave)
must release the SDA line at
this point to allow the transmitter
to continue sending new data.
Standby Mode
The AT24CS16 features a low‑power Standby mode that is enabled when any one of the following occurs:
• A valid power-up sequence is performed (see Power-Up Requirements and Reset Behavior).
• A Stop condition is received by the device unless it initiates an internal write cycle (see Write Operations).
• At the completion of an internal write cycle (see Write Operations).
5.5
Software Reset
After an interruption in protocol, power loss or system Reset, any two‑wire device can be protocol reset by clocking
SCL until SDA is released by the EEPROM and goes high. The number of clock cycles until SDA is released by the
EEPROM will vary. The software Reset sequence should not take more than nine dummy clock cycles. Once the
software Reset sequence is complete, new protocol can be sent to the device by sending a Start condition followed
by the protocol. Refer to Figure 5-2 for an illustration.
© 2020 Microchip Technology Inc.
Datasheet
DS20006342A-page 14
AT24CS16
Device Operation and Communication
Figure 5-2. Software Reset
Dummy Clock Cycles
SCL
1
2
3
8
SDA Released
by EEPROM
9
Device is
Software Reset
SDA
In the event that the device is still non-responsive or remains active on the SDA bus, a power cycle must be used to
reset the device (see Power-Up Requirements and Reset Behavior).
© 2020 Microchip Technology Inc.
Datasheet
DS20006342A-page 15
AT24CS16
Memory Organization
6.
Memory Organization
The AT24CS16 is internally organized as 128 pages of 16 bytes each.
6.1
Device Addressing
Accessing the device requires an 8‑bit device address byte following a Start condition to enable the device for a read
or write operation.
The Most Significant four bits of the device address byte is referred to as the device type identifier. The device type
identifier ‘1010’ (Ah) is required in bits 7 through 4 of the device address byte (see Table 6-1).
The AT24CS16 utilizes a separate memory block containing a factory programmed 128-bit serial number. Access to
this memory location is similar to the EEPROM region with the exception that the device type identifier is set to ‘1011’
(Bh) in bits 7 through 4 of the device address byte (see Table 6-1).
Following the 4-bit device type identifier in the bit 3, bit 2 and bit 1 position of the device address byte are bits A10,
A9 and A8 which are the three Most Significant bits of the memory array word address.
The eighth bit (bit 0) of the device address byte is the Read/Write Select bit. A read operation is initiated if this bit is
high and a write operation is initiated if this bit is low.
Upon the successful comparison of the device address byte, the AT24CS16 will return an ACK. If a valid comparison
is not made, the device will NACK.
Table 6-1. Device Address Byte
Package
Device Type Identifier
Most Significant Bits of
the Word Address
R/W Select
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
EEPROM
1
0
1
0
A10
A9
A8
R/W
Serial Number
1
0
1
1
0
0
0
R/W
For all operations except the current address read, a word address byte must be transmitted to the device
immediately following the device address byte. The word address byte consists of the remaining eight bits of the
11‑bit memory array word address and is used to specify which byte location in the EEPROM to start reading or
writing. Refer to Table 6-2 to review these bit positions.
Table 6-2. Word Address Byte
Access Area
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
EEPROM
A7
A6
A5
A4
A3
A2
A1
A0
Serial Number
1
0
X
X
X
X
X
X
© 2020 Microchip Technology Inc.
Datasheet
DS20006342A-page 16
AT24CS16
Write Operations
7.
Write Operations
All write operations for the AT24CS16 begin with the master sending a Start condition, followed by a device address
byte with the R/W bit set to logic ‘0’, and then by the word address byte. The data value(s) to be written to the device
immediately follow the word address byte.
7.1
Byte Write
The AT24CS16 supports the writing of a single 8-bit byte. Selecting a data word in the AT24CS16 requires 11-bit
word address.
Upon receipt of the proper device address and the word address bytes, the EEPROM will send an Acknowledge. The
device will then be ready to receive the 8-bit data word. Following receipt of the 8‑bit data word, the EEPROM will
respond with an ACK. The addressing device, such as a bus master, must then terminate the write operation with a
Stop condition. At that time, the EEPROM will enter an internally self-timed write cycle, which will be completed within
tWR, while the data word is being programmed into the nonvolatile EEPROM. All inputs are disabled during this write
cycle, and the EEPROM will not respond until the write is complete.
Figure 7-1. Byte Write
1
SCL
2
3
4
5
6
7
8
9
1
2
Device Address Byte
SDA
1
0
1
0
A10
4
5
6
7
8
9
1
2
3
A8
0
0
A7
A6
A5
A4
A3
A2
4
5
6
7
8
9
D2
D1
D0
0
Data Word
Word Address Byte
MSb
Start
by
Master
7.2
A9
3
A1
A0
0
D7
D6
D5
D4
D3
MSb
MSb
ACK
from
Slave
ACK
from
Slave
ACK
from
Slave
Stop
by
Master
Page Write
A page write operation allows up to 16 bytes to be written in the same write cycle, provided all bytes are in the same
row of the memory array (where address bits A10 through A4 are the same). Partial page writes of less than 16 bytes
are also allowed.
A page write is initiated the same way as a byte write, but the bus master does not send a Stop condition after the
first data word is clocked in. Instead, after the EEPROM acknowledges receipt of the first data word, the bus master
can transmit up to fifteen additional data words. The EEPROM will respond with an ACK after each data word is
received. Once all data to be written has been sent to the device, the bus master must issue a Stop condition (see
Figure 7-2) at which time the internally self-timed write cycle will begin.
The lower four bits of the word address are internally incremented following the receipt of each data word. The higher
order address bits are not incremented and retain the memory page row location. Page write operations are limited to
writing bytes within a single physical page, regardless of the number of bytes actually being written. When the
incremented word address reaches the page boundary, the address counter will rollover to the beginning of the same
page. Nevertheless, creating a rollover event should be avoided as previously loaded data in the page could become
unintentionally altered.
© 2020 Microchip Technology Inc.
Datasheet
DS20006342A-page 17
AT24CS16
Write Operations
Figure 7-2. Page Write
1
SCL
2
3
4
5
6
7
8
9
1
2
3
Device Address Byte
SDA
1
0
1
0
A10
A9
4
5
6
7
8
9
A1
A0
0
Word Address Byte
A8
0
A7
0
MSb
A6
A5
A4
A3
A2
MSb
Start
by
Master
ACK
from
Slave
1
2
ACK
from
Slave
3
4
5
6
7
8
9
Data Word (n)
D7
D6
D5
D4
D3
1
2
3
4
5
7
8
9
Data Word (n+x), max of 16 without rollover
D2
D1
D0
0
MSb
D7
D6
D5
D4
D3
D2
D1
D0
0
MSb
ACK
from
Slave
7.3
6
ACK
from
Slave
Stop
by
Master
Acknowledge Polling
An Acknowledge Polling routine can be implemented to optimize time-sensitive applications that would prefer not to
wait the fixed maximum write cycle time (tWR). This method allows the application to know immediately when the
Serial EEPROM write cycle has completed, so a subsequent operation can be started.
Once the internally self-timed write cycle has started, an Acknowledge Polling routine can be initiated. This involves
repeatedly sending a Start condition followed by a valid device address byte with the R/W bit set at logic ‘0’. The
device will not respond with an ACK while the write cycle is ongoing. Once the internal write cycle has completed, the
EEPROM will respond with an ACK, allowing a new read or write operation to be immediately initiated. A flowchart
has been included below in Figure 7-3 to better illustrate this technique.
Figure 7-3. Acknowledge Polling Flowchart
Send any
Write
protocol.
Send
Stop
condition
to initiate the
Write cycle.
Send Start
condition followed
by a valid
Device Address
byte with R/W = 0.
Did
the device
ACK?
YES
Proceed to
next Read or
Write operation.
NO
7.4
Write Cycle Timing
The length of the self-timed write cycle (tWR) is defined as the amount of time from the Stop condition that begins the
internal write cycle to the Start condition of the first device address byte sent to the AT24CS16 that it subsequently
responds to with an ACK. Figure 7-4 has been included to show this measurement. During the internally self-timed
write cycle, any attempts to read from or write to the memory array will not be processed.
© 2020 Microchip Technology Inc.
Datasheet
DS20006342A-page 18
AT24CS16
Write Operations
Figure 7-4. Write Cycle Timing
SCL
8
9
9
ACK
ACK
Data Word n
SDA
D0
tWR
Stop
Condition
7.5
Start
Condition
First Acknowledge from the device
to a valid device address sequence after
write cycle is initiated. The minimum tWR
can only be determined through
the use of an ACK Polling routine.
Stop
Condition
Write Protection
The AT24CS16 utilizes a hardware data protection scheme that allows the user to write‑protect the entire memory
contents when the WP pin is at VCC (or a valid VIH). No write protection will be set if the WP pin is at GND or left
floating.
Table 7-1. AT24CS16 Write-Protect Behavior
WP Pin Voltage
Part of the Array Protected
VCC
Full Array
GND
None - Write Protection Not Enabled
The status of the WP pin is sampled at the Stop condition for every byte write or page write operation prior to the start
of an internally self‑timed write cycle. Changing the WP pin state after the Stop condition has been sent will not alter
or interrupt the execution of the write cycle.
If an attempt is made to write to the device while the WP pin has been asserted, the device will acknowledge the
device address, word address and data bytes, but no write cycle will occur when the Stop condition is issued. The
device will immediately be ready to accept a new read or write command.
© 2020 Microchip Technology Inc.
Datasheet
DS20006342A-page 19
AT24CS16
Read Operations
8.
Read Operations
Read operations are initiated the same way as write operations with the exception that the Read/Write Select bit in
the device address byte must be a logic ‘1’. There are four read operations:
•
•
•
•
Current Address Read
Random Address Read
Sequential Read
Serial Number Read
Note: The AT24CS16 contains a single Address Pointer register, which is shared by both the EEPROM and the
serial number. As such, when changing from one region to the other, the first read operation in the new region should
begin with a dummy write sequence (i.e., a random read operation with the new region’s device address and word
address bytes) in order to ensure the Address Pointer is set to a known value. See Serial Number Read for additional
requirements on the serial number read.
8.1
Current Address Read
The internal data word address counter maintains the last address accessed during the last read or write operation,
incremented by one. This address stays valid between operations as long as the VCC is maintained to the part. The
address rollover during a read is from the last byte of the last page to the first byte of the first page of the memory.
A current address read operation will output data according to the location of the internal data word address counter.
This is initiated with a Start condition, followed by a valid device address byte with the R/W bit set to logic ‘1’. The
device will ACK this sequence and the current address data word is serially clocked out on the SDA line. All types of
read operations will be terminated if the bus master does not respond with an ACK (it NACKs) during the ninth clock
cycle. After the NACK response, the master may send a Stop condition to complete the protocol, or it can send a
Start condition to begin the next sequence.
Figure 8-1. Current Address Read
1
SCL
2
3
4
5
6
7
8
9
1
2
Device Address Byte
SDA
1
1
0
A10
A9
4
5
6
7
8
9
D2
D1
D0
1
Data Word (n)
A8
1
0
MSb
Start
by
Master
8.2
0
3
D7
D6
D5
D4
D3
MSb
ACK
from
Slave
NACK
from
Master
Stop
by
Master
Random Read
A random read begins in the same way as a byte write operation does to load in a new data word address. This is
known as a “dummy write” sequence; however, the data byte and the Stop condition of the byte write must be omitted
to prevent the part from entering an internal write cycle. Once the device address and word address are clocked in
and acknowledged by the EEPROM, the bus master must generate another Start condition. The bus master now
initiates a current address read by sending a Start condition, followed by a valid device address byte with the R/W bit
set to logic ‘1’. In this second device address byte, the bit positions usually reserved for the Most Significant bits of
the word address (bit 3, 2 and 1) are “don't care” bits since the address that will be read from is determined only by
what was sent in the dummy write portion of the sequence. The EEPROM will ACK the device address and serially
clock out the data word on the SDA line. All types of read operations will be terminated if the bus master does not
respond with an ACK (it NACKs) during the ninth clock cycle. After the NACK response, the master may send a Stop
condition to complete the protocol, or it can send a Start condition to begin the next sequence.
© 2020 Microchip Technology Inc.
Datasheet
DS20006342A-page 20
AT24CS16
Read Operations
Figure 8-2. Random Read
1
SCL
2
3
4
5
6
7
8
9
1
2
3
Device Address Byte
SDA
1
0
1
0
A10
A9
4
5
6
7
8
9
A1
A0
0
Word Address Byte
A8
0
0
A7
MSb
A6
A5
A4
A3
A2
MSb
Start
by
Master
ACK
from
Slave
ACK
from
Slave
Dummy Write
1
2
3
4
5
6
7
8
9
1
2
3
0
1
0
X
X
X
1
0
D7
MSb
6
7
8
9
D6
D5
D4
D3
D2
D1
D0
1
MSb
Start
by
Master
8.3
5
Data Word (n)
Device Address Byte
1
4
ACK
from
Slave
NACK
from
Master
Stop
by
Master
Sequential Read
Sequential reads are initiated by either a current address read or a random read. After the bus master receives a
data word, it responds with an Acknowledge. As long as the EEPROM receives an ACK, it will continue to increment
the word address and serially clock out sequential data words. When the maximum memory address is reached, the
data word address will rollover and the sequential read will continue from the beginning of the memory array. All
types of read operations will be terminated if the bus master does not respond with an ACK (it NACKs) during the
ninth clock cycle. After the NACK response, the master may send a Stop condition to complete the protocol, or it can
send a Start condition to begin the next sequence.
Figure 8-3. Sequential Read
1
SCL
2
3
4
5
6
7
8
9
1
2
3
Device Address Byte
SDA
1
0
1
0
A10
A9
A8
1
6
7
8
9
0
D7
D6
D5
D4
D3
D2
D1
D0
0
MSb
Start
by
Master
ACK
from
Slave
2
3
4
5
6
7
8
9
1
2
Data Word (n+1)
D7
5
Data Word (n)
MSb
1
4
D6
D5
D4
D3
D2
ACK
from
Master
3
4
5
6
7
9
1
2
Data Word (n+2)
D1
D0
0
MSb
D7
D6
D5
D4
D3
D2
3
4
5
6
7
8
9
D1
D0
1
Data Word (n+x)
D1
D0
0
MSb
D7
D6
D5
D4
D3
D2
MSb
ACK
from
Master
8.4
8
ACK
from
Master
NACK
from
Master
Stop
by
Master
Serial Number Read
Reading the serial number is similar to the sequential read sequence but requires use of the specific Device Address
and Word Address bytes as specified in Table 6-1 and Table 6-2.
© 2020 Microchip Technology Inc.
Datasheet
DS20006342A-page 21
AT24CS16
Read Operations
Note: The entire 128-bit value must be read from the starting address of the serial number block to ensure a unique
number.
Since the Address Pointer of the device is shared between the regular EEPROM array and the serial number block, a
dummy write sequence, as part of a random read or sequential read protocol, should be performed to ensure the
Address Pointer is set to a known value. Reading the serial number from a location other than the first address of the
block will not result in a unique serial number.
Additionally, the word address contains a ‘10’ sequence in bit A11 and A10 of the word address, regardless of the
intended address as depicted in Table 6-2. If a word address other than ‘10’ is used, then the device will output
undefined data.
Note: If the application desires to read the first byte of the serial number, the word address input would need to be
80h.
When the end of the 128-bit serial number is reached (16 bytes of data), the data word address will roll over back to
the beginning of the 128‑bit serial number. The serial number read operation is terminated when the bus master does
not respond with an ACK (it NACKs) during the ninth clock cycle. After the NACK response, the master may send a
Stop condition to complete the protocol, or it can send a Start condition to begin the next sequence (see Figure 8-4).
Figure 8-4. Serial Number Read
SCL
1
2
3
4
5
6
7
8
9
1
2
Device Address Byte
SDA
1
0
1
1
0
0
3
4
5
6
7
8
9
0
0
0
Word Address Byte
0
0
0
MSb
1
0
0
0
0
0
MSb
Start Condition
by Master
ACK
from Slave
ACK
from Slave
Dummy Write
1
2
1
0
3
4
5
6
7
8
9
1
2
0
1
0
D7
D6
Device Address Byte
1
1
0
MSb
Start Condition
by Master
© 2020 Microchip Technology Inc.
0
3
4
5
6
7
8
9
1
2
D1
D0
0
D7
D6
Serial Number Byte0
D5
D4
D3
D2
3
4
5
6
7
8
9
D1
D0
1
Serial Number Byte15
MSb
D5
D4
D3
D2
MSb
ACK
from Slave
ACK
from Master
Datasheet
Stop Condition
NACK
by Master
from Master
DS20006342A-page 22
AT24CS16
Device Default Condition from Microchip
9.
Device Default Condition from Microchip
The AT24CS16 is delivered with the EEPROM array set to logic ‘1’, resulting in FFh data in all locations.
© 2020 Microchip Technology Inc.
Datasheet
DS20006342A-page 23
AT24CS16
Packaging Information
10.
Packaging Information
10.1
Package Marking Information
AT24CS16: Package Marking Information
8-Lead TSSOP
8-Lead SOIC
ATHYWW
## %CO
ATMLHYWW
## % CO
YYWWNNN
8-Pad UDFN
YYWWNNN
5-Lead SOT23
2.0 x 3.0 mm Body
##
H%
NNN
Note 1:
##%UYY
WWNNN
designates pin 1
Note 2: Package drawings are not to scale
Catalog Number Truncation
AT24CS16
Truncation Code ##: NA
Date Codes
YY = Year
16: 2016
17: 2017
18: 2018
19: 2019
Voltages
20: 2020
21: 2021
22: 2022
23: 2023
Y = Year
6: 2016
7: 2017
8: 2018
9: 2019
0: 2020
1: 2021
2: 2022
3: 2023
WW = Work Week of Assembly
02: Week 2
04: Week 4
...
52: Week 52
Country of Origin
Device Grade
CO = Country of Origin
H or U: Industrial Grade
% = Minimum Voltage
M: 1.7V min
Atmel Truncation
AT: Atmel
ATM: Atmel
ATML: Atmel
Trace Code
NNN = Alphanumeric Trace Code (2 Characters for Small Packages)
© 2020 Microchip Technology Inc.
Datasheet
DS20006342A-page 24
AT24CS16
Packaging Information
8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm (.150 In.) Body [SOIC]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2X
0.10 C A–B
D
A
D
NOTE 5
N
E
2
E1
2
E1
E
2X
0.10 C A–B
2X
0.10 C A–B
NOTE 1
2
1
e
B
NOTE 5
NX b
0.25
C A–B D
TOP VIEW
0.10 C
C
A A2
SEATING
PLANE
8X
A1
SIDE VIEW
0.10 C
h
R0.13
h
R0.13
H
0.23
L
SEE VIEW C
(L1)
VIEW A–A
VIEW C
Microchip Technology Drawing No. C04-057-SN Rev F Sheet 1 of 2
© 2020 Microchip Technology Inc.
© 2020 Microchip Technology Inc.
Datasheet
DS20006342A-page 25
AT24CS16
Packaging Information
8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm (.150 In.) Body [SOIC]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Units
Dimension Limits
Number of Pins
N
e
Pitch
Overall Height
A
Molded Package Thickness
A2
§
Standoff
A1
Overall Width
E
Molded Package Width
E1
Overall Length
D
Chamfer (Optional)
h
Foot Length
L
L1
Footprint
Foot Angle
c
Lead Thickness
b
Lead Width
Mold Draft Angle Top
Mold Draft Angle Bottom
MIN
1.25
0.10
0.25
0.40
0°
0.17
0.31
5°
5°
MILLIMETERS
NOM
8
1.27 BSC
6.00 BSC
3.90 BSC
4.90 BSC
1.04 REF
-
MAX
1.75
0.25
0.50
1.27
8°
0.25
0.51
15°
15°
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. § Significant Characteristic
3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or
protrusions shall not exceed 0.15mm per side.
4. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
5. Datums A & B to be determined at Datum H.
Microchip Technology Drawing No. C04-057-SN Rev F Sheet 2 of 2
© 2020 Microchip Technology Inc.
© 2020 Microchip Technology Inc.
Datasheet
DS20006342A-page 26
AT24CS16
Packaging Information
8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm (.150 In.) Body [SOIC]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
SILK SCREEN
C
Y1
X1
E
RECOMMENDED LAND PATTERN
Units
Dimension Limits
E
Contact Pitch
Contact Pad Spacing
C
Contact Pad Width (X8)
X1
Contact Pad Length (X8)
Y1
MIN
MILLIMETERS
NOM
1.27 BSC
5.40
MAX
0.60
1.55
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Microchip Technology Drawing C04-2057-SN Rev F
© 2020 Microchip Technology Inc.
© 2020 Microchip Technology Inc.
Datasheet
DS20006342A-page 27
MAT24CS16
Packaging Diagrams and Parameters
Packaging Information
8-Lead Plastic Thin Shrink Small Outline (ST) – 4.4 mm Body [TSSOP]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
D
N
E
E1
NOTE 1
1
2
b
e
c
A
φ
A2
A1
L
L1
Units
Dimension Limits
Number of Pins
MILLIMETERS
MIN
N
NOM
MAX
8
Pitch
e
Overall Height
A
–
0.65 BSC
–
Molded Package Thickness
A2
0.80
1.00
1.05
Standoff
A1
0.05
–
0.15
1.20
Overall Width
E
Molded Package Width
E1
4.30
6.40 BSC
4.40
Molded Package Length
D
2.90
3.00
3.10
Foot Length
L
0.45
0.60
0.75
Footprint
L1
4.50
1.00 REF
Foot Angle
φ
0°
–
8°
Lead Thickness
c
0.09
–
0.20
Lead Width
b
0.19
–
0.30
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side.
3. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-086B
© 2007 Microchip Technology Inc.
© 2020 Microchip Technology Inc.
DS00049AR-page 117
Datasheet
DS20006342A-page 28
M
Note:
AT24CS16
Packaging Diagrams and Parameters
Packaging Information
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2009 Microchip Technology Inc.
DS00049BC-page 96
© 2020 Microchip Technology Inc.
Datasheet
DS20006342A-page 29
AT24CS16
Packaging Information
8-Lead Ultra Thin Plastic Dual Flat, No Lead Package (Q4B) - 2x3 mm Body [UDFN]
Atmel Legacy YNZ Package
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
D
A
B
N
(DATUM A)
E
(DATUM B)
NOTE 1
2X
0.10 C
1
2
2X
0.10 C
TOP VIEW
A1
0.10 C
C
SEATING
PLANE
A
8X
(A3)
SIDE VIEW
0.10
0.08 C
C A B
D2
e
2
1 2
0.10
E2
C A B
K
N
L
8X b
0.10
0.05
e
C A B
C
BOTTOM VIEW
Microchip Technology Drawing C04-21355-Q4B Rev A Sheet 1 of 2
© 2018 Microchip Technology Incorporated
© 2020 Microchip Technology Inc.
Datasheet
DS20006342A-page 30
AT24CS16
Packaging Information
8-Lead Ultra Thin Plastic Dual Flat, No Lead Package (Q4B) - 2x3 mm Body [UDFN]
Atmel Legacy YNZ Package
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Units
Dimension Limits
Number of Terminals
N
e
Pitch
A
Overall Height
Standoff
A1
Terminal Thickness
A3
Overall Length
D
Exposed Pad Length
D2
Overall Width
E
Exposed Pad Width
E2
b
Terminal Width
Terminal Length
L
Terminal-to-Exposed-Pad
K
MIN
0.50
0.00
1.40
1.20
0.18
0.35
0.20
MILLIMETERS
NOM
8
0.50 BSC
0.55
0.02
0.152 REF
2.00 BSC
1.50
3.00 BSC
1.30
0.25
0.40
-
MAX
0.60
0.05
1.60
1.40
0.30
0.45
-
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Package is saw singulated
3. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-21355-Q4B Rev A Sheet 2 of 2
© 2018 Microchip Technology Incorporated
© 2020 Microchip Technology Inc.
Datasheet
DS20006342A-page 31
AT24CS16
Packaging Information
8-Lead Ultra Thin Plastic Dual Flat, No Lead Package (Q4B) - 2x3 mm Body [UDFN]
Atmel Legacy YNZ Package
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
X2
EV
G2
8
ØV
C
Y2
G1
Y1
1
2
SILK SCREEN
X1
E
RECOMMENDED LAND PATTERN
Units
Dimension Limits
E
Contact Pitch
Optional Center Pad Width
X2
Optional Center Pad Length
Y2
Contact Pad Spacing
C
Contact Pad Width (X8)
X1
Contact Pad Length (X8)
Y1
Contact Pad to Center Pad (X8)
G1
Contact Pad to Contact Pad (X6)
G2
Thermal Via Diameter
V
Thermal Via Pitch
EV
MIN
MILLIMETERS
NOM
0.50 BSC
MAX
1.60
1.40
2.90
0.30
0.85
0.20
0.33
0.30
1.00
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
2. For best soldering results, thermal vias, if used, should be filled or tented to avoid solder loss during
reflow process
Microchip Technology Drawing C04-21355-Q4B Rev A
© 2018 Microchip Technology Incorporated
© 2020 Microchip Technology Inc.
Datasheet
DS20006342A-page 32
AT24CS16
Packaging Information
5-Lead Plastic Thin Small Outline Transistor (NMB) [TSOT]
Atmel Legacy Global Package Code TSZ
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
0.20 C 2X
D
e1
A
D
N
E/2
E1/2
E1
E
(DATUM D)
(DATUM A-B)
0.15 C D
2X
NOTE 1
1
2
0.20 C
e
B
NX b
0.20
C A-B D
TOP VIEW
A
A A2
0.20 C
SEATING PLANE
A
SEE SHEET 2
A1
C
SIDE VIEW
Microchip Technology Drawing C04-21344 Rev B Sheet 1 of 2
© 2018 Microchip Technology Inc.
© 2020 Microchip Technology Inc.
Datasheet
DS20006342A-page 33
AT24CS16
Packaging Information
5-Lead Plastic Thin Small Outline Transistor (NMB) [TSOT]
Atmel Legacy Global Package Code TSZ
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
(c)
θ
L
L1
VIEW A-A
SHEET 1
Units
Dimension Limits
N
Number of Leads
e
Pitch
e1
Outside lead pitch
A
Overall Height
A2
Molded Package Thickness
Standoff
A1
Overall Width
E
Molded Package Width
E1
Overall Length
D
Foot Length
L
Footprint
L1
Foot Angle
θ
c
Lead Thickness
b
Lead Width
MIN
0.70
-
0.30
0°
0.08
0.30
MILLIMETERS
NOM
5
0.95 BSC
1.90 BSC
0.90
2.80 BSC
1.60 BSC
2.90 BSC
0.60 REF
-
MAX
1.10
1.00
0.10
0.60
8°
0.20
0.50
Notes:
1. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or
protrusions shall not exceed 0.25mm per side.
2. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-21344 Rev B Sheet 2 of 2
© 2018 Microchip Technology Inc.
© 2020 Microchip Technology Inc.
Datasheet
DS20006342A-page 34
AT24CS16
Packaging Information
5-Lead Plastic Thin Small Outline Transistor (NMB) [TSOT]
Atmel Legacy Global Package Code TSZ
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
X1
5
Y1
SILK SCREEN
C
1
2
G
E
RECOMMENDED LAND PATTERN
Units
Dimension Limits
E
Contact Pitch
Contact Pad Spacing
C
Contact Pad Width (X5)
X1
Contact Pad Length (X5)
Y1
Contact Pad to Center Pad (X2)
G
MIN
MILLIMETERS
NOM
0.95 BSC
2.60
MAX
0.60
1.05
0.20
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
2. For best soldering results, thermal vias, if used, should be filled or tented to avoid solder loss during
reflow process
Microchip Technology Drawing C04-23344 Rev B
© 2018 Microchip Technology Inc.
© 2020 Microchip Technology Inc.
Datasheet
DS20006342A-page 35
AT24CS16
Revision History
11.
Revision History
Revision A (April 2020)
Updated to Microchip template. Microchip DS20006342 replaces Atmel document 8859. Corrected tLOW typo from
400 ns to 500 ns. Corrected tAA typo from 550 ns to 450 ns. Updated Package Marking Information. Updated the
“Software Reset” section. Added ESD rating. Removed lead finish designation. Updated trace code format in
package markings. Updated formatting throughout for clarification. Added a figure for “System Configuration Using
2‑Wire Serial EEPROMs”. Updated “Block Diagram” figure. Added POR recommendations section. Updated
formatting to current template. Updated the SOIC, TSSOP, UDFN and SOT23 package drawings to Microchip format.
Atmel Document 8859 Revision C (March 2017)
Corrected ISB2 spec to 6.0 µA.
Atmel Document 8859 Revision B (January 2015)
Added bulk SOIC and TSSOP, and UDFN Expanded Quantity options. Updated from preliminary to complete status,
ordering code table, 8X and 8MA2 package drawings and the disclaimer page. Corrected pinouts from bottom to top
view and reorganization figures. No changes to functional specification.
Atmel Document 8859 Revision A (February 2013)
Initial release of this document.
© 2020 Microchip Technology Inc.
Datasheet
DS20006342A-page 36
AT24CS16
The Microchip Website
Microchip provides online support via our website at http://www.microchip.com/. This website is used to make files
and information easily available to customers. Some of the content available includes:
•
•
•
Product Support – Data sheets and errata, application notes and sample programs, design resources, user’s
guides and hardware support documents, latest software releases and archived software
General Technical Support – Frequently Asked Questions (FAQs), technical support requests, online
discussion groups, Microchip design partner program member listing
Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of
seminars and events, listings of Microchip sales offices, distributors and factory representatives
Product Change Notification Service
Microchip’s product change notification service helps keep customers current on Microchip products. Subscribers will
receive email notification whenever there are changes, updates, revisions or errata related to a specified product
family or development tool of interest.
To register, go to http://www.microchip.com/pcn and follow the registration instructions.
Customer Support
Users of Microchip products can receive assistance through several channels:
•
•
•
•
Distributor or Representative
Local Sales Office
Embedded Solutions Engineer (ESE)
Technical Support
Customers should contact their distributor, representative or ESE for support. Local sales offices are also available to
help customers. A listing of sales offices and locations is included in this document.
Technical support is available through the website at: http://www.microchip.com/support
© 2020 Microchip Technology Inc.
Datasheet
DS20006342A-page 37
AT24CS16
Product Identification System
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
AT2 4 C S 16-SS HM-B
Shipping Carrier Option
B = Bulk (Tubes)
T = Tape and Reel, Standard Quantity Option
E = Tape and Reel, Extended Quantity Option
Product Family
24CS = Serial EEPROM, plus
128-bit Serial Number
Operating Voltage
M = 1.7V to 5.5V
Device Density
Device Grade or
Wafer/Die Thickness
16 = 16 Kilobit
H or U = Industrial Temperature Range
(-40°C to +85°C)
11
= 11mil Wafer Thickness
Package Option
SS
X
MA
ST
WWU
= SOIC
= TSSOP
= 2.0mm x 3.0mm UDFN
= SOT23
= Wafer Unsawn
Examples
Device
Package
Package
Drawing
Code
Package
Option
Shipping Carrier Option
AT24CS16‑SSHM‑B
SOIC
SN
SS
Bulk (Tubes)
AT24CS16‑SSHM‑T
SOIC
SN
SS
Tape and Reel
AT24CS16‑XHM‑B
TSSOP
ST
X
Bulk (Tubes)
AT24CS16‑XHM‑T
TSSOP
ST
X
Tape and Reel
AT24CS16‑MAHM‑T
UDFN
Q4B
MA
Tape and Reel
AT24CS16‑MAHM‑E
UDFN
Q4B
MA
Extended Qty. Tape and Reel
AT24CS16‑STUM‑T
SOT23
NMB
ST
Tape and Reel
Device Grade
Industrial
Temperature
(-40°C to +85°C)
Microchip Devices Code Protection Feature
Note the following details of the code protection feature on Microchip devices:
•
•
•
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
Microchip believes that its family of products is one of the most secure families of its kind on the market today,
when used in the intended manner and under normal conditions.
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these
methods, to our knowledge, require using the Microchip products in a manner outside the operating
specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of
intellectual property.
Microchip is willing to work with the customer who is concerned about the integrity of their code.
© 2020 Microchip Technology Inc.
Datasheet
DS20006342A-page 38
AT24CS16
•
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code
protection does not mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection
features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital
Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you
may have a right to sue for relief under that Act.
Legal Notice
Information contained in this publication regarding device applications and the like is provided only for your
convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with
your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER
EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend,
indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such
use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights unless
otherwise stated.
Trademarks
The Microchip name and logo, the Microchip logo, Adaptec, AnyRate, AVR, AVR logo, AVR Freaks, BesTime,
BitCloud, chipKIT, chipKIT logo, CryptoMemory, CryptoRF, dsPIC, FlashFlex, flexPWR, HELDO, IGLOO, JukeBlox,
KeeLoq, Kleer, LANCheck, LinkMD, maXStylus, maXTouch, MediaLB, megaAVR, Microsemi, Microsemi logo, MOST,
MOST logo, MPLAB, OptoLyzer, PackeTime, PIC, picoPower, PICSTART, PIC32 logo, PolarFire, Prochip Designer,
QTouch, SAM-BA, SenGenuity, SpyNIC, SST, SST Logo, SuperFlash, Symmetricom, SyncServer, Tachyon,
TempTrackr, TimeSource, tinyAVR, UNI/O, Vectron, and XMEGA are registered trademarks of Microchip Technology
Incorporated in the U.S.A. and other countries.
APT, ClockWorks, The Embedded Control Solutions Company, EtherSynch, FlashTec, Hyper Speed Control,
HyperLight Load, IntelliMOS, Libero, motorBench, mTouch, Powermite 3, Precision Edge, ProASIC, ProASIC Plus,
ProASIC Plus logo, Quiet-Wire, SmartFusion, SyncWorld, Temux, TimeCesium, TimeHub, TimePictra, TimeProvider,
Vite, WinPath, and ZL are registered trademarks of Microchip Technology Incorporated in the U.S.A.
Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut, BlueSky, BodyCom,
CodeGuard, CryptoAuthentication, CryptoAutomotive, CryptoCompanion, CryptoController, dsPICDEM,
dsPICDEM.net, Dynamic Average Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial Programming, ICSP,
INICnet, Inter-Chip Connectivity, JitterBlocker, KleerNet, KleerNet logo, memBrain, Mindi, MiWi, MPASM, MPF,
MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM,
PICDEM.net, PICkit, PICtail, PowerSmart, PureSilicon, QMatrix, REAL ICE, Ripple Blocker, SAM-ICE, Serial Quad
I/O, SMART-I.S., SQI, SuperSwitcher, SuperSwitcher II, Total Endurance, TSHARC, USBCheck, VariSense,
ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A.
and other countries.
SQTP is a service mark of Microchip Technology Incorporated in the U.S.A.
The Adaptec logo, Frequency on Demand, Silicon Storage Technology, and Symmcom are registered trademarks of
Microchip Technology Inc. in other countries.
GestIC is a registered trademark of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip
Technology Inc., in other countries.
All other trademarks mentioned herein are property of their respective companies.
©
2020, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved.
ISBN: 978-1-5224-5964-4
AMBA, Arm, Arm7, Arm7TDMI, Arm9, Arm11, Artisan, big.LITTLE, Cordio, CoreLink, CoreSight, Cortex, DesignStart,
DynamIQ, Jazelle, Keil, Mali, Mbed, Mbed Enabled, NEON, POP, RealView, SecurCore, Socrates, Thumb,
© 2020 Microchip Technology Inc.
Datasheet
DS20006342A-page 39
AT24CS16
TrustZone, ULINK, ULINK2, ULINK-ME, ULINK-PLUS, ULINKpro, µVision, Versatile are trademarks or registered
trademarks of Arm Limited (or its subsidiaries) in the US and/or elsewhere.
Quality Management System
For information regarding Microchip’s Quality Management Systems, please visit http://www.microchip.com/quality.
© 2020 Microchip Technology Inc.
Datasheet
DS20006342A-page 40
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© 2020 Microchip Technology Inc.
Datasheet
DS20006342A-page 41