Features
• Serial Peripheral Interface (SPI) Compatible
• Supports SPI Modes 0 (0,0) and 3 (1,1)
– Data Sheet Describes Mode 0 Operation
• Low-voltage and Standard-voltage Operation
•
•
•
•
•
•
•
•
– VCC = 1.8V to 5.5V
20 MHz Clock Rate (5V)
8-byte Page Mode
Block Write Protection
– Protect 1/4, 1/2, or Entire Array
Write Protect (WP) Pin and Write Disable Instructions for Both Hardware and Software
Data Protection
Self-timed Write Cycle (5 ms max)
High Reliability
– Endurance: One Million Write Cycles
– Data Retention: 100 Years
Green (Pb/Halogen-free/Rohs Compliant) Packaging Options
Die Sales: Wafer Form, Waffle Pack, Bumped Wafers
Description
The AT25010B/020B/040B provides 1024/2048/4096 bits of serial electrically erasable programmable read-only memory (EEPROM) organized as 128/256/512 words
of 8 bits each. The device is optimized for use in many industrial and commercial
applications where low-power and low-voltage operation are essential. The
AT25010B/020B/040B is available in space saving, JEDEC SOIC, UDFN, TSSOP,
XDFN and VFBGA packages.
SPI Serial
EEPROM
1K (128x8)
2K (256x8)
4K (512x8)
AT25010B
AT25020B
AT25040B
The AT25010B/020B/040B is enabled through the Chip Select pin (CS) and accessed
via a three-wire interface consisting of Serial Data Input (SI), Serial Data Output (SO),
and Serial Clock (SCK). All programming cycles are completely self-timed, and no
separate erase cycle is required before write.
Block write protection is enabled by programming the status register with one of four
blocks of write protection. Separate Program Enable and Program disable instructions
are provided for additional data protection. Hardware data protection is provided via
the WP pin to protect against inadvertent write attempts. The HOLD pin may be used
to suspend any serial communication without resetting the serial sequence.
Table 0-1.
Pin Configuration
SOIC, TSSOP
Pin Name
Function
CS
Chip Select
SCK
Serial Data Clock
SI
Serial Data Input
SO
Serial Data Output
GND
Ground
VCC
Power Supply
WP
Write Protect
HOLD
Suspends Serial Input
CS
1
8
VCC
SO
WP
GND
2
7
3
6
4
5
HOLD
SCK
SI
8-lead UDFN, XDFN
VCC 8
HOLD 7
SCK 6
SI 5
1 CS
2 SO
3 WP
4 GND
Bottom View
8-ball VFBGA
VCC 8
HOLD 7
SCK 6
1
CS
2
3
SO
WP
SI 5
4
GND
Bottom View
8707B–SEEPR–3/10
1.
Absolute Maximum Ratings*
Operating Temperature ............................ −40°C to + 125°C
Storage Temperature................................ −65°C to + 150°C
Voltage on Any Pin
with Respect to Ground ................................ −1.0V to + 7.0V
Maximum Operating Voltage.................................... 6.25V
DC Output Current ................................................. 5.0 mA
Figure 1-1.
*NOTICE:
Stresses beyond those listed under
“Absolute Maximum Ratings” may cause
permanent damage to the device. This is
a stress rating only and functional operation of the device at these or any other
conditions beyond those indicated in the
operational sections of this specification
is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Block Diagram
VCC
STATUS
REGISTER
MEMORY ARRAY
128/256/512 X 8
ADDRESS
DECODER
DATA
REGISTER
OUTPUT
BUFFER
MODE
DECODE
LOGIC
CLOCK
GENERATOR
2
AT25010B/020B/040B
8707B–SEEPR–3/10
AT25010B/020B/040B
Table 1-1.
Pin Capacitance (1)
Applicable over recommended operating range from TA = 25°C, f = 1.0 MHz, VCC = +5.0V (unless otherwise noted)
Symbol
Test Conditions
COUT
CIN
Note:
Max
Units
Conditions
Output Capacitance (SO)
8
pF
VOUT = 0V
Input Capacitance (CS, SCK, SI, WP, HOLD)
6
pF
VIN = 0V
1. This parameter is characterized and is not 100% tested.
Table 1-2.
DC Characteristics(1)
Applicable over recommended operating range from: TAI = −40⋅C to +85⋅C, VCC = +1.8V to +5.5V, (unless otherwise noted)
Symbol
Parameter
VCC1
Supply Voltage
VCC2
Max
Units
1.8
5.5
V
Supply Voltage
2.5
5.5
V
VCC3
Supply Voltage
4.5
5.5
V
ICC1
Supply Current
VCC = 5.0V at 20 MHz, SO = Open, Read
8.5
10.0
mA
ICC2
Supply Current
VCC = 5.0V at 10 MHz, SO = Open, Read, Write
4.5
5.0
mA
ICC3
Supply Current
VCC = 5.0V at 1 MHz, SO = Open, Read, Write
2.0
3.0
mA
ISB1
Standby Current
VCC = 1.8V, CS = VCC
0.1
0.5
µA
ISB2
Standby Current
VCC = 2.5V, CS = VCC
0.2
1.0
µA
ISB3
Standby Current
VCC = 5.0V, CS = VCC
2.0
3.5
µA
IIL
Input Leakage
VIN = 0V to VCC
−3.0
Output Leakage
VIN = 0V to VCC, TAC = 0°C to 70°C
−3.0
3.0
µA
Input Low-voltage
−0.6
VCC x 0.3
V
VIH(1)
Input High-voltage
VCC x 0.7
VCC + 0.5
V
VOL1
Output Low-voltage
0.4
V
VOH1
Output High-voltage
VOL2
Output Low-voltage
VOH2
Output High-voltage
IOL
VIL
(1)
Note:
Test Condition
3.6V ≤ VCC ≤ 5.5V
1.8V ≤ VCC ≤ 3.6V
Min
IOL = 3.0 mA
IOH = −1.6 mA
µA
VCC − 0.8
IOL = 0.15 mA
IOH = −100 µA
Typ
V
0.2
VCC − 0.2
V
V
1. VIL min and VIH max are reference only and are not tested.
3
8707B–SEEPR–3/10
Table 1-3.
AC Characteristics
Applicable over recommended operating range from TAI = −40 to +85°C, VCC = As Specified,
CL = 1 TTL Gate and 30 pF (unless otherwise noted)
4
Symbol
Parameter
Voltage
Min
Max
Units
fSCK
SCK Clock Frequency
4.5 − 5.5
2.5 − 5.5
1.8 − 5.5
0
0
0
20
10
5
MHz
tRI
Input Rise Time
4.5 − 5.5
2.5 − 5.5
1.8 − 5.5
2
2
2
µs
tFI
Input Fall Time
4.5 − 5.5
2.5 − 5.5
1.8 − 5.5
2
2
2
µs
tWH
SCK High Time
4.5 − 5.5
2.5 − 5.5
1.8 − 5.5
20
40
80
ns
tWL
SCK Low Time
4.5 − 5.5
2.5 − 5.5
1.8 − 5.5
20
40
80
ns
tCS
CS High Time
4.5 − 5.5
2.5 − 5.5
1.8 − 5.5
100
100
200
ns
tCSS
CS Setup Time
4.5 − 5.5
2.5 − 5.5
1.8 − 5.5
100
100
200
ns
tCSH
CS Hold Time
4.5 − 5.5
2.5 − 5.5
1.8 − 5.5
100
100
200
ns
tSU
Data In Setup Time
4.5 − 5.5
2.5 − 5.5
1.8 − 5.5
20
40
80
ns
tH
Data In Hold Time
4.5 − 5.5
2.5 - 5.5
1.8 - 5.5
20
40
80
ns
tHD
Hold Setup Time
4.5 − 5.5
2.5 − 5.5
1.8 − 5.5
20
40
80
ns
tCD
Hold Hold Time
4.5 − 5.5
2.5 − 5.5
1.8 − 5.5
20
40
80
ns
tV
Output Valid
4.5 − 5.5
2.5 − 5.5
1.8 − 5.5
0
0
0
tHO
Output Hold Time
4.5 − 5.5
2.5 − 5.5
1.8 − 5.5
0
0
0
tLZ
Hold to Output Low Z
4.5 − 5.5
2.5 − 5.5
1.8 − 5.5
0
0
0
20
40
80
ns
ns
25
50
100
ns
AT25010B/020B/040B
8707B–SEEPR–3/10
AT25010B/020B/040B
Table 1-3.
AC Characteristics (Continued)
Applicable over recommended operating range from TAI = −40 to +85°C, VCC = As Specified,
CL = 1 TTL Gate and 30 pF (unless otherwise noted)
Symbol
Parameter
Voltage
tHZ
Hold to Output High Z
tDIS
tWC
Endurance(1)
Note:
2.
Max
Units
4.5 − 5.5
2.5 − 5.5
1.8 − 5.5
25
50
100
ns
Output Disable Time
4.5 − 5.5
2.5 − 5.5
1.8 − 5.5
25
50
100
ns
Write Cycle Time
4.5 − 5.5
2.5 − 5.5
1.8 − 5.5
5
5
5
ms
5.0V, 25⋅C, Page Mode
Min
1M
Write Cycles
1. This parameter is characterized and is not 100% tested.
Serial Interface Description
MASTER: The device that generates the serial clock.
SLAVE: Because the serial clock pin (SCK) is always an input, the AT25010B/020B/040B always operates as a
slave.
TRANSMITTER/RECEIVER: The AT25010B/020B/040B has separate pins designated for data transmission (SO)
and reception (SI).
MSB: The Most Significant Bit (MSB) is the first bit transmitted and received.
SERIAL OP-CODE: After the device is selected with CS going low, the first byte will be received. This byte contains the op-code that defines the operations to be performed. The op-code also contains address bit A8 in both
the read and write instructions.
INVALID OP-CODE: If an invalid op-code is received, no data will be shifted into the AT25010B/020B/040B, and
the serial output pin (SO) will remain in a high impedance state until the falling edge of CS is detected again. This
will reinitialize the serial communication.
CHIP SELECT: The AT25010B/020B/040B is selected when the CS pin is low. When the device is not selected,
data will not be accepted via the SI pin, and the SO pin will remain in a high impedance state.
HOLD: The HOLD pin is used in conjunction with the CS pin to select the AT25010B/020B/040B. When the device
is selected and a serial sequence is underway, HOLD can be used to pause the serial communication with the
master device without resetting the serial sequence. To pause, the HOLD pin must be brought low while the SCK
pin is low. To resume serial communication, the HOLD pin is brought high while the SCK pin is low (SCK may still
toggle during HOLD). Inputs to the SI pin will be ignored while the SO pin is in the high impedance state.
WRITE PROTECT: The write protect pin (WP) will allow normal read/write operations when held high. When the
WP pin is brought low, all write operations are inhibited.
WP going low while CS is still low will interrupt a write to the AT25010B/020B/040B. If the internal write cycle has
already been initiated, WP going low will have no effect on any write operation.
5
8707B–SEEPR–3/10
Figure 2-1.
SPI Serial Interface
AT25010B/020B/040B
6
AT25010B/020B/040B
8707B–SEEPR–3/10
AT25010B/020B/040B
3.
Functional Description
The AT25010B/020B/040B is designed to interface directly with the synchronous serial peripheral interface (SPI) of
the 6805 and 68HC11 series of microcontrollers.
The AT25010B/020B/040B utilizes an 8-bit instruction register. The list of instructions and their operation codes
are contained in Figure 3-1. All instructions, addresses, and data are transferred with the MSB first and start with a
high-to-low CS transition.
Table 3-1.
Instruction Set for the AT25010B/020B/040B
Instruction Name
Instruction Format
WREN
0000 X110
Set Write Enable Latch
WRDI
0000 X100
Reset Write Enable Latch
RDSR
0000 X101
Read Status Register
WRSR
0000 X001
Write Status Register
READ
0000 A011
Read Data from Memory Array
WRITE
0000 A010
Write Data to Memory Array
Note:
Operation
“A” represents MSB address bit A8.
WRITE ENABLE (WREN): The device will power up in the write disable state when VCC is applied. All programming instructions must therefore be preceded by a Write Enable instruction. The WP pin must be held high during
a WREN instruction.
WRITE DISABLE (WRDI): To protect the device against inadvertent writes, the Write Disable instruction disables
all programming modes. The WRDI instruction is independent of the status of the WP pin.
READ STATUS REGISTER (RDSR): The Read Status Register instruction provides access to the status register.
The read/busy and write enable status of the device can be determined by the RDSR instruction. Similarly, the
block write protection bits indicate the extent of protection employed. These bits are set by using the WRSR
instruction.
Table 3-2.
Status Register Format
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
X
X
X
X
BP1
BP0
WEN
RDY
Table 3-3.
Read Status Register Bit Definition
Bit
Definition
Bit 0 (RDY)
Bit 0 = “0” (RDY) indicates the device is ready.
Bit 0 = “1” indicates the write cycle is in progress.
Bit 1 (WEN)
Bit 1 = “0” indicates the device is not write enabled.
Bit 1 = “1” indicates the device is write enabled.
Bit 2 (BP0)
See Table 3-4.
Bit 3 (BP1)
See Table 3-4.
Bits 4–7 are “0”s when device is not in an internal write cycle.
Bits 0–7 are “1”s during an internal write cycle.
7
8707B–SEEPR–3/10
WRITE STATUS REGISTER (WRSR): The WRSR instruction allows the user to select one of four levels of protection. The AT25010B/020B/040B is divided into four array segments. One-quarter, one-half, or all of the memory
segments can be protected. Any of the data within any selected segment will therefore be read only. The block
write protection levels and corresponding status register control bits are shown in Table 3-4.
Bits BP1 and BP0 are nonvolatile cells that have the same properties and functions as the regular memory cells
(e.g., WREN, tWC, RDSR).
Table 3-4.
Block Write Protect Bits
Status Register Bits
Array Addresses Protected
Level
BP1
BP0
AT25010B
AT25020B
AT25040B
0
0
0
None
None
None
1 (1/4)
0
1
60−7F
C0−FF
180−1FF
2 (1/2)
1
0
40−7F
80−FF
100−1FF
3 (All)
1
1
00−7F
00−FF
000−1FF
READ SEQUENCE (READ): Reading the AT25010B/020B/040B via the SO pin requires the following sequence.
After the CS line is pulled low to select a device, the read op-code (including A8) is transmitted via the SI line followed by the byte address to be read (A7−A0). Upon completion, any data on the SI line will be ignored. The data
(D7−D0) at the specified address is then shifted out onto the SO line. If only one byte is to be read, the CS line
should be driven high after the data comes out. The read sequence can be continued since the byte address is
automatically incremented and data will continue to be shifted out. When the highest address is reached, the
address counter will roll over to the lowest address allowing the entire memory to be read in one continuous read
cycle.
WRITE SEQUENCE (WRITE): In order to program the AT25010B/020B/040B, the Write Protect pin (WP) must be
held high and two separate instructions must be executed. First, the device must be write enabled via the WREN
instruction. Then a Write (WRITE) instruction may be executed. Also, the address of the memory location(s) to be
programmed must be outside the protected address field location selected by the block write protection level. During an internal write cycle, all commands will be ignored except the RDSR instruction.
A Write instruction requires the following sequence. After the CS line is pulled low to select the device, the WRITE
op-code (including A8) is transmitted via the SI line followed by the byte address (A7−A0) and the data (D7−D0) to
be programmed. Programming will start after the CS pin is brought high. The low-to-high transition of the CS pin
must occur during the SCK low time immediately after clocking in the D0 (LSB) data bit.
The ready/busy status of the device can be determined by initiating a Read Status Register (RDSR) instruction. If
Bit 0 = “1”, the write cycle is still in progress. If Bit 0 = “0”, the write cycle has ended. Only the RDSR instruction is
enabled during the write programming cycle.
The AT25010B/020B/040B is capable of an 8-byte page write operation. After each byte of data is received, the
three low-order address bits are internally incremented by one; the six high-order bits of the address will remain
constant. If more than 8 bytes of data are transmitted, the address counter will roll over and the previously written
data will be overwritten. The AT25010B/020B/040B is automatically returned to the write disable state at the completion of a write cycle.
Note:
8
If the WP pin is brought low or if the device is not write enabled (WREN), the device will ignore the Write instruction and
will return to the standby state, when CS is brought high. A new CS falling edge is required to reinitiate the serial
communication.
AT25010B/020B/040B
8707B–SEEPR–3/10
AT25010B/020B/040B
4.
Timing Diagrams
Figure 4-1.
Synchronous Data Timing (for Mode 0)
t CS
VIH
CS
VIL
t CSH
tCSS
VIH
t WH
SCK
t WL
VIL
tH
t SU
VIH
SI
VALID IN
VIL
tV
VOH
SO
t HO
t DIS
HI-Z
HI-Z
VOL
Figure 4-2.
WREN Timing
CS
SCK
SI
WREN OP-CODE
HI-Z
SO
Figure 4-3.
WRDI Timing
CS
SCK
SI
SO
WRDI OP-CODE
HI-Z
9
8707B–SEEPR–3/10
Figure 4-4.
RDSR Timing
CS
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
SCK
SI
INSTRUCTION
DATA OUT
HIGH IMPEDANCE
SO
7
6
5
4
3
2
1
0
8
9
10
11
12
13
14
15
MSB
Figure 4-5.
WRSR Timing
CS
0
1
2
3
4
5
6
7
SCK
DATA IN
SI
6
5
4
3
2
1
0
HIGH IMPEDANCE
SO
Figure 4-6.
7
INSTRUCTION
READ Timing
CS
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
SCK
INSTRUCTION
SI
BYTE ADDRESS
8
7
9th
6
5
4
3
2
1
0
BIT OF ADDRESS
DATA OUT
SO
HIGH IMPEDANCE
7
6
5
4
3
2
1
0
MSB
10
AT25010B/020B/040B
8707B–SEEPR–3/10
AT25010B/020B/040B
Figure 4-7.
WRITE Timing
CS
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
SCK
INSTRUCTION
BYTE ADDRESS
8
SI
7
9th
SO
Figure 4-8.
6
5
4
3
2
DATA IN
1
0
7
6
5
4
3
2
1
0
BIT OF ADDRESS
HIGH IMPEDANCE
HOLD Timing
CS
t CD
t CD
SCK
t HD
HOLD
t HD
t HZ
SO
tLZ
11
8707B–SEEPR–3/10
5.
Ordering Code Detail
AT 2 5 0 1 0 B - S S H L - B
Atmel Designator
Shipping Carrier Option
B or blank = Bulk (tubes)
T = Tape and reel
Product Family
Operating Voltage
L
Device Density
010 = 1k
020 = 2k
040 = 4k
Device Revision
= 1.8V to 5.5V
Package Device Grade or
Wafer/Die Thickness
H
= Green, NiPdAu lead finish,
Industrial Temperature Range
(-40˚C to +85˚C)
U = Green, matte Sn lead finish,
Industrial Temperature range
(-40˚C to +85˚C)
11 = 11mil wafer thickness
Package Option
SS =
X =
MA =
ME =
C =
WWU
WDT
12
JEDEC SOIC
TSSOP
UDFN
XDFN
VFBGA
= Wafer unsawn
= Die in Tape and Reel
AT25010B/020B/040B
8707B–SEEPR–3/10
AT25010B/020B/040B
6.
Part Markings
AT25010B-SSHL
|---|---|---|---|---|---|---|---|
A
T
M
L
H
Y
W
W
|---|---|---|---|---|---|---|---|
5
1
B
L
@
|---|---|---|---|---|---|---|---|
ATMEL LOT NUMBER
|---|---|---|---|---|---|---|---|
|
PIN 1 INDICATOR (DOT)
LINE 1:
LINE 2:
LINE 3:
ATML=ATMEL H=MATERIAL SET/GRADE YWW=DATE CODE
51B=AT25010B, L=1.8 to 5.5v, @=COUNTRY of ORIGIN
ATMEL LOT NUMBER
AT25010B-XHL
PIN 1 INDICATOR(DOT)
| |---|---|---|---|---|---|
*
A
T
H
Y
W
W
|---|---|---|---|---|---|
5
1
B
L
@
|---|---|---|---|---|---|---|
ATMEL LOT NUMBER
|---|---|---|---|---|---|---|
LINE 1:
LINE 2:
LINE 3:
AT=ATMEL H=MATERIAL SET/GRADE YWW=DATE CODE
51B=AT25010B, L=1.8 to 5.5v, @=COUNTRY of ORIGIN
ATMEL LOT NUMBER
AT25010B-CUL
|---|---|---|---|
5
1
B
U
|---|---|---|---|
Y
M
X
X
|---|---|---|---|
|
