AT25010B/AT25020B/
AT25040B
SPI Serial EEPROM 1 Kbit (128 x 8), 2 Kbits (256 x 8)
and 4 Kbits (512 x 8)
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
Serial Peripheral Interface (SPI) Compatible
Supports SPI Modes 0 (0,0) and 3 (1,1):
– Data sheet describes mode 0 operation
Low-Voltage Operation:
– 1.8V (VCC = 1.8V to 5.5V)
Industrial Temperature Range: -40°C to +85°C
20 MHz Clock Rate (5V)
8‑Byte Page Mode
Block Write Protection:
– Protect 1/4, 1/2 or entire array
Write-Protect (WP) Pin and Write Disable Instructions for Both Hardware and Software Data Protection
Self-Timed Write Cycle within 5 ms Maximum
ESD Protection > 4,000V
High Reliability:
– Endurance: 1,000,000 write cycles
– Data retention: 100 years
Green (Lead-free/Halide-free/RoHS Compliant) Package Options
Die Sale Options: Wafer Form and Bumped Wafers
Packages
•
8-Lead SOIC, 8-Lead TSSOP, 8-Pad UDFN and 8-Ball VFBGA
© 2019 Microchip Technology Inc.
DS20006251A-page 1
AT25010B/AT25020B/AT25040B
Table of Contents
Features......................................................................................................................................................... 1
Packages........................................................................................................................................................1
1.
Package Types (not to scale)..................................................................................................................4
2.
Pin Description........................................................................................................................................ 5
2.1.
2.2.
2.3.
2.4.
2.5.
2.6.
2.7.
2.8.
3.
Description.............................................................................................................................................. 7
3.1.
3.2.
4.
Absolute Maximum Ratings..........................................................................................................9
DC and AC Operating Range.......................................................................................................9
DC Characteristics....................................................................................................................... 9
AC Characteristics......................................................................................................................10
SPI Synchronous Data Timimg.................................................................................................. 12
Electrical Specifications..............................................................................................................12
Device Operation.................................................................................................................................. 14
5.1.
5.2.
5.3.
5.4.
6.
SPI Bus Master Connections to Serial EEPROMs.......................................................................7
Block Diagram.............................................................................................................................. 8
Electrical Characteristics.........................................................................................................................9
4.1.
4.2.
4.3.
4.4.
4.5.
4.6.
5.
Chip Select (CS)...........................................................................................................................5
Serial Data Output (SO)............................................................................................................... 5
Write-Protect (WP)....................................................................................................................... 5
Ground (GND).............................................................................................................................. 5
Serial Data Input (SI)....................................................................................................................5
Serial Data Clock (SCK)...............................................................................................................6
Suspend Serial Input (HOLD).......................................................................................................6
Device Power Supply (VCC)......................................................................................................... 6
Interfacing the AT25010B/AT25020B/AT25040B on the SPI Bus.............................................. 14
Device Opcodes......................................................................................................................... 15
Hold Function............................................................................................................................. 15
Write Protection..........................................................................................................................16
Device Commands and Addressing......................................................................................................17
6.1.
6.2.
STATUS Register Bit Definition and Function............................................................................ 17
Read STATUS Register (RDSR)..................................................................................................18
6.3.
Write Enable (WREN) and Write Disable (WRDI)......................................................................... 18
6.4.
Write STATUS Register (WRSR).................................................................................................. 19
7.
Read Sequence.................................................................................................................................... 21
8.
Write Sequence.....................................................................................................................................22
8.1.
8.2.
8.3.
9.
Byte Write...................................................................................................................................22
Page Write..................................................................................................................................22
Polling Routine........................................................................................................................... 23
Packaging Information.......................................................................................................................... 24
© 2019 Microchip Technology Inc.
DS20006251A-page 2
AT25010B/AT25020B/AT25040B
9.1.
Package Marking Information.....................................................................................................24
10. Revision History.................................................................................................................................... 34
The Microchip Website.................................................................................................................................35
Product Change Notification Service............................................................................................................35
Customer Support........................................................................................................................................ 35
Product Identification System.......................................................................................................................36
Microchip Devices Code Protection Feature................................................................................................ 36
Legal Notice................................................................................................................................................. 37
Trademarks.................................................................................................................................................. 37
Quality Management System....................................................................................................................... 38
Worldwide Sales and Service.......................................................................................................................39
© 2019 Microchip Technology Inc.
DS20006251A-page 3
AT25010B/AT25020B/AT25040B
Package Types (not to scale)
1.
Package Types (not to scale)
8-Lead SOIC/TSSOP
(Top View)
CS
1
8
Vcc
SO
2
7
HOLD
WP
3
6
SCK
GND
4
5
SI
8-Ball VFBGA
(Top View)
8-Pad UDFN
(Top View)
CS
1
8
Vcc
SO
2
7
HOLD
WP
3
6
SCK
GND
4
5
SI
© 2019 Microchip Technology Inc.
CS
1
8
Vcc
SO
2
7
HOLD
WP
3
6
SCK
GND
4
5
SI
DS20006251A-page 4
AT25010B/AT25020B/AT25040B
Pin Description
2.
Pin Description
The descriptions of the pins are listed in Table 2-1.
Table 2-1. Pin Function Table
Name
8-Lead SOIC
8-Lead TSSOP
8-Pad UDFN(1)
8-Ball VFBGA
CS
1
1
1
1
Chip Select
SO
WP(2)
2
2
2
2
Serial Data Output
3
3
3
3
Write-Protect
GND
4
4
4
4
Ground
SI
5
5
5
5
Serial Data Input
SCK
HOLD(2)
6
6
6
6
Serial Data Clock
7
7
7
7
Suspends Serial Input
VCC
8
8
8
8
Device Power Supply
Function
Note:
1. The exposed pad on this package can be connected to GND or left floating.
2. The Write-Protect (WP) and Hold (HOLD) pins should be driven high or low as appropriate.
2.1
Chip Select (CS)
The AT25010B/AT25020B/AT25040B is selected when the Chip Select (CS) pin is low. When the device is not
selected, data will not be accepted via the Serial Data Input (SI) pin, and the Serial Output (SO) pin will remain in
a high‑impedance state.
To ensure robust operation, the CS pin should follow VCC upon power-up. It is therefore recommended to connect CS
to VCC using a pull-up resistor (less than or equal to 10 kΩ). After power-up, a low level on CS is required prior to any
sequence being initiated.
2.2
Serial Data Output (SO)
The Serial Data Output (SO) pin is used to transfer data out of the AT25010B/AT25020B/AT25040B. During a read
sequence, data is shifted out on this pin after the falling edge of the Serial Data Clock (SCK).
2.3
Write-Protect (WP)
The Write-Protect (WP) pin will allow normal read/write operations when held high. When the WP pin is brought low,
all write operations are inhibited. WP going low while CS is still low will interrupt a write operation. If the internal write
cycle has already been initiated, WP going low will have no effect on any write operation.
2.4
Ground (GND)
The ground reference for the Device Power Supply (VCC). The Ground (GND) pin should be connected to the system
ground.
2.5
Serial Data Input (SI)
The Serial Data Input (SI) pin is used to transfer data into the device. It receives instructions, addresses and data.
Data is latched on the rising edge of the Serial Data Clock (SCK).
© 2019 Microchip Technology Inc.
DS20006251A-page 5
AT25010B/AT25020B/AT25040B
Pin Description
2.6
Serial Data Clock (SCK)
The Serial Data Clock (SCK) pin is used to synchronize the communication between a master and the AT25010B/
AT25020B/AT25040B. Instructions, addresses or data present on the Serial Data Input (SI) pin is latched in on the
rising edge of SCK, while output on the Serial Data Output (SO) pin is clocked out on the falling edge of SCK.
2.7
Suspend Serial Input (HOLD)
The Suspend Serial Input (HOLD) pin is used in conjunction with the Chip Select (CS) pin to pause the AT25010B/
AT25020B/AT25040B. When the device is selected and a serial sequence is underway, HOLD can be used to pause
the serial communication with the master device without resetting the serial sequence. To pause, the HOLD pin must
be brought low while the Serial Data Clock (SCK) pin is low. To resume serial communication, the HOLD pin is
brought high while the SCK pin is low (SCK may still toggle during HOLD). Inputs to the Serial Data Input (SI) pin will
be ignored while the Serial Data Output (SO) pin will be in the high‑impedance state.
2.8
Device Power Supply (VCC)
The Device Power Supply (VCC) pin is used to supply the source voltage to the device. Operations at invalid VCC
voltages may produce spurious results and should not be attempted.
© 2019 Microchip Technology Inc.
DS20006251A-page 6
AT25010B/AT25020B/AT25040B
Description
3.
Description
The AT25010B/AT25020B/AT25040B provides 1,024/2,048/4,096 bits of Serial Electrically Erasable and
Programmable Read-Only Memory (EEPROM) organized as 128/256/512 words of 8 bits each. The device is
optimized for use in many industrial and commercial applications where low‑power and low‑voltage operation are
essential. The device is available in space-saving 8‑lead SOIC, 8‑lead TSSOP, 8‑pad UDFN and 8‑ball VFBGA
packages. All packages operate from 1.8V to 5.5V.
3.1
SPI Bus Master Connections to Serial EEPROMs
SPI Master:
Microcontroller
Data Clock (SCK)
Data Output (SO)
Data Input (SI)
SI
CS3 CS2 CS1 CS0
© 2019 Microchip Technology Inc.
SO SCK
SI
SO SCK
SI
SO SCK
SI
SO SCK
Slave 0
AT25XXX
Slave 1
AT25XXX
Slave 2
AT25XXX
Slave 3
AT25XXX
CS
CS
CS
CS
DS20006251A-page 7
AT25010B/AT25020B/AT25040B
Description
Block Diagram
Memory
System Control
Module
CS
High-Voltage
Generation
Circuit
Power-on
Reset
Generator
VCC
Pause
Operation
Control
HOLD
Register Bank:
STATUS Register
SO
EEPROM Array
1 page
Column Decoder
WP
Data Register
Row Decoder
3.2
Address Register
and Counter
SCK
Data Output
Buffer
GND
Write Protection
Control
© 2019 Microchip Technology Inc.
SI
DS20006251A-page 8
AT25010B/AT25020B/AT25040B
Electrical Characteristics
4.
Electrical Characteristics
4.1
Absolute Maximum Ratings
Operating temperature
-40°C to +125°C
Storage temperature
-65°C to +150°C
Voltage on any pin with respect to ground
-1.0V to +7.0V
VCC
6.25V
DC output current
5.0 mA
ESD protection
> 4 kV
Note: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
This is a stress rating only and functional operation of the device at these or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.
4.2
DC and AC Operating Range
Table 4-1. DC and AC Operating Range
AT25010B/AT25020B/AT25040B
4.3
Operating Temperature (Case)
Industrial Temperature Range
-40°C to +85°C
VCC Power Supply
Low-Voltage Grade
1.8V to 5.5V
DC Characteristics
Table 4-2. DC Characteristics(1)
Parameter
Symbol
Minimum
Typical
Maximum
Units
Supply Voltage
VCC1
1.8
—
5.5
V
Supply Voltage
VCC2
2.5
—
5.5
V
Supply Voltage
VCC3
4.5
—
5.5
V
Supply Current
ICC1
—
8.5
10.0
mA
VCC = 5.0V at 20 MHz,
SO = Open, Read
Supply Current
ICC2
—
4.5
5.0
mA
VCC = 5.0V at 10 MHz,
SO = Open, Read, Write
Supply Current
ICC3
—
2.0
3.0
mA
VCC = 5.0V at 1 MHz,
SO = Open, Read, Write
Standby Current
ISB1
—
0.1
0.5
µA
VCC = 1.8V, CS = VCC
Standby Current
ISB2
—
0.2
1.0
µA
VCC = 2.5V, CS = VCC
Standby Current
ISB3
—
2.0
3.5
µA
VCC = 5.0V, CS = VCC
IIL
-3.0
—
3.0
µA
VIN = 0V to VCC
Input Leakage
© 2019 Microchip Technology Inc.
Conditions
DS20006251A-page 9
AT25010B/AT25020B/AT25040B
Electrical Characteristics
...........continued
Parameter
Symbol
Minimum
Typical
Maximum
Units
IOL
-3.0
—
3.0
µA
Input
Low-Voltage
VIL(2)
-0.6
—
VCC x 0.3
V
Input
High-Voltage
VIH(2)
VCC x 0.7
—
VCC + 0.5
V
Output
Low-Voltage
VOL1
—
—
0.4
V
3.6V ≤ VCC ≤ 5.5V
IOL = 3.0 mA
Output
High-Voltage
VOH1
VCC - 0.8
—
—
V
3.6V ≤ VCC ≤ 5.5V
IOH = -1.6 mA
Output
Low-Voltage
VOL2
—
—
0.2
V
1.8V ≤ VCC ≤ 3.6V
IOL = 0.15 mA
Output
High-Voltage
VOH2
VCC - 0.2
—
—
V
1.8V ≤ VCC ≤ 3.6V
IOH = -100 µA
Output Leakage
Conditions
VIN = 0V to VCC,
TA = 0°C to +70°C
Note:
1. Applicable over recommended operating range from: TA = -40°C to +85°C, VCC = 1.8V to 5.5V (unless
otherwise noted).
2. VIL min and VIH max are reference only and are not tested.
4.4
AC Characteristics
Table 4-3. AC Characteristics(1)
Parameter
SCK Clock Frequency
Symbol
Minimum
Maximum
Units
Conditions
fSCK
0
20
MHz
VCC = 4.5V to 5.5V
0
10
MHz
VCC = 2.5V to 5.5V
0
5
MHz
VCC = 1.8V to 5.5V
Input Rise Time
tRI
—
2000
ns
VCC = 1.8V to 5.5V
Input Fall Time
tFI
—
2000
ns
VCC = 1.8V to 5.5V
SCK High Time
tWH
20
—
ns
VCC = 4.5V to 5.5V
40
—
ns
VCC = 2.5V to 5.5V
80
—
ns
VCC = 1.8V to 5.5V
20
—
ns
VCC = 4.5V to 5.5V
40
—
ns
VCC = 2.5V to 5.5V
80
—
ns
VCC = 1.8V to 5.5V
100
—
ns
VCC = 4.5V to 5.5V
100
—
ns
VCC = 2.5V to 5.5V
200
—
ns
VCC = 1.8V to 5.5V
SCK Low Time
CS High Time
© 2019 Microchip Technology Inc.
tWL
tCS
DS20006251A-page 10
AT25010B/AT25020B/AT25040B
Electrical Characteristics
...........continued
Parameter
CS Setup Time
CS Hold Time
Data In Setup Time
Data In Hold Time
HOLD Setup Time
HOLD Hold Time
Output Valid
Output Hold Time
HOLD to Output Low-Z
HOLD to Output High-Z
Output Disable Time
Write Cycle Time
© 2019 Microchip Technology Inc.
Symbol
Minimum
Maximum
Units
tCSS
100
—
ns
VCC = 4.5V to 5.5V
100
—
ns
VCC = 2.5V to 5.5V
200
—
ns
VCC = 1.8V to 5.5V
100
—
ns
VCC = 4.5V to 5.5V
100
—
ns
VCC = 2.5V to 5.5V
200
—
ns
VCC = 1.8V to 5.5V
20
—
ns
VCC = 4.5V to 5.5V
40
—
ns
VCC = 2.5V to 5.5V
80
—
ns
VCC = 1.8V to 5.5V
20
—
ns
VCC = 4.5V to 5.5V
40
—
ns
VCC = 2.5V to 5.5V
80
—
ns
VCC = 1.8V to 5.5V
20
—
ns
VCC = 4.5V to 5.5V
40
—
ns
VCC = 2.5V to 5.5V
80
—
ns
VCC = 1.8V to 5.5V
20
—
ns
VCC = 4.5V to 5.5V
40
—
ns
VCC = 2.5V to 5.5V
80
—
ns
VCC = 1.8V to 5.5V
0
20
ns
VCC = 4.5V to 5.5V
0
40
ns
VCC = 2.5V to 5.5V
0
80
ns
VCC = 1.8V to 5.5V
0
—
ns
VCC = 4.5V to 5.5V
0
—
ns
VCC = 2.5V to 5.5V
0
—
ns
VCC = 1.8V to 5.5V
0
25
ns
VCC = 4.5V to 5.5V
0
50
ns
VCC = 2.5V to 5.5V
0
100
ns
VCC = 1.8V to 5.5V
—
25
ns
VCC = 4.5V to 5.5V
—
50
ns
VCC = 2.5V to 5.5V
—
100
ns
VCC = 1.8V to 5.5V
—
25
ns
VCC = 4.5V to 5.5V
—
50
ns
VCC = 2.5V to 5.5V
—
100
ns
VCC = 1.8V to 5.5V
—
5
ms
VCC = 1.8V to 5.5V
tCSH
tSU
tH
tHD
tCD
tV
tHO
tLZ
tHZ
tDIS
tWC
Conditions
DS20006251A-page 11
AT25010B/AT25020B/AT25040B
Electrical Characteristics
Note:
1. Applicable over recommended operating range from TA = -40°C to +85°C, VCC = As Specified, CL = 1 TTL
Gate and 30 pF (unless otherwise noted).
4.5
SPI Synchronous Data Timimg
tCS
VIH
CS
VIL
tCSS
tCSH
VIH
SCK
tWH
tWL
VIL
tSU
tH
VIH
SI
Valid Data In
VIL
tV
VOH
SO
VOL
tHO
tDIS
High
Impedance
High
Impedance
4.6
Electrical Specifications
4.6.1
Power-Up Requirements and Reset Behavior
During a power-up sequence, the VCC supplied to the AT25010B/AT25020B/AT25040B should monotonically rise
from GND to the minimum VCC level, as specified in Table 4-1, with a slew rate no faster than 0.1 V/µs.
4.6.1.1
Device Reset
To prevent inadvertent write operations or any other spurious events from occurring during a power-up sequence, the
AT25010B/AT25020B/AT25040B includes a Power-on Reset (POR) circuit. Upon power-up, the device will not
respond to any instructions until the VCC level crosses the internal voltage threshold (VPOR) that brings the device out
of Reset and into Standby mode.
The system designer must ensure the instructions are not sent to the device until the VCC supply has reached a
stable value greater than or equal to the minimum VCC level. Additionally, once the VCC is greater than or equal to the
minimum VCC level, the bus master must wait at least tPUP before sending the first instruction to the device. See Table
4-4 for the values associated with these power-up parameters.
Table 4-4. Power-Up Conditions(1)
Symbol
Parameter
tPUP
Time required after VCC is stable before the device can accept instructions
VPOR
Power-on Reset Threshold Voltage
tPOFF
Minimum time at VCC = 0V between power cycles
Min.
Max.
Units
100
－
µs
－
1.5
V
500
－
ms
Note:
1. These parameters are characterized but they are not 100% tested in production.
If an event occurs in the system where the VCC level supplied to the AT25010B/AT25020B/AT25040B drops below
the maximum VPOR level specified, it is recommended that a full-power cycle sequence be performed by first driving
© 2019 Microchip Technology Inc.
DS20006251A-page 12
AT25010B/AT25020B/AT25040B
Electrical Characteristics
the VCC pin to GND in less than 1 ms, waiting at least the minimum tPOFF time and then performing a new power-up
sequence in compliance with the requirements defined in this section.
4.6.2
Pin Capacitance
Table 4-5. Pin Capacitance(1,2)
Symbol
Test Condition
Max.
Units
Conditions
COUT
Output Capacitance (SO)
8
pF
VOUT = 0V
CIN
Input Capacitance (CS, SCK, SI, WP, HOLD)
6
pF
VIN = 0V
Note:
1. This parameter is characterized but is not 100% tested in production.
2. Applicable over recommended operating range from: TA = 25°C, fSCK = 1.0 MHz, VCC = 5.0V (unless otherwise
noted).
4.6.3
EEPROM Cell Performance Characteristics
Table 4-6. EEPROM Cell Performance Characteristics
Operation
Write
Endurance(1)
Data Retention(1)
Test Condition
TA = 25°C, VCC = 5.0V,
Page Write mode
TA = 55°C
Min.
Max.
Units
1,000,000
—
Write Cycles
100
—
Years
Note:
1. Performance is determined through characterization and the qualification process.
4.6.4
Software Reset
The SPI interface of the AT25010B/AT25020B/AT25040B can be reset by toggling the CS input. If the CS line is
already in the Active state, it must complete a transition from the Inactive state (≥VIH) to the Active state (≤VIL) and
then back to the Inactive state (≥VIH) without sending clocks on the SCK line. Upon completion of this sequence, the
device will be ready to receive a new opcode on the SI line.
4.6.5
Device Default State at Power-Up
The AT25010B/AT25020B/AT25040B default state upon power-up consists of:
• Standby Power mode
• A high-to-low-level transition on CS is required to enter Active state
• Write Enable Latch (WEL) bit in the STATUS register = 0
4.6.6
•
Ready/Busy bit in the STATUS register = 0, indicating the device is ready to accept a new command
•
•
•
Device is not selected
Not in Hold condition
BP1 and BP0 bits in the STATUS register are unchanged from their previous state due to the fact that they are
nonvolatile values
Device Default Condition
The AT25010B/AT25020B/AT25040B is shipped from Microchip to the customer with the EEPROM array set to an all
FFh data pattern (logic ‘1’ state). The Block Write‑Protect bits in the STATUS register are set to logic ‘0’.
© 2019 Microchip Technology Inc.
DS20006251A-page 13
AT25010B/AT25020B/AT25040B
Device Operation
5.
Device Operation
The AT25010B/AT25020B/AT25040B is controlled by a set of instructions that are sent from a host controller,
commonly referred to as the SPI Master. The SPI Master communicates with the AT25010B/AT25020B/AT25040B via
the SPI bus which is comprised of four signal lines: Chip Select (CS), Serial Data Clock (SCK), Serial Data Input (SI)
and Serial Data Output (SO).
The SPI protocol defines a total of four modes of operation (Mode 0, 1, 2 or 3) with each mode differing in respect to
the SCK polarity and phase and how the polarity and phase control the flow of data on the SPI bus. The AT25010B/
AT25020B/AT25040B supports the two most common modes, SPI Modes 0 and 3. With SPI Modes 0 and 3, data is
always latched in on the rising edge of SCK and always output on the falling edge of SCK. The only difference
between SPI Modes 0 and 3 is the polarity of the SCK signal when in the inactive state (when the SPI Master is in
Standby mode and not transferring any data). SPI Mode 0 is defined as a low SCK while CS is not asserted (at VCC)
and SPI Mode 3 has SCK high in the inactive state. The SCK Idle state must match when the CS is deasserted both
before and after the communication sequence in SPI Mode 0 and 3. The figures in this document depict Mode 0 with
a solid line on SCK while CS is inactive and Mode 3 with a dotted line.
Figure 5-1. SPI Mode 0 and Mode 3
CS
SCK
SI
Mode 3
Mode 3
Mode 0
Mode 0
MSB
SO
5.1
LSB
MSB
LSB
Interfacing the AT25010B/AT25020B/AT25040B on the SPI Bus
Communication to and from the AT25010B/AT25020B/AT25040B must be initiated by the SPI Master device, such as
a microcontroller. The SPI Master device must generate the serial clock for the AT25010B/AT25020B/AT25040B on
the Serial Data Clock (SCK) pin. The AT25010B/AT25020B/AT25040B always operates as a slave due to the fact that
the SCK is always an input.
5.1.1
Selecting the Device
The AT25010B/AT25020B/AT25040B is selected when the Chip Select (CS) pin is low. When the device is not
selected, data will not be accepted via the Serial Data Input (SI) pin, and the Serial Data Output (SO) pin will remain
in a high‑impedance state.
5.1.2
Sending Data to the Device
The AT25010B/AT25020B/AT25040B uses the SI pin to receive information. All instructions, addresses and data
input bytes are clocked into the device with the Most Significant bit (MSb) first. The SI pin samples on the first rising
edge of the SCK line after the CS has been asserted.
5.1.3
Receiving Data from the Device
Data output from the device is transmitted on the SO pin, with the MSb output first. The SO data is latched on the first
falling edge of SCK after the instruction has been clocked into the device, such as the Read from Memory Array
(READ) and Read STATUS Register (RDSR) instructions. See Read Sequence for more details.
© 2019 Microchip Technology Inc.
DS20006251A-page 14
AT25010B/AT25020B/AT25040B
Device Operation
5.2
Device Opcodes
5.2.1
Serial Opcode
After the device is selected by driving CS low, the first byte will be received on the SI pin. This byte contains the
opcode that defines the operation to be performed. Refer to Table 6-1 for a list of all opcodes that the AT25010B/
AT25020B/AT25040B will respond to.
5.2.2
Invalid Opcode
If an invalid opcode is received, no data will be shifted into AT25010B/AT25020B/AT25040B and the SO pin will
remain in a high‑impedance state until the falling edge of CS is detected again. This will reinitialize the serial
communication.
5.3
Hold Function
The Suspend Serial Input (HOLD) pin is used to pause the serial communication with the device without having to
stop or reset the clock sequence. The Hold mode, however, does not have an effect on the internal write cycle.
Therefore, if a write cycle is in progress, asserting the HOLD pin will not pause the operation and the write cycle will
continue to completion.
The Hold mode can only be entered while the CS pin is asserted. The Hold mode is activated by asserting the HOLD
pin during the SCK low pulse. If the HOLD pin is asserted during the SCK high pulse, then the Hold mode will not be
started until the beginning of the next SCK low pulse. The device will remain in the Hold mode as long as the HOLD
pin and CS pin are asserted.
While in Hold mode, the SO pin will be in a high-impedance state. In addition, both the SI pin and the SCK pin will be
ignored. The Write-Protect (WP) pin, however, can still be asserted or deasserted while in the Hold mode.
To end the Hold mode and resume serial communication, the HOLD pin must be deasserted during the SCK low
pulse. If the HOLD pin is deasserted during the SCK high pulse, then the Hold mode will not end until the beginning
of the next SCK low pulse.
If the CS pin is deasserted while the HOLD pin is still asserted, then any operation that may have been started will be
aborted and the device will reset the WEL bit in the STATUS register back to the logic ‘0’ state.
Figure 5-2. Hold Mode
CS
SCK
HOLD
Hold
© 2019 Microchip Technology Inc.
Hold
Hold
DS20006251A-page 15
AT25010B/AT25020B/AT25040B
Device Operation
Figure 5-3. Hold Timing
CS
t CD
t CD
SCK
HOLD
t HD
t HD
t HZ
SO
tLZ
5.4
Write Protection
The Write-Protect (WP) pin will allow normal read and write operations when held high. When the WP pin is brought
low, all write operations are inhibited. The WP pin going low while CS is still low will interrupt a write operation. If the
internal write cycle has already been initiated, WP going low will have no effect on any write operation.
© 2019 Microchip Technology Inc.
DS20006251A-page 16
AT25010B/AT25020B/AT25040B
Device Commands and Addressing
6.
Device Commands and Addressing
The AT25010B/AT25020B/AT25040B is designed to interface directly with the synchronous Serial Peripheral
Interface (SPI). The AT25010B/AT25020B/AT25040B utilizes an 8‑bit instruction register. The list of instructions and
their operation codes are contained in Table 6-1. All instructions, addresses and data are transferred with the MSb
first and start with a high‑to‑low CS transition.
Table 6-1. Instruction Set for the AT25010B/AT25020B/AT25040B
Instruction Name
Instruction Format
Operates On
Operation Description
WREN
0000 X110
STATUS Register
Set Write Enable Latch (WEL)
WRDI
0000 X100
STATUS Register
Reset Write Enable Latch (WEL)
RDSR
0000 X101
STATUS Register
Read STATUS Register
WRSR
0000 X001
STATUS Register
Write STATUS Register
READ
0000 A011
Memory Array
Read from Memory Array
WRITE
0000 A010
Memory Array
Write to Memory Array
Note:
1. “A” represents the MSb address bit (A8) for the AT25040B and a “don't care” bit for the AT25010B and
AT25020B.
6.1
STATUS Register Bit Definition and Function
The AT25010B/AT25020B/AT25040B includes an 8‑bit STATUS register. The STATUS register bits modulate various
features of the device as shown in Table 6-2 and Table 6-3. These bits can be changed by specific instructions that
are detailed in the following sections.
Table 6-2. STATUS Register Format
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
X
X
X
X
BP1
BP0
WEL
RDY/BSY
Table 6-3. STATUS Register Bit Definition
Bit
7:4
3:2
Name
RFU
BP1
BP0
Reserved for Future Use
Block Write Protection
Type
R
R/W
Description
0
Reads as zeros when the device is not in a write cycle
1
Reads as ones when the device is in a write cycle
00 No array write protection (Factory Default)
01 Quarter array write protection (see Table 6-4)
10 Half array write protection (see Table 6-4)
11 Entire array write protection (see Table 6-4)
1
0
WEL
Write Enable Latch
RDY/BSY Ready/Busy Status
© 2019 Microchip Technology Inc.
R
R
0
Device is not write enabled (Power-up Default)
1
Device is write enabled
0
Device is ready for a new sequence
1
Device is busy with an internal operation
DS20006251A-page 17
AT25010B/AT25020B/AT25040B
Device Commands and Addressing
6.2
Read STATUS Register (RDSR)
The Read STATUS Register (RDSR) instruction provides access to the STATUS register. The ready/busy and write
enable status of the device can be determined by the RDSR instruction. Similarly, the Block Write-Protect (BP1, BP0)
bits indicate the extent of memory array protection employed. The STATUS register is read by asserting the CS pin,
followed by sending in a 05h opcode on the SI pin. Upon completion of the opcode, the device will return the 8‑bit
STATUS register value on the SO pin.
Figure 6-1. RDSR Waveform
CS
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
SCK
RDSR Opcode (05h)
SI
0
0
0
0
0
1
0
1
MSB
STATUS Register Data Out
SO
High-Impedance
D7
D6
D5
D4
D3
D2
D1
D0
MSB
6.3
Write Enable (WREN) and Write Disable (WRDI)
Enabling and disabling writing to the STATUS register and EEPROM array is accomplished through the Write Enable
(WREN) instruction and the Write Disable (WRDI) instruction. These functions change the status of the WEL bit in the
STATUS register.
6.3.1
Write Enable Instruction (WREN)
The Write Enable Latch (WEL) bit of the STATUS register must be set to a logic ‘1’ prior to each Write STATUS
Register (WRSR) and Write to Memory Array (WRITE) instructions. This is accomplished by sending a WREN (06h)
instruction to the AT25010B/AT25020B/AT25040B. First, the CS pin is driven low to select the device and then a
WREN instruction is clocked in on the SI pin. Then the CS pin can be driven high and the WEL bit will be updated in
the STATUS register to a logic ‘1’. The device will power‑up in the Write Disable state (WEL = 0). The WP pin must
be held high during a WREN instruction.
© 2019 Microchip Technology Inc.
DS20006251A-page 18
AT25010B/AT25020B/AT25040B
Device Commands and Addressing
Figure 6-2. WREN Timing
CS
0
1
2
3
4
5
6
7
SCK
WREN Opcode (06h)
SI
0
0
0
0
0
1
1
0
MSB
High-Impedance
SO
6.3.2
Write Disable Instruction (WRDI)
To protect the device against inadvertent writes, the Write Disable (WRDI) instruction (opcode 04h) disables all
programming modes by setting the WEL bit to a logic ‘0’. The WRDI instruction is independent of the status of the WP
pin.
Figure 6-3. WRDI Timing
CS
0
1
2
3
4
5
6
7
SCK
WRDI Opcode (04h)
SI
0
0
0
0
0
1
0
0
MSB
SO
6.4
High-Impedance
Write STATUS Register (WRSR)
The Write STATUS Register (WRSR) instruction enables the SPI Master to change selected bits of the STATUS
register. Before a WRSR instruction can be initiated, a WREN instruction must be executed to set the WEL bit to
logic ‘1’. Upon completion of a WREN instruction, a WRSR instruction can be executed.
Note: The WRSR instruction has no effect on bit 7, bit 6, bit 5, bit 4, bit 1 and bit 0 of the STATUS register. Only bit 3
and bit 2 can be changed via the WRSR instruction. These modifiable bits are the Block Protect (BP1, BP0) bits.
These bits are nonvolatile bits that have the same properties and functions as regular EEPROM cells. Their values
are retained while power is removed from the device.
The AT25010B/AT25020B/AT25040B will not respond to commands other than a RDSR after a WRSR instruction until
the self‑timed internal write cycle has completed. When the write cycle is completed, the WEL bit in the STATUS
register is reset to logic ‘0’.
© 2019 Microchip Technology Inc.
DS20006251A-page 19
AT25010B/AT25020B/AT25040B
Device Commands and Addressing
Figure 6-4. WRSR Waveform
CS
tWC(1)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
X
X
SCK
STATUS Register Data In
WRSR Opcode (01h)
SI
0
0
0
0
0
0
0
1
X
MSB
X
X
X
D3
D2
MSB
High-Impedance
SO
Note:
1. This instruction initiates a self-timed internal write cycle (tWC) on the rising edge of CS after a valid sequence.
6.4.1
Block Write-Protect Function
The WRSR instruction allows the user to select one of four possible combinations as to how the memory array will be
inhibited from writing through changing the Block Write-Protect bits (BP1, BP0). The four levels of array protection
are:
• None of the memory array is protected.
• Upper quarter (¼) address range is write-protected meaning the highest order address bits are read-only.
• Upper half (½) address range is write-protected meaning the highest order address bits are read-only.
• All of the memory array is write-protected meaning all address bits are read-only.
The Block Write Protection levels and corresponding STATUS register control bits are shown in Table 6-4.
Table 6-4. Block Write-Protect Bits
Level
STATUS Register Bits
Write-Protected/Read‑Only Address Range
BP1
BP0
AT25010B
AT25020B
AT25040B
0
0
0
None
None
None
1(1/4)
0
1
60h-7Fh
C0h-FFh
180h-1FFh
2(1/2)
1
0
40h-7Fh
80h-FFh
100h-1FFh
3(All)
1
1
00h-7Fh
00h-FFh
000h-1FFh
© 2019 Microchip Technology Inc.
DS20006251A-page 20
AT25010B/AT25020B/AT25040B
Read Sequence
7.
Read Sequence
Reading the AT25010B/AT25020B/AT25040B via the SO pin requires the following sequence. After the CS line is
pulled low to select a device, the READ (03h) instruction (including A8 for the AT25040B) is transmitted via the SI line
followed by the 8‑bit address to be read (A7 - A0). Refer to Table 7-1 for the address bits for AT25010B/AT25020B/
AT25040B.
Table 7-1. AT25010B/AT25020B/AT25040B Address Bits
Address
AT25010B
AT25020B
AT25040B
AN
A6-A0
A7-A0
A8-A0
Don’t Care Bits
A7
None
None
Upon completion of the 8‑bit address, any data on the SI line will be ignored. The data (D7‑D0) at the specified
address is then shifted out onto the SO line. If only one byte is to be read, the CS line should be driven high after the
data comes out. The read sequence can be continued since the byte address is automatically incremented and data
will continue to be shifted out. When the highest‑order address bit is reached, the address counter will rollover to the
lowest‑order address bit allowing the entire memory to be read in one continuous read cycle regardless of the starting
address.
Figure 7-1. Read Waveform
CS
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
SCK
READ Opcode (03h)
SI
0
0
0
0
0 A(1) 1
MSB
Address Bits A7-A0
1
A
A
A
A
A
A
A
A
MSB
Data Byte 1
SO
High-Impedance
D
MSB
D
D
D
D
D
D
D
D
D
MSB
Note:
1. “A” represents the MSb address bit (A8) for the AT25040B and a “don’t care” bit for the AT25010B and
AT25020B.
© 2019 Microchip Technology Inc.
DS20006251A-page 21
AT25010B/AT25020B/AT25040B
Write Sequence
8.
Write Sequence
In order to program the AT25010B/AT25020B/AT25040B, two separate instructions must be executed. First, the
device must be write enabled via the Write Enable (WREN) instruction. Then, one of the two possible write sequences
described in this section may be executed.
Note: If the WP pin is brought low or the device is not Write Enabled (WREN), the device will ignore the WRITE
instruction and will return to the standby state when CS is brought high. A new CS assertion is required to re-initiate
communication.
The address of the memory location(s) to be programmed must be outside the protected address field location
selected by the block write protection level. During an internal write cycle, all commands will be ignored except the
RDSR instruction. Refer to Table 8-1 for the address bits for AT25010B/AT25020B/AT25040B.
Table 8-1. AT25010B/AT25020B/AT25040B Address Bits
8.1
Address
AT25010B
AT25020B
AT25040B
AN
A6-A0
A7-A0
A8-A0
Don’t Care Bits
A7
None
None
Byte Write
A byte write requires the following sequence and is depicted in Figure 8-1. After the CS line is pulled low to select the
device, the WRITE (02h) instruction (including A8 for the AT25040B) is transmitted via the SI line followed by the 8‑bit
address and the data (D7‑D0) to be programmed. Programming will start after the CS pin is brought high. The
low‑to‑high transition of the CS pin must occur during the SCK low time (Mode 0) and SCK high time (Mode 3)
immediately after clocking in the D0 (LSB) data bit. The AT25010B/AT25020B/AT25040B is automatically returned to
the Write Disable state (STATUS register bit WEL = 0) at the completion of a write cycle.
Figure 8-1. Byte Write
CS
SCK
tWC(1)
0
1
2
4
3
5
6
7
8
WRITE Opcode (02h)
SI
0
0
0
0
0 A(2) 1
MSB
SO
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23
Address Bits A7-A0
0
A
MSB
A
A
A
A
A
A
Data In
A D7 D6 D5 D4 D3 D2 D1 D0
MSB
High-Impedance
Note:
1. This instruction initiates a self-timed internal write cycle (tWC) on the rising edge of CS after a valid sequence.
2. “A” represents the MSb address bit (A8) for the AT25040B and a “don’t care” bit for the AT25010B and
AT25020B.
8.2
Page Write
A page write sequence allows up to 8 bytes to be written in the same write cycle, provided that all bytes are in the
same row of the memory array. Partial page writes of less than 8 bytes are allowed. After each byte of data is
received, the three lowest order address bits are internally incremented following the receipt of each data byte. The
higher order address bits are not incremented and retain the memory array page location. If more bytes of data are
transmitted than will fit to the end of that memory row, the address counter will rollover to the beginning of the same
row. Nevertheless, creating a rollover event should be avoided as previously loaded data in the page could become
© 2019 Microchip Technology Inc.
DS20006251A-page 22
AT25010B/AT25020B/AT25040B
Write Sequence
unintentionally altered. The AT25010B/AT25020B/AT25040B is automatically returned to the Write Disable state
(WEL = 0) at the completion of a write cycle.
Figure 8-2. Page Write
CS
tWC(1)
0
SCK
1
2
4
3
5
6
7
8
WRITE Opcode (02h)
SI
0
0
0
0
0 A(2) 1
MSB
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23
Address Bits A7-A0
0
A
MSB
A
A
A
A
A
A
Data In Byte 1
A
D
D
D
D
D
D
Data In Byte 8
D
D
MSB
D
D
D
D
D
D
D
D
MSB
High-Impedance
SO
Note:
1. This instruction initiates a self‑timed internal write cycle (tWC) on the rising edge of CS after a valid sequence.
2. “A” represents the MSb address bit (A8) for the AT25040B and a “don’t care” bit for the AT25010B and
AT25020B.
8.3
Polling Routine
A polling routine can be implemented to optimize time‑sensitive applications that would not prefer to wait the fixed
maximum write cycle time (tWC). This method allows the application to know immediately when the write cycle has
completed to start a subsequent operation.
Once the internally-timed write cycle has started, a polling routine can be initiated. This involves repeatedly sending
Read STATUS Register (RDSR) instruction to determine if the device has completed its self-timed internal write cycle.
If the RDY/BSY bit (bit 0 of STATUS register) = 1, the write cycle is still in progress. If bit 0 = 0, the write cycle has
ended. If the RDY/BSY bit = 1, repeated RDSR commands can be executed until the RDY/BSY bit = 0, signaling that
the device is ready to execute a new instruction. Only the Read STATUS Register (RDSR) instruction is enabled
during the write cycle.
Figure 8-3. Polling Flowchart
Send Valid
Write
Protocol
Deassert
CS to VCC to
Initiate a
Write Cycle
Send RDSR
Instruction
to the Device
Does
RDY/BSY
= 0?
YES
Continue to
Next Operation
NO
© 2019 Microchip Technology Inc.
DS20006251A-page 23
AT25010B/AT25020B/AT25040B
Packaging Information
9.
Packaging Information
9.1
Package Marking Information
AT25010B, AT25020B and AT25040B: Package Marking Information
8-lead TSSOP
8-lead SOIC
ATMLHYWW
###% CO
YYWWNNN
ATHYWW
###%CO
YYWWNNN
8-pad UDFN
8-ball VFBGA
2.0 x 3.0 mm Body
1.5 x 2.0 mm Body
###
H%
NNN
Note 1:
###U
WNNN
designates pin 1
Note 2: Package drawings are not to scale
Catalog Number Truncation
AT25010B
Truncation Code ###: 51B
AT25020B
Truncation Code ###: 52B
AT25040B
Truncation Code ###: 54B
Date Codes
YY = Year
16: 2016
17: 2017
18: 2018
19: 2019
Voltages
20: 2020
21: 2021
22: 2022
23: 2023
Y = Year
6: 2016
7: 2017
8: 2018
9: 2019
0: 2020
1: 2021
2: 2022
3: 2023
WW = Work Week of Assembly
02: Week 2
04: Week 4
...
52: Week 52
% = Minimum Voltage
L: 1.8V min
Country of Origin
Device Grade
Atmel Truncation
CO = Country of Origin
H or U: Industrial Grade
AT:
ATM:
ATML:
Atmel
Atmel
Atmel
Lot Number or Trace Code
NNN = Alphanumeric Trace Code (2 Characters for Small Packages)
© 2019 Microchip Technology Inc.
DS20006251A-page 24
AT25010B/AT25020B/AT25040B
Packaging Information
8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm (.150 In.) Body [SOIC]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2X
0.10 C A–B
D
A
D
NOTE 5
N
E
2
E1
2
E1
E
NOTE 1
2
1
e
B
NOTE 5
NX b
0.25
C A–B D
TOP VIEW
0.10 C
C
A A2
SEATING
PLANE
8X
A1
SIDE VIEW
0.10 C
h
R0.13
h
R0.13
H
SEE VIEW C
VIEW A–A
0.23
L
(L1)
VIEW C
Microchip Technology Drawing No. C04-057-SN Rev E Sheet 1 of 2
© 2017 Microchip Technology Inc.
© 2019 Microchip Technology Inc.
DS20006251A-page 25
AT25010B/AT25020B/AT25040B
Packaging Information
8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm (.150 In.) Body [SOIC]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Units
Dimension Limits
Number of Pins
N
e
Pitch
Overall Height
A
Molded Package Thickness
A2
§
Standoff
A1
Overall Width
E
Molded Package Width
E1
Overall Length
D
Chamfer (Optional)
h
Foot Length
L
L1
Footprint
Foot Angle
c
Lead Thickness
b
Lead Width
Mold Draft Angle Top
Mold Draft Angle Bottom
MIN
1.25
0.10
0.25
0.40
0°
0.17
0.31
5°
5°
MILLIMETERS
NOM
8
1.27 BSC
6.00 BSC
3.90 BSC
4.90 BSC
1.04 REF
-
MAX
1.75
0.25
0.50
1.27
8°
0.25
0.51
15°
15°
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. § Significant Characteristic
3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or
protrusions shall not exceed 0.15mm per side.
4. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
5. Datums A & B to be determined at Datum H.
Microchip Technology Drawing No. C04-057-SN Rev E Sheet 2 of 2
© 2017 Microchip Technology Inc.
© 2019 Microchip Technology Inc.
DS20006251A-page 26
AT25010B/AT25020B/AT25040B
Packaging Information
8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm Body [SOIC]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
SILK SCREEN
C
Y1
X1
E
RECOMMENDED LAND PATTERN
Units
Dimension Limits
E
Contact Pitch
Contact Pad Spacing
C
Contact Pad Width (X8)
X1
Contact Pad Length (X8)
Y1
MIN
MILLIMETERS
NOM
1.27 BSC
5.40
MAX
0.60
1.55
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Microchip Technology Drawing C04-2057-SN Rev E
© 2017 Microchip Technology Inc.
© 2019 Microchip Technology Inc.
DS20006251A-page 27
M
AT25010B/AT25020B/AT25040B
Packaging Diagrams and Parameters
Packaging Information
8-Lead Plastic Thin Shrink Small Outline (ST) – 4.4 mm Body [TSSOP]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
D
N
E
E1
NOTE 1
1
2
b
e
c
A
φ
A2
A1
L
L1
Units
Dimension Limits
Number of Pins
MILLIMETERS
MIN
N
NOM
MAX
8
Pitch
e
Overall Height
A
–
0.65 BSC
–
Molded Package Thickness
A2
0.80
1.00
1.05
Standoff
A1
0.05
–
0.15
1.20
Overall Width
E
Molded Package Width
E1
4.30
6.40 BSC
4.40
Molded Package Length
D
2.90
3.00
3.10
Foot Length
L
0.45
0.60
0.75
Footprint
L1
4.50
1.00 REF
Foot Angle
φ
0°
–
8°
Lead Thickness
c
0.09
–
0.20
Lead Width
b
0.19
–
0.30
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side.
3. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-086B
© 2007 Microchip Technology Inc.
© 2019 Microchip Technology Inc.
DS00049AR-page 117
DS20006251A-page 28
M
Note:
AT25010B/AT25020B/AT25040B
Packaging Diagrams and Parameters
Packaging Information
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS00049BC-page 96
© 2019 Microchip Technology Inc.
2009 Microchip Technology Inc.
DS20006251A-page 29
AT25010B/AT25020B/AT25040B
Packaging Information
8-Lead Ultra Thin Plastic Dual Flat, No Lead Package (Q4B) - 2x3 mm Body [UDFN]
Atmel Legacy YNZ Package
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
D
A
B
N
(DATUM A)
E
(DATUM B)
NOTE 1
2X
0.10 C
1
2
2X
0.10 C
TOP VIEW
A1
0.10 C
C
SEATING
PLANE
A
8X
(A3)
SIDE VIEW
0.10
0.08 C
C A B
D2
e
2
1 2
0.10
E2
C A B
K
N
L
8X b
e
0.10
0.05
C A B
C
BOTTOM VIEW
Microchip Technology Drawing C04-21355-Q4B Rev A Sheet 1 of 2
© 2017 Microchip Technology Inc.
© 2019 Microchip Technology Inc.
DS20006251A-page 30
AT25010B/AT25020B/AT25040B
Packaging Information
8-Lead Ultra Thin Plastic Dual Flat, No Lead Package (Q4B) - 2x3 mm Body [UDFN]
Atmel Legacy YNZ Package
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Notes:
Units
Dimension Limits
Number of Terminals
N
e
Pitch
A
Overall Height
Standoff
A1
Terminal Thickness
A3
Overall Length
D
Exposed Pad Length
D2
Overall Width
E
Exposed Pad Width
E2
b
Terminal Width
Terminal Length
L
Terminal-to-Exposed-Pad
K
MIN
0.50
0.00
1.40
1.20
0.18
0.35
0.20
MILLIMETERS
NOM
8
0.50 BSC
0.55
0.02
0.152 REF
2.00 BSC
1.50
3.00 BSC
1.30
0.25
0.40
-
MAX
0.60
0.05
1.60
1.40
0.30
0.45
-
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Package is saw singulated
3. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-21355-Q4B Rev A Sheet 2 of 2
© 2017 Microchip Technology Inc.
© 2019 Microchip Technology Inc.
DS20006251A-page 31
AT25010B/AT25020B/AT25040B
Packaging Information
8-Lead Ultra Thin Plastic Dual Flat, No Lead Package (Q4B) - 2x3 mm Body [UDFN]
Atmel Legacy YNZ Package
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
X2
EV
G2
8
ØV
C
Y2
G1
Y1
1
2
SILK SCREEN
X1
E
RECOMMENDED LAND PATTERN
Units
Dimension Limits
E
Contact Pitch
Optional Center Pad Width
X2
Optional Center Pad Length
Y2
Contact Pad Spacing
C
Contact Pad Width (X8)
X1
Contact Pad Length (X8)
Y1
Contact Pad to Center Pad (X8)
G1
Contact Pad to Contact Pad (X6)
G2
Thermal Via Diameter
V
Thermal Via Pitch
EV
MIN
MILLIMETERS
NOM
0.50 BSC
MAX
1.60
1.40
2.90
0.30
0.85
0.20
0.33
0.30
1.00
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
2. For best soldering results, thermal vias, if used, should be filled or tented to avoid solder loss during
reflow process
Microchip Technology Drawing C04-21355-Q4B Rev A
© 2017 Microchip Technology Inc.
© 2019 Microchip Technology Inc.
DS20006251A-page 32
AT25010B/AT25020B/AT25040B
Packaging Information
0.10
d
(4X)
0.08 C
d
f
E
0.10 C
A
C
D
2. b
j
j
PIN 1 BALL PAD CORNER
n 0.15 m C A B
n 0.08m C
A1
B
A2
TOP VIEW
PIN 1 BALL PAD CORNER
3
2
1
A
SIDE VIEW
4
d
(d1)
8
7
6
5
COMMON DIMENSIONS
(Unit of Measure - mm)
e
(e1)
BOTTOM VIEW
8 SOLDER BALLS
Notes:
1. This drawing is for general information only.
2. Dimension ‘b’ is measured at maximum solder ball diameter.
3. Solder ball composition shall be 95.5Sn-4.0Ag-.5Cu.
SYMBOL
MIN
NOM
MAX
A
0.73
0.79
0.85
A1
0.09
0.14
0.19
A2
0.40
0.45
0.50
b
0.20
0.25
0.30
D
NOTE
2
1.50 BSC
E
2.0 BSC
e
0.50 BSC
e1
0.25 REF
d
1.00 BSC
d1
0.25 REF
7/1/14
TITLE
GPC
DRAWING NO.
8U3-1, 8-ball, 1.50mm x 2.00mm body, 0.50mm pitch,
Very Thin, Fine-Pitch Ball Grid Array Package (VFBGA)
GXU
8U3-1
REV.
G
Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://
www.microchip.com/packaging.
© 2019 Microchip Technology Inc.
DS20006251A-page 33
AT25010B/AT25020B/AT25040B
Revision History
10.
Revision History
Revision A (October 2019)
Updated to Microchip template. Microchip DS20006251 replaces Atmel document 8707. Updated Part Marking
Information. Added ESD rating. Removed the 8‑pad XDFN detail and ordering code. Removed lead finish
designation. Added POR recommendations section. Updated trace code format in package markings. Updated
section content throughout for clarification. Updated the 8U3‑1 VFBGA package drawing. Updated the SOIC, TSSOP
and UDFN package drawings to the Microchip equivalents.
Atmel Document 8707 Revision F (January 2015)
Added the UDFN Expanded Quantity Option. Updated the 8MA2 package outline drawing and the ordering
information section.
Atmel Document 8707 Revision E (May 2014)
Updated part markings, package drawings, package 8A2 to 8X, template, logos, and disclaimer page. No change to
functional specification.
Atmel Document 8707 Revision D (April 2013)
Corrected WRSR waveform figure 4-5, bit 7 is not writable. Updated Atmel logos and disclaimer page.
Atmel Document 8707 Revision C (June 2011)
Corrected AT25040B-SSHL marking detail. Replaced 8A2 package drawing with version E.
Atmel Document 8707 Revision B (October 2010)
Removed Preliminary.
Atmel Document 8707 Revision B (March 2010)
Replaced 8Y6 with 8MA2.
Atmel Document 8707 Revision A (February 2010)
Initial document release.
© 2019 Microchip Technology Inc.
DS20006251A-page 34
AT25010B/AT25020B/AT25040B
The Microchip Website
Microchip provides online support via our website at http://www.microchip.com/. This website is used to make files
and information easily available to customers. Some of the content available includes:
•
•
•
Product Support – Data sheets and errata, application notes and sample programs, design resources, user’s
guides and hardware support documents, latest software releases and archived software
General Technical Support – Frequently Asked Questions (FAQs), technical support requests, online
discussion groups, Microchip design partner program member listing
Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of
seminars and events, listings of Microchip sales offices, distributors and factory representatives
Product Change Notification Service
Microchip’s product change notification service helps keep customers current on Microchip products. Subscribers will
receive email notification whenever there are changes, updates, revisions or errata related to a specified product
family or development tool of interest.
To register, go to http://www.microchip.com/pcn and follow the registration instructions.
Customer Support
Users of Microchip products can receive assistance through several channels:
•
•
•
•
Distributor or Representative
Local Sales Office
Embedded Solutions Engineer (ESE)
Technical Support
Customers should contact their distributor, representative or ESE for support. Local sales offices are also available to
help customers. A listing of sales offices and locations is included in this document.
Technical support is available through the website at: http://www.microchip.com/support
© 2019 Microchip Technology Inc.
DS20006251A-page 35
AT25010B/AT25020B/AT25040B
Product Identification System
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
AT 2 5 0 1 0 B- SS H L - B
Shipping Carrier Option
B = Bulk (Tubes)
T = Tape and Reel, Standard Quantity Option
E = Tape and Reel, Extended Quantity Option
Product Family
25 = Standard SPI
Serial EEPROM
Operating Voltage
Device Density
Device Grade or
Wafer/Die Thickness
L = 1.8V to 5.5V
010 = 1-Kilobit
020 = 2-Kilobit
040 = 4-Kilobit
H or U = Industrial Temperature Range
(-40°C to +85°C)
11
= 11mil Wafer Thickness
Device Revision
Package Option
SS
X
MA
C
WWU
WDT
= SOIC
= TSSOP
= 2.0mm x 3.0mm UDFN
= VFBGA
= Wafer Unsawn
= Die in Tape and Reel
Note: Refer to automotive data sheet for automotive grade ordering information.
Examples:
Device
Package
Package
Drawing
Code
Package
Option
Shipping Carrier
Option
Device Grade
AT25040B‑SSHL‑B
SOIC
SN
SS
Bulk (Tubes)
AT25010B‑SSHL‑T
SOIC
SN
SS
Tape and Reel
Industrial
Temperature
(-40°C to 85°C)
AT25020B‑SSHL‑T
SOIC
SN
SS
Tape and Reel
AT25020B‑XHL‑B
TSSOP
ST
X
Bulk (Tubes)
AT25010B‑XHL‑T
TSSOP
ST
X
Tape and Reel
AT25040B‑MAHL‑E
UDFN
Q4B
MA
Tape and Reel
AT25020B‑MAHL‑T
UDFN
Q4B
MA
Tape and Reel
AT25010B‑MAHL‑E
UDFN
Q4B
MA
Tape and Reel
VFBGA
8U3-1
C
Tape and Reel
AT25040B‑CUL‑T
Microchip Devices Code Protection Feature
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
© 2019 Microchip Technology Inc.
DS20006251A-page 36
AT25010B/AT25020B/AT25040B
•
•
•
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today,
when used in the intended manner and under normal conditions.
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these
methods, to our knowledge, require using the Microchip products in a manner outside the operating
specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of
intellectual property.
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code
protection does not mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection
features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital
Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you
may have a right to sue for relief under that Act.
Legal Notice
Information contained in this publication regarding device applications and the like is provided only for your
convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with
your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER
EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend,
indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such
use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights unless
otherwise stated.
Trademarks
The Microchip name and logo, the Microchip logo, Adaptec, AnyRate, AVR, AVR logo, AVR Freaks, BesTime,
BitCloud, chipKIT, chipKIT logo, CryptoMemory, CryptoRF, dsPIC, FlashFlex, flexPWR, HELDO, IGLOO, JukeBlox,
KeeLoq, Kleer, LANCheck, LinkMD, maXStylus, maXTouch, MediaLB, megaAVR, Microsemi, Microsemi logo, MOST,
MOST logo, MPLAB, OptoLyzer, PackeTime, PIC, picoPower, PICSTART, PIC32 logo, PolarFire, Prochip Designer,
QTouch, SAM-BA, SenGenuity, SpyNIC, SST, SST Logo, SuperFlash, Symmetricom, SyncServer, Tachyon,
TempTrackr, TimeSource, tinyAVR, UNI/O, Vectron, and XMEGA are registered trademarks of Microchip Technology
Incorporated in the U.S.A. and other countries.
APT, ClockWorks, The Embedded Control Solutions Company, EtherSynch, FlashTec, Hyper Speed Control,
HyperLight Load, IntelliMOS, Libero, motorBench, mTouch, Powermite 3, Precision Edge, ProASIC, ProASIC Plus,
ProASIC Plus logo, Quiet-Wire, SmartFusion, SyncWorld, Temux, TimeCesium, TimeHub, TimePictra, TimeProvider,
Vite, WinPath, and ZL are registered trademarks of Microchip Technology Incorporated in the U.S.A.
Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut, BlueSky, BodyCom,
CodeGuard, CryptoAuthentication, CryptoAutomotive, CryptoCompanion, CryptoController, dsPICDEM,
dsPICDEM.net, Dynamic Average Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial Programming, ICSP,
INICnet, Inter-Chip Connectivity, JitterBlocker, KleerNet, KleerNet logo, memBrain, Mindi, MiWi, MPASM, MPF,
MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM,
PICDEM.net, PICkit, PICtail, PowerSmart, PureSilicon, QMatrix, REAL ICE, Ripple Blocker, SAM-ICE, Serial Quad
I/O, SMART-I.S., SQI, SuperSwitcher, SuperSwitcher II, Total Endurance, TSHARC, USBCheck, VariSense,
ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A.
and other countries.
SQTP is a service mark of Microchip Technology Incorporated in the U.S.A.
The Adaptec logo, Frequency on Demand, Silicon Storage Technology, and Symmcom are registered trademarks of
Microchip Technology Inc. in other countries.
GestIC is a registered trademark of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip
Technology Inc., in other countries.
© 2019 Microchip Technology Inc.
DS20006251A-page 37
AT25010B/AT25020B/AT25040B
All other trademarks mentioned herein are property of their respective companies.
©
2019, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved.
ISBN: 978-1-5224-5155-6
AMBA, Arm, Arm7, Arm7TDMI, Arm9, Arm11, Artisan, big.LITTLE, Cordio, CoreLink, CoreSight, Cortex, DesignStart,
DynamIQ, Jazelle, Keil, Mali, Mbed, Mbed Enabled, NEON, POP, RealView, SecurCore, Socrates, Thumb,
TrustZone, ULINK, ULINK2, ULINK-ME, ULINK-PLUS, ULINKpro, µVision, Versatile are trademarks or registered
trademarks of Arm Limited (or its subsidiaries) in the US and/or elsewhere.
Quality Management System
For information regarding Microchip’s Quality Management Systems, please visit http://www.microchip.com/quality.
© 2019 Microchip Technology Inc.
DS20006251A-page 38
Worldwide Sales and Service
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© 2019 Microchip Technology Inc.
DS20006251A-page 39
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