AT25080A (1),AT25160A (2)
AT25320A (3),AT25640A (4)
SPI Automotive Temperature Serial EEPROMs
NOT RECOMMENDED
FOR NEW DESIGNS
8K (1024 x 8), 16K (2048 x 8), 32K (4096 x 8), 64K (8192 x 8)
DATASHEET
1. AT25080A Replaced by
AT25080B Automotive
Features
2. AT25160A Replaced by
AT25160B Automotive
3. AT25320A Replaced by
AT25320B Automotive
4. AT25640A Replaced by
AT25640B Automotive
Serial Peripheral Interface (SPI) Compatible
Supports SPI Modes 0 (0,0) and 3 (1,1)
̶
Data Sheet Describes Mode 0 Operation
Medium-voltage and Standard-voltage Operation
̶
2.7 (VCC = 2.7V to 5.5V)
Extended Temperature Range: –40C to 125C
5MHz Clock Rate
32-byte Page Mode
Block Write Protection
̶
Protect 1/4, 1/2, or Entire Array
Write Protect (WP) Pin and Write Disable Instructions for Both Hardware and
Software Data Protection
Self-timed Write Cycle (2ms at 5.0V VCC Typical)
High Reliability
̶
̶
Endurance: 1,000,000 Write Cycles
Data Retention: 100 Years
8-lead JEDEC SOIC and TSSOP Packages
Description
The AT25080A/160A/320A/640A provides 8,192/16,384/32,768/65,536 bits of
Serial Electrically-Erasable Programmable Read-only Memory (EEPROM)
organized as 1,024/2,048/4,096/8,192 words of 8 bits each. The device is
optimized for use in many automotive applications where low-power and
low-voltage operation are essential. The AT25080A/160A/320A/640A is available
in space-saving 8-lead JEDEC SOIC and TSSOP packages.
The AT25080A/160A/320A/640A is enabled through the Chip Select pin (CS) and
accessed via a 3-Wire interface consisting of Serial Data Input (SI), Serial Data
Output (SO), and Serial Clock (SCK). All programming cycles are completely
self-timed, and no separate erase cycle is required before write.
Block write protection is enabled by programming the status register with one of
four blocks of write protection. Separate program enable and program disable
instructions are provided for additional data protection. Hardware data protection
is provided via the WP pin to protect against inadvertent write attempts to the
status register. The HOLD pin may be used to suspend any serial communication
without resetting the serial sequence.
Atmel-5082E-SEEPROM-AT25080A-160A-320A-640A-Auto-Datasheet_102014
1.
Pin Configurations and Pinouts
Table 1-1.
Pin Name
2.
Pin Configurations
Function
CS
Chip Select
SCK
Serial Data Clock
SI
Serial Data Input
SO
Serial Data Output
GND
Ground
VCC
Power Supply
WP
Write Protect
HOLD
Suspends Serial Input
8-lead TSSOP
(Top View)
(Top View)
CS
1
8
VCC
SO
2
7
HOLD
WP
3
6
SCK
GND
4
5
SI
CS
SO
WP
GND
1
2
3
4
8
7
6
5
VCC
HOLD
SCK
SI
Absolute Maximum Ratings*
Operating Temperature 40C to +125C
Storage Temperature 65C to +150C
Voltage on Any Pin
with Respect to Ground 1.0V to +7.0V
Maximum Operating Voltage . . . . . . . . . . . . . . . 6.25V
DC Output Current . . . . . . . . . . . . . . . . . . . . . . .5.0mA
2
8-lead SOIC
*Notice: Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent damage
to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
AT25080A/160A/320A/640A Automotive [DATASHEET]
Atmel-5082E-SEEPROM-AT25080A-160A-320A-640A-Auto-Datasheet_102014
3.
Block Diagram
Figure 3-1.
Block Diagram
VCC
GND
Memory Array
Status
Register
1,024/2,048/
4,096/8,192
x 8
Address
Decoder
Data
Register
Output
Buffer
SI
CS
WP
SCK
Mode Decode
Logic
Clock
Generator
SO
HOLD
AT25080A/160A/320A/640A Automotive [DATASHEET]
Atmel-5082E-SEEPROM-AT25080A-160A-320A-640A-Auto-Datasheet_102014
3
4.
Memory Organization
4.1
Pin Capacitance
Table 4-1.
Pin Capacitance(1)
Applicable over recommended operating range from TA = 25C, f = 1.0MHz, VCC = +5.0V (unless otherwise noted).
Symbol
Test Conditions
COUT
CIN
Note:
4.2
1.
Max
Units
Conditions
Output Capacitance (SO)
8
pF
VOUT = 0V
Input Capacitance (CS, SCK, SI, WP, HOLD)
6
pF
VIN = 0V
This parameter is characterized and is not 100% tested.
DC Characteristics
Table 4-2.
DC Characteristics
Applicable over recommended operating range from: TA = 40C to +125C, VCC = +2.7V to +5.5V.
Symbol
Parameter
VCC1
Supply Voltage
ICC1
Supply Current
ICC2
Max
Units
5.5
V
VCC = 5.0V at 5MHz, SO = Open, Read
6.0
mA
Supply Current
VCC = 5.0V at 1MHz
3.0
mA
ICC3
Supply Current
VCC = 5.0V at 5MHz,
SO = Open, Read, Write
7.0
mA
ISB1
Standby Current
VCC = 2.7V, CS = VCC
0.2
10.0(1)
μA
ISB2
Standby Current
VCC = 5.0V, CS = VCC
2.0
13.0(1)
μA
IIL
Input Leakage
VIN = 0V to VCC
3.0
IOL
Output Leakage
VIN = 0V to VCC
3.0
3.0
μA
VIL(2)
Input Low-voltage
0.6
VCC x 0.3
V
VIH(2)
Input High-voltage
VCC x 0.7
VCC + 0.5
V
VOL1
Output Low-voltage
2.7V VCC 5.5V
IOL = 3.0mA
0.4
V
VOH1
Output High-voltage
2.7V VCC 5.5V
IOH = 1.6mA
Notes:
4
1.
2.
Test Condition
Min
Typ
2.7
Worst case measured at 125C.
VIL min and VIH max are reference only and are not tested.
AT25080A/160A/320A/640A Automotive [DATASHEET]
Atmel-5082E-SEEPROM-AT25080A-160A-320A-640A-Auto-Datasheet_102014
VCC 0.8
μA
V
4.3
AC Characteristics
Table 4-3.
AC Characteristics
Applicable over recommended operating range from TA = 40C to +125C, VCC = As Specified, CL = 1 TTL Gate and 100pF
(unless otherwise noted).
Symbol
Parameter
Voltage
Min
Max
Units
fSCK
SCK Clock Frequency
2.7 – 5.5
0
5
MHz
tRI
Input Rise Time
2.7 – 5.5
2
μs
tFI
Input Fall Time
2.7 – 5.5
2
μs
tWH
SCK High Time
2.7 – 5.5
40
ns
tWL
SCK Low Time
2.7 – 5.5
40
ns
tCS
CS High Time
2.7 – 5.5
80
ns
tCSS
CS Setup Time
2.7 – 5.5
80
ns
tCSH
CS Hold Time
2.7 – 5.5
80
ns
tSU
Data In Setup Time
2.7 – 5.5
5
ns
tH
Data In Hold Time
2.7 – 5.5
20
ns
tHDS
Hold Setup Time
2.7 – 5.5
40
ns
tHDN
Hold Time
2.7 – 5.5
40
ns
tV
Output Valid
2.7 – 5.5
0
tHO
Output Hold Time
2.7 – 5.5
0
tLZ
Hold to Output Low Z
2.7 – 5.5
0
tHZ
Hold to Output High Z
tDIS
40
ns
ns
40
ns
2.7 – 5.5
80
ns
Output Disable Time
2.7 – 5.5
80
ns
tWC
Write Cycle Time
2.7 – 5.5
5
ms
Endurance(1)
5.0V, 25°C, Page Mode
Note:
1.
1,000,000
Write Cycles
This parameter is characterized and is not 100% tested.
AT25080A/160A/320A/640A Automotive [DATASHEET]
Atmel-5082E-SEEPROM-AT25080A-160A-320A-640A-Auto-Datasheet_102014
5
5.
Serial Interface Description
Master: The device which generates the serial clock.
Slave: Because the Serial Clock pin (SCK) is always an input, the AT25080A/160A/320A/640A always operates
as a slave.
Transmitter/receiver: The AT25080A/160A/320A/640A has separate pins designated for data transmission
(SO) and reception (SI).
MSB: The Most Significant Bit (MSB) is the first bit transmitted and received.
Serial Opcode: After the device is selected with CS going low, the first byte will be received. This byte contains
the opcode that defines the operations to be performed.
Invalid Opcode: If an invalid opcode is received, no data will be shifted into the AT25080A/160A/320A/640A,
and the Serial Output pin (SO) will remain in a high-impedance state until the falling edge of CS is detected
again. This will reinitialize the serial communication.
Chip Select: The AT25080A/160A/320A/640A is selected when the CS pin is low. When the device is not
selected, data will not be accepted via the SI pin, and the Serial Output pin (SO) will remain in a high-impedance
state.
Hold: The HOLD pin is used in conjunction with the CS pin to select the AT25080A/160A/320A/640A. When the
device is selected and a serial sequence is underway, HOLD can be used to pause the serial communication
with the master device without resetting the serial sequence. To pause, the HOLD pin must be brought low while
the SCK pin is low. To resume serial communication, the HOLD pin is brought high while the SCK pin is low
(SCK may still toggle during HOLD). Inputs to the SI pin will be ignored while the SO pin is in the
high-impedance state.
Write Protect: The Write Protect pin (WP) will allow normal Read/Write operations when held high. When the
WP pin is brought low and WPEN bit is one, all Write operations to the status register are inhibited. WP going
low while CS is still low will interrupt a write to the status register. If the internal write cycle has already been
initiated, WP going low will have no effect on any Write operation to the status register. The WP pin function is
blocked when the WPEN bit in the status register is zero. This will allow the user to install the
AT25080A/160A/320A/640A in a system with the WP pin tied to ground and still be able to write to the status
register. All WP pin functions are enabled when the WPEN bit is set to one.
6
AT25080A/160A/320A/640A Automotive [DATASHEET]
Atmel-5082E-SEEPROM-AT25080A-160A-320A-640A-Auto-Datasheet_102014
Figure 5-1.
SPI Serial Interface
Master:
Microcontroller
Data Out (MOSI)
Data In (MISO)
Serial Clock (SPI CK)
SS0
SS1
SS2
SS3
Slave:
AT25080A/160A/320A
SI
SO
SCK
CS
SI
SO
SCK
CS
SI
SO
SCK
CS
SI
SO
SCK
CS
AT25080A/160A/320A/640A Automotive [DATASHEET]
Atmel-5082E-SEEPROM-AT25080A-160A-320A-640A-Auto-Datasheet_102014
7
6.
Functional Description
The AT25080A/160A/320A/640A is designed to interface directly with the synchronous Serial Peripheral
Interface (SPI) of the 6805 and 68HC11 series of microcontrollers.
The AT25080A/160A/320A/640A utilizes an 8-bit instruction register. The list of instructions and their operation
codes are contained in the below table. All instructions, addresses, and data are transferred with the MSB first
and start with a high-to-low CS transition.
Table 6-1.
Instruction Set for the AT25080A/160A/320A/640A
Instruction Name
Instruction Format
Operation
WREN
0000 X110
Set Write Enable Latch
WRDI
0000 X100
Reset Write Enable Latch
RDSR
0000 X101
Read Status Register
WRSR
0000 X001
Write Status Register
READ
0000 X011
Read Data from Memory Array
WRITE
0000 X010
Write Data to Memory Array
Write Enable (WREN): The device will power-up in the Write Disable state when VCC is applied. All
programming instructions must therefore be preceded by a Write Enable instruction.
Write Disable (WRDI): To protect the device against inadvertent writes, the Write Disable instruction disables
all programming modes. The WRDI instruction is independent of the status of the WP pin.
Read Status Register (RDSR): The Read Status register instruction provides access to the status register. The
Ready/Busy and Write Enable status of the device can be determined by the RDSR instruction. Similarly, the
block write protection bits indicate the extent of protection employed. These bits are set by using the WRSR
instruction.
Table 6-2.
8
Status Register Format
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
WPEN
X
X
X
BP1
BP0
WEN
RDY
AT25080A/160A/320A/640A Automotive [DATASHEET]
Atmel-5082E-SEEPROM-AT25080A-160A-320A-640A-Auto-Datasheet_102014
Table 6-3.
Bit
Read Status Register Bit Definition
Definition
Bit 0 (RDY)
Bit 1 (WEN)
Bit 0 = 0 (RDY) indicates the device is ready.
Bit 0 = 1 indicates the write cycle is in progress.
Bit 1= 0 indicates the device is not write-enabled.
Bit 1 = 1 indicates the device is write-enabled.
Bit 2 (BP0)
See Table 6-4.
Bit 3 (BP1)
See Table 6-4.
Bits 4 6 are zeroes when device is not in an internal write cycle.
Bit 7 (WPEN)
See Table 6-4.
Bits 0 7 are ones during an internal write cycle.
Write Status Register (WRSR): The WRSR instruction allows the user to select one of four levels of protection.
The AT25080A/160A/320A/640A is divided into four array segments. One-quarter (¼), one-half (½), or all of the
memory segments can be protected. Any of the data within any selected segment will therefore be read-only.
The block write protection levels and corresponding status register control bits are shown in the below table.
Bits BP0, BP1, and WPEN are nonvolatile cells which have the same properties and functions as the regular
memory cells (e.g., WREN, tWC, RDSR).
Table 6-4.
Block Write Protect Bits
Status Register Bits
Array Addresses Protected
Level
BP1
BP0
AT25080A
AT25160A
AT25320A
AT25640A
0
0
0
None
None
None
None
1 (¼)
0
1
0300 03FF
0600 07FF
0C00 0FFF
1800 1FFF
2 (½)
1
0
0200 03FF
0400 07FF
0800 0FFF
1000 1FFF
3 (All)
1
1
0000 03FF
0000 07FF
0000 0FFF
0000 1FFF
The WRSR instruction also allows the user to enable or disable the Write Protect (WP) pin through the use of
the Write Protect Enable (WPEN) bit. Hardware write protection is enabled when the WP pin is low and the
WPEN bit is one. Hardware write protection is disabled when either the WP pin is high or the WPEN bit is zero.
When the device is hardware write protected, writes to the status register, including the block protect bits and
the WPEN bit, and the block-protected sections in the memory array are disabled. Writes are only allowed to
sections of the memory that are not block-protected.
Note:
When the WPEN bit is hardware write protected, it cannot be changed back to zero as long as the WP
pin is held low.
AT25080A/160A/320A/640A Automotive [DATASHEET]
Atmel-5082E-SEEPROM-AT25080A-160A-320A-640A-Auto-Datasheet_102014
9
Table 6-5.
WPEN Operation
WPEN
WP
WEN
Protected Blocks
Unprotected Blocks
Status Register
0
X
0
Protected
Protected
Protected
0
X
1
Protected
Writeable
Writeable
1
Low
0
Protected
Protected
Protected
1
Low
1
Protected
Writeable
Protected
X
High
0
Protected
Protected
Protected
X
High
1
Protected
Writeable
Writeable
Read Sequence (Read): Reading the AT25080A/160A/320A/640A via the Serial Output (SO) pin requires the
following sequence. After the CS line is pulled low to select a device, the read opcode is transmitted via the SI
line followed by the byte address to be read (A15 A0, see Table 6-6). Upon completion, any data on the SI line
will be ignored. The data (D7 D0) at the specified address is then shifted out onto the SO line. If only one byte
is to be read, the CS line should be driven high after the data comes out. The can be continued since the byte
address is automatically incremented and data will continue to be shifted out. When the highest address is
reached, the address counter will roll-over to the lowest address, allowing the entire memory to be read in one
continuous read cycle.
Write Sequence (Write): In order to program the AT25080A/160A/320A/640A, two separate instructions must
be executed. First, the device must be write enabled via the WREN instruction. Then a Write instruction may
be executed. Also, the address of the memory location(s) to be programmed must be outside the protected
address field location selected by the block write protection level. During an internal write cycle, all commands
will be ignored except the RDSR instruction.
A Write instruction requires the following sequence. After the CS line is pulled low to select the device, the Write
opcode is transmitted via the SI line followed by the byte address (A15 A0) and the data (D7 – D0) to be
programmed (See Table 6-6). Programming will start after the CS pin is brought high. The low-to-high transition
of the CS pin must occur during the SCK low-time immediately after clocking in the D0 (LSB) data bit.
The Ready/Busy status of the device can be determined by initiating a Read Status Register (RDSR)
instruction. If Bit 0 = one, the write cycle is still in progress. If Bit 0 = zero, the write cycle has ended. Only the
RDSR instruction is enabled during the write programming cycle.
The AT25080A/160A/320A/640A is capable of a 32-byte Page Write operation. After each byte of data is
received, the five low-order address bits are internally incremented by one; the high-order bits of the address
will remain constant. If more than 32 bytes of data are transmitted, the address counter will roll-over and the
previously written data will be overwritten. The AT25080A/160A/320A/640A is automatically returned to the
write disable state at the completion of a write cycle.
Note:
If the device is not Write Enabled (WREN), the device will ignore the Write instruction and will return to
the standby state, when CS is brought high. A new CS falling edge is required to reinitiate the serial
communication.
Table 6-6.
10
Address Key
Address
AT25080A
AT25160A
AT25320A
AT25640A
AN
A9–A0
A10–A0
A11–A0
A12–A0
Don’t Care Bits
A15–A10
A15–A11
A15–A12
A15–A13
AT25080A/160A/320A/640A Automotive [DATASHEET]
Atmel-5082E-SEEPROM-AT25080A-160A-320A-640A-Auto-Datasheet_102014
7.
Timing Diagrams
Figure 7-1.
Synchronous Data Timing (for Mode 0)
tCS
VIH
CS
VIL
tCSS
tCSH
VIH
tWH
SCK
tWL
VIL
tSU
tH
VIH
SI
Valid In
VIL
tV
VOH
tDIS
HI-Z
HI-Z
SO
tHO
VOL
Figure 7-2.
WREN Timing
CS
SCK
SI
WREN Opcode
HI-Z
SO
Figure 7-3.
WRDI Timing
CS
SCK
SI
SO
WRDI Opcode
HI-Z
AT25080A/160A/320A/640A Automotive [DATASHEET]
Atmel-5082E-SEEPROM-AT25080A-160A-320A-640A-Auto-Datasheet_102014
11
Figure 7-4.
RDSR Timing
CS
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
SCK
SI
Instruction
Data Out
High-impedance
SO
7
6
5
4
3
2
1
0
8
9
10
11
12
13
14
15
MSB
Figure 7-5.
WRSR Timing
CS
0
1
2
3
4
5
6
7
SCK
Data In
SI
6
5
4
3
2
1
0
High-impedance
SO
Figure 7-6.
7
Instruction
Read Timing
CS
0
1
2
3
4
5
6
7
8
9
10 11 20 21 22 23 24 25 26 27 28 29 30 31
SCK
Byte Address
SI
Instruction
15 14 13
...
3
2
1
0
Data Out
SO
High-impedance
7
MSB
12
AT25080A/160A/320A/640A Automotive [DATASHEET]
Atmel-5082E-SEEPROM-AT25080A-160A-320A-640A-Auto-Datasheet_102014
6
5
4
3
2
1
0
Figure 7-7.
Write Timing
CS
0
1
2
3
4
5
6
7
8
9 10 11 20 21 22 23 24 25 26 27 28 29 30 31
SCK
Byte Address
SI
SO
Figure 7-8.
15 14 13 ... 3
Instruction
2
Data In
1
0
7
6
5
4
3
2
1
0
High-impedance
HOLD Timing
CS
tHDN
tHDN
SCK
tHDS
tHDS
HOLD
tHZ
SO
tLZ
AT25080A/160A/320A/640A Automotive [DATASHEET]
Atmel-5082E-SEEPROM-AT25080A-160A-320A-640A-Auto-Datasheet_102014
13
8.
Ordering Code Detail
A T 2 5 0 8 0 A N - 1 0 S Q - 2 .7
Atmel Designator
Operating Voltage
2.7 = 2.7V to 5.5V
Product Family
25 = SPI-Compatible
Serial EEPROM
Package Device Grade
Q = Matte Tin Finish
Automotive Temperature Range
(-40°C to +125°C)
Device Density
Package Type
080
160
320
640
S
T
= 8 kilobit
= 16 kilobit
= 32 kilobit
= 64 kilobit
= JEDEC SOIC
= TSSOP
Speed Type
Device Revision
Package Variation
(Package Type Dependent)
N = 0.150” width SOIC
14
AT25080A/160A/320A/640A Automotive [DATASHEET]
Atmel-5082E-SEEPROM-AT25080A-160A-320A-640A-Auto-Datasheet_102014
10 = Default Value
Note: This field is not used for
Serial EEPROM products.
9.
Product Markings
AT25080A, AT25160A, AT25320A and AT25640A:
Automotive Package Marking Information
8-lead TSSOP
8-lead SOIC
ATMELYWW
25####N
SQ27
Q%
5####
Note: Lot Number, location of assembly and
YWW date code on the bottom side of
the package.
Note: Lot Number and location of assembly
on the bottom side of the package.
Note 1:
designates pin 1
Note 2: Package drawings are not to scale
Catalog Number Truncation
AT25080A
Truncation Code ####: 080A
AT25160A
Truncation Code ####: 160A
AT25320A
Truncation Code ####: 320A
AT25640A
Truncation Code ####: 640A
Date Codes
Y = Year
4: 2014
5: 2015
6: 2016
7: 2017
Voltages
8: 2018
9: 2019
0: 2020
1: 2021
M = Month
A: January
B: February
...
L: December
WW = Work Week of Assembly
02: Week 2
04: Week 4
...
52: Week 52
% = Minimum Voltage
3: 2.7V min
Country of Assembly
Lot Number
Grade/Lead Finish Material
@ = Country of Assembly
AAA...A = Atmel Wafer Lot Number
Q: Automotive/Matte Tin/SnAgCu
Trace Code
Atmel Truncation
XX = Trace Code (Atmel Lot Numbers Correspond to Code)
Example: AA, AB.... YZ, ZZ
AT: Atmel
ATM: Atmel
ATML: Atmel
3/11/14
TITLE
Package Mark Contact:
DL-CSO-Assy_eng@atmel.com
25080-16-32-640AAM, AT25080A, AT25160A, AT25320A and
AT25640A Automotive Package Marking Information
DRAWING NO.
REV.
25080-16-32-640AAM
A
AT25080A/160A/320A/640A Automotive [DATASHEET]
Atmel-5082E-SEEPROM-AT25080A-160A-320A-640A-Auto-Datasheet_102014
15
10.
Ordering Information
Atmel Ordering Code
AT25080AN-10SQ-2.7(1)
AT25080A-10TQ-2.7
(1)
AT25160AN-10SQ-2.7(2)
AT25160A-10TQ-2.7
(2)
AT25320AN-10SQ-2.7(3)
AT25320A-10TQ-2.7
(3)
AT25640AN-10SQ-2.7(4)
AT25640A-10TQ-2.7
Notes:
1.
2.
3.
4.
(4)
Lead Finish
Package
Matte Tin
Lead-free/Halogen-free
8S1
Matte Tin
Lead-free/Halogen-free
8S1
Matte Tin
Lead-free/Halogen-free
8S1
Matte Tin
Lead-free/Halogen-free
8S1
8X
8X
8X
8X
Voltage
Operation Range
2.7V to 5.5V
Automotive Temperature
40C to 125C)
2.7V to 5.5V
Automotive Temperature
40C to 125C)
2.7V to 5.5V
Automotive Temperature
40C to 125C)
2.7V to 5.5V
Automotive Temperature
40C to 125C)
AT25080A is not recommended for new design; replaced by AT25080B Automotive.
AT25160A is not recommended for new design; replaced by AT25160B Automotive.
AT25320A is not recommended for new design; replaced by AT25320B Automotive.
AT25640A is not recommended for new design; replaced by AT25640B Automotive.
Package Type
16
8S1
8-lead, 0.15" wide, Plastic Gull Wing Small Outline (JEDEC SOIC)
8X
8-lead, 4.40mm body, Plastic Thin Shrink Small Outline Package (TSSOP)
AT25080A/160A/320A/640A Automotive [DATASHEET]
Atmel-5082E-SEEPROM-AT25080A-160A-320A-640A-Auto-Datasheet_102014
11.
Packaging Information
11.1
8S1 — 8-lead JEDEC SOIC
C
1
E
E1
L
N
Ø
TOP VIEW
END VIEW
e
b
COMMON DIMENSIONS
(Unit of Measure = mm)
A
A1
D
SIDE VIEW
SYMBOL MIN
A
1.35
MAX
–
1.75
A1
0.10
–
0.25
b
0.31
–
0.51
C
0.17
–
0.25
D
4.80
–
5.05
E1
3.81
–
3.99
E
5.79
–
6.20
e
Notes: This drawing is for general information only.
Refer to JEDEC Drawing MS-012, Variation AA
for proper dimensions, tolerances, datums, etc.
NOM
NOTE
1.27 BSC
L
0.40
–
1.27
Ø
0°
–
8°
6/22/11
Package Drawing Contact:
packagedrawings@atmel.com
TITLE
8S1, 8-lead (0.150” Wide Body), Plastic Gull Wing
Small Outline (JEDEC SOIC)
GPC
SWB
DRAWING NO.
REV.
8S1
G
AT25080A/160A/320A/640A Automotive [DATASHEET]
Atmel-5082E-SEEPROM-AT25080A-160A-320A-640A-Auto-Datasheet_102014
17
11.2
8-lead — 8-lead TSSOP
C
1
Pin 1 indicator
this corner
E1
E
L1
N
L
Top View
End View
A
b
A1
e
A2
SYMBOL
D
Side View
Notes:
COMMON DIMENSIONS
(Unit of Measure = mm)
1. This drawing is for general information only.
Refer to JEDEC Drawing MO-153, Variation AA, for proper
dimensions, tolerances, datums, etc.
2. Dimension D does not include mold Flash, protrusions or gate
burrs. Mold Flash, protrusions and gate burrs shall not exceed
0.15mm (0.006in) per side.
3. Dimension E1 does not include inter-lead Flash or protrusions.
Inter-lead Flash and protrusions shall not exceed 0.25mm
(0.010in) per side.
4. Dimension b does not include Dambar protrusion.
Allowable Dambar protrusion shall be 0.08mm total in excess
of the b dimension at maximum material condition. Dambar
cannot be located on the lower radius of the foot. Minimum
space between protrusion and adjacent lead is 0.07mm.
5. Dimension D and E1 to be determined at Datum Plane H.
MIN
NOM
MAX
A
-
-
1.20
A1
0.05
-
0.15
A2
0.80
1.00
1.05
D
2.90
3.00
3.10
2, 5
E
NOTE
6.40 BSC
E1
4.30
4.40
4.50
3, 5
b
0.19
0.25
0.30
4
e
L
0.65 BSC
0.45
L1
C
0.60
0.75
1.00 REF
0.09
-
0.20
2/27/14
TITLE
Package Drawing Contact:
packagedrawings@atmel.com
18
8X, 8-lead 4.4mm Body, Plastic Thin
Shrink Small Outline Package (TSSOP)
AT25080A/160A/320A/640A Automotive [DATASHEET]
Atmel-5082E-SEEPROM-AT25080A-160A-320A-640A-Auto-Datasheet_102014
GPC
TNR
DRAWING NO.
8X
REV.
E
12.
Revision History
Doc. Rev.
5028E
Date
10/2014
Comments
Added part markings and ordering code detail. Updated template, logos, and disclaimer page.
No changes to functional specification.
AT25080A not recommended for new design; replaced by AT25080B Automotive.
AT25160A not recommended for new design; replaced by AT25160B Automotive.
5028D
08/2012
5082D
09/2007
AT25320A not recommended for new design; replaced by AT25320B Automotive.
AT25640A not recommended for new design; replaced by AT25640B Automotive.
Updated to new template.
Added overline to HOLD in Pin Configuration figure.
Implemented revision history.
5082C
02/2007
Removed PDIP package offering.
Removed Pb’d parts.
AT25080A/160A/320A/640A Automotive [DATASHEET]
Atmel-5082E-SEEPROM-AT25080A-160A-320A-640A-Auto-Datasheet_102014
19
XXXXXX
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T: (+1)(408) 441.0311
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|
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© 2014 Atmel Corporation. / Rev.: Atmel-5082E-SEEPROM-AT25080A-160A-320A-640A-Auto-Datasheet_102014.
Atmel®, Atmel logo and combinations thereof, Enabling Unlimited Possibilities®, and others are registered trademarks or trademarks of Atmel Corporation in U.S. and
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DISCLAIMER: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right
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