AT25512N-SH-T

AT25512 SPI Serial EEPROM 512 Kbits (65,536 x 8) Features • Serial Peripheral Interface (SPI) Compatible • Supports SPI Modes 0 (0,0) and 3 (1,1): – Data sheet describes mode 0 operation • Low-Voltage Operation: – 1.8V (VCC = 1.8V to 5.5V) • Industrial Temperature Range: -40°C to +85°C • 20 MHz Clock Rate (5V) • 128‑Byte Page Mode • Block Write Protection: – Protect 1/4, 1/2 or entire array • Write-Protect (WP) Pin and Write Disable Instructions for Both Hardware and Software Data Protection • Self-Timed Write Cycle within 5 ms Maximum • ESD Protection > 4,000V • High Reliability: – Endurance: 1,000,000 write cycles – Data retention: 100 years • Green (Lead-free/Halide-free/RoHS Compliant) Package Options • Die Sale Options: Wafer Form and Bumped Wafers Packages • 8-Lead SOIC, 8-Lead TSSOP and 8-Pad UDFN © 2019 Microchip Technology Inc. Datasheet DS20006218A-page 1 AT25512 Table of Contents Features.......................................................................................................................... 1 Packages.........................................................................................................................1 1. Package Types (not to scale).................................................................................... 4 2. Pin Description.......................................................................................................... 5 2.1. 2.2. 2.3. 2.4. 2.5. 2.6. 2.7. Chip Select (CS)...........................................................................................................................5 Serial Data Output (SO)............................................................................................................... 5 Write-Protect (WP)....................................................................................................................... 5 Ground......................................................................................................................................... 5 Serial Data Input (SI)....................................................................................................................6 Serial Data Clock (SCK)...............................................................................................................6 Device Power Supply (VCC)......................................................................................................... 6 3. Description.................................................................................................................7 3.1. 3.2. SPI Bus Master Connections to Serial EEPROMs.......................................................................7 Block Diagram.............................................................................................................................. 8 4. Electrical Characteristics........................................................................................... 9 4.1. 4.2. 4.3. 4.4. 4.5. 4.6. Absolute Maximum Ratings..........................................................................................................9 DC and AC Operating Range.......................................................................................................9 DC Characteristics....................................................................................................................... 9 AC Characteristics......................................................................................................................10 SPI Synchronous Data Timimg.................................................................................................. 13 Electrical Specifications..............................................................................................................13 5. Device Operation.....................................................................................................15 5.1. 5.2. 5.3. 5.4. Interfacing the AT25512 on the SPI Bus.................................................................................... 15 Device Opcodes......................................................................................................................... 16 Hold Function............................................................................................................................. 16 Write Protection..........................................................................................................................17 6. Device Commands and Addressing........................................................................ 18 6.1. 6.2. STATUS Register Bit Definition and Function............................................................................ 18 Read STATUS Register (RDSR)..................................................................................................19 6.3. Write Enable (WREN) and Write Disable (WRDI)......................................................................... 19 6.4. Write STATUS Register (WRSR).................................................................................................. 20 7. Read Sequence.......................................................................................................23 8. Write Sequence....................................................................................................... 24 8.1. 8.2. 8.3. Byte Write...................................................................................................................................24 Page Write..................................................................................................................................24 Polling Routine........................................................................................................................... 25 © 2019 Microchip Technology Inc. Datasheet DS20006218A-page 2 AT25512 9. Packaging Information.............................................................................................26 9.1. Package Marking Information.....................................................................................................26 10. Revision History.......................................................................................................35 The Microchip Website.................................................................................................. 36 Product Change Notification Service.............................................................................36 Customer Support......................................................................................................... 36 Product Identification System........................................................................................ 37 Microchip Devices Code Protection Feature................................................................. 37 Legal Notice...................................................................................................................38 Trademarks................................................................................................................... 38 Quality Management System........................................................................................ 39 Worldwide Sales and Service........................................................................................40 © 2019 Microchip Technology Inc. Datasheet DS20006218A-page 3 AT25512 Package Types (not to scale) 1. Package Types (not to scale) 8-Lead SOIC/TSSOP (Top View) CS 1 8 Vcc SO 2 7 HOLD WP 3 6 SCK GND 4 5 SI 8-Pad UDFN (Top View) CS 1 8 Vcc SO 2 7 HOLD WP 3 6 SCK GND 4 5 SI © 2019 Microchip Technology Inc. Datasheet DS20006218A-page 4 AT25512 Pin Description 2. Pin Description The descriptions of the pins are listed in Table 2-1. Table 2-1. Pin Function Table Name 8-Lead SOIC 8-Lead TSSOP 8-Pad UDFN(1) Function CS 1 1 1 Chip Select SO WP(2) 2 2 2 Serial Data Output 3 3 3 Write-Protect GND 4 4 4 Ground SI 5 5 5 Serial Data Input SCK HOLD(2) 6 6 6 Serial Data Clock 7 7 7 Suspends Serial Input VCC 8 8 8 Device Power Supply Note:  1. The exposed pad on this package can be connected to GND or left floating. 2. The Write-Protect (WP) and Hold (HOLD) pins should be driven high or low as appropriate. 2.1 Chip Select (CS) The AT25512 is selected when the Chip Select (CS) pin is low. When the device is not selected, data will not be accepted via the Serial Data Input (SI) pin, and the Serial Output (SO) pin will remain in a highimpedance state. To ensure robust operation, the CS pin should follow VCC upon power-up. It is therefore recommended to connect CS to VCC using a pull-up resistor (less than or equal to 10 kΩ). After power-up, a low level on CS is required prior to any sequence being initiated. 2.2 Serial Data Output (SO) The Serial Data Output (SO) pin is used to transfer data out of the AT25512. During a read sequence, data is shifted out on this pin after the falling edge of the Serial Data Clock (SCK). 2.3 Write-Protect (WP) The Write-Protect (WP) pin will allow normal read/write operations when held high. When the WP pin is brought low and WPEN bit is set to a logic ‘1’, all write operations to the STATUS register are inhibited. WP going low while CS is still low will interrupt a write operation to the STATUS register. If the internal write cycle has already been initiated, WP going low will have no effect on any write operation to the STATUS register. The WP pin function is blocked when the WPEN bit in the STATUS register is set to a logic ‘0’. This will allow the user to install the AT25512 in a system with the WP pin tied to ground and still be able to write to the STATUS register. All WP pin functions are enabled when the WPEN bit is set to a logic ‘1’. 2.4 Ground The ground reference for the power supply. GND should be connected to the system ground. © 2019 Microchip Technology Inc. Datasheet DS20006218A-page 5 AT25512 Pin Description 2.5 Serial Data Input (SI) The Serial Data Input (SI) pin is used to transfer data into the device. It receives instructions, addresses and data. Data is latched on the rising edge of the Serial Data Clock (SCK). 2.6 Serial Data Clock (SCK) The Serial Data Clock (SCK) pin is used to synchronize the communication between a master and the AT25512. Instructions, addresses or data present on the Serial Data Input (SI) pin is latched in on the rising edge of SCK, while output on the Serial Data Output (SO) pin is clocked out on the falling edge of SCK. 2.7 Device Power Supply (VCC) The Device Power Supply (VCC) pin is used to supply the source voltage to the device. Operations at invalid VCC voltages may produce spurious results and should not be attempted. © 2019 Microchip Technology Inc. Datasheet DS20006218A-page 6 AT25512 Description 3. Description The AT25512 provides 524,288 bits of Serial Electrically Erasable and Programmable Read-Only Memory (EEPROM) organized as 65,536 words of 8 bits each. The device is optimized for use in many industrial and commercial applications where low‑power and low‑voltage operation are essential. The device is available in space-saving 8‑lead SOIC, 8‑lead TSSOP and 8‑pad UDFN packages. All packages operate from 1.8V to 5.5V. 3.1 SPI Bus Master Connections to Serial EEPROMs SPI Master: Microcontroller Data Clock (SCK) Data Output (SO) Data Input (SI) SI CS3 CS2 CS1 CS0 © 2019 Microchip Technology Inc. SO SCK SI SO SCK SI SO SCK SI SO SCK Slave 0 AT25XXX Slave 1 AT25XXX Slave 2 AT25XXX Slave 3 AT25XXX CS CS CS CS Datasheet DS20006218A-page 7 AT25512 Description Block Diagram Memory System Control Module CS High-Voltage Generation Circuit Power-on Reset Generator VCC Pause Operation Control HOLD Register Bank: STATUS Register SO EEPROM Array 1 page Row Decoder 3.2 Address Register and Counter Column Decoder WP SCK Data Register Data Output Buffer GND SI Write Protection Control © 2019 Microchip Technology Inc. Datasheet DS20006218A-page 8 AT25512 Electrical Characteristics 4. Electrical Characteristics 4.1 Absolute Maximum Ratings Operating temperature -55°C to +125°C Storage temperature -65°C to +150°C Voltage on any pin with respect to ground -1.0V to +7.0V VCC 6.25V DC output current 5.0 mA ESD protection > 4 kV Note:  Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 4.2 DC and AC Operating Range Table 4-1. DC and AC Operating Range AT25512 4.3 Operating Temperature (Case) Industrial Temperature Range -40°C to +85°C VCC Power Supply Low-Voltage Grade 1.8V to 5.5V DC Characteristics Table 4-2. DC Characteristics(1) Parameter Symbol Minimum Typical Maximum Units Conditions Supply Voltage VCC1 1.8 — 5.5 V Supply Voltage VCC2 2.7 — 5.5 V Supply Voltage VCC3 4.5 — 5.5 V Supply Current ICC1 — 9.0 10.0 mA VCC = 5.0V at 20 MHz, SO = Open, Read Supply Current ICC2 — 5.0 7.0 mA VCC = 5.0V at 10 MHz, SO = Open, Read, Write Supply Current ICC3 — 2.2 3.5 mA VCC = 5.0V at 1 MHz, SO = Open, Read, Write Standby Current ISB1 — 0.2 3.0 µA VCC = 1.8V, CS = VCC © 2019 Microchip Technology Inc. Datasheet DS20006218A-page 9 AT25512 Electrical Characteristics ...........continued Parameter Symbol Minimum Typical Maximum Units Conditions Standby Current ISB2 — 0.5 3.0 µA VCC = 2.7V, CS = VCC Standby Current ISB3 — 2.0 5.0 µA VCC = 5.0V, CS = VCC Input Leakage IIL -3.0 — 3.0 µA VIN = 0V to VCC Output Leakage IOL -3.0 — 3.0 µA VIN = 0V to VCC, TA = 0°C to +70°C Input Low-Voltage VIL(2) -1.0 — VCC x 0.3 V Input High-Voltage VIH(2) VCC x 0.7 — VCC + 0.5 V Output Low-Voltage VOL1 — — 0.4 V 3.6V ≤ VCC ≤ 5.5V IOL = 3.0 mA Output High-Voltage VOH1 VCC - 0.8 — — V 3.6V ≤ VCC ≤ 5.5V IOH = -1.6 mA Output Low-Voltage VOL2 — — 0.2 V 1.8V ≤ VCC ≤ 3.6V IOL = 0.15 mA Output High-Voltage VOH2 VCC - 0.2 — — V 1.8V ≤ VCC ≤ 3.6V IOH = -100 µA Note:  1. Applicable over recommended operating range from: TA = -40°C to +85°C, VCC = 1.8V to 5.5V (unless otherwise noted). 2. VIL min. and VIH max. are reference only and are not tested. 4.4 AC Characteristics Table 4-3. AC Characteristics(1) Parameter SCK Clock Frequency Input Rise Time © 2019 Microchip Technology Inc. Symbol fSCK tRI Minimum Maximum Units Conditions 0 20 MHz VCC = 4.5V to 5.5V 0 10 MHz VCC = 2.7V to 5.5V 0 5 MHz VCC = 1.8V to 5.5V — 2000 ns VCC = 4.5V to 5.5V — 2000 ns VCC = 2.7V to 5.5V — 2000 ns VCC = 1.8V to 5.5V Datasheet DS20006218A-page 10 AT25512 Electrical Characteristics ...........continued Parameter Input Fall Time SCK High Time SCK Low Time CS High Time CS Setup Time CS Hold Time Data In Setup Time Data In Hold Time HOLD Setup Time HOLD Hold Time © 2019 Microchip Technology Inc. Symbol tFI tWH tWL tCS tCSS tCSH tSU tH tHD tCD Minimum Maximum Units Conditions — 2000 ns VCC = 4.5V to 5.5V — 2000 ns VCC = 2.7V to 5.5V — 2000 ns VCC = 1.8V to 5.5V 20 — ns VCC = 4.5V to 5.5V 40 — ns VCC = 2.7V to 5.5V 80 — ns VCC = 1.8V to 5.5V 20 — ns VCC = 4.5V to 5.5V 40 — ns VCC = 2.7V to 5.5V 80 — ns VCC = 1.8V to 5.5V 100 — ns VCC = 4.5V to 5.5V 100 — ns VCC = 2.7V to 5.5V 200 — ns VCC = 1.8V to 5.5V 100 — ns VCC = 4.5V to 5.5V 100 — ns VCC = 2.7V to 5.5V 200 — ns VCC = 1.8V to 5.5V 100 — ns VCC = 4.5V to 5.5V 100 — ns VCC = 2.7V to 5.5V 200 — ns VCC = 1.8V to 5.5V 5 — ns VCC = 4.5V to 5.5V 10 — ns VCC = 2.7V to 5.5V 20 — ns VCC = 1.8V to 5.5V 5 — ns VCC = 4.5V to 5.5V 10 — ns VCC = 2.7V to 5.5V 20 — ns VCC = 1.8V to 5.5V 5 — ns VCC = 4.5V to 5.5V 10 — ns VCC = 2.7V to 5.5V 20 — ns VCC = 1.8V to 5.5V 5 — ns VCC = 4.5V to 5.5V 10 — ns VCC = 2.7V to 5.5V 20 — ns VCC = 1.8V to 5.5V Datasheet DS20006218A-page 11 AT25512 Electrical Characteristics ...........continued Parameter Symbol Output Valid tV Output Hold Time HOLD to Output Low Z HOLD to Output High Z Output Disable Time Write Cycle Time tHO tLZ tHZ tDIS tWC Minimum Maximum Units Conditions 0 20 ns VCC = 4.5V to 5.5V 0 40 ns VCC = 2.7V to 5.5V 0 80 ns VCC = 1.8V to 5.5V 0 — ns VCC = 4.5V to 5.5V 0 — ns VCC = 2.7V to 5.5V 0 — ns VCC = 1.8V to 5.5V 0 25 ns VCC = 4.5V to 5.5V 0 50 ns VCC = 2.7V to 5.5V 0 100 ns VCC = 1.8V to 5.5V — 25 ns VCC = 4.5V to 5.5V — 50 ns VCC = 2.7V to 5.5V — 100 ns VCC = 1.8V to 5.5V — 25 ns VCC = 4.5V to 5.5V — 50 ns VCC = 2.7V to 5.5V — 100 ns VCC = 1.8V to 5.5V — 5 ms VCC = 4.5V to 5.5V — 5 ms VCC = 2.7V to 5.5V — 5 ms VCC = 1.8V to 5.5V Note:  1. Applicable over recommended operating range from TA = -40°C to +85°C, VCC = As Specified, CL = 1 TTL Gate and 30 pF (unless otherwise noted). © 2019 Microchip Technology Inc. Datasheet DS20006218A-page 12 AT25512 Electrical Characteristics 4.5 SPI Synchronous Data Timimg tCS VIH CS VIL tCSS tCSH VIH tWH SCK tWL VIL tSU tH VIH SI Valid Data In VIL tV VOH SO VOL tHO tDIS High Impedance High Impedance 4.6 Electrical Specifications 4.6.1 Power-Up Requirements and Reset Behavior During a power-up sequence, the VCC supplied to the AT25512 should monotonically rise from GND to the minimum VCC level, as specified in Table 4-1, with a slew rate no faster than 0.1 V/µs. 4.6.1.1 Device Reset To prevent inadvertent write operations or any other spurious events from occurring during a power-up sequence, the AT25512 includes a Power-on Reset (POR) circuit. Upon power-up, the device will not respond to any instructions until the VCC level crosses the internal voltage threshold (VPOR) that brings the device out of Reset and into Standby mode. The system designer must ensure the instructions are not sent to the device until the VCC supply has reached a stable value greater than or equal to the minimum VCC level. Additionally, once the VCC is greater than or equal to the minimum VCC level, the bus master must wait at least tPUP before sending the first instruction to the device. See Table 4-4 for the values associated with these power-up parameters. Table 4-4. Power-Up Conditions(1) Symbol Parameter tPUP Time required after VCC is stable before the device can accept instructions VPOR Power-on Reset Threshold Voltage tPOFF Minimum time at VCC = 0V between power cycles Min. Max. Units 100 － µs － 1.5 V 500 － ms Note:  1. These parameters are characterized but they are not 100% tested in production. If an event occurs in the system where the VCC level supplied to the AT25512 drops below the maximum VPOR level specified, it is recommended that a full-power cycle sequence be performed by first driving the VCC pin to GND in less than 1 ms, waiting at least the minimum tPOFF time and then performing a new power-up sequence in compliance with the requirements defined in this section. © 2019 Microchip Technology Inc. Datasheet DS20006218A-page 13 AT25512 Electrical Characteristics 4.6.2 Pin Capacitance Table 4-5. Pin Capacitance(1,2) Symbol COUT CIN Test Condition Max. Units Conditions Output Capacitance (SO) 8 pF VOUT = 0V Input Capacitance (CS, SCK, SI, WP, HOLD) 6 pF VIN = 0V Note:  1. This parameter is characterized but is not 100% tested in production. 2. Applicable over recommended operating range from: TA = 25°C, fSCK = 1.0 MHz, VCC = 5.0V (unless otherwise noted). 4.6.3 EEPROM Cell Performance Characteristics Table 4-6. EEPROM Cell Performance Characteristics Operation Test Condition Write Endurance(1) TA = 25°C, VCC = 5.0V, Page Write mode Data Retention(1) TA = 55°C Min. Max. Units 1,000,000 — Write Cycles 100 — Years Note:  1. Performance is determined through characterization and the qualification process. 4.6.4 Software Reset The SPI interface of the AT25512 can be reset by toggling the CS input. If the CS line is already in the active state, it must complete a transition from the inactive state (≥VIH) to the active state (≤VIL) and then back to the inactive state (≥VIH) without sending clocks on the SCK line. Upon completion of this sequence, the device will be ready to receive a new opcode on the SI line. 4.6.5 Device Default State at Power-Up The AT25512 default state upon power-up consists of: • Standby Power mode • A high-to-low-level transition on CS is required to enter active state • Write Enable Latch (WEL) bit in the STATUS register = 0 • Ready/Busy bit in the STATUS register = 0, indicating the device is ready to accept a new command • Device is not selected • Not in Hold condition • WPEN, BP1 and BP0 bits in the STATUS register are unchanged from their previous state due to the fact that they are nonvolatile values 4.6.6 Device Default Condition The AT25512 is shipped from Microchip to the customer with the EEPROM array set to an all FFh data pattern (logic ‘1’ state). The Write-Protect Enable bit in the STATUS register is set to logic ‘0’ and the Block Write‑Protection bits in the STATUS register are set to logic ‘0’. © 2019 Microchip Technology Inc. Datasheet DS20006218A-page 14 AT25512 Device Operation 5. Device Operation The AT25512 is controlled by a set of instructions that are sent from a host controller, commonly referred to as the SPI Master. The SPI Master communicates with the AT25512 via the SPI bus which is comprised of four signal lines: Chip Select (CS), Serial Data Clock (SCK), Serial Data Input (SI) and Serial Data Output (SO). The SPI protocol defines a total of four modes of operation (Mode 0, 1, 2 or 3) with each mode differing in respect to the SCK polarity and phase and how the polarity and phase control the flow of data on the SPI bus. The AT25512 supports the two most common modes, SPI Modes 0 and 3. With SPI Modes 0 and 3, data is always latched in on the rising edge of SCK and always output on the falling edge of SCK. The only difference between SPI Modes 0 and 3 is the polarity of the SCK signal when in the inactive state (when the SPI Master is in Standby mode and not transferring any data). SPI Mode 0 is defined as a low SCK while CS is not asserted (at VCC) and SPI Mode 3 has SCK high in the inactive state. The SCK Idle state must match when the CS is deasserted both before and after the communication sequence in SPI Mode 0 and 3. The figures in this document depict Mode 0 with a solid line on SCK while CS is inactive and Mode 3 with a dotted line. Figure 5-1. SPI Mode 0 and Mode 3 CS SCK SI Mode 3 Mode 3 Mode 0 Mode 0 MSB SO 5.1 LSB MSB LSB Interfacing the AT25512 on the SPI Bus Communication to and from the AT25512 must be initiated by the SPI Master device, such as a microcontroller. The SPI Master device must generate the serial clock for the AT25512 on the Serial Data Clock (SCK) pin. The AT25512 always operates as a slave due to the fact that the SCK is always an input. 5.1.1 Selecting the Device The AT25512 is selected when the Chip Select (CS) pin is low. When the device is not selected, data will not be accepted via the Serial Data Input (SI) pin, and the Serial Data Output (SO) pin will remain in a high‑impedance state. 5.1.2 Sending Data to the Device The AT25512 uses the SI pin to receive information. All instructions, addresses and data input bytes are clocked into the device with the Most Significant bit (MSb) first. The SI pin samples on the first rising edge of the SCK line after the CS has been asserted. © 2019 Microchip Technology Inc. Datasheet DS20006218A-page 15 AT25512 Device Operation 5.1.3 Receiving Data from the Device Data output from the device is transmitted on the SO pin, with the MSb output first. The SO data is latched on the first falling edge of SCK after the instruction has been clocked into the device, such as the Read from Memory Array (READ) and Read STATUS Register (RDSR) instructions. See Read Sequence for more details. 5.2 Device Opcodes 5.2.1 Serial Opcode After the device is selected by driving CS low, the first byte will be received on the SI pin. This byte contains the opcode that defines the operation to be performed. Refer to Table 6-1 for a list of all opcodes that the AT25512 will respond to. 5.2.2 Invalid Opcode If an invalid opcode is received, no data will be shifted into AT25512 and the SO pin will remain in a highimpedance state until the falling edge of CS is detected again. This will reinitialize the serial communication. 5.3 Hold Function The Suspend Serial Input (HOLD) pin is used to pause the serial communication with the device without having to stop or reset the clock sequence. The Hold mode, however, does not have an effect on the internal write cycle. Therefore, if a write cycle is in progress, asserting the HOLD pin will not pause the operation and the write cycle will continue to completion. The Hold mode can only be entered while the CS pin is asserted. The Hold mode is activated by asserting the HOLD pin during the SCK low pulse. If the HOLD pin is asserted during the SCK high pulse, then the Hold mode will not be started until the beginning of the next SCK low pulse. The device will remain in the Hold mode as long as the HOLD pin and CS pin are asserted. While in Hold mode, the SO pin will be in a high-impedance state. In addition, both the SI pin and the SCK pin will be ignored. The Write-Protect (WP) pin, however, can still be asserted or deasserted while in the Hold mode. To end the Hold mode and resume serial communication, the HOLD pin must be deasserted during the SCK low pulse. If the HOLD pin is deasserted during the SCK high pulse, then the Hold mode will not end until the beginning of the next SCK low pulse. If the CS pin is deasserted while the HOLD pin is still asserted, then any operation that may have been started will be aborted and the device will reset the WEL bit in the STATUS register back to the logic ‘0’ state. © 2019 Microchip Technology Inc. Datasheet DS20006218A-page 16 AT25512 Device Operation Figure 5-2. Hold Mode CS SCK HOLD Hold Hold Hold Figure 5-3. Hold Timing CS t CD t CD SCK HOLD t HD t HD t HZ SO tLZ 5.4 Write Protection The Write-Protect (WP) pin will allow normal read and write operations when held high. When the WP pin is brought low and WPEN bit is a logic ‘1’, all write operations to the STATUS register are inhibited. The WP pin going low while CS is still low will interrupt a Write STATUS Register (WRSR). If the internal write cycle has already been initiated, WP going low will have no effect on any write operation to the STATUS register. The WP pin function is blocked when the WPEN bit in the STATUS register is a logic ‘0’. This will allow the user to install the AT25512 device in a system with the WP pin tied to ground and still be able to write to the STATUS register. All WP pin functions are enabled when the WPEN bit is set to a logic ‘1’. © 2019 Microchip Technology Inc. Datasheet DS20006218A-page 17 AT25512 Device Commands and Addressing 6. Device Commands and Addressing The AT25512 is designed to interface directly with the synchronous Serial Peripheral Interface (SPI). The AT25512 utilizes an 8‑bit instruction register. The list of instructions and their operation codes are contained in Table 6-1. All instructions, addresses and data are transferred with the MSb first and start with a high‑to‑low CS transition. Table 6-1. Instruction Set for the AT25512 6.1 Instruction Name Instruction Format Operates On Operation Description WREN 0000 X110 STATUS Register Set Write Enable Latch (WEL) WRDI 0000 X100 STATUS Register Reset Write Enable Latch (WEL) RDSR 0000 X101 STATUS Register Read STATUS Register WRSR 0000 X001 STATUS Register Write STATUS Register READ 0000 X011 Memory Array Read from Memory Array WRITE 0000 X010 Memory Array Write to Memory Array STATUS Register Bit Definition and Function The AT25512 includes an 8‑bit STATUS register. The STATUS register bits modulate various features of the device as shown in Table 6-2 and Table 6-3. These bits can be changed by specific instructions that are detailed in the following sections. Table 6-2. STATUS Register Format Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 WPEN X X X BP1 BP0 WEL RDY/BSY Table 6-3. STATUS Register Bit Definition Bit 7 Name WPEN Write-Protect Enable Type R/W Description 0 See Table 6-5 (Factory Default) 1 See Table 6-5 (Factory Default) 6:4 RFU Reserved for Future Use R 0 Reads as zeros when the device is not in a write cycle 1 Reads as ones when the device is in a write cycle 3:2 BP1 BP0 Block Write Protection R/W 00 No array write protection (Factory Default) 01 Quarter array write protection (see Table 6-4) 10 Half array write protection (see Table 6-4) 11 Entire array write protection (see Table 6-4) 1 WEL Write Enable Latch R 0 Device is not write enabled (Power-up Default) 1 Device is write enabled © 2019 Microchip Technology Inc. Datasheet DS20006218A-page 18 AT25512 Device Commands and Addressing ...........continued Bit 0 Name Type RDY/BSY Ready/Busy Status Description 0 Device is ready for a new sequence R 1 Device is busy with an internal operation 6.2 Read STATUS Register (RDSR) The Read STATUS Register (RDSR) instruction provides access to the STATUS register. The ready/busy and write enable status of the device can be determined by the RDSR instruction. Similarly, the Block Write Protection (BP[1:0]) bits indicate the extent of memory array protection employed. The STATUS register is read by asserting the CS pin, followed by sending in a 05h opcode on the SI pin. Upon completion of the opcode, the device will return the 8‑bit STATUS register value on the SO pin. Figure 6-1. RDSR Waveform CS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SCK RDSR Opcode (05h) SI 0 0 0 0 0 1 0 1 MSB STATUS Register Data Out SO High-Impedance D7 D6 D5 D4 D3 D2 D1 D0 MSB 6.3 Write Enable (WREN) and Write Disable (WRDI) Enabling and disabling writing to the STATUS register and EEPROM array is accomplished through the Write Enable (WREN) instruction and the Write Disable (WRDI) instruction. These functions change the status of the WEL bit in the STATUS register. 6.3.1 Write Enable Instruction (WREN) The Write Enable Latch (WEL) bit of the STATUS register must be set to a logic ‘1’ prior to each Write STATUS Register (WRSR) and Write to Memory Array (WRITE) instructions. This is accomplished by sending a WREN (06h) instruction to the AT25512. First, the CS pin is driven low to select the device and then a WREN instruction is clocked in on the SI pin. Then the CS pin can be driven high and the WEL bit will be updated in the STATUS register to a logic ‘1’. The device will power‑up in the Write Disable state (WEL = 0). © 2019 Microchip Technology Inc. Datasheet DS20006218A-page 19 AT25512 Device Commands and Addressing Figure 6-2. WREN Timing CS 0 1 2 3 4 5 6 7 SCK WREN Opcode (06h) SI 0 0 0 0 0 1 1 0 MSB High-Impedance SO 6.3.2 Write Disable Instruction (WRDI) To protect the device against inadvertent writes, the Write Disable (WRDI) instruction (opcode 04h) disables all programming modes by setting the WEL bit to a logic ‘0’. The WRDI instruction is independent of the status of the WP pin. Figure 6-3. WRDI Timing CS 0 1 2 3 4 5 6 7 SCK WRDI Opcode (04h) SI 0 0 0 0 0 1 0 0 MSB SO 6.4 High-Impedance Write STATUS Register (WRSR) The Write STATUS Register (WRSR) instruction enables the SPI Master to change selected bits of the STATUS register. Before a WRSR instruction can be initiated, a WREN instruction must be executed to set the WEL bit to logic ‘1’. Upon completion of a WREN instruction, a WRSR instruction can be executed. Note:  The WRSR instruction has no effect on bit 6, bit 5, bit 4, bit 1 and bit 0 of the STATUS register. Only bit 7, bit 3 and bit 2 can be changed via the WRSR instruction. These modifiable bits are the Write-Protect Enable (WPEN) and Block Protect (BP[1:0]) bits. These three bits are nonvolatile bits that have the same properties and functions as regular EEPROM cells. Their values are retained while power is removed from the device. © 2019 Microchip Technology Inc. Datasheet DS20006218A-page 20 AT25512 Device Commands and Addressing The AT25512 will not respond to commands other than a RDSR after a WRSR instruction until the self‑timed internal write cycle has completed. When the write cycle is completed, the WEL bit in the STATUS register is reset to logic ‘0’. Figure 6-4. WRSR Waveform CS tWC(1) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SCK STATUS Register Data In WRSR Opcode (01h) SI 0 0 0 0 0 MSB 0 0 1 D7 X X X D3 D2 X X MSB High-Impedance SO Note:  1. 6.4.1 This instruction initiates a self-timed internal write cycle (tWC) on the rising edge of CS after a valid sequence. Block Write-Protect Function The WRSR instruction allows the user to select one of four possible combinations as to how the memory array will be inhibited from writing through changing the Block Write-Protect bits (BP[1:0]). The four levels of array protection are: • None of the memory array is protected. • Upper quarter (¼) address range is write-protected meaning the highest order address bits are read‑only. • Upper half (½) address range is write-protected meaning the highest order address bits are read‑only. • All of the memory array is write-protected meaning all address bits are read‑only. The Block Write Protection levels and corresponding STATUS register control bits are shown in Table 6-4. Table 6-4. Block Write-Protect Bits Level STATUS Register Bits Write-Protected/Read‑Only Address Range BP1 BP0 AT25512 0 0 0 None 1(1/4) 0 1 C000h-FFFFh 2(1/2) 1 0 8000h-FFFFh 3(All) 1 1 0000h-FFFFh © 2019 Microchip Technology Inc. Datasheet DS20006218A-page 21 AT25512 Device Commands and Addressing 6.4.2 Write-Protect Enable Function The WRSR instruction also allows the user to enable or disable the Write-Protect (WP) pin through the use of the Write-Protect Enable (WPEN) bit. When the WPEN bit is set to logic ‘0’, the ability to write the EEPROM array is dictated by the values of the Block Write-Protect (BP[1:0]) bits. The ability to write the STATUS register is controlled by the WEL bit. When the WPEN bit is set to logic ‘1’, the STATUS register is read-only. Hardware Write Protection is enabled when both the WP pin is low and the WPEN bit has been set to a logic ‘1’. When the device is Hardware Write‑Protected, writes to the STATUS register, including the Block Write‑Protect, WEL and WPEN bits and to the sections in the memory array selected by the Block Write‑Protect bits are disabled. When Hardware Write Protection is enabled, writes are only allowed to sections of the memory that are not block‑protected. Hardware Write Protection is disabled when either the WP pin is high or the WPEN bit is a logic ‘0’. When Hardware Write Protection is disabled, writes are only allowed to sections of the memory that are not block‑protected. Refer to Table 6-5 for additional information. Note:  When the WPEN bit is Hardware Write‑Protected, it cannot be set back to a logic ‘0’ as long as the WP pin is held low. Table 6-5. WPEN Operation WPEN WP Pin WEL Protected Blocks Unprotected Blocks STATUS Register 0 x 0 Protected Protected Protected 0 x 1 Protected Writable Writable 1 Low 0 Protected Protected Protected 1 Low 1 Protected Writable Protected x High 0 Protected Protected Protected x High 1 Protected Writable Writable © 2019 Microchip Technology Inc. Datasheet DS20006218A-page 22 AT25512 Read Sequence 7. Read Sequence Reading the AT25512 via the SO pin requires the following sequence. After the CS line is pulled low to select a device, the READ (03h) instruction is transmitted via the SI line followed by the 16‑bit address to be read. Refer to Table 7-1 for the address bits for AT25512. Table 7-1. AT25512 Address Bits Address AT25512 AN A15—A0 Upon completion of the 16‑bit address, any data on the SI line will be ignored. The data (D7‑D0) at the specified address is then shifted out onto the SO line. If only one byte is to be read, the CS line should be driven high after the data comes out. The read sequence can be continued since the byte address is automatically incremented and data will continue to be shifted out. When the highest‑order address bit is reached, the address counter will rollover to the lowest‑order address bit allowing the entire memory to be read in one continuous read cycle regardless of the starting address. Figure 7-1. Read Waveform CS 0 1 2 3 4 5 6 7 8 9 10 11 12 19 20 21 22 23 24 25 26 27 28 29 30 31 SCK READ Opcode (03h) SI 0 0 0 0 0 MSB 0 1 Address Bits A15-A0 1 A A A A A A A A A MSB Data Byte 1 SO High-Impedance D MSB © 2019 Microchip Technology Inc. Datasheet D D D D D D D D D MSB DS20006218A-page 23 AT25512 Write Sequence 8. Write Sequence In order to program the AT25512, two separate instructions must be executed. First, the device must be write enabled via the Write Enable (WREN) instruction. Then, one of the two possible write sequences described in this section may be executed. Note:  If the device is not Write Enabled (WREN), the device will ignore the WRITE instruction and will return to the standby state when CS is brought high. A new CS assertion is required to re‑initiate communication. The address of the memory location(s) to be programmed must be outside the protected address field location selected by the block write protection level. During an internal write cycle, all commands will be ignored except the RDSR instruction. Refer to Table 8-1 for the address bits for AT25512. Table 8-1. AT25512 Address Bits 8.1 Address AT25512 AN A15—A0 Byte Write A Byte Write requires the following sequence and is depicted in Figure 8-1. After the CS line is pulled low to select the device, the WRITE (02h) instruction is transmitted via the SI line followed by the 16‑bit address and the data (D7‑D0) to be programmed. Programming will start after the CS pin is brought high. The low‑to‑high transition of the CS pin must occur during the SCK low time (Mode 0) and SCK high time (Mode 3) immediately after clocking in the D0 (LSB) data bit. The AT25512 is automatically returned to the Write Disable state (STATUS register bit WEL = 0) at the completion of a write cycle. Figure 8-1. Byte Write CS tWC(1) 0 1 2 3 4 5 6 7 8 9 10 11 12 21 22 23 24 25 26 27 28 29 30 31 SCK WRITE Opcode (02h) SI 0 0 0 0 0 MSB SO 0 1 Address Bits A15-A0 0 A A A A A A MSB A Data In A A D7 D6 D5 D4 D3 D2 D1 D0 MSB High-Impedance Note:  1. This instruction initiates a self-timed internal write cycle (tWC) on the rising edge of CS after a valid sequence. 8.2 Page Write A Page Write sequence allows up to 128 bytes to be written in the same write cycle, provided that all bytes are in the same row of the memory array. Partial Page Writes of less than 128 bytes are allowed. After each byte of data is received, the seven lowest order address bits are internally incremented © 2019 Microchip Technology Inc. Datasheet DS20006218A-page 24 AT25512 Write Sequence following the receipt of each data byte. The higher order address bits are not incremented and retain the memory array page location. If more bytes of data are transmitted that what will fit to the end of that memory row, the address counter will rollover to the beginning of the same row. Nevertheless, creating a rollover event should be avoided as previously loaded data in the page could become unintentionally altered. The AT25512 is automatically returned to the Write Disable state (WEL = 0) at the completion of a write cycle. Figure 8-2. Page Write CS tWC(1) 0 1 2 3 4 5 6 7 8 9 21 22 23 24 25 26 27 28 29 30 31 SCK WRITE Opcode (02h) SI 0 0 0 0 0 0 1 MSB Address Bits A15-A0 A 0 MSB A A A A Data In Byte 1 A D D D D MSB D D Data In Byte 128 D D D D D D D D D D MSB High-Impedance SO Note:  1. 8.3 This instruction initiates a self‑timed internal write cycle (tWC) on the rising edge of CS after a valid sequence. Polling Routine A polling routine can be implemented to optimize time‑sensitive applications that would not prefer to wait the fixed maximum write cycle time (tWC). This method allows the application to know immediately when the write cycle has completed to start a subsequent operation. Once the internally-timed write cycle has started, a polling routine can be initiated. This involves repeatedly sending Read STATUS Register (RDSR) instruction to determine if the device has completed its self-timed internal write cycle. If the RDY/BSY bit (bit 0 of STATUS register) = 1, the write cycle is still in progress. If bit 0 = 0, the write cycle has ended. If the RDY/BSY bit = 1, repeated RDSR commands can be executed until the RDY/BSY bit = 0, signaling that the device is ready to execute a new instruction. Only the Read STATUS Register (RDSR) instruction is enabled during the write cycle. Figure 8-3. Polling Flowchart Send Valid Write Protocol Deassert CS to VCC to Initiate a Write Cycle Send RDSR Instruction to the Device Does RDY/BSY = 0? YES Continue to Next Operation NO © 2019 Microchip Technology Inc. Datasheet DS20006218A-page 25 AT25512 Packaging Information 9. Packaging Information 9.1 Package Marking Information AT25512: Package Marking Information 8-lead TSSOP 8-lead SOIC 8-pad UDFN 5.0 x 6.0 mm Body ATMLHYWW ## % CO YYWWNNN Note 1: ATHYWW ## %CO YYWWNNN ATMLHYWW ## % CO YYWWNNN designates pin 1 Note 2: Package drawings are not to scale Catalog Number Truncation AT25512 Truncation Code ##: 5F Date Codes YY = Year 16: 2016 17: 2017 18: 2018 19: 2019 Voltages 20: 2020 21: 2021 22: 2022 23: 2023 Y = Year 6: 2016 7: 2017 8: 2018 9: 2019 0: 2020 1: 2021 2: 2022 3: 2023 WW = Work Week of Assembly 02: Week 2 04: Week 4 ... 52: Week 52 Country of Origin Device Grade CO = Country of Origin H or U: Industrial Grade % = Minimum Voltage L or M: 1.8V min Atmel Truncation AT: Atmel ATM: Atmel ATML: Atmel Lot Number or Trace Code NNN = Alphanumeric Trace Code (2 Characters for Small Packages) © 2019 Microchip Technology Inc. Datasheet DS20006218A-page 26 AT25512 Packaging Information 8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm (.150 In.) Body [SOIC] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2X 0.10 C A–B D A D NOTE 5 N E 2 E1 2 E1 E NOTE 1 2 1 e B NOTE 5 NX b 0.25 C A–B D TOP VIEW 0.10 C C A A2 SEATING PLANE 8X A1 SIDE VIEW 0.10 C h R0.13 h R0.13 H 0.23 L SEE VIEW C (L1) VIEW A–A VIEW C Microchip Technology Drawing No. C04-057-SN Rev E Sheet 1 of 2 © 2017 Microchip Technology Inc. © 2019 Microchip Technology Inc. Datasheet DS20006218A-page 27 AT25512 Packaging Information 8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm (.150 In.) Body [SOIC] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Units Dimension Limits Number of Pins N e Pitch Overall Height A Molded Package Thickness A2 § Standoff A1 Overall Width E Molded Package Width E1 Overall Length D Chamfer (Optional) h Foot Length L L1 Footprint Foot Angle c Lead Thickness b Lead Width Mold Draft Angle Top Mold Draft Angle Bottom MIN 1.25 0.10 0.25 0.40 0° 0.17 0.31 5° 5° MILLIMETERS NOM 8 1.27 BSC 6.00 BSC 3.90 BSC 4.90 BSC 1.04 REF - MAX 1.75 0.25 0.50 1.27 8° 0.25 0.51 15° 15° Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. § Significant Characteristic 3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15mm per side. 4. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. 5. Datums A & B to be determined at Datum H. Microchip Technology Drawing No. C04-057-SN Rev E Sheet 2 of 2 © 2017 Microchip Technology Inc. © 2019 Microchip Technology Inc. Datasheet DS20006218A-page 28 AT25512 Packaging Information 8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm Body [SOIC] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging SILK SCREEN C Y1 X1 E RECOMMENDED LAND PATTERN Units Dimension Limits E Contact Pitch Contact Pad Spacing C Contact Pad Width (X8) X1 Contact Pad Length (X8) Y1 MIN MILLIMETERS NOM 1.27 BSC 5.40 MAX 0.60 1.55 Notes: 1. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. Microchip Technology Drawing C04-2057-SN Rev E © 2017 Microchip Technology Inc. © 2019 Microchip Technology Inc. Datasheet DS20006218A-page 29 MAT25512 Packaging Diagrams and Parameters Packaging Information 8-Lead Plastic Thin Shrink Small Outline (ST) – 4.4 mm Body [TSSOP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D N E E1 NOTE 1 1 2 b e c A φ A2 A1 L L1 Units Dimension Limits Number of Pins MILLIMETERS MIN N NOM MAX 8 Pitch e Overall Height A – 0.65 BSC – Molded Package Thickness A2 0.80 1.00 1.05 Standoff A1 0.05 – 0.15 1.20 Overall Width E Molded Package Width E1 4.30 6.40 BSC 4.40 Molded Package Length D 2.90 3.00 3.10 Foot Length L 0.45 0.60 0.75 Footprint L1 4.50 1.00 REF Foot Angle φ 0° – 8° Lead Thickness c 0.09 – 0.20 Lead Width b 0.19 – 0.30 Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side. 3. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Microchip Technology Drawing C04-086B © 2007 Microchip Technology Inc. © 2019 Microchip Technology Inc. DS00049AR-page 117 Datasheet DS20006218A-page 30 M Note: AT25512 Packaging Diagrams and Parameters Packaging Information For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2009 Microchip Technology Inc. DS00049BC-page 96 © 2019 Microchip Technology Inc. Datasheet DS20006218A-page 31 AT25512 Packaging Information /HDG8OWUD7KLQ3ODVWLF'XDO)ODW1R/HDG3DFNDJH4%[PP%RG\>8')1@ $WPHO/HJDF\