Features
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Serial Peripheral Interface (SPI) Compatible
Supports SPI Modes 0 (0,0) and 3 (1,1)
128-byte Page Mode Only for Write Operations
Low-voltage and Standard-voltage Operation
– 2.7 (VCC = 2.7V to 5.5V)
– 1.8 (VCC = 1.8V to 5.5V)
10 MHz (5V), 5MHz (2.7V) and 2 MHz (1.8V) Clock Rate
Block Write Protection
Protect 1/4, 1/2, or Entire Array
Write Protect (WP) Pin and Write Disable Instructions for
both Hardware and Software Data Protection
High Reliability
– Endurance: 100K Write Cycles
– Data Retention: >40 Years
8-lead PDIP, 8-lead EIAJ SOIC, 16-lead JEDEC SOIC, 8-lead Leadless Array Package,
and 8-lead SOIC Array Package (SAP)
Die Sales: Wafer Form, Waffle Pack, and Bumped Wafers
Description
The AT25HP256/512 provides 262,144/524,288 bits of serial electrically erasable programmable read only memory (EEPROM) organized as 32,768/65,536 words of 8-bits
each. The device is optimized for use in many industrial and commercial applications
where high-speed, low-power, and low-voltage operation are essential. The
AT25HP256/512 is available in a space saving 8-lead PDIP (AT25HP256/512), 8-lead
EIAJ SOIC (AT25HP256), 16-lead JEDEC SOIC (AT25HP512), 8-lead Leadless Array
(AT25HP256/512) package, and 8-lead SOIC Array package (SAP). In addition, the
entire family is available in 2.7V (2.7V to 5.5V) and 1.8V (1.8V to 5.5V) versions.
Table 1. Pin Configurations
Pin Name
Function
CS
Chip Select
SCK
Serial Data Clock
SI
Serial Data Input
SO
Serial Data Output
GND
Ground
VCC
Power Supply
WP
Write Protect
256K (32,768 x 8)
512K (65,536 x 8)
AT25HP256(1)
AT25HP512
Note:
1. Not recommended for
new design; please refer to
AT25256A datasheet.
16-lead SOIC
CS
SO
NC
NC
NC
NC
WP
GND
1
2
3
4
5
6
7
8
VCC
HOLD
NC
NC
NC
NC
SCK
SI
16
15
14
13
12
11
10
9
8-lead Leadless Array
VCC
HOLD
SCK
SI
Suspends Serial Input
HOLD
SPI Serial
EEPROMs
8
1
7
2
6
3
5
4
CS
SO
WP
GND
Bottom View
8-lead SOIC Array Package
(SAP)
VCC
HOLD
SCK
SI
8
7
1
2
6
3
5
4
Bottom View
CS
SO
WP
GND
8-lead SOIC
8-lead PDIP
CS
1
8
VCC
SO
2
7
HOLD
WP
GND
3
6
SCK
4
5
SI
CS
1
8
SO
2
7
HOLD
WP
GND
3
6
SCK
4
5
SI
VCC
Rev. 1113L–SEEPR–3/06
1
The AT25HP256/512 is enabled through the Chip Select pin (CS) and accessed via a 3wire interface consisting of Serial Data Input (SI), Serial Data Output (SO), and Serial
Clock (SCK). All programming cycles are completely self-timed, and no separate erase
cycle is required before write.
Block Write protection is enabled by programming the status register with top ¼, top ½
or entire array of write protection. Separate Program Enable and Program Disable
instructions are provided for additional data protection. Hardware data protection is provided via the WP pin to protect against inadvertent write attempts to the status register.
The HOLD pin may be used to suspend any serial communication without resetting the
serial sequence.
Absolute Maximum Ratings*
Operating Temperature..................................–55°C to +125°C
*NOTICE:
Storage Temperature .....................................–65°C to +150°C
Voltage on Any Pin
with Respect to Ground .................................... –1.0V to +7.0V
Maximum Operating Voltage .......................................... 6.25V
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended
periods may affect device reliability.
DC Output Current........................................................ 5.0 mA
Figure 1. Block Diagram
32,768/65,536 x 8
2
AT25HP256/512
1113L–SEEPR–3/06
AT25HP256/512
Table 2. Pin Capacitance(1)
Applicable over recommended operating range from TA = 25°C, f = 1.0 MHz, VCC = +5.0V (unless otherwise noted)
Symbol
Test Conditions
COUT
Output Capacitance (SO)
CIN
Note:
Max
Units
Conditions
8
pF
VOUT = 0V
6
pF
VIN = 0V
Input Capacitance (CS, SCK, SI, WP, HOLD)
1. This parameter is characterized and is not 100% tested.
Table 3. DC Characteristics
Applicable over recommended operating range from: TAI = –40°C to +85°C, VCC = +1.8V to +5.5V,
TAC = 0°C to +70°C, VCC = +1.8V to +5.5V (unless otherwise noted)
Symbol
Parameter
VCC1
Supply Voltage
VCC2
Max
Units
1.8
3.6
V
Supply Voltage
2.7
5.5
V
VCC3
Supply Voltage
4.5
5.5
V
ICC1
Supply Current
VCC = 5.0V at 5 MHz, SO = Open Read
6.0
10.0
mA
ICC2
Supply Current
VCC = 5.0V at 5 MHz, SO = Open Write
4.0
7.0
mA
ISB1
Standby Current
VCC = 1.8V, CS = VCC
0.1
2.0
µA
ISB2
Standby Current
VCC = 2.7V, CS = VCC
0.2
2.0
µA
ISB3
Standby Current
VCC = 5.0V, CS = VCC
2.0
5.0
µA
IIL
Input Leakage
VIN = 0V to VCC
–3.0
3.0
µA
IOL
Output Leakage
VIN = 0V to VCC, TAC = 0°C to 70°C
–3.0
3.0
µA
Input Low Voltage
–0.6
VCC x 0.3
V
Input High Voltage
VCC x 0.7
VCC + 0.5
V
0.4
V
VIL(1)
VIH
(1)
VOL1
Output Low Voltage
VOH1
Output High Voltage
VOL2
Output Low Voltage
VOH2
Output High Voltage
Note:
Test Condition
4.5V ≤ VCC ≤ 5.5V
1.8V ≤ VCC ≤ 3.6V
Min
IOL = 3.0 mA
IOH = –1.6 mA
VCC – 0.8
IOL = 0.15 mA
IOH = –100 µA
Typ
V
0.2
VCC – 0.2
V
V
1. VIL and VIH max are reference only and are not tested.
3
1113L–SEEPR–3/06
Table 4. AC Characteristics
Applicable over recommended operating range from TA = –40°C to +85°C, VCC = As Specified,
CL = 1 TTL Gate and 30 pF (unless otherwise noted)
Symbol
Parameter
Voltage
Min
Max
Units
fSCK
SCK Clock Frequency
4.5 – 5.5
2.7 – 5.5
1.8 – 5.5
0
0
0
10
5
2
MHz
tRI
Input Rise Time
4.5 – 5.5
2.7 – 5.5
1.8 – 5.5
2
2
2
µs
tFI
Input Fall Time
4.5 – 5.5
2.7 – 5.5
1.8 – 5.5
2
2
2
µs
tWH
SCK High Time
4.5 – 5.5
2.7 – 5.5
1.8 – 5.5
40
80
200
ns
tWL
SCK Low Time
4.5 – 5.5
2.7 – 5.5
1.8 – 5.5
40
80
200
ns
tCS
CS High Time
4.5 – 5.5
2.7 – 5.5
1.8 – 5.5
50
100
250
ns
tCSS
CS Setup Time
4.5 – 5.5
2.7 – 5.5
1.8 – 5.5
50
100
250
ns
tCSH
CS Hold Time
4.5 – 5.5
2.7 – 5.5
1.8 – 5.5
50
100
250
ns
tSU
Data In Setup Time
4.5 – 5.5
2.7 – 5.5
1.8 – 5.5
12
20
50
ns
tH
Data In Hold Time
4.5 – 5.5
2.7 – 5.5
1.8 – 5.5
10
20
50
ns
tHD
Hold Setup Time
4.5 – 5.5
2.7 – 5.5
1.8 – 5.5
25
50
100
ns
tCD
Hold Hold Time
4.5 – 5.5
2.7 – 5.5
1.8 – 5.5
25
50
100
ns
tV
Output Valid
4.5 – 5.5
2.7 – 5.5
1.8 – 5.5
0
0
0
tHO
Output Hold Time
4.5 – 5.5
2.7 – 5.5
1.8 – 5.5
0
0
0
tLZ
Hold to Output Low Z
4.5 – 5.5
2.7 – 5.5
1.8 – 5.5
0
0
0
4
40
80
200
ns
ns
100
200
300
ns
AT25HP256/512
1113L–SEEPR–3/06
AT25HP256/512
Table 4. AC Characteristics (Continued)
Applicable over recommended operating range from TA = –40°C to +85°C, VCC = As Specified,
CL = 1 TTL Gate and 30 pF (unless otherwise noted)
Symbol
Parameter
Voltage
tHZ
Hold to Output High Z
tDIS
tWC
Note:
Max
Units
4.5 – 5.5
2.7 – 5.5
1.8 – 5.5
100
200
300
ns
Output Disable Time
4.5 – 5.5
2.7 – 5.5
1.8 – 5.5
100
100
250
ns
Write Cycle Time
4.5 – 5.5
2.7 – 5.5
1.8 – 5.5
10
10
10
ms
4.5 – 5.5
2.7 – 5.5
1.8 – 5.5
1. This parameter is characterized and is not 100% tested.
Endurance(1)
5.0V, 25°C, Page Mode
Min
100K
Write Cycles
5
1113L–SEEPR–3/06
Serial Interface
Description
MASTER: The device that generates the serial clock.
SLAVE: Because the serial clock pin (SCK) is always an input, the AT25HP256/512
always operates as a slave.
TRANSMITTER/RECEIVER: The AT25HP256/512 has separate pins designated for
data transmission (SO) and reception (SI).
MSB: The Most Significant Bit (MSB) is the first bit transmitted and received.
SERIAL OP-CODE: After the device is selected with CS going low, the first byte will be
received. This byte contains the op-code that defines the operations to be performed.
INVALID OP-CODE: If an invalid op-code is received, no data will be shifted into the
AT25HP256/512, and the serial output pin (SO) will remain in a high impedance state
until the falling edge of CS is detected again. This will reinitialize the serial
communication.
CHIP SELECT: The AT25HP256/512 is selected when the CS pin is low. When the
device is not selected, data will not be accepted via the SI pin, and the SO will remain in
a high impedance state.
HOLD: The HOLD pin is used in conjunction with the CS pin to select the
AT25HP256/512. When the device is selected and a serial sequence is underway,
HOLD can be used to pause the serial communication with the master device without
resetting the serial sequence. To pause, the HOLD pin must be brought low while the
SCK pin is low. To resume serial communication, the HOLD pin is brought high while the
SCK pin is low (SCK may still toggle during HOLD). Inputs to the SI pin will be ignored
while the SO pin is in the high impedance state.
WRITE PROTECT: The write protect pin (WP) will allow normal read/write operations
when held high. When the WP pin is brought low and WPEN bit is “1”, all write operations to the status register are inhibited. WP going low while CS is still low will interrupt a
write to the status register. If the internal write cycle has already been initiated, WP
going low will have no effect on any write operation to the status register. The WP pin
function is blocked when the WPEN bit in the status register is “0”. This will allow the
user to install the AT25HP256/512 in a system with the WP pin tied to ground and still
be able to write to the status register. All WP pin functions are enabled when the WPEN
bit is set to “1”.
6
AT25HP256/512
1113L–SEEPR–3/06
AT25HP256/512
SPI Serial Interface
Figure 2. Functional Description
AT25HP256/512
7
1113L–SEEPR–3/06
The AT25HP256/512 is designed to interface directly with the synchronous serial
peripheral interface (SPI) of the 6800 type series of microcontrollers.
The AT25HP256/512 utilizes an 8-bit instruction register. The list of instructions and
their operation codes are contained in Table 5. All instructions, addresses, and data are
transferred with the MSB first and start with a high-to-low CS transition.
Table 5. Instruction Set for the AT25HP256/512
Instruction Name
Instruction Format
Operation
WREN
0000 X110
Set Write Enable Latch
WRDI
0000 X100
Reset Write Enable Latch
RDSR
0000 X101
Read Status Register
WRSR
0000 X001
Write Status Register
READ
0000 X011
Read Data from Memory Array
WRITE
0000 X010
Write Data to Memory Array
WRITE ENABLE (WREN): The device will power up in the write disable state when VCC
is applied. All programming instructions must therefore be preceded by a Write Enable
instruction.
WRITE DISABLE (WRDI): To protect the device against inadvertent writes, the Write
Disable instruction disables all programming modes. The WRDI instruction is independent of the status of the WP pin.
READ STATUS REGISTER (RDSR): The Read Status Register instruction provides
access to the status register. The Ready/Busy and Write Enable status of the device
can be determined by the RDSR instruction. Similarly, the block write protection bits
indicate the extent of protection employed. These bits are set by using the WRSR
instruction.
Table 6. Status Register Format
8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
WPEN
X
X
X
BP1
BP0
WEN
RDY
AT25HP256/512
1113L–SEEPR–3/06
AT25HP256/512
Table 7. Read Status Register Bit Definition
Bit
Definition
Bit 0 (RDY)
Bit 0 = “0” (RDY) indicates the device is ready. Bit 0 = “1” indicates the write
cycle is in progress.
Bit 1 (WEN)
Bit 1= “0” indicates the device is not write-enabled. Bit 1 = “1” indicates the
device is write-enabled.
Bit 2 (BP0)
See Table 8.
Bit 3 (BP1)
See Table 8.
Bits 4-6 are “0”s when device is not in an internal write cycle.
Bit 7 (WPEN)
See Table 9.
Bits 0-7 are “1”s during an internal write cycle.
WRITE STATUS REGISTER (WRSR): The WRSR instruction allows the user to select
one of four levels of protection. The AT25HP256/512 is divided into four array segments. Top quarter (1/4), top half (1/2), or all of the memory segments can be protected.
Any of the data within any selected segment will therefore be READ only. The block
write protection levels and corresponding status register control bits are shown in Table
8.
The three bits, BP0, BP1, and WPEN are nonvolatile cells that have the same properties
and functions as the regular memory cells (e.g., WREN, tWC, RDSR).
Table 8. Block Write Protect Bits
Status Register Bits
Level
Array Addresses Protected
BP1
BP0
AT25HP256/512
0
0
0
None
1(1/4)
0
1
6000 - 7FFF/C000 - FFFF
2(1/2)
1
0
4000 - 7FFF/8000 - FFFF
3(All)
1
1
0000 - 7FFF/0000 - FFFF
The WRSR instruction also allows the user to enable or disable the write protect (WP)
pin through the use of the write protect enable (WPEN) bit. Hardware write protection is
enabled when the WP pin is low and the WPEN bit is “1”. Hardware write protection is
disabled when either the WP pin is high or the WPEN bit is “0.” When the device is hardware write protected, writes to the status register, including the block protect bits and the
WPEN bit, and the block-protected sections in the memory array are disabled. Writes
are only allowed to sections of the memory which are not block-protected.
NOTE: When the WPEN bit is hardware write protected, it cannot be changed back to
“0” as long as the WP pin is held low.
Table 9. WPEN Operation
WPEN
WP
WEN
ProtectedBlocks
UnprotectedBlocks
Status Register
0
X
0
Protected
Protected
Protected
0
X
1
Protected
Writable
Writable
1
Low
0
Protected
Protected
Protected
9
1113L–SEEPR–3/06
Table 9. WPEN Operation (Continued)
WPEN
WP
WEN
ProtectedBlocks
UnprotectedBlocks
Status Register
1
Low
1
Protected
Writable
Protected
X
High
0
Protected
Protected
Protected
X
High
1
Protected
Writable
Writable
READ SEQUENCE (READ): Reading the AT25HP256/512 via the SO pin requires the
following sequence. After the CS line is pulled low to select a device, the read op-code
is transmitted via the SI line followed by the byte address to be read (see Table 10).
Upon completion, any data on the SI line will be ignored. The data (D7–D0) at the specified address is then shifted out onto the SO line. If only one byte is to be read, the CS
line should be driven high after the data comes out. The read sequence can be continued since the byte address is automatically incremented and data will continue to be
shifted out. When the highest address is reached, the address counter will roll over to
the lowest address allowing the entire memory to be read in one continuous read cycle.
WRITE SEQUENCE (WRITE): In order to program the AT25HP256/512, two separate
instructions must be executed. First, the device must be write enabled via the WREN
instruction. Then a Write instruction may be executed. Also, the address of the memory
location(s) to be programmed must be outside the protected address field location
selected by the block write protection level. During an internal write cycle, all commands
will be ignored except the RDSR instruction.
A Write instruction requires the following sequence. After the CS line is pulled low to
select the device, the Write op-code is transmitted via the SI line followed by the byte
address and the data (D7–D0) to be programmed (see Table 10). Programming will start
after the CS pin is brought high. The Low-to-High transition of the CS pin must occur
during the SCK low time immediately after clocking in the D0 (LSB) data bit.
The Ready/Busy status of the device can be determined by initiating a Read Status
Register (RDSR) instruction. If Bit 0 = “1”, the write cycle is still in progress. If Bit 0 = “0”,
the write cycle has ended. Only the RDSR instruction is enabled during the write programming cycle.
The AT25HP256/512 is capable of a 128-byte page write operation. After each byte of
data is received, the seven low-order address bits are internally incremented by one; the
high-order bits of the address will remain constant. If more than 128 bytes of data are
transmitted, the address counter will roll over and the previously written data will be
overwritten. The AT25HP256/512 is automatically returned to the write disable state at
the completion of a write cycle.
NOTE: If the device is not write enabled (WREN), the device will ignore the Write
instruction and will return to the standby state, when CS is brought high. A new CS falling edge is required to reinitiate the serial communication.
Table 10. Address Key
Address
AT25HP256/512
AN
A14 – A0 / A15 – A0
Don’t Care Bits
A15 / none
NOTE: 128-byte Page Write operation only. Content of the page in the array will not be
guaranteed if less than 128 bytes of data is received (byte write is not supported).
10
AT25HP256/512
1113L–SEEPR–3/06
AT25HP256/512
Timing Diagrams (for SPI Mode 0 (0,0))
Figure 3. Synchronous Data Timing
tCS
VIH
CS
VIL
tCSS
tCSH
VIH
SKC
VIL
tSU
SI
tWL
tWH
tH
VIH
VALID IN
VIL
tV
VOH
tDIS
HI - Z
HI - Z
SO
tHO
VOL
Figure 4. WREN Timing
CS
SCK
SI
SO
Figure 5. WRDI Timing
CS
SCK
SI
SO
WRDI OP-CODE
HI-Z
11
1113L–SEEPR–3/06
Figure 6. RDSR Timing
CS
0
1
2
3
4
5
6
7
8
9
10
7
6
5
11
12
13
14
15
2
1
0
SCK
SI
SO
INSTRUCTION
HIGH IMPEDANCE
DATA OUT
4
3
MSB
Figure 7. WRSR Timing
Figure 8. READ Timing
12
AT25HP256/512
1113L–SEEPR–3/06
AT25HP256/512
Figure 9. WRITE Timing (AT25HP256)
CS
0
1
2
3
4
5
6
7
8
9
10 11 20 21 22 23
24 25 26
27
28 29 30
31
SCK
1ST BYTE DATA IN
BYTE ADDRESS
15 14 13
INSTRUCTION
SI
...
3
2
1
0
7
6
5
4
3
2
1
0
HIGH IMPEDANCE
SO
Figure 10. PAGE WRITE Timing (AT25HP512)
CS
0
1
2
3
4
5
6
7
8
9
10 11 20 21 22 23
24 25 26 1043 1044 1045 1046 1047
SCK
BYTE ADDRESS 1st BYTE DATA IN
15 14 13 12
INSTRUCTION
SI
3
2
1
0
7
6
5
128th BYTE DATA IN
4
3
2
1
0
HIGH IMPEDANCE
SO
Figure 11. HOLD Timing
CS
tCD
tCD
SCK
tHD
tHD
HOLD
tHZ
SO
tLZ
13
1113L–SEEPR–3/06
AT25HP256 Ordering Information(1)
Ordering Code
(2)
AT25HP256-10PU-2.7
AT25HP256-10PU-1.8(2)
AT25HP256W-10SU-2.7(2)
AT25HP256W-10SU-1.8(2)
AT25HP256C1-10CU-2.7(2)
AT25HP256C1-10CU-1.8(2)
AT25HP256Y4-10YU-1.8(2)
AT25HP256-W2.7-11(3)
AT25HP256-W1.8-11(3)
Notes:
Package
Operation Range
8P3
8P3
8S2
8S2
8CN1
8CN1
8Y4
Lead-free/Halogen-free/
Industrial Temperature
(–40°C to 85°C)
Die Sale
Die Sale
Industrial Temperature
(–40°C to 85°C)
1. This device is not recommended for new design. Please refer to AT25256A datasheet. For 2.7 devices used in 4.5V to 5.5V
range, please refer to performance values in the AC and DC characteristics table.
2. “U” designates Green Package & RoHS compliant.
3. Available in waffle pack and wafer form; order as SL719 for wafer form. Bumped die available upon request. Please contact
Serial EEPROM marketing.
Package Type
8CN1
8-lead, 0.300” Wide, Leadless Array Package (LAP)
8P3
8-lead, 0.300" Wide, Plastic Dual In-line Package (PDIP)
8S2
8-lead, 0.200" Wide, Plastic Small Outline Package (EIAJ)
8Y4
8-lead, 6.00 mm x 4.90 mm Body, Dual Footprint, Non-leaded, Small Array Package (SAP)
Options
–2.7
Low Voltage (2.7V to 5.5V)
–1.8
Low Voltage (1.8V to 5.5V)
14
AT25HP256/512
1113L–SEEPR–3/06
AT25HP256/512
AT25HP512 Ordering Information(1)
Ordering Code
Package
Operation Range
AT25HP512C1-10CI-2.7
AT25HP512-10PI-2.7
AT25HP512W2-10SI-2.7
8CN1
8P3
16S2
Industrial Temperature
(–40°C to 85°C)
AT25HP512C1-10CI-1.8
AT25HP512-10PI-1.8
AT25HP512W2-10SI-1.8
8CN1
8P3
16S2
Industrial Temperature
(–40°C to 85°C)
AT25HP512C1-10CU-2.7(2)
AT25HP512C1-10CU-1.8(2)
AT25HP512-10PU-2.7(2)
AT25HP512-10PU-1.8(2)
AT25HP512W2-10SU-2.7(2)
AT25HP512W2-10SU-1.8(2)
8CN1
8CN1
8P3
8P3
16S2
16S2
Lead-free/ Halogen-free
Industrial Temperature
(–40°C to 85°C)
Die Sale
Die Sale
Industrial Temperature
(–40°C to 85°C)
AT25HP512-W2.7-11(3)
AT25HP512-W1.8-11(3)
Notes:
1. For 2.7V devices used in the 4.5V to 5.5V range, please refer to performance values in the AC and DC characteristics tables.
2. “U” designates Green Package & RoHS compliant.
3. Available in waffle pack and wafer form; order as SL719 for wafer form. Bumped die available upon request. Contact Serial
EEPROM marketing.
Package Type
8CN1
8-lead, 0.300" Wide, Leadless Array Package (LAP)
8P3
8-lead, 0.300" Wide, Plastic Dual In-line Package (PDIP)
16S2
16-lead, 0.300" Wide, Plastic Gull Wing Small Outline Package (JEDEC SOIC)
Options
–2.7
Low Voltage (2.7V to 5.5V)
–1.8
Low Voltage (1.8V to 5.5V)
15
1113L–SEEPR–3/06
Packaging Information
8CN1 – LAP
Marked Pin1 Indentifier
E
A
A1
D
Top View
Side View
Pin1 Corner
L1
0.10 mm
TYP
8
1
e
7
COMMON DIMENSIONS
(Unit of Measure = mm)
2
3
6
b
5
4
e1
L
Bottom View
Note:
SYMBOL
MIN
NOM
MAX
A
0.94
1.04
1.14
A1
0.30
0.34
0.38
b
0.36
0.41
0.46
D
7.90
8.00
8.10
E
4.90
5.00
5.10
e
NOTE
1
1.27 BSC
e1
0.60 REF
L
0.62
.0.67
0.72
1
L1
0.92
0.97
1.02
1
1. Metal Pad Dimensions.
11/13/01
R
16
2325 Orchard Parkway
San Jose, CA 95131
TITLE
8CN1, 8-lead (8 x 5 x 1.04 mm Body), Lead Pitch 1.27 mm,
Leadless Array Package (LAP)
DRAWING NO.
8CN1
REV.
A
AT25HP256/512
1113L–SEEPR–3/06
AT25HP256/512
8P3 – PDIP
E
1
E1
N
Top View
c
eA
End View
COMMON DIMENSIONS
(Unit of Measure = inches)
D
e
D1
A2 A
SYMBOL
A
b2
b3
b
4 PLCS
Side View
L
NOM
MAX
NOTE
–
–
0.210
2
A2
0.115
0.130
0.195
b
0.014
0.018
0.022
5
b2
0.045
0.060
0.070
6
b3
0.030
0.039
0.045
6
c
0.008
0.010
0.014
D
0.355
0.365
0.400
3
D1
0.005
–
–
3
E
0.300
0.310
0.325
4
E1
0.240
0.250
0.280
3
e
0.100 BSC
eA
0.300 BSC
L
Notes:
MIN
0.115
0.130
4
0.150
2
1. This drawing is for general information only; refer to JEDEC Drawing MS-001, Variation BA, for additional information.
2. Dimensions A and L are measured with the package seated in JEDEC seating plane Gauge GS-3.
3. D, D1 and E1 dimensions do not include mold Flash or protrusions. Mold Flash or protrusions shall not exceed 0.010 inch.
4. E and eA measured with the leads constrained to be perpendicular to datum.
5. Pointed or rounded lead tips are preferred to ease insertion.
6. b2 and b3 maximum dimensions do not include Dambar protrusions. Dambar protrusions shall not exceed 0.010 (0.25 mm).
01/09/02
R
2325 Orchard Parkway
San Jose, CA 95131
TITLE
8P3, 8-lead, 0.300" Wide Body, Plastic Dual
In-line Package (PDIP)
DRAWING NO.
REV.
8P3
B
17
1113L–SEEPR–3/06
16S2 – JEDEC SOIC
C
1
H
L
E
N
A1
Top View
End View
e
COMMON DIMENSIONS
(Unit of Measure = inches)
b
A
D
Side View
MIN
NOM
A
0.0926
–
0.1043
A1
0.0040
–
0.0118
b
0.0130
–
0.0200
C
0.0091
–
0.0125
D
0.3977
–
0.4133
2
E
0.2914
–
0.2992
3
H
0.3940
–
0.4190
L
0.0160
–
0.050
SYMBOL
e
MAX
NOTE
5
4
0.050 BSC
Notes: 1. This drawing is for general information only; refer to JEDEC drawing MS-013, Variation AA, for additional information.
2. Dimension D does not include mold Flash, protrusions or gate burrs. Mold Flash, protrusions and gate burrs shall not exceed
3. Dimension E does not include inter-lead Flash or protrusion. Inter-lead Flash and protrusions shall not exceed 0.25 mm
4.
5. The lead width B, as measured 0.36 mm (0.014") or greater above the seating plane, shall not exceed a maximum value of 0.61 mm
(0.024") per side.
1/9/02
R
18
2325 Orchard Parkway
San Jose, CA 95131
TITLE
16S2, 16-lead, 0.300" Wide Body, Plastic Gull
Wing Small Outline Package (SOIC)
DRAWING NO.
16S2
REV.
A
AT25HP256/512
1113L–SEEPR–3/06
AT25HP256/512
8S2 – EIAJ SOIC
C
1
E
E1
L
N
Top View
∅
End View
e
b
COMMON DIMENSIONS
(Unit of Measure = mm)
A
SYMBOL
A1
D
Side View
NOM
MAX
NOTE
A
1.70
2.16
A1
0.05
0.25
b
0.35
0.48
5
C
0.15
0.35
5
D
5.13
5.35
E1
5.18
5.40
E
7.70
8.26
L
0.51
0.85
∅
0°
8°
e
Notes: 1.
2.
3.
4.
5.
MIN
1.27 BSC
2, 3
4
This drawing is for general information only; refer to EIAJ Drawing EDR-7320 for additional information.
Mismatch of the upper and lower dies and resin burrs are not included.
It is recommended that upper and lower cavities be equal. If they are different, the larger dimension shall be regarded.
Determines the true geometric position.
Values b and C apply to pb/Sn solder plated terminal. The standard thickness of the solder layer shall be 0.010 +0.010/−0.005 mm.
10/7/03
R
2325 Orchard Parkway
San Jose, CA 95131
TITLE
8S2, 8-lead, 0.209" Body, Plastic Small
Outline Package (EIAJ)
DRAWING NO.
8S2
REV.
C
19
1113L–SEEPR–3/06
8Y4 – SAP
PIN 1 INDEX AREA
A
D1
PIN 1 ID
D
E1
L
A1
E
e
b
e1
A
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL
MIN
NOM
MAX
A
–
–
0.90
A1
0.00
–
0.05
D
5.80
6.00
6.20
E
4.70
4.90
5.10
D1
2.85
3.00
3.15
E1
2.85
3.00
3.15
b
0.35
0.40
0.45
e
1.27 TYP
e1
3.81 REF
L
0.50
0.60
NOTE
0.70
5/24/04
R
20
1150 E. Cheyenne Mtn. Blvd.
Colorado Springs, CO 80906
TITLE
8Y4, 8-lead (6.00 x 4.90 mm Body) SOIC Array Package
(SAP) Y4
DRAWING NO.
REV.
8Y4
A
AT25HP256/512
1113L–SEEPR–3/06
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