AT25M01-SSHM-T

AT25M01 SPI Serial EEPROM 1-Mbit (131,072 x 8) DATASHEET Features  Serial Peripheral Interface (SPI) Compatible Supports SPI Modes 0 (0,0) and 3 (1,1) Datasheet Describes Mode 0 Operation Low-voltage Operation  High Frequency Operation    ̶ ̶ VCC = 1.7V to 5.5V 20MHz Clock Rate Capable from 4.5V to 5.5V VCC 10MHz Clock Rate Capable from 2.5V to 5.5V VCC 5MHz Clock Rate Capable from 1.7V to 5.5V VCC ̶ ̶   256-byte Page Mode and Byte Write Operation Supported Block Write Protection ̶    Protect ¼, ½, or Entire Array Write Protect (WP) Pin and Write Disable Instructions for Both Hardware and Software Data Protection Self-timed Write Cycle (5ms max) High-reliability ̶ Endurance: 1,000,000 Write Cycles Data Retention: 100 Years ̶  Green Package Options (Pb/Halide-free/RoHS Compliant)  Die Sales Options: Wafer Form, Waffle Pack, and Bumped Die ̶ 8-lead JEDEC SOIC, 8-lead EIAJ SOIC, and 8-ball WLCSP Description The Atmel® AT25M01 provides 1,048,576 bits of Serial Electrically Erasable Programmable Read-Only Memory (EEPROM) organized as 131,072 words of 8 bits each. The device is optimized for use in many industrial and commercial applications where low-power and low-voltage operation are essential. The AT25M01 is enabled through the Chip Select pin (CS) and accessed via a 3-wire interface consisting of Serial Data Input (SI), Serial Data Output (SO), and Serial Clock (SCK). All programming cycles are completely self-timed, and no separate Erase cycle is required before Write. Block Write protection is enabled by programming the status register with top ¼, top ½ or entire array of write protection. Separate Program Enable and Program Disable instructions are provided for additional data protection. Hardware data protection is provided via the WP pin to protect against inadvertent write attempts to the status register. The HOLD pin may be used to suspend any serial communication without resetting the serial sequence. Atmel-8824E-SEEPROM-AT25M01-Datasheet_052016 1. Pin Configurations Figure 1. 2. Pin Configurations 8-lead SOIC Function CS Chip Select SO Serial Data Output CS 1 WP Write Protect SO 2 7 HOLD WP 3 6 SCK GND 4 5 SI GND Ground SI Serial Data Input SCK Serial Data Clock HOLD Suspends Serial Input VCC Device Power Supply 8 VCC Top View VCC SI SCK WP HOLD SO CS GND Bottom View * Note: Drawings are not to scale. Absolute Maximum Ratings* Operating Temperature . . . . . . . . . . -55°C to +125°C Storage Temperature . . . . . . . . . . . . -65°C to +150°C Voltage on Any Pin with Respect to Ground . . . . . . . . . . . . -1.0V to +7.0V Maximum Operating Voltage . . . . . . . . . . . . . . . 6.25V DC Output Current . . . . . . . . . . . . . . . . . . . . . . .5.0mA 2 8-ball WLCSP Pin Name AT25M01 [DATASHEET] Atmel-8824E-SEEPROM-AT25M01-Datasheet_052016 *Notice: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 3. Block Diagram Figure 3-1. Block Diagram VCC Status Register GND Memory Array 131,072 x 8 Address Decoder Data Register Output Buffer SI CS WP SCK Mode Decode Logic Clock Generator SO HOLD AT25M01 [DATASHEET] Atmel-8824E-SEEPROM-AT25M01-Datasheet_052016 3 4. Electrical Specifications 4.1 Pin Capacitance Table 4-1. Pin Capacitance(1) Applicable over recommended operating range from TA = 25°C, f = 1.0MHz, VCC = 5.0V (unless otherwise noted). Symbol Test Conditions COUT CIN Note: 4.2 1. Max Units Conditions Output Capacitance (SO) 8 pF VOUT = 0V Input Capacitance (CS, SCK, SI, WP, HOLD) 6 pF VIN = 0V This parameter is characterized and is not 100% tested. DC Characteristics Table 4-2. DC Characteristics Applicable over recommended operating range from TAI = -40°C to +85°C, VCC = 1.7V to 5.5V, (unless otherwise noted). Symbol Parameter VCC1 Supply Voltage VCC2 Max Units 1.7 5.5 V Supply Voltage 2.5 5.5 V VCC3 Supply Voltage 4.5 5.5 V ICC1 Supply Current VCC = 5.0V at 20MHz, SO = Open, Read 7.0 10.0 mA ICC2 Supply Current VCC = 5.0V at 10MHz, SO = Open, Read, Write 5.0 7.0 mA ICC3 Supply Current VCC = 5.0V at 1MHz, SO = Open, Read, Write 2.2 3.5 mA ISB1 Standby Current VCC = 1.7V, CS = VCC 0.2 3.0 μA ISB2 Standby Current VCC = 2.5V, CS = VCC 0.4 3.0 μA ISB3 Standby Current VCC = 5.0V, CS = VCC 2.0 5.0 μA IIL Input Leakage VIN = 0V to VCC -3.0 3.0 μA IOL Output Leakage VIN = 0V to VCC, TAC = 0°C to 70°C -3.0 3.0 μA Input Low-voltage -1.0 VCC x 0.3 V VIH Input High-voltage VCC x 0.7 VCC + 0.5 V VOL1 Output Low-voltage 0.4 V VOH1 Output High-voltage VOL2 Output Low-voltage VOH2 Output High-voltage VIL(1) (1) Note: 4 1. Test Condition 3.6  VCC  5.5V 1.7V  VCC  3.6V Min IOL = 3.0mA IOH = 1.6mA VIL min and VIH max are reference only and are not tested. AT25M01 [DATASHEET] Atmel-8824E-SEEPROM-AT25M01-Datasheet_052016 VCC – 0.8 IOL = 0.15mA IOH = 100μA Typ V 0.2 VCC – 0.2 V V 4.3 AC Characteristics Table 4-3. AC Characteristics Applicable over recommended operating range from TAI = -40°C to + 85°C, VCC = As Specified, CL = 1TTL Gate and 30pF (unless otherwise noted). Symbol Parameter Voltage Min Max Units fSCK SCK Clock Frequency 4.5V – 5.5V 2.5V – 5.5V 1.7V – 5.5V 0 0 0 20 10 5 MHz tRI Input Rise Time 4.5V – 5.5V 2.5V – 5.5V 1.7V – 5.5V 15 40 80 ns tFI Input Fall Time 4.5V – 5.5V 2.5V – 5.5V 1.7V – 5.5V 15 40 80 ns tWH SCK High Time 4.5V – 5.5V 2.5V – 5.5V 1.7V – 5.5V 20 40 80 ns tWL SCK Low Time 4.5V – 5.5V 2.5V – 5.5V 1.7V – 5.5V 20 40 80 ns tCS CS High Time 4.5V – 5.5V 2.5V – 5.5V 1.7V – 5.5V 100 100 200 ns tCSS CS Setup Time 4.5V – 5.5V 2.5V – 5.5V 1.7V – 5.5V 100 100 200 ns tCSH CS Hold Time 4.5V – 5.5V 2.5V – 5.5V 1.7V – 5.5V 100 100 200 ns tSU Data In Setup Time 4.5V – 5.5V 2.5V – 5.5V 1.7V – 5.5V 5 10 20 ns tH Data In Hold Time 4.5V – 5.5V 2.5V – 5.5V 1.7V – 5.5V 5 10 20 ns tHD Hold Setup Time 4.5V – 5.5V 2.5V – 5.5V 1.7V – 5.5V 5 10 20 ns tCD Hold Hold Time 4.5V – 5.5V 2.5V – 5.5V 1.7V – 5.5V 5 10 20 ns tV Output Valid 4.5V – 5.5V 2.5V – 5.5V 1.7V – 5.5V 0 0 0 tHO Output Hold Time 4.5V – 5.5V 2.5V – 5.5V 1.7V – 5.5V 0 0 0 20 40 80 ns ns AT25M01 [DATASHEET] Atmel-8824E-SEEPROM-AT25M01-Datasheet_052016 5 Table 4-3. AC Characteristics (Continued) Applicable over recommended operating range from TAI = -40°C to + 85°C, VCC = As Specified, CL = 1TTL Gate and 30pF (unless otherwise noted). Symbol Parameter Voltage Min Max Units tLZ Hold to Output Low Z 4.5V – 5.5V 2.5V – 5.5V 1.7V – 5.5V 0 0 0 25 50 100 ns tHZ Hold to Output High Z 4.5V – 5.5V 2.5V – 5.5V 1.7V – 5.5V 25 50 100 ns tDIS Output Disable Time 4.5V – 5.5V 2.5V – 5.5V 1.7V – 5.5V 25 50 100 ns tWC Write Cycle Time 4.5V – 5.5V 2.5V – 5.5V 1.7V – 5.5V 5 5 5 ms Endurance(1) 25°C, Page Mode, 5.0V Notes: 5. 1. 1,000,000 Write Cycles This parameter is characterized and is not 100% tested. Contact Atmel for further information. Serial Interface Description Master: The device that generates the serial clock. Slave: Because the Serial Clock pin (SCK) is always an input, the AT25M01 always operates as a slave. Transmitter/Receiver: The AT25M01 has separate pins designated for data transmission (SO) and reception (SI). MSB: The Most Significant Bit (MSB) is the first bit transmitted and received. Serial Opcode: After the device is selected with CS going low, the first byte will be received. This byte contains the opcode that defines the operations to be performed. Invalid Opcode: If an invalid opcode is received, no data will be shifted into the AT25M01, and the Serial Output pin (SO) will remain in a high-impedance state until the falling edge of CS is detected again. This will reinitialize the serial communication. Chip Select: The AT25M01 is selected when the CS pin is low. When the device is not selected, data will not be accepted via the SI pin, and the Serial Output pin (SO) will remain in a high impedance state. Hold: The HOLD pin is used in conjunction with the CS pin to select the AT25M01. When the device is selected and a serial sequence is underway, Hold can be used to pause the serial communication with the master device without resetting the serial sequence. To pause, the HOLD pin must be brought low while the SCK pin is low. To resume serial communication, the HOLD pin is brought high while the SCK pin is low (SCK may still toggle during HOLD). Inputs to the SI pin will be ignored while the SO pin is in the high impedance state. Write Protect: The Write Protect pin (WP) will allow normal read/write operations when held high. When the WP pin is brought low, and WPEN bit is one, all write operations to the status register are inhibited. WP going low while CS is still low will interrupt a write to the status register. If the internal write cycle has already been initiated, WP going low will have no effect on any write operation to the status register. The WP pin function is blocked when the WPEN bit in the status register is zero. This will allow the user to install the AT25M01 in a system with the WP pin tied to ground and still be able to write to the status register. All WP pin functions are enabled when the WPEN bit is set to one. 6 AT25M01 [DATASHEET] Atmel-8824E-SEEPROM-AT25M01-Datasheet_052016 Figure 5-1. SPI Serial Interface Master: Microcontroller Data Out (MOSI) Data In (MISO) Serial Clock (SPI CK) SS0 SS1 SS2 SS3 Slave: AT25M01 SI SO SCK CS SI SO SCK CS SI SO SCK CS SI SO SCK CS AT25M01 [DATASHEET] Atmel-8824E-SEEPROM-AT25M01-Datasheet_052016 7 6. Functional Description The AT25M01 is designed to interface directly with the synchronous Serial Peripheral Interface (SPI) of the 6800 type series of microcontrollers. The AT25M01 utilizes an 8-bit instruction register. The list of instructions and their operation codes are contained in Table 6-1. All instructions, addresses, and data are transferred with the MSB first and start with a high-to-low CS transition. Table 6-1. Instruction Set for Atmel AT25M01 Instruction Name Instruction Format Operation WREN 0000 x110 Set Write Enable Latch WRDI 0000 x100 Reset Write Enable Latch RDSR 0000 x101 Read Status Register WRSR 0000 x001 Write Status Register READ 0000 x011 Read Data from Memory Array WRITE 0000 x010 Write Data to Memory Array Write Enable (WREN): The device will power-up in the write disable state when VCC is applied. All programming instructions must therefore be preceded by a Write Enable instruction. Write Disable (WRDI): To protect the device against inadvertent writes, the Write Disable instruction disables all programming modes. The WRDI instruction is independent of the status of the WP pin. Read Status Register (RDSR): The Read Status Register instruction provides access to the status register. The Ready/Busy and Write Enable status of the device can be determined by the RDSR instruction. Similarly, the Block Write Protection bits indicate the extent of protection employed. These bits are set by using the WRSR instruction. Table 6-2. Status Register Format Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 WPEN X X X BP1 BP0 WEN RDY Table 6-3. Read Status Register Bit Detection Bit Definition Bit 0 (RDY) Bit 0 = 0 (RDY) indicates the device is ready. Bit 0 = 1 indicates the write cycle is in progress. Bit 1 (WEN) Bit 1 = 0 indicates the device is not write enabled. Bit 1 = 1 indicates the device is write enabled. Bit 2 (BP0) See Table 6-4 on page 9. Bit 3 (BP1) See Table 6-4 on page 9. Bits 4  6 are zeros when device is not in an internal write cycle. Bit 7 (WPEN) See Table 6-5 on page 9. Bits 0  7 are ones during an internal write cycle. 8 AT25M01 [DATASHEET] Atmel-8824E-SEEPROM-AT25M01-Datasheet_052016 Write Status Register (WRSR): The WRSR instruction allows the user to select one of four levels of protection. The AT25M01 is divided into four array segments. Top quarter (¼), top half (½), or all of the memory segments can be protected. Any of the data within any selected segment will therefore be read-only. The block write protection levels and corresponding status register control bits are shown in Table 6-4. The three bits, BP0, BP1, and WPEN are nonvolatile cells that have the same properties and functions as the regular memory cells (e.g. WREN, tWC, RDSR). Table 6-4. Block Write Protect Bits Status Register Bits Array Addresses Protected Level BP1 BP0 AT25M01 0 0 0 None 1(¼) 0 1 18000h – 1FFFFh 2(½) 1 0 10000h – 1FFFFh 3(All) 1 1 00000h – 1FFFFh The WRSR instruction also allows the user to enable or disable the Write Protect (WP) pin through the use of the Write Protect Enable (WPEN) bit. Hardware Write Protection is enabled when the WP pin is low and the WPEN bit is one. Hardware Write Protection is disabled when either the WP pin is high or the WPEN bit is zero. When the device is hardware write protected, writes to the Status Register, including the Block Protect bits and the WPEN bit, and the block protected sections in the memory array are disabled. Writes are only allowed to sections of the memory which are not block protected (see Table 6-5). Note: When the WPEN bit is hardware write protected, it cannot be changed back to zero, as long as the WP pin is held low. Table 6-5. WPEN Operation WPEN WP WEN Protected Blocks Unprotected Blocks Status Register 0 x 0 Protected Protected Protected 0 x 1 Protected Writable Writable 1 Low 0 Protected Protected Protected 1 Low 1 Protected Writable Protected X High 0 Protected Protected Protected X High 1 Protected Writable Writable Read Sequence (READ): Reading the AT25M01 via the SO pin requires the following sequence. After the CS line is pulled low to select a device, the Read opcode is transmitted via the SI line followed by the a 3-byte address to be read (see Table 6-6 on page 10). Upon completion, any data on the SI line will be ignored. The data (D7 – D0) at the specified address is then shifted out onto the SO line. If only one byte is to be read, the CS line should be driven high after the data comes out. The read sequence can be continued since the byte address is automatically incremented and data will continue to be shifted out. When the highest address is reached, the address counter will roll over to the lowest address allowing the entire memory to be read in one continuous read cycle. AT25M01 [DATASHEET] Atmel-8824E-SEEPROM-AT25M01-Datasheet_052016 9 Write Sequence (Write): In order to program the AT25M01, two separate instructions must be executed. First, the device must be write enabled via the Write Enable (WREN) Instruction. Then, a Write instruction may be executed. Also, the address of the memory location(s) to be programmed must be outside the protected address field location selected by the block write protection level. During an internal write cycle, all commands will be ignored except the RDSR instruction. A Write Instruction requires the following sequence. After the CS line is pulled low to select the device, the Write opcode is transmitted via the SI line followed by the byte address and the data (D7 – D0) to be programmed (see Table 6-6). Programming will start after the CS pin is brought high. (The Low-to-High transition of the CS pin must occur during the SCK low time immediately after clocking in the D0 (LSB) data bit. The Ready/Busy status of the device can be determined by initiating a Read Status Register (RDSR) Instruction. If Bit 0 = 1, the Write cycle is still in progress. If Bit 0 = 0, the Write cycle has ended. Only the Read Status Register instruction is enabled during the Write programming cycle. The AT25M01 is capable of a 256-byte Page Write operation. After each byte of data is received, the eight low order address bits are internally incremented by one; the high order bits of the address will remain constant. If more than 256 bytes of data are transmitted, the address counter will roll-over and the previously written data will be overwritten. The AT25M01 is automatically returned to the write disable state at the completion of a Write cycle. Note: If the device is not Write Enabled (WREN), the device will ignore the Write instruction and will return to the standby state, when CS is brought high. A new CS falling edge is required to re-initiate the serial communication. Table 6-6. Note: 10 Address Key Address AT25M01 A(n) A23  A0 The A23 through A17 address bits of the most significant address byte are don’t care values as these bits fall outside the addressable 1Mbit range. AT25M01 [DATASHEET] Atmel-8824E-SEEPROM-AT25M01-Datasheet_052016 7. Timing Diagrams (for SPI Mode 0 (0, 0)) Figure 7-1. Synchronous Data Timing tCS VIH CS VIL tCSS tCSH VIH tWH SCK tWL VIL tSU tH VIH SI Valid In VIL tV VOH tDIS HI-Z HI-Z SO tHO VOL Figure 7-2. WREN Timing CS SCK SI WREN Opcode HI-Z SO Figure 7-3. WRDI Timing CS SCK SI SO WRDI Opcode HI-Z AT25M01 [DATASHEET] Atmel-8824E-SEEPROM-AT25M01-Datasheet_052016 11 Figure 7-4. RDSR Timing CS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SCK SI Instruction Data Out High-impedance SO 7 6 5 4 3 2 1 0 8 9 10 11 12 13 14 15 MSB Figure 7-5. WRSR Timing CS 0 1 2 3 4 5 6 7 SCK Data In SI 6 5 4 3 2 1 0 High-impedance SO Figure 7-6. 7 Instruction READ Timing CS 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39 SCK Instruction SI Byte Address 23 22 21 ... 3 2 1 0 Data Out SO High-impedance 7 MSB 12 AT25M01 [DATASHEET] Atmel-8824E-SEEPROM-AT25M01-Datasheet_052016 6 5 4 3 2 1 0 Figure 7-7. Write Timing CS 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39 SCK Instruction Byte Address SI SO Figure 7-8. 23 22 21 ... 3 2 Data In 1 0 7 6 5 4 3 2 1 0 High-impedance Hold Timing CS tCD tCD SCK tHD tHD HOLD tHZ SO tLZ AT25M01 [DATASHEET] Atmel-8824E-SEEPROM-AT25M01-Datasheet_052016 13 8. Part Marking AT25M01: Package Marking Information 8-lead EIAJ 8-lead SOIC ATMLHYWW ## % @ AAAAAAAA ATMLHYWW ## % @ AAAAAAAA Note 1: 8-ball WLCSP ATMLUYWW ## % @ AAAAAAAA designates pin 1 Note 2: Package drawings are not to scale Catalog Number Truncation AT25M01 Date Codes Truncation Code ##: 5G Y = Year 5: 2015 6: 2016 7: 2017 8: 2018 WW = Work Week of Assembly 02: Week 2 04: Week 4 ... 52: Week 52 Voltages 9: 2019 0: 2020 1: 2021 2: 2022 Country of Assembly Lot Number @ = Country of Assembly AAA...A = Atmel Wafer Lot Number % = Minimum Voltage L: 1.8V min D: 2.5V min Grade/Lead Finish Material U: Industrial/LeadFree Ball H: Industrial/NiPdAu Atmel Truncation ATML: Atmel 7/9/15 TITLE 25M01SM, AT25M01 Standard Package Marking Information Package Mark Contact: DL-CSO-Assy_eng@atmel.com 14 AT25M01 [DATASHEET] Atmel-8824E-SEEPROM-AT25M01-Datasheet_052016 DRAWING NO. REV. 25M01SM B 9. Ordering Code Detail AT2 5 M 0 1 - S S H M - B Atmel Designator Shipping Carrier Option B = Bulk (Tubes) T = Tape and Reel Product Family Operating Voltage 25 = Standard SPI Serial EEPROM M = 1.7V to 5.5V Device Density Package Device Grade or Wafer/Die Thickness M = Megabit Family 01 = 1 Megabit H = Green, NiPdAu Lead Finish Industrial Temperature Range (-40ºC to 85ºC) U = Green, Matte Tin Lead Finish Industrial Temperature Range (-40ºC to 85ºC) 11 = 11mil Wafer Thickness Package Option SS = JEDEC SOIC S = EIAJ SOIC U = WLCSP WWU = Whole Wafer, Unsawn 10. Ordering Information Additional package types that are not listed below may be available for order. Please contact Atmel for availability details. Delivery Information Atmel Ordering Code Lead Finish Package AT25M01-SSHM-B Form Quantity Bulk (Tubes) 100 per Tube Tape and Reel 4,000 per Reel Bulk (Tubes) 95 per Tube Tape and Reel 2,000 per Reel Tape and Reel 5,000 per Reel Operation Range 8S1 AT25M01-SSHM-T AT25M01-SHM-B NiPdAu (Lead-free/Halogen-free) 8S2 AT25M01-SHM-T AT25M01-UUM-T(1) AT25M01-WWU11M(2) Notes: 1. 2. SnAgCu (Lead-free/Halogen-free) N/A 8U-7 Wafer Sale Industrial Temperature (-40C to 85C) Note 2 WLCSP Package — CAUTION: Exposure to ultraviolet (UV) light can degrade the data stored in the EEPROM cells. Therefore, customers who use a WLCSP product must ensure that exposure to ultraviolet light does not occur. For wafer sales, please contact Atmel Sales. Package Type 8S1 8-lead, 0.150" wide, Plastic Gull Wing Small Outline (JEDEC SOIC) 8S2 8-lead, 0.208" wide, Plastic Small Package Outline (EIAJ SOIC) 8U-7 8-ball, Wafer Level Chip Scale Package (WLCSP) AT25M01 [DATASHEET] Atmel-8824E-SEEPROM-AT25M01-Datasheet_052016 15 11. Packaging Information 11.1 8S1 — 8-lead JEDEC SOIC C 1 E E1 L N Ø TOP VIEW END VIEW e b COMMON DIMENSIONS (Unit of Measure = mm) A A1 D SIDE VIEW Notes: This drawing is for general information only. Refer to JEDEC Drawing MS-012, Variation AA for proper dimensions, tolerances, datums, etc. MIN NOM MAX – – 1.75 A1 0.10 – 0.25 b 0.31 – 0.51 C 0.17 – 0.25 SYMBOL A D 4.90 BSC E 6.00 BSC E1 3.90 BSC e 1.27 BSC L 0.40 – 1.27 Ø 0° – 8° NOTE 3/6/2015 Package Drawing Contact: packagedrawings@atmel.com 16 TITLE 8S1, 8-lead (0.150” Wide Body), Plastic Gull Wing Small Outline (JEDEC SOIC) AT25M01 [DATASHEET] Atmel-8824E-SEEPROM-AT25M01-Datasheet_052016 GPC SWB DRAWING NO. REV. 8S1 H 11.2 8S2 — 8-lead EIAJ SOIC TOP VIEW END VIEW C 1 E E1 L 8 q SIDE VIEW e b A COMMON DIMENSIONS (Unit of Measure = mm) A1 D Notes: 1. This drawing is for general information only; refer to EIAJ Drawing EDR-7320 for additional information. 2. Mismatch of the upper and lower dies and resin burrs aren't included. 3. Determines the true geometric position. 4. Values b,C apply to plated terminal. The standard thickness of the plating layer shall measure between 0.007 to .021 mm. SYMBOL MIN MAX NOM NOTE A 1.70 2.16 A1 0.05 0.25 b 0.35 0.48 4 C 0.15 0.35 4 D 5.13 5.35 E1 5.18 5.40 E 7.70 8.26 L 0.51 0.85 q 0° 8° e 1.27 BSC 2 3 11/10/14 TITLE Package Drawing Contact: packagedrawings@atmel.com 8S2, 8-lead, 0.208” Body, Plastic Small Outline Package (EIAJ) GPC DRAWING NO. REV. STN 8S2 G AT25M01 [DATASHEET] Atmel-8824E-SEEPROM-AT25M01-Datasheet_052016 17 11.3 8U-7 — 8-ball WLCSP TOP VIEW SIDE VIEW BALL SIDE D Pin 1 1 2 3 4 A1 5 Øb 5 3 4 2 1 Pin 1 A A B B E e C C A2 e2 d2 d A Note: Dimensions are not to scale COMMON DIMENSIONS (Unit of Measure = mm) PIN ASSIGNMENT MATRIX A MIN TYP MAX A 0.460 0.499 0.538 A1 0.164 - 0.224 0.280 0.305 0.330 SYMBOL 1 2 3 4 5 VCC n/a HOLD n/a CS A2 B n/a SCK n/a SO n/a C SI n/a WP n/a GND E Contact Atmel for details e 0.867 e2 0.500 d 1.000 d2 0.500 D Contact Atmel for details b NOTE 0.239 0.269 0.299 07/19/2015 Package Drawing Contact: packagedrawings@atmel.com 18 AT25M01 [DATASHEET] Atmel-8824E-SEEPROM-AT25M01-Datasheet_052016 TITLE GPC DRAWING NO. REV. 8U-7, 8-ball (5x3 Array) Wafer Level Chip-Scale Package (WLCSP) GXG 8U-7 D 12. Revision History Doc. Rev. Date Comments 8823E 05/2016 Correct ordering information WLCSP note. 8823D 07/2015 Update the tRI and tFI maximum values, part markings page, and the 8S1 and 8U-7 package drawings. 8823C 01/2015 Correct the Write Timing figure. Update the 8S2 and 8U-7 package drawings, the ordering information section, and the disclaimer page. Add part marking. 8823B 03/2013 Update datasheet status from advance to complete. Update footers and Atmel fax number. 8823A 12/2012 Initial document release. AT25M01 [DATASHEET] Atmel-8824E-SEEPROM-AT25M01-Datasheet_052016 19 XXXXXX Atmel Corporation 1600 Technology Drive, San Jose, CA 95110 USA T: (+1)(408) 441.0311 F: (+1)(408) 436.4200 | www.atmel.com © 2016 Atmel Corporation. / Rev.: Atmel-8824E-SEEPROM-AT25M01-Datasheet_052016. Atmel®, Atmel logo and combinations thereof, Enabling Unlimited Possibilities®, and others are registered trademarks or trademarks of Atmel Corporation in U.S. and other countries. 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