AT25M02
SPI Serial EEPROM 2 Mbits (262,144 x 8)
Features
• Serial Peripheral Interface (SPI) Compatible
• Supports SPI Modes 0 (0,0) and 3 (1,1):
– Data sheet describes mode 0 operation
• Low-Voltage and Standard-Voltage Operation:
– 1.7V (VCC = 1.7V to 5.5V)
– 2.5V (VCC = 2.5V to 5.5V)
• Industrial Temperature Range: -40°C to +85°C
• 5 MHz Clock Rate (5V)
• 256‑Byte Page Mode
• Block Write Protection:
– Protect 1/4, 1/2 or entire array
• Write-Protect (WP) Pin and Write Disable Instructions for Both Hardware and Software Data
Protection
• Self-Timed Write Cycle within 10 ms Maximum
• ESD Protection > 4,000V
• High Reliability:
– Endurance: 1,000,000 write cycles
– Data retention: 100 years
• Green (Lead-free/Halide-free/RoHS Compliant) Package Options
• Die Sale Options: Wafer Form and Bumped Wafers
Packages
• 8-Lead SOIC and 8-Ball WLCSP
© 2019 Microchip Technology Inc.
Datasheet
20006230A-page 1
AT25M02
Table of Contents
Features.......................................................................................................................... 1
Packages.........................................................................................................................1
1. Package Types (not to scale).................................................................................... 4
2. Pin Description.......................................................................................................... 5
2.1.
2.2.
2.3.
2.4.
2.5.
2.6.
2.7.
2.8.
Chip Select (CS)...........................................................................................................................5
Serial Data Output (SO)............................................................................................................... 5
Write-Protect (WP)....................................................................................................................... 5
Ground (GND).............................................................................................................................. 5
Serial Data Input (SI)....................................................................................................................6
Serial Data Clock (SCK)...............................................................................................................6
Suspend Serial Input (HOLD).......................................................................................................6
Device Power Supply (VCC)......................................................................................................... 6
3. Description.................................................................................................................7
3.1.
3.2.
SPI Bus Master Connections to Serial EEPROMs.......................................................................7
Block Diagram.............................................................................................................................. 8
4. Electrical Characteristics........................................................................................... 9
4.1.
4.2.
4.3.
4.4.
4.5.
4.6.
Absolute Maximum Ratings..........................................................................................................9
DC and AC Operating Range.......................................................................................................9
DC Characteristics....................................................................................................................... 9
AC Characteristics......................................................................................................................11
SPI Synchronous Data Timimg.................................................................................................. 12
Electrical Specifications..............................................................................................................12
5. Device Operation.....................................................................................................14
5.1.
5.2.
5.3.
5.4.
Interfacing the AT25M02 on the SPI Bus................................................................................... 14
Device Opcodes......................................................................................................................... 15
Hold Function............................................................................................................................. 15
Write Protection..........................................................................................................................16
6. Device Commands and Addressing........................................................................ 17
6.1.
6.2.
STATUS Register Bit Definition and Function............................................................................ 17
Read STATUS Register (RDSR) and Low-Power Write Poll (LPWP)........................................... 18
6.3.
Write Enable (WREN) and Write Disable (WRDI)......................................................................... 19
6.4.
Write STATUS Register (WRSR).................................................................................................. 20
7. Read Sequence.......................................................................................................23
8. Write Sequence....................................................................................................... 24
8.1.
8.2.
8.3.
Byte Write...................................................................................................................................24
Page Write..................................................................................................................................24
Internal Writing Methodology......................................................................................................25
© 2019 Microchip Technology Inc.
Datasheet
20006230A-page 2
AT25M02
8.4.
Polling Routine........................................................................................................................... 25
9. Packaging Information.............................................................................................27
9.1.
Package Marking Information.....................................................................................................27
10. Revision History.......................................................................................................32
The Microchip Website.................................................................................................. 33
Product Change Notification Service.............................................................................33
Customer Support......................................................................................................... 33
Product Identification System........................................................................................ 34
Microchip Devices Code Protection Feature................................................................. 34
Legal Notice...................................................................................................................35
Trademarks................................................................................................................... 35
Quality Management System........................................................................................ 36
Worldwide Sales and Service........................................................................................37
© 2019 Microchip Technology Inc.
Datasheet
20006230A-page 3
AT25M02
Package Types (not to scale)
1.
Package Types (not to scale)
8-Lead SOIC
(Top View)
CS
1
8
Vcc
SO
2
7
HOLD
WP
3
6
SCK
GND
4
5
SI
8-Ball WLCSP
(Top View)
Vcc
CS
SO
HOLD
SCK
WP
SI
© 2019 Microchip Technology Inc.
GND
Datasheet
20006230A-page 4
AT25M02
Pin Description
2.
Pin Description
The descriptions of the pins are listed in Table 2-1.
Table 2-1. Pin Function Table
Name
8-Lead SOIC
8-Ball WLCSP
CS
1
A3
Function
Chip Select
SO
WP(1)
2
B4
Serial Data Output
3
C4
Write-Protect
GND
4
D3
Ground
SI
5
D2
Serial Data Input
SCK
HOLD(1)
6
C1
Serial Data Clock
7
B2
Suspends Serial Input
VCC
8
A2
Device Power Supply
Note:
1. The Write-Protect (WP) and Hold (HOLD) pins should be driven high or low as appropriate.
2.1
Chip Select (CS)
The AT25M02 is selected when the Chip Select (CS) pin is low. When the device is not selected, data will
not be accepted via the Serial Data Input (SI) pin, and the Serial Output (SO) pin will remain in
a high‑impedance state.
To ensure robust operation, the CS pin should follow VCC upon power-up. It is therefore recommended to
connect CS to VCC using a pull-up resistor (less than or equal to 10 kΩ). After power-up, a low level on
CS is required prior to any sequence being initiated.
2.2
Serial Data Output (SO)
The Serial Data Output (SO) pin is used to transfer data out of the AT25M02. During a read sequence,
data is shifted out on this pin after the falling edge of the Serial Data Clock (SCK).
2.3
Write-Protect (WP)
The Write-Protect (WP) pin will allow normal read/write operations when held high. When the WP pin is
brought low and the WPEN bit is set to a logic ‘1’, all write operations to the STATUS register are
inhibited. WP going low while CS is still low will interrupt a write operation to the STATUS register. If the
internal write cycle has already been initiated, WP going low will have no effect on any write operation to
the STATUS register. The WP pin function is blocked when the WPEN bit in the STATUS register is set to
a logic ‘0’. This will allow the user to install the AT25M02 in a system with the WP pin tied to ground and
still be able to write to the STATUS register. All WP pin functions are enabled when the WPEN bit is set to
a logic ‘1’.
2.4
Ground (GND)
The ground reference for the Device Power Supply (VCC). The Ground (GND) pin should be connected to
the system ground.
© 2019 Microchip Technology Inc.
Datasheet
20006230A-page 5
AT25M02
Pin Description
2.5
Serial Data Input (SI)
The Serial Data Input (SI) pin is used to transfer data into the device. It receives instructions, addresses
and data. Data is latched on the rising edge of the Serial Data Clock (SCK).
2.6
Serial Data Clock (SCK)
The Serial Data Clock (SCK) pin is used to synchronize the communication between a master and the
AT25M02. Instructions, addresses or data present on the Serial Data Input (SI) pin is latched in on the
rising edge of SCK, while output on the Serial Data Output (SO) pin is clocked out on the falling edge of
SCK.
2.7
Suspend Serial Input (HOLD)
The Suspend Serial Input (HOLD) pin is used in conjunction with the Chip Select (CS) pin to pause the
AT25M02. When the device is selected and a serial sequence is underway, HOLD can be used to pause
the serial communication with the master device without resetting the serial sequence. To pause, the
HOLD pin must be brought low while the Serial Data Clock (SCK) pin is low. To resume serial
communication, the HOLD pin is brought high while the SCK pin is low (SCK may still toggle during
HOLD). Inputs to the Serial Data Input (SI) pin will be ignored while the Serial Data Output (SO) pin will
be in the high‑impedance state.
2.8
Device Power Supply (VCC)
The Device Power Supply (VCC) pin is used to supply the source voltage to the device. Operations at
invalid VCC voltages may produce spurious results and should not be attempted.
© 2019 Microchip Technology Inc.
Datasheet
20006230A-page 6
AT25M02
Description
3.
Description
The AT25M02 provides 2,097,152 bits of Serial Electrically Erasable and Programmable Read-Only
Memory (EEPROM) organized as 262,144 words of 8 bits each. The device is optimized for use in many
industrial and commercial applications where low‑power and low‑voltage operation are essential. The
device is available in space-saving 8‑lead SOIC and 8-ball WLCSP packages. All packages operate from
1.7V to 5.5V or 2.5V to 5.5V.
3.1
SPI Bus Master Connections to Serial EEPROMs
SPI Master:
Microcontroller
Data Clock (SCK)
Data Output (SO)
Data Input (SI)
SI
CS3 CS2 CS1 CS0
© 2019 Microchip Technology Inc.
SO SCK
SI
SO SCK
SI
SO SCK
SI
SO SCK
Slave 0
AT25XXX
Slave 1
AT25XXX
Slave 2
AT25XXX
Slave 3
AT25XXX
CS
CS
CS
CS
Datasheet
20006230A-page 7
AT25M02
Description
Block Diagram
Memory
System Control
Module
CS
High-Voltage
Generation
Circuit
Power-on
Reset
Generator
VCC
Pause
Operation
Control
HOLD
Register Bank:
STATUS Register
SO
EEPROM Array
1 page
WP
Row Decoder
3.2
Column Decoder
Address Register
and Counter
SCK
Data Register
Data Output
Buffer
GND
© 2019 Microchip Technology Inc.
SI
Write Protection
Control
Datasheet
20006230A-page 8
AT25M02
Electrical Characteristics
4.
Electrical Characteristics
4.1
Absolute Maximum Ratings
Operating temperature
-55°C to +125°C
Storage temperature
-65°C to +150°C
Voltage on any pin with respect to ground
-1.0V to +7.0V
VCC
6.25V
DC output current
5.0 mA
ESD protection
> 4 kV
Note: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to
the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operation listings of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
4.2
DC and AC Operating Range
Table 4-1. DC and AC Operating Range
AT25M02
4.3
Operating Temperature (Case)
Industrial Temperature Range
-40°C to +85°C
VCC Power Supply
Low-Voltage Grade
1.7V to 5.5V
Standard-Voltage Grade
2.5V to 5.5V
DC Characteristics
Table 4-2. DC Characteristics (1)
Parameter
Symbol Minimum Typical(1) Maximum Units Conditions
Supply Voltage
VCC1
1.7
—
5.5
V
Supply Voltage
VCC2
2.5
—
5.5
V
Supply Current
ICC1
—
0.3
1.0
mA
VCC = 1.8V(3) at 1 MHz,
SO = Open, Read
Supply Current
ICC2
—
0.5
1.0
mA
VCC = 1.8V(3) at 5 MHz,
SO = Open, Read, Write
Supply Current
ICC3
—
1.0
2.0
mA
VCC = 5.0V at 1 MHz,
SO = Open, Read
Supply Current
ICC4
—
2.0
3.0
mA
VCC = 5.0V at 5 MHz,
SO = Open, Read
© 2019 Microchip Technology Inc.
Datasheet
20006230A-page 9
AT25M02
Electrical Characteristics
...........continued
Parameter
Symbol Minimum Typical(1) Maximum Units Conditions
Supply Current
ICC5
—
0.3
2.0
mA
VCC = 1.8V(3),
SO = Open, During tWC,
CS = VCC
Supply Current
ICC6
—
0.5
3.0
mA
VCC = 5.0V,
SO = Open, During tWC,
CS = VCC
Standby
Current
ISB1
—
0.08
1.0
µA
VCC = 1.8V(3), CS = VCC
Standby
Current
ISB2
—
0.08
2.0
µA
VCC = 2.5V, CS = VCC
Standby
Current
ISB3
—
0.15
3.0
µA
VCC = 5.5V, CS = VCC
Input Leakage
IIL
-3.0
—
3.0
µA
VIN = 0V to VCC
Output
Leakage
IOL
-3.0
—
3.0
µA
VIN = 0V to VCC,
TA = 0°C to +70°C
Input
Low-Voltage
VIL(2)
-1.0
—
VCC x 0.3
V
Input
High-Voltage
VIH(2)
VCC x 0.7
—
VCC + 0.5
V
Output
Low-Voltage
VOL1
—
—
0.4
V
3.6V ≤ VCC ≤ 5.5V IOL = 3.0 mA
Output
High-Voltage
VOH1
VCC - 0.8
—
—
V
3.6V ≤ VCC ≤ 5.5V IOH = -1.6 mA
Output
Low-Voltage
VOL2
—
—
0.2
V
1.7V ≤ VCC ≤ 3.6V IOL = 0.15 mA
Output
High-Voltage
VOH2
VCC - 0.2
—
—
V
1.7V ≤ VCC ≤ 3.6V IOH = -100 µA
Note:
1. Applicable over recommended operating range from: TA = -40°C to +85°C, VCC = 1.7V to 5.5V
(unless otherwise noted). Typical values characterized at TA = +25°C unless otherwise noted.
2. VIL min and VIH max are reference only and are not tested.
3. This parameter is characterized but is not 100% tested in production.
© 2019 Microchip Technology Inc.
Datasheet
20006230A-page 10
AT25M02
Electrical Characteristics
4.4
AC Characteristics
Table 4-3. AC Characteristics(1)
Parameter
Symbol
Minimum
Maximum
Units
SCK Clock Frequency
fSCK
0
5
MHz
Input Rise Time
tRI(2)
—
80
ns
Input Fall Time
tFI(2)
—
80
ns
SCK High Time
tWH
80
—
ns
SCK Low Time
tWL
80
—
ns
CS High Time
tCS
200
—
ns
CS Setup Time
tCSS
200
—
ns
CS Hold Time
tCSH
200
—
ns
Data In Setup Time
tSU
20
—
ns
Data In Hold Time
tH
20
—
ns
HOLD Setup Time
tHD
20
—
ns
HOLD Hold Time
tCD
20
—
ns
Output Valid
tV
0
80
ns
Output Hold Time
tHO
0
—
ns
HOLD to Output Low-Z
tLZ
0
100
ns
HOLD to Output High-Z
tHZ
—
100
ns
Output Disable Time
tDIS
—
100
ns
Write Cycle Time
tWC
—
10
ms
Note:
1. Applicable over recommended operating range from TA = -40°C to +85°C, VCC = As Specified,
CL = 1 TTL Gate and 30 pF (unless otherwise noted).
2. This parameter is ensured by characterization only.
© 2019 Microchip Technology Inc.
Datasheet
20006230A-page 11
AT25M02
Electrical Characteristics
4.5
SPI Synchronous Data Timimg
tCS
VIH
CS
VIL
tCSS
tCSH
VIH
SCK
tWH
tWL
VIL
tSU
tH
VIH
SI
Valid Data In
VIL
tV
VOH
SO
VOL
tHO
tDIS
High
Impedance
High
Impedance
4.6
Electrical Specifications
4.6.1
Power-Up Requirements and Reset Behavior
During a power-up sequence, the VCC supplied to the AT25M02 should monotonically rise from GND to
the minimum VCC level, as specified in Table 4-1, with a slew rate no faster than 0.1 V/µs.
4.6.1.1
Device Reset
To prevent inadvertent write operations or any other spurious events from occurring during a power-up
sequence, the AT25M02 includes a Power-on Reset (POR) circuit. Upon power-up, the device will not
respond to any instructions until the VCC level crosses the internal voltage threshold (VPOR) that brings
the device out of Reset and into Standby mode.
The system designer must ensure the instructions are not sent to the device until the VCC supply has
reached a stable value greater than or equal to the minimum VCC level. Additionally, once the VCC is
greater than or equal to the minimum VCC level, the bus master must wait at least tPUP before sending the
first instruction to the device. See Table 4-4 for the values associated with these power-up parameters.
Table 4-4. Power-Up Conditions(1)
Symbol
Parameter
tPUP
Time required after VCC is stable before the device can accept instructions
VPOR
tPOFF
Min. Max. Units
100
－
µs
Power-on Reset Threshold Voltage
－
1.5
V
Minimum time at VCC = 0V between power cycles
1
－
ms
Note:
1. These parameters are characterized but they are not 100% tested in production.
If an event occurs in the system where the VCC level supplied to the AT25M02 drops below the maximum
VPOR level specified, it is recommended that a full-power cycle sequence be performed by first driving the
VCC pin to GND in less than 1 ms, waiting at least the minimum tPOFF time and then performing a new
power-up sequence in compliance with the requirements defined in this section.
© 2019 Microchip Technology Inc.
Datasheet
20006230A-page 12
AT25M02
Electrical Characteristics
4.6.1.2
Pin Capacitance
Table 4-5. Pin Capacitance(1,2)
Symbol
Test Condition
Max.
Units
Conditions
COUT
Output Capacitance (SO)
8
pF
VOUT = 0V
CIN
Input Capacitance (CS, SCK, SI, WP, HOLD)
6
pF
VIN = 0V
Note:
1. This parameter is characterized but is not 100% tested in production.
2. Applicable over recommended operating range from: TA = 25°C, fSCK = 1.0 MHz, VCC = 5.0V
(unless otherwise noted).
4.6.1.3
EEPROM Cell Performance Characteristics
Table 4-6. EEPROM Cell Performance Characteristics
Operation
Test Condition
Write Endurance(1)
TA = 25°C, VCC(min.) < VCC < VCC(max.),
Byte(2) or Page Write mode
Data Retention(1)
TA = 55°C
Min.
Max.
Units
1,000,000
—
Write Cycles
100
—
Years
Note:
1. Performance is determined through characterization and the qualification process.
2. Due to the memory array architecture, the Write Cycle Endurance is specified for writes in groups
of four data bytes. The beginning of any 4-byte boundaries can be determined by multiplying any
integer (N) by four (i.e., 4*N). The end address can be found by adding three to the beginning value
(i.e., 4*N+3). See Internal Writing Methodology for more details on this implementation.
4.6.1.4
Software Reset
The SPI interface of the AT25M02 can be reset by toggling the CS input. If the CS line is already in the
active state, it must complete a transition from the inactive state (≥VIH) to the active state (≤VIL) and then
back to the inactive state (≥VIH) without sending clocks on the SCK line. Upon completion of this
sequence, the device will be ready to receive a new opcode on the SI line.
4.6.1.5
Device Default State at Power-Up
The AT25M02 default state upon power-up consists of:
• Standby Power mode
• A high-to-low-level transition on CS is required to enter active state
• Write Enable Latch (WEL) bit in the STATUS register = 0
• Ready/Busy bit in the STATUS register = 0, indicating the device is ready to accept a new command
• Device is not selected
• Not in Hold condition
• WPEN, BP1 and BP0 bits in the STATUS register are unchanged from their previous state due to the
fact that they are nonvolatile values
4.6.1.6
Device Default Condition
The AT25M02 is shipped from Microchip to the customer with the EEPROM array set to an all FFh data
pattern (logic ‘1’ state). The Write-Protect Enable bit in the STATUS register is set to logic ‘0’ and the
Block Write‑Protection bits in the STATUS register are set to logic ‘0’.
© 2019 Microchip Technology Inc.
Datasheet
20006230A-page 13
AT25M02
Device Operation
5.
Device Operation
The AT25M02 is controlled by a set of instructions that are sent from a host controller, commonly referred
to as the SPI Master. The SPI Master communicates with the AT25M02 via the SPI bus which is
comprised of four signal lines: Chip Select (CS), Serial Data Clock (SCK), Serial Data Input (SI) and
Serial Data Output (SO).
The SPI protocol defines a total of four modes of operation (Mode 0, 1, 2 or 3) with each mode differing in
respect to the SCK polarity and phase and how the polarity and phase control the flow of data on the SPI
bus. The AT25M02 supports the two most common modes, SPI Modes 0 and 3. With SPI Modes 0 and 3,
data is always latched in on the rising edge of SCK and always output on the falling edge of SCK. The
only difference between SPI Modes 0 and 3 is the polarity of the SCK signal when in the inactive state
(when the SPI Master is in Standby mode and not transferring any data). SPI Mode 0 is defined as a low
SCK while CS is not asserted (at VCC) and SPI Mode 3 has SCK high in the inactive state. The SCK Idle
state must match when the CS is deasserted both before and after the communication sequence in SPI
Mode 0 and 3. The figures in this document depict Mode 0 with a solid line on SCK while CS is inactive
and Mode 3 with a dotted line.
Figure 5-1. SPI Mode 0 and Mode 3
CS
SCK
SI
Mode 3
Mode 3
Mode 0
Mode 0
MSB
LSB
SO
5.1
MSB
LSB
Interfacing the AT25M02 on the SPI Bus
Communication to and from the AT25M02 must be initiated by the SPI Master device, such as a
microcontroller. The SPI Master device must generate the serial clock for the AT25M02 on the Serial Data
Clock (SCK) pin. The AT25M02 always operates as a slave due to the fact that the SCK is always an
input.
5.1.1
Selecting the Device
The AT25M02 is selected when the Chip Select (CS) pin is low. When the device is not selected, data will
not be accepted via the Serial Data Input (SI) pin, and the Serial Data Output (SO) pin will remain in a
high‑impedance state.
5.1.2
Sending Data to the Device
The AT25M02 uses the SI pin to receive information. All instructions, addresses and data input bytes are
clocked into the device with the Most Significant bit (MSb) first. The SI pin samples on the first rising edge
of the SCK line after the CS has been asserted.
© 2019 Microchip Technology Inc.
Datasheet
20006230A-page 14
AT25M02
Device Operation
5.1.3
Receiving Data from the Device
Data output from the device is transmitted on the SO pin, with the MSb output first. The SO data is
latched on the first falling edge of SCK after the instruction has been clocked into the device, such as the
Read from Memory Array (READ) and Read STATUS Register (RDSR) instructions. See 7. Read
Sequence for more details.
5.2
Device Opcodes
5.2.1
Serial Opcode
After the device is selected by driving CS low, the first byte will be received on the SI pin. This byte
contains the opcode that defines the operation to be performed. Refer to Table 6-1 for a list of all opcodes
that the AT25M02 will respond to.
5.2.2
Invalid Opcode
If an invalid opcode is received, no data will be shifted into AT25M02 and the SO pin will remain in
a high‑impedance state until the falling edge of CS is detected again. This will reinitialize the serial
communication.
5.3
Hold Function
The Suspend Serial Input (HOLD) pin is used to pause the serial communication with the device without
having to stop or reset the clock sequence. The Hold mode, however, does not have an effect on the
internal write cycle. Therefore, if a write cycle is in progress, asserting the HOLD pin will not pause the
operation and the write cycle will continue to completion.
The Hold mode can only be entered while the CS pin is asserted. The Hold mode is activated by
asserting the HOLD pin during the SCK low pulse. If the HOLD pin is asserted during the SCK high pulse,
then the Hold mode will not be started until the beginning of the next SCK low pulse. The device will
remain in the Hold mode as long as the HOLD pin and CS pin are asserted.
While in Hold mode, the SO pin will be in a high-impedance state. In addition, both the SI pin and the
SCK pin will be ignored. The Write-Protect (WP) pin, however, can still be asserted or deasserted while in
the Hold mode.
To end the Hold mode and resume serial communication, the HOLD pin must be deasserted during the
SCK low pulse. If the HOLD pin is deasserted during the SCK high pulse, then the Hold mode will not end
until the beginning of the next SCK low pulse.
If the CS pin is deasserted while the HOLD pin is still asserted, then any operation that may have been
started will be aborted and the device will reset the WEL bit in the STATUS register back to the logic ‘0’
state.
© 2019 Microchip Technology Inc.
Datasheet
20006230A-page 15
AT25M02
Device Operation
Figure 5-2. Hold Mode
CS
SCK
HOLD
Hold
Hold
Hold
Figure 5-3. Hold Timing
CS
t CD
t CD
SCK
HOLD
t HD
t HD
t HZ
SO
tLZ
5.4
Write Protection
The Write-Protect (WP) pin will allow normal read and write operations when held high. When the WP pin
is brought low and WPEN bit is a logic ‘1’, all write operations to the STATUS register are inhibited. The
WP pin going low while CS is still low will interrupt a Write STATUS Register (WRSR). If the internal write
cycle has already been initiated, WP going low will have no effect on any write operation to the STATUS
register. The WP pin function is blocked when the WPEN bit in the STATUS register is a logic ‘0’. This will
allow the user to install the AT25M02 device in a system with the WP pin tied to ground and still be able
to write to the STATUS register. All WP pin functions are enabled when the WPEN bit is set to a logic ‘1’.
© 2019 Microchip Technology Inc.
Datasheet
20006230A-page 16
AT25M02
Device Commands and Addressing
6.
Device Commands and Addressing
The AT25M02 is designed to interface directly with the synchronous Serial Peripheral Interface (SPI). The
AT25M02 utilizes an 8‑bit instruction register. The list of instructions and their operation codes are
contained in Table 6-1. All instructions, addresses and data are transferred with the MSb first and start
with a high‑to‑low CS transition.
Table 6-1. Instruction Set for the AT25M02
6.1
Instruction Name
Instruction Format
Operates On
Operation Description
WREN
0000 0110 (06h)
STATUS Register
Set Write Enable Latch (WEL)
WRDI
0000 0100 (04h)
STATUS Register
Reset Write Enable Latch (WEL)
RDSR
0000 0101 (05h)
STATUS Register
Read STATUS Register
WRSR
0000 0001 (01h)
STATUS Register
Write STATUS Register
READ
0000 0011 (03h)
Memory Array
Read from Memory Array
WRITE
0000 0010 (02h)
0000 0111 (07h)
Memory Array
Write to Memory Array
LPWP
0000 1000 (08h)
STATUS Register
Low-Power Write Poll
STATUS Register Bit Definition and Function
The AT25M02 includes an 8‑bit STATUS register. The STATUS register bits modulate various features of
the device as shown in Table 6-2 and Table 6-3. These bits can be changed by specific instructions that
are detailed in the following sections.
Table 6-2. STATUS Register Format
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
WPEN
X
X
X
BP1
BP0
WEL
RDY/BSY
Table 6-3. STATUS Register Bit Definition
Bit
7
Name
WPEN
Write-Protect Enable
Type
R/W
Description
0 See Table 6-5 (Factory Default)
1 See Table 6-5 (Factory Default)
6:4
RFU
Reserved for Future Use
R
0 Reads as zeros when the device is not in a write
cycle
1 Reads as ones when the device is in a write cycle
3:2
BP1
BP0
Block Write Protection
R/W 00 No array write protection (Factory Default)
01 Quarter array write protection (see Table 6-4)
10 Half array write protection (see Table 6-4)
11 Entire array write protection (see Table 6-4)
© 2019 Microchip Technology Inc.
Datasheet
20006230A-page 17
AT25M02
Device Commands and Addressing
...........continued
Bit
1
Name
WEL
Type
Write Enable Latch
Description
0 Device is not write enabled (Power-up Default)
R
1 Device is write enabled
0
RDY/BSY Ready/Busy Status
0 Device is ready for a new sequence
R
1 Device is busy with an internal operation
6.2
Read STATUS Register (RDSR) and Low-Power Write Poll (LPWP)
6.2.1
Read STATUS Register (RDSR)
The Read STATUS Register (RDSR) instruction provides access to the STATUS register. The ready/busy
and write enable status of the device can be determined by the RDSR instruction. Similarly, the Block
Write Protection (BP1, BP0) bits indicate the extent of memory array protection employed. The STATUS
register is read by asserting the CS pin, followed by sending in a 05h opcode on the SI pin. Upon
completion of the opcode, the device will return the 8‑bit STATUS register value on the SO pin.
Figure 6-1. RDSR Waveform
CS
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
SCK
RDSR Opcode (05h)
SI
0
0
0
0
0
1
0
1
MSB
STATUS Register Data Out
SO
High-Impedance
D7
D6
D5
D4
D3
D2
D1
D0
MSB
6.2.2
Low-Power Write Poll (LPWP)
The Low-Power Write Poll command can be used after any write command as a means to check if the
device has completed its internal write cycle. The LPWP command requires an opcode of 08h and will
return an FFh value when the part is still busy completing the write cycle. The LPWP command will return
a 00h value if the part is no longer in a write cycle. Refer to Polling Routine for a description on
implementing a polling routine. Continuous reading of the LPWP state is supported and the value output
by the device will be updated every eight bits.
© 2019 Microchip Technology Inc.
Datasheet
20006230A-page 18
AT25M02
Device Commands and Addressing
Figure 6-2. LPWP Waveform
CS
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
SCK
LPWP Opcode (08h)
SI
0
0
0
0
1
0
0
0
MSB
FFh or 00h Data Out
SO
High Impedance
D7
D6
D5
D4
D3
D2
D1
D0
MSB
6.3
Write Enable (WREN) and Write Disable (WRDI)
Enabling and disabling writing to the STATUS register and EEPROM array is accomplished through the
Write Enable (WREN) instruction and the Write Disable (WRDI) instruction. These functions change the
status of the WEL bit in the STATUS register.
6.3.1
Write Enable Instruction (WREN)
The Write Enable Latch (WEL) bit of the STATUS register must be set to a logic ‘1’ prior to each Write
STATUS Register (WRSR) and Write to Memory Array (WRITE) instructions. This is accomplished by
sending a WREN (06h) instruction to the AT25M02. First, the CS pin is driven low to select the device and
then a WREN instruction is clocked in on the SI pin. Then the CS pin can be driven high and the WEL bit
will be updated in the STATUS register to a logic ‘1’. The device will power‑up in the Write Disable state
(WEL = 0).
Figure 6-3. WREN Timing
CS
0
1
2
3
4
5
6
7
SCK
WREN Opcode (06h)
SI
0
0
0
0
0
1
1
0
MSB
SO
© 2019 Microchip Technology Inc.
High-Impedance
Datasheet
20006230A-page 19
AT25M02
Device Commands and Addressing
6.3.2
Write Disable Instruction (WRDI)
To protect the device against inadvertent writes, the Write Disable (WRDI) instruction (opcode 04h)
disables all programming modes by setting the WEL bit to a logic ‘0’. The WRDI instruction is independent
of the status of the WP pin.
Figure 6-4. WRDI Timing
CS
0
1
2
3
4
5
6
7
SCK
WRDI Opcode (04h)
SI
0
0
0
0
0
1
0
0
MSB
SO
6.4
High-Impedance
Write STATUS Register (WRSR)
The Write STATUS Register (WRSR) instruction enables the SPI Master to change selected bits of the
STATUS register. Before a WRSR instruction can be initiated, a WREN instruction must be executed to set
the WEL bit to logic ‘1’. Upon completion of a WREN instruction, a WRSR instruction can be executed.
Note: The WRSR instruction has no effect on bit 6, bit 5, bit 4, bit 1 and bit 0 of the STATUS register. Only
bit 7, bit 3 and bit 2 can be changed via the WRSR instruction. These modifiable bits are the Write-Protect
Enable (WPEN) and Block Protect (BP1, BP0) bits. These three bits are nonvolatile bits that have the
same properties and functions as regular EEPROM cells. Their values are retained while power is
removed from the device.
The AT25M02 will not respond to commands other than a RDSR after a WRSR instruction until
the self‑timed internal write cycle has completed. When the write cycle is completed, the WEL bit in the
STATUS register is reset to logic ‘0’.
© 2019 Microchip Technology Inc.
Datasheet
20006230A-page 20
AT25M02
Device Commands and Addressing
Figure 6-5. WRSR Waveform
CS
tWC(1)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
SCK
STATUS Register Data In
WRSR Opcode (01h)
SI
0
0
0
0
0
MSB
0
0
1
D7
X
X
X
D3
D2
X
X
MSB
High-Impedance
SO
Note:
1. This instruction initiates a self-timed internal write cycle (tWC) on the rising edge of CS after a valid
sequence.
6.4.1
Block Write-Protect Function
The WRSR instruction allows the user to select one of four possible combinations as to how the memory
array will be inhibited from writing through changing the Block Write-Protect bits (BP1, BP0). The four
levels of array protection are:
• None of the memory array is protected.
• Upper quarter (¼) address range is write-protected meaning the highest order address bits are
read‑only.
• Upper half (½) address range is write-protected meaning the highest order address bits are
read‑only.
• All of the memory array is write-protected meaning all address bits are read‑only.
The Block Write Protection levels and corresponding STATUS register control bits are shown in Table 6-4.
Table 6-4. Block Write-Protect Bits
Level
6.4.2
STATUS Register Bits
Write-Protected/Read‑Only Address Range
BP1
BP0
AT25M02
0
0
0
None
1(1/4)
0
1
30000h–3FFFFh
2(1/2)
1
0
20000h – 3FFFFh
3(All)
1
1
00000h – 3FFFFh
Write-Protect Enable Function
The WRSR instruction also allows the user to enable or disable the Write-Protect (WP) pin through the use
of the Write-Protect Enable (WPEN) bit. When the WPEN bit is set to logic ‘0’, the ability to write the
EEPROM array is dictated by the values of the Block Write-Protect (BP1, BP0) bits. The ability to write
© 2019 Microchip Technology Inc.
Datasheet
20006230A-page 21
AT25M02
Device Commands and Addressing
the STATUS register is controlled by the WEL bit. When the WPEN bit is set to logic ‘1’, the STATUS
register is read-only.
Hardware Write Protection is enabled when both the WP pin is low and the WPEN bit has been set to a
logic ‘1’. When the device is Hardware Write‑Protected, writes to the STATUS register, including the Block
Write‑Protect, WEL and WPEN bits and to the sections in the memory array selected by the Block
Write‑Protect bits are disabled. When Hardware Write Protection is enabled, writes are only allowed to
sections of the memory that are not block‑protected.
Hardware Write Protection is disabled when either the WP pin is high or the WPEN bit is a logic ‘0’. When
Hardware Write Protection is disabled, writes are only allowed to sections of the memory that are not
block‑protected. Refer to Table 6-5 for additional information.
Note: When the WPEN bit is Hardware Write‑Protected, it cannot be set back to a logic ‘0’ as long as
the WP pin is held low.
Table 6-5. WPEN Operation
WPEN
WP
Pin
WEL
Protected Blocks
Unprotected Blocks
STATUS Register
0
x
0
Protected
Protected
Protected
0
x
1
Protected
Writable
Writable
1
Low
0
Protected
Protected
Protected
1
Low
1
Protected
Writable
Protected
x
High
0
Protected
Protected
Protected
x
High
1
Protected
Writable
Writable
© 2019 Microchip Technology Inc.
Datasheet
20006230A-page 22
AT25M02
Read Sequence
7.
Read Sequence
Reading the AT25M02 via the SO pin requires the following sequence. After the CS line is pulled low to
select a device, the READ (03h) instruction is transmitted via the SI line followed by the 24‑bit address to
be read. Refer to Table 7-1 for the address bits for AT25M02.
Table 7-1. AT25M02 Address Bits
Address
AT25M02
AN
A17—A0
Don't Care Bits
A23—A18
Upon completion of the 24‑bit address, any data on the SI line will be ignored. The data (D7‑D0) at the
specified address is then shifted out onto the SO line. If only one byte is to be read, the CS line should be
driven high after the data comes out. The read sequence can be continued since the byte address is
automatically incremented and data will continue to be shifted out. When the highest‑order address bit is
reached, the address counter will rollover to the lowest‑order address bit allowing the entire memory to be
read in one continuous read cycle regardless of the starting address.
Figure 7-1. Read Waveform
CS
0
1
2
3
4
5
6
7
8
9
10 11 12
28 29 31 32 33 34 35 36 37 38 39 40 41
SCK
READ Opcode (03h)
SI
0
0
0
0
0
MSB
0
1
Address Bits A23-A0
1
A
A
A
A
A
A
A
A
A
MSB
Data Byte 1
SO
High-Impedance
D
MSB
© 2019 Microchip Technology Inc.
Datasheet
D
D
D
D
D
D
D
D
D
MSB
20006230A-page 23
AT25M02
Write Sequence
8.
Write Sequence
In order to program the AT25M02, two separate instructions must be executed. First, the device must be
write enabled via the Write Enable (WREN) instruction. Then, one of the two possible write sequences
described in this section may be executed.
Note: If the device is not Write Enabled (WREN), the device will ignore the WRITE instruction and will
return to the standby state when CS is brought high. A new CS assertion is required to re-initiate
communication.
The address of the memory location(s) to be programmed must be outside the protected address field
location selected by the block write protection level. During an internal write cycle, all commands will be
ignored except the RDSR instruction. Refer to Table 8-1 for the address bits for AT25M02.
Table 8-1. AT25M02 Address Bits
8.1
Address
AT25M02
AN
A17—A0
Don’t Care Bits
A23—A18
Byte Write
A byte write requires the following sequence and is depicted in Figure 8-1. After the CS line is pulled low
to select the device, the WRITE (02h or 07h) instruction is transmitted via the SI line followed by the 24‑bit
address and the data (D7‑D0) to be programmed. Programming will start after the CS pin is brought high.
The low‑to‑high transition of the CS pin must occur during the SCK low time (Mode 0) and SCK high time
(Mode 3) immediately after clocking in the D0 (LSB) data bit. The AT25M02 is automatically returned to
the Write Disable state (STATUS register bit WEL = 0) at the completion of a write cycle.
Figure 8-1. Byte Write
CS
tWC(1)
0
1
2
3
4
5
6
7
8
9
10 11 12
28 29 31 32 33 34 35 36 37 38 39
SCK
WRITE Opcode (02h)
SI
0
0
0
0
0
MSB
SO
0
1
Address Bits A23-A0
0
A
A
A
A
A
A
MSB
A
Data In
A
A D7 D6 D5 D4 D3 D2 D1 D0
MSB
High-Impedance
Note:
1. This instruction initiates a self-timed internal write cycle (tWC) on the rising edge of CS after a valid
sequence.
8.2
Page Write
A page write sequence allows up to 256 bytes to be written in the same write cycle, provided that all
bytes are in the same row of the memory array. Partial page writes of less than 256 bytes are allowed.
After each byte of data is received, the eight lowest order address bits are internally incremented
© 2019 Microchip Technology Inc.
Datasheet
20006230A-page 24
AT25M02
Write Sequence
following the receipt of each data byte. The higher order address bits are not incremented and retain the
memory array page location. If more bytes of data are transmitted that what will fit to the end of that
memory row, the address counter will rollover to the beginning of the same row. Nevertheless, creating a
rollover event should be avoided as previously loaded data in the page could become unintentionally
altered. The AT25M02 is automatically returned to the Write Disable state (WEL = 0) at the completion of
a write cycle.
Figure 8-2. Page Write
CS
tWC(1)
0
1
2
3
4
5
6
7
8
9
29 30 31 32 33 34 35 36 37 38 39
SCK
WRITE Opcode (02h)
SI
0
0
0
0
0
MSB
0
1
Address Bits A23-A0
0
A
MSB
A
A
A
A
Data In Byte 1
A
D
D
D
D
MSB
D
D
Data In Byte 256
D
D
D
D
D
D
D
D
D
D
MSB
High-Impedance
SO
Note:
1.
8.3
This instruction initiates a self‑timed internal write cycle (tWC) on the rising edge of CS after a valid
sequence.
Internal Writing Methodology
The AT25M02 incorporates a built-in error detection and correction (EDC) logic scheme. The EEPROM
array is internally organized as a group of four connected 8-bit bytes plus an additional six ECC (Error
Correction Code) bits of EEPROM. These 38 bits are referred to as the internal physical data word.
During a read sequence, the EDC logic compares each 4-byte physical data word with its corresponding
six ECC bits. If a single bit out of the 4-byte region reads incorrectly, the EDC logic will detect the bad bit
and replace it with a correct value before the data is serially clocked out. This architecture significantly
improves the reliability of the AT25M02 compared to an implementation that does not utilize EDC.
It is important to note that data is always physically written to the part at the internal physical data word
level, regardless of the number of bytes written. Writing single bytes is still possible with the byte write
operation, but internally, the other three bytes within that 4-byte location where the single byte was
written, along with the six ECC bits will be updated. Due to this architecture, the AT25M02 EEPROM write
endurance is rated at the internal physical data word level (4-byte word). The system designer needs to
optimize the application writing algorithms to observe these internal word boundaries in order to reach the
endurance rating.
8.4
Polling Routine
A polling routine can be implemented to optimize time‑sensitive applications that would not prefer to wait
the fixed maximum write cycle time (tWC). This method allows the application to know immediately when
the write cycle has completed to start a subsequent operation.
Once the internally-timed write cycle has started, a polling routine can be initiated. This involves
repeatedly sending Read STATUS Register (RDSR) instruction to determine if the device has completed
its self-timed internal write cycle. If the RDY/BSY bit (bit 0 of STATUS register) = 1, the write cycle is still
in progress. If bit 0 = 0, the write cycle has ended. If the RDY/BSY bit = 1, repeated RDSR commands can
© 2019 Microchip Technology Inc.
Datasheet
20006230A-page 25
AT25M02
Write Sequence
be executed until the RDY/BSY bit = 0, signaling that the device is ready to execute a new instruction.
Only the Read STATUS Register (RDSR) and the Low-Power Write Poll (LPWP) instructions are is enabled
during the write cycle.
Figure 8-3. Polling Flowchart
Send Valid
Write
Protocol
Deassert
CS to VCC to
Initiate a
Write Cycle
Send RDSR
Instruction
to the Device
Does
RDY/BSY
= 0?
YES
Continue to
Next Operation
NO
© 2019 Microchip Technology Inc.
Datasheet
20006230A-page 26
AT25M02
Packaging Information
9.
Packaging Information
9.1
Package Marking Information
AT25M02: Package Marking Information
8-ball WLCSP
8-lead SOIC
ATMLUYWW
## % CO
YYWWNNN
ATMLHYWW
## % CO
YYWWNNN
Note 1:
designates pin 1
Note 2: Package drawings are not to scale
Catalog Number Truncation
AT25M02
Truncation Code ##: 5H
Date Codes
YY = Year
16: 2016
17: 2017
18: 2018
19: 2019
Voltages
20: 2020
21: 2021
22: 2022
23: 2023
Y = Year
6: 2016
7: 2017
8: 2018
9: 2019
0: 2020
1: 2021
2: 2022
3: 2023
WW = Work Week of Assembly
02: Week 2
04: Week 4
...
52: Week 52
Country of Origin
Device Grade
CO = Country of Origin
H or U: Industrial Grade
% = Minimum Voltage
M: 1.7V min
D: 2.5V min
Atmel Truncation
AT: Atmel
ATM: Atmel
ATML: Atmel
Lot Number or Trace Code
NNN = Alphanumeric Trace Code (2 Characters for Small Packages)
© 2019 Microchip Technology Inc.
Datasheet
20006230A-page 27
AT25M02
Packaging Information
8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm (.150 In.) Body [SOIC]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2X
0.10 C A–B
D
A
D
NOTE 5
N
E
2
E1
2
E1
E
NOTE 1
2
1
e
B
NOTE 5
NX b
0.25
C A–B D
TOP VIEW
0.10 C
C
A A2
SEATING
PLANE
8X
A1
SIDE VIEW
0.10 C
h
R0.13
h
R0.13
H
0.23
L
SEE VIEW C
(L1)
VIEW A–A
VIEW C
Microchip Technology Drawing No. C04-057-SN Rev E Sheet 1 of 2
© 2017 Microchip Technology Inc.
© 2019 Microchip Technology Inc.
Datasheet
20006230A-page 28
AT25M02
Packaging Information
8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm (.150 In.) Body [SOIC]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Units
Dimension Limits
Number of Pins
N
e
Pitch
Overall Height
A
Molded Package Thickness
A2
§
Standoff
A1
Overall Width
E
Molded Package Width
E1
Overall Length
D
Chamfer (Optional)
h
Foot Length
L
L1
Footprint
Foot Angle
c
Lead Thickness
b
Lead Width
Mold Draft Angle Top
Mold Draft Angle Bottom
MIN
1.25
0.10
0.25
0.40
0°
0.17
0.31
5°
5°
MILLIMETERS
NOM
8
1.27 BSC
6.00 BSC
3.90 BSC
4.90 BSC
1.04 REF
-
MAX
1.75
0.25
0.50
1.27
8°
0.25
0.51
15°
15°
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. § Significant Characteristic
3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or
protrusions shall not exceed 0.15mm per side.
4. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
5. Datums A & B to be determined at Datum H.
Microchip Technology Drawing No. C04-057-SN Rev E Sheet 2 of 2
© 2017 Microchip Technology Inc.
© 2019 Microchip Technology Inc.
Datasheet
20006230A-page 29
AT25M02
Packaging Information
8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm Body [SOIC]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
SILK SCREEN
C
Y1
X1
E
RECOMMENDED LAND PATTERN
Units
Dimension Limits
E
Contact Pitch
Contact Pad Spacing
C
Contact Pad Width (X8)
X1
Contact Pad Length (X8)
Y1
MIN
MILLIMETERS
NOM
1.27 BSC
5.40
MAX
0.60
1.55
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Microchip Technology Drawing C04-2057-SN Rev E
© 2017 Microchip Technology Inc.
© 2019 Microchip Technology Inc.
Datasheet
20006230A-page 30
AT25M02
Packaging Information
TOP VIEW
BOTTOM SIDE
k
12
A1 CORNER
0.015 (4X)
A
34
43
A
A
B
B
21
e1
E
C
C
D
D
D
e
d1
d2
B
SIDE VIEW
A
A1 CORNER
A2
db
v
d0.015 m C
d0.05 m C A B
SEATING PLANE
C
k
COMMON DIMENSIONS
(Unit of Measure = mm)
A1
0.20 C
PIN ASSIGNMENT MATRIX
A
SYMBOL
MIN
TYP
MAX
A
0.313
0.334
0.355
A1
—
0.094
—
1
2
3
4
A2
—
0.240
—
n/a
VCC
CS
n/a
D
d1
B
n/a
HOLD
n/a
SO
C
SCK
n/a
n/a
WP
D
n/a
SI
GND
n/a
1.00 BSC
1.40 BSC
Contact Microchip for details
e
0.50 BSC
e1
2.10 BSC
b
3
Contact Microchip for details
d2
E
NOTE
0.170
0.185
0.200
Note: 1. Dimensions are NOT to scale.
2. Solder ball composition is 95.5Sn-4.0Ag-0.5Cu.
3. Product offered with Back Side Coating
9/22/15
TITLE
8U-11, 8-ball 4x4 Array, Custom Pitch
Wafer Level Chip Scale Package (WLCSP)
GPC
DRAWING NO.
REV.
GAC
8U-10
E
Note: For the most current package drawings, please see the Microchip Packaging Specification located
at http://www.microchip.com/packaging.
© 2019 Microchip Technology Inc.
Datasheet
20006230A-page 31
AT25M02
Revision History
10.
Revision History
Revision A (July 2019)
Updated to Microchip template. Microchip DS20006230 replaces Atmel document 8832. Updated Part
Marking Information. Added ESD rating. Removed lead finish designation. Changed Data Retention spec
to 100 year. Updated trace code format in package markings. Updated section content throughout for
clarification. Updated the SOIC package drawing to the Microchip equivalent.
Atmel Document 8832 Revision C (January 2017)
Updated Power On Requirements and Reset Behavior section.
Atmel Document 8832 Revision B (February 2016)
Removed Preliminary status and updated 8U-10 package drawing.
Atmel Document 8832 Revision A (May 2015)
Initial document release.
© 2019 Microchip Technology Inc.
Datasheet
20006230A-page 32
AT25M02
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related to a specified product family or development tool of interest.
To register, go to http://www.microchip.com/pcn and follow the registration instructions.
Customer Support
Users of Microchip products can receive assistance through several channels:
•
•
•
•
Distributor or Representative
Local Sales Office
Embedded Solutions Engineer (ESE)
Technical Support
Customers should contact their distributor, representative or ESE for support. Local sales offices are also
available to help customers. A listing of sales offices and locations is included in this document.
Technical support is available through the web site at: http://www.microchip.com/support
© 2019 Microchip Technology Inc.
Datasheet
20006230A-page 33
AT25M02
Product Identification System
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
AT25M 02 -S SH Mx x-T
Shipping Carrier Option
T = Tape and Reel
B = Bulk (Tubes)
Product Family
25 = SPI Serial EEPROM
Product Variation /
Customer Specific Option
xx = Applies to selecte packages only.
See ordering table for details.
Device Density
M02 = 2 Megabit
Operating Voltage
M = 1.7V to 5.5V
D = 2.5V to 5.5V
Package Device Grade or
Wafer/Die Thickness
H or U = Industrial Temperature Range
(-40°C to +85°C)
11
= 11mil Wafer Thickness
Package Option
SS
= SOIC
U1
= 8-ball, 4x4 Grid Array, WLCSP
WWU = Wafer Unsawn
Examples:
Package
Package
Drawing
Code
Package
Option
Voltage
Shipping Carrier
Option
Device Grade
AT25M02‑SSHM‑B
SOIC
SN
SS
1.7V to 5.5V
Bulk (Tubes)
AT25M02‑SSHD‑B
SOIC
SN
SS
2.5V to 5.5V
Bulk (Tubes)
Industrial
Temperature
(-40°C to 85°C)
AT25M02‑SSHM‑T
SOIC
SN
SS
1.7V to 5.5V
Tape and Reel
AT25M02‑SSHD‑T
SOIC
SN
SS
2.5V to 5.5V
Tape and Reel
WLCSP
8U‑10
U1
1.7V to 5.5V
Tape and Reel
Device
AT25M02‑U1UM0B‑T
Microchip Devices Code Protection Feature
Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.
• Microchip believes that its family of products is one of the most secure families of its kind on the
market today, when used in the intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of
these methods, to our knowledge, require using the Microchip products in a manner outside the
operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is
engaged in theft of intellectual property.
© 2019 Microchip Technology Inc.
Datasheet
20006230A-page 34
AT25M02
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their
code. Code protection does not mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the
code protection features of our products. Attempts to break Microchip’s code protection feature may be a
violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software
or other copyrighted work, you may have a right to sue for relief under that Act.
Legal Notice
Information contained in this publication regarding device applications and the like is provided only for
your convenience and may be superseded by updates. It is your responsibility to ensure that your
application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY
OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS
CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE.
Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life
support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend,
indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting
from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual
property rights unless otherwise stated.
Trademarks
The Microchip name and logo, the Microchip logo, Adaptec, AnyRate, AVR, AVR logo, AVR Freaks,
BesTime, BitCloud, chipKIT, chipKIT logo, CryptoMemory, CryptoRF, dsPIC, FlashFlex, flexPWR,
HELDO, IGLOO, JukeBlox, KeeLoq, Kleer, LANCheck, LinkMD, maXStylus, maXTouch, MediaLB,
megaAVR, Microsemi, Microsemi logo, MOST, MOST logo, MPLAB, OptoLyzer, PackeTime, PIC,
picoPower, PICSTART, PIC32 logo, PolarFire, Prochip Designer, QTouch, SAM-BA, SenGenuity, SpyNIC,
SST, SST Logo, SuperFlash, Symmetricom, SyncServer, Tachyon, TempTrackr, TimeSource, tinyAVR,
UNI/O, Vectron, and XMEGA are registered trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
APT, ClockWorks, The Embedded Control Solutions Company, EtherSynch, FlashTec, Hyper Speed
Control, HyperLight Load, IntelliMOS, Libero, motorBench, mTouch, Powermite 3, Precision Edge,
ProASIC, ProASIC Plus, ProASIC Plus logo, Quiet-Wire, SmartFusion, SyncWorld, Temux, TimeCesium,
TimeHub, TimePictra, TimeProvider, Vite, WinPath, and ZL are registered trademarks of Microchip
Technology Incorporated in the U.S.A.
Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut, BlueSky,
BodyCom, CodeGuard, CryptoAuthentication, CryptoAutomotive, CryptoCompanion, CryptoController,
dsPICDEM, dsPICDEM.net, Dynamic Average Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial
Programming, ICSP, INICnet, Inter-Chip Connectivity, JitterBlocker, KleerNet, KleerNet logo, memBrain,
Mindi, MiWi, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient
Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, PowerSmart, PureSilicon, QMatrix, REAL ICE,
Ripple Blocker, SAM-ICE, Serial Quad I/O, SMART-I.S., SQI, SuperSwitcher, SuperSwitcher II, Total
Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are
trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated in the U.S.A.
© 2019 Microchip Technology Inc.
Datasheet
20006230A-page 35
AT25M02
The Adaptec logo, Frequency on Demand, Silicon Storage Technology, and Symmcom are registered
trademarks of Microchip Technology Inc. in other countries.
GestIC is a registered trademark of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of
Microchip Technology Inc., in other countries.
All other trademarks mentioned herein are property of their respective companies.
©
2019, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved.
ISBN: 978-1-5224-4754-2
Quality Management System
For information regarding Microchip’s Quality Management Systems, please visit http://
www.microchip.com/quality.
© 2019 Microchip Technology Inc.
Datasheet
20006230A-page 36
Worldwide Sales and Service
AMERICAS
ASIA/PACIFIC
ASIA/PACIFIC
EUROPE
Corporate Office
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7200
Fax: 480-792-7277
Technical Support:
http://www.microchip.com/support
Web Address:
http://www.microchip.com
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Tel: 678-957-9614
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Sweden - Stockholm
Tel: 46-8-5090-4654
UK - Wokingham
Tel: 44-118-921-5800
Fax: 44-118-921-5820
© 2019 Microchip Technology Inc.
Datasheet
20006230A-page 37
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