Features
• Fast Read Access Time – 120 ns
• Fast Byte Write – 200 µs
• Self-timed Byte Write Cycle
•
•
•
•
•
•
•
•
– Internal Address and Data Latches
– Internal Control Timer
– Automatic Clear Before Write
Direct Microprocessor Control
– READY/BUSY Open Drain Output
– DATA Polling
Low Power
– 30 mA Active Current
– 100 µA CMOS Standby Current
High Reliability
– Endurance: 105 Cycles
– Data Retention: 10 Years
5V ± 10% Supply
CMOS and TTL Compatible Inputs and Outputs
JEDEC Approved Byte-wide Pinout
Industrial Temperature Ranges
Green (Pb/Halide-Free) Packaging Option
64K (8K x 8)
Parallel
EEPROMs
AT28C64E
1. Description
The AT28C64E is a low-power, high-performance 8,192 words by 8-bit nonvolatile
electrically erasable and programmable read-only memory with popular, easy-to-use
features. The device is manufactured with Atmel’s reliable nonvolatile technology.
The AT28C64E is accessed like a Static RAM for the read or write cycles without the
need for external components. During a byte write, the address and data are latched
internally, freeing the microprocessor address and data bus for other operations. Following the initiation of a write cycle, the device will go to a busy state and
automatically clear and write the latched data using an internal control timer. The
device includes two methods for detecting the end of a write cycle, level detection of
RDY/BUSY (unless pin 1 is N.C.) and DATA Polling of I/O7. Once the end of a write
cycle has been detected, a new access for a read or write can begin.
The CMOS technology offers fast access times of 120 ns at low power dissipation.
When the chip is deselected, the standby current is less than 100 µA.
Atmel’s AT28C64E has additional features to ensure high quality and manufacturability. The device utilizes error correction internally for extended endurance and for
improved data retention characteristics. An extra 32 bytes of EEPROM are available
for device identification or tracking.
0001I–PEEPR–10/06
2.2
Function
A0 - A12
Addresses
CE
Chip Enable
OE
Output Enable
WE
Write Enable
I/O0 - I/O7
Data Inputs/Outputs
RDY/BUSY
Ready/Busy Output
NC
No Connect
DC
Don’t Connect
2.1
PDIP, SOIC Top View
28
27
26
25
24
23
22
21
20
19
18
17
16
15
28
27
26
25
24
23
22
21
20
19
18
17
16
15
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
A1
A2
LCC, PLCC Top View
A7
A12
RDY/BUSY (or NC)
DC
VCC
WE
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
2.3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
VCC
WE
NC
A8
A9
A11
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
A6
A5
A4
A3
A2
A1
A0
NC
I/O0
5
6
7
8
9
10
11
12
13
29
28
27
26
25
24
23
22
21
A8
A9
A11
NC
OE
A10
CE
I/O7
I/O6
I/O1
I/O2
VSS
DC
I/O3
I/O4
I/O5
RDY/BUSY (or NC)
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
GND
OE
A11
A9
A8
NC
WE
VCC
RDY/BUSY (or NC)
A12
A7
A6
A5
A4
A3
4
3
2
1
32
31
30
Pin Name
TSOP Top View
14
15
16
17
18
19
20
2. Pin Configurations
Note:
2
PLCC package pins 1 and 17 are DON’T CONNECT.
AT28C64E
0001I–PEEPR–10/06
AT28C64E
3. Block Diagram
4. Absolute Maximum Ratings*
Temperature under Bias ................................ -55°C to +125°C
Storage Temperature ..................................... -65°C to +150°C
All Input Voltages (including NC Pins)
with Respect to Ground ...................................-0.6V to +6.25V
All Output Voltages
with Respect to Ground .............................-0.6V to VCC + 0.6V
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect
device reliability
Voltage on OE and A9
with Respect to Ground ...................................-0.6V to +13.5V
3
0001I–PEEPR–10/06
5. Device Operation
5.1
Read
The AT28C64E is accessed like a Static RAM. When CE and OE are low and WE is high, the
data stored at the memory location determined by the address pins is asserted on the outputs.
The outputs are put in a high impedance state whenever CE or OE is high. This dual line control
gives designers increased flexibility in preventing bus contention.
5.2
Byte Write
Writing data into the AT28C64E is similar to writing into a Static RAM. A low pulse on the WE or
CE input with OE high and CE or WE low (respectively) initiates a byte write. The address location is latched on the falling edge of WE (or CE); the new data is latched on the rising edge.
Internally, the device performs a self-clear before write. Once a byte write has been started, it
will automatically time itself to completion. Once a programming operation has been initiated and
for the duration of tWC, a read operation will effectively be a polling operation.
5.3
Fast Byte Write
The AT28C64E offers a byte write time of 200 µs maximum. This feature allows the entire
device to be rewritten in 1.6 seconds.
5.4
READY/BUSY
Pin 1 is an open drain RDY/BUSY output that can be used to detect the end of a write cycle.
RDY/BUSY is actively pulled low during the write cycle and is released at the completion of
the write. The open-drain connection allows for OR-tying of several devices to the same
RDY/BUSY line.
5.5
Data Polling
The AT28C64E provides DATA Polling to signal the completion of a write cycle. During a
write cycle, an attempted read of the data being written results in the complement of that data for
I/O7 (the other outputs are indeterminate). When the write cycle is finished, true data appears on
all outputs.
5.6
Write Protection
Inadvertent writes to the device are protected against in the following ways: (a) VCC sense – if
VCC is below 3.8V (typical), the write function is inhibited; (b) VCC power on delay – once VCC has
reached 3.8V, the device will automatically time out 5 ms (typical) before allowing a byte write;
and (c) write inhibit – holding any one of OE low, CE high or WE high inhibits byte write cycles.
5.7
Chip Clear
The contents of the entire memory of the AT28C64E may be set to the high state by the CHIP
CLEAR operation. By setting CE low and OE to 12 volts, the chip is cleared when a 10 msec low
pulse is applied to WE.
5.8
Device Identification
An extra 32 bytes of EEPROM memory are available to the user for device identification. By raising A9 to 12 ± 0.5V and using address locations 1FE0H to 1FFFH the additional bytes may be
written to or read from in the same manner as the regular memory array.
4
AT28C64E
0001I–PEEPR–10/06
AT28C64E
6. DC and AC Operating Range
AT28C64E-12
Operating Temperature (Case)
-40°C - 85°C
5V ± 10%
VCC Power Supply
7. Operating Modes
Mode
CE
OE
WE
I/O
Read
VIL
VIL
VIH
DOUT
VIL
VIH
VIL
DIN
VIH
X(1)
X
High Z
Write Inhibit
X
X
VIH
Write Inhibit
X
VIL
X
Output Disable
X
VIH
X
High Z
Chip Erase
VIL
VH(3)
VIL
High Z
Write
(2)
Standby/Write Inhibit
Notes:
1. X can be VIL or VIH.
2. Refer to AC programming waveforms.
3. VH = 12.0V ± 0.5V.
8. DC Characteristics
Symbol
Parameter
Condition
ILI
Input Load Current
ILO
Min
Max
Units
VIN = 0V to VCC + 1V
10
µA
Output Leakage Current
VI/O = 0V to VCC
10
µA
ISB1
VCC Standby Current CMOS
CE = VCC - 0.3V to VCC + 1.0V
100
µA
ISB2
VCC Standby Current TTL
CE = 2.0V to VCC + 1.0V
3
mA
ICC
VCC Active Current AC
f = 5 MHz; IOUT = 0 mA
CE = VIL
45
mA
VIL
Input Low Voltage
0.8
V
VIH
Input High Voltage
VOL
Output Low Voltage
IOL = 2.1 mA
= 4.0 mA for RDY/BUSY
VOH
Output High Voltage
IOH = -400 µA
2.0
V
0.45
2.4
V
V
5
0001I–PEEPR–10/06
9. AC Read Characteristics
AT28C64E-12
Symbol
Parameter
tACC
Min
Max
Units
Address to Output Delay
120
ns
(1)
CE to Output Delay
120
ns
tOE(2)
OE to Output Delay
10
60
ns
tDF(3)(4)
CE or OE High to Output Float
0
45
ns
tOH
Output Hold from OE, CE or Address, whichever occurred first
0
tCE
ns
10. AC Read Waveforms(1)(2)(3)(4)
Notes:
1. CE may be delayed up to tACC - tCE after the address transition without impact on tACC.
2. OE may be delayed up to tCE - tOE after the falling edge of CE without impact on tCE or by tACC - tOE after an address change
without impact on tACC.
3. tDF is specified from OE or CE whichever occurs first (CL = 5 pF).
4. This parameter is characterized and is not 100% tested.
6
AT28C64E
0001I–PEEPR–10/06
AT28C64E
11. Input Test Waveforms and Measurement Level
tR, tF < 20 ns
12. Output Test Load
13. Pin Capacitance
f = 1 MHz, T = 25°C(1)
Symbol
Typ
Max
Units
Conditions
CIN
4
6
pF
VIN = 0V
COUT
8
12
pF
VOUT = 0V
Note:
1. This parameter is characterized and is not 100% tested.
7
0001I–PEEPR–10/06
14. AC Write Characteristics
Symbol
Parameter
Min
Max
tAS, tOES
Address, OE Setup Time
10
ns
tAH
Address Hold Time
50
ns
tWP
Write Pulse Width (WE or CE)
100
tDS
Data Setup Time
50
ns
tDH, tOEH
Data, OE Hold Time
10
ns
tCS, tCH
CE to WE and WE to CE Setup and Hold Time
0
ns
tDB
Time to Device Busy
50
ns
tWC
Write Cycle Time
200
µs
1000
Units
ns
15. AC Write Waveforms
15.1
WE Controlled
15.2
CE Controlled
8
AT28C64E
0001I–PEEPR–10/06
AT28C64E
16. Data Polling Characteristics(1)
Symbol
Parameter
tDH
Data Hold Time
tOEH
OE Hold Time
tOE
tWR
Notes:
Min
Max
Units
10
ns
10
ns
(2)
OE to Output Delay
Write Recovery Time
Typ
ns
0
ns
1. These parameters are characterized and not 100% tested.
2. See “AC Read Characteristics”.
17. Data Polling Waveforms
18. Chip Erase Waveforms
tS = tH = 1 µsec (min.)
tW = 10 msec (min.)
VH = 12.0 ± 0.5V
9
0001I–PEEPR–10/06
10
AT28C64E
0001I–PEEPR–10/06
AT28C64E
19. Ordering Information
19.1
Standard Package
ICC (mA)
tACC
(ns)
Active
Standby
Ordering Code
Package
120
45
0.1
AT28C64E-12JI
AT28C64E-12PI
AT28C64E-12SI
AT28C64E-12TI
32J
28P6
28S
28T
19.2
Industrial
(-40° C to 85° C)
Green Package (Pb/Halide-free)
ICC (mA)
tACC
(ns)
Active
Standby
120
45
0.1
19.3
Operation Range
Ordering Code
Package
AT28C64E-12JU
AT28C64E-12PU
AT28C64E-12SU
AT28C64E-12TU
32J
28P6
28S
28T
Operation Range
Industrial
(-40° C to 85° C)
Package Type
32J
32-lead, Plastic J-leaded Chip Carrier (PLCC)
28P6
28-lead, 0.600" Wide, Plastic Dull Inline Package (PDIP)
28S
28-lead, 0.300" Wide, Plastic Gull Wing, Small Outline (SOIC)
28T
28-lead, Plastic Thin Small Outline Package (TSOP)
20. Valid Part Numbers
The following table lists standard Atmel® products that can be ordered.
Device Numbers
AT28C64E
Speed
12
Package and Temperature Combinations
JI, JU, PI, PU, SI, SU, TI, TU
21. Die Products
Reference Section: Parallel EEPROM Die Products
11
0001I–PEEPR–10/06
22. Packaging Information
22.1
32J – PLCC
1.14(0.045) X 45˚
PIN NO. 1
IDENTIFIER
1.14(0.045) X 45˚
0.318(0.0125)
0.191(0.0075)
E1
E2
B1
E
B
e
A2
D1
A1
D
A
0.51(0.020)MAX
45˚ MAX (3X)
COMMON DIMENSIONS
(Unit of Measure = mm)
D2
Notes:
1. This package conforms to JEDEC reference MS-016, Variation AE.
2. Dimensions D1 and E1 do not include mold protrusion.
Allowable protrusion is .010"(0.254 mm) per side. Dimension D1
and E1 include mold mismatch and are measured at the extreme
material condition at the upper or lower parting line.
3. Lead coplanarity is 0.004" (0.102 mm) maximum.
SYMBOL
MIN
NOM
MAX
A
3.175
–
3.556
A1
1.524
–
2.413
A2
0.381
–
–
D
12.319
–
12.573
D1
11.354
–
11.506
D2
9.906
–
10.922
E
14.859
–
15.113
E1
13.894
–
14.046
E2
12.471
–
13.487
B
0.660
–
0.813
B1
0.330
–
0.533
e
NOTE
Note 2
Note 2
1.270 TYP
10/04/01
R
12
2325 Orchard Parkway
San Jose, CA 95131
TITLE
32J, 32-lead, Plastic J-leaded Chip Carrier (PLCC)
DRAWING NO.
REV.
32J
B
AT28C64E
0001I–PEEPR–10/06
AT28C64E
22.2
28P6 – PDIP
D
PIN
1
E1
A
SEATING PLANE
A1
L
B
B1
e
E
0º ~ 15º
C
COMMON DIMENSIONS
(Unit of Measure = mm)
REF
MIN
NOM
MAX
A
–
–
4.826
A1
0.381
–
–
D
36.703
–
37.338
E
15.240
–
15.875
E1
13.462
–
13.970
B
0.356
–
0.559
B1
1.041
–
1.651
L
3.048
–
3.556
C
0.203
–
0.381
eB
15.494
–
17.526
SYMBOL
eB
Notes:
1. This package conforms to JEDEC reference MS-011, Variation AB.
2. Dimensions D and E1 do not include mold Flash or Protrusion.
Mold Flash or Protrusion shall not exceed 0.25 mm (0.010").
e
NOTE
Note 2
Note 2
2.540 TYP
09/28/01
R
2325 Orchard Parkway
San Jose, CA 95131
TITLE
28P6, 28-lead (0.600"/15.24 mm Wide) Plastic Dual
Inline Package (PDIP)
DRAWING NO.
28P6
REV.
B
13
0001I–PEEPR–10/06
22.3
28S – SOIC
Dimensions in Millimeters and (Inches).
Controlling dimension: Millimeters.
0.51(0.020)
0.33(0.013)
7.60(0.2992) 10.65(0.419)
7.40(0.2914) 10.00(0.394)
PIN 1
1.27(0.50) BSC
TOP VIEW
18.10(0.7125)
17.70(0.6969)
2.65(0.1043)
2.35(0.0926)
0.30(0.0118)
0.10(0.0040)
SIDE VIEWS
0.32(0.0125)
0.23(0.0091)
0º ~ 8º
1.27(0.050)
0.40(0.016)
8/4/03
R
14
2325 Orchard Parkway
San Jose, CA 95131
TITLE
28S, 28-lead, 0.300" Body, Plastic Gull Wing Small Outline (SOIC)
JEDEC Standard MS-013
DRAWING NO.
REV.
28S
B
AT28C64E
0001I–PEEPR–10/06
AT28C64E
22.4
28T – TSOP
PIN 1
0º ~ 5º
c
Pin 1 Identifier Area
D1 D
L
b
e
L1
A2
E
A
GAGE PLANE
SEATING PLANE
COMMON DIMENSIONS
(Unit of Measure = mm)
A1
MIN
NOM
MAX
A
–
–
1.20
A1
0.05
–
0.15
A2
0.90
1.00
1.05
D
13.20
13.40
13.60
D1
11.70
11.80
11.90
Note 2
E
7.90
8.00
8.10
Note 2
L
0.50
0.60
0.70
SYMBOL
Notes:
1. This package conforms to JEDEC reference MO-183.
2. Dimensions D1 and E do not include mold protrusion. Allowable
protrusion on E is 0.15 mm per side and on D1 is 0.25 mm per side.
3. Lead coplanarity is 0.10 mm maximum.
L1
NOTE
0.25 BASIC
b
0.17
0.22
0.27
c
0.10
–
0.21
e
0.55 BASIC
12/06/02
R
2325 Orchard Parkway
San Jose, CA 95131
TITLE
28T, 28-lead (8 x 13.4 mm) Plastic Thin Small Outline
Package, Type I (TSOP)
DRAWING NO.
REV.
28T
C
15
0001I–PEEPR–10/06
Atmel Corporation
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Tel: 1(408) 441-0311
Fax: 1(408) 487-2600
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0001I–PEEPR–10/06