AT28HC256E-70TU

AT28HC256 Military Grade 256-Kbit (32,768 x 8) High-Speed Paged Parallel EEPROM Features • • • • • • • • • • • Fast Read Access Time: 90 ns Automatic Page Write Operation: – Internally organized as 32,768 x 8 (256K) – Internal address and data latches for 64 bytes – Internal control timer Fast Write Cycle Time: – Page Write cycle time: 3 ms or 10 ms maximum – 1 to 64-byte Page Write operation Low-Power Dissipation: – 80 mA active current – 3 mA CMOS standby current Hardware and Software Data Protection DATA Polling for End of Write Detection High Reliability CMOS Technology: – Endurance: 10,000 or 100,000 cycles – Data retention: 10 years Single 5V ± 10% Supply CMOS and TTL Compatible Inputs and Outputs ® JEDEC Approved Byte-Wide Pinout Full Military Temperature Range Packages • 32-Lead CERDIP, 32-Lead Flatpack, 32-Lead CLCC and 30-Pin PGA © 2020 Microchip Technology Inc. Datasheet DS20006352A-page 1 AT28HC256 Table of Contents Features......................................................................................................................................................... 1 Packages........................................................................................................................................................1 1. Package Types (not to scale)..................................................................................................................4 2. Pin Descriptions...................................................................................................................................... 5 3. Description.............................................................................................................................................. 6 3.1. 4. Block Diagram.............................................................................................................................. 6 Electrical Characteristics.........................................................................................................................7 4.1. 4.2. 4.3. 4.4. Absolute Maximum Ratings..........................................................................................................7 DC and AC Operating Range.......................................................................................................7 DC Characteristics....................................................................................................................... 7 Pin Capacitance........................................................................................................................... 8 5. Normalized ICC Graphics.........................................................................................................................9 6. Device Operation.................................................................................................................................. 10 6.1. 6.2. 6.3. 6.4. 6.5. 6.6. 6.7. 6.8. 6.9. 6.10. 6.11. 6.12. 6.13. 6.14. 6.15. 6.16. 6.17. 7. Packaging Information.......................................................................................................................... 21 7.1. 8. Operating Modes........................................................................................................................ 11 AC Read Characteristics............................................................................................................ 11 AC Read Waveforms..................................................................................................................12 Input Test Waveforms and Measurement Level......................................................................... 12 Output Test Load........................................................................................................................ 12 AC Write Characteristics............................................................................................................ 13 AC Write Waveforms.................................................................................................................. 13 Page Mode Characteristics........................................................................................................ 14 Page Mode Write Waveforms(1,2)............................................................................................... 15 Chip Erase Waveforms...............................................................................................................15 Software Data Protection Enable Algorithm(1)............................................................................16 Software Data Protection Disable Algorithm(1)...........................................................................17 Software Protected Program Cycle Waveform(1,2)..................................................................... 18 Data Polling Characteristics(1)....................................................................................................18 Data Polling Waveforms............................................................................................................. 19 Toggle Bit Characteristics(1)....................................................................................................... 19 Toggle Bit Waveforms.................................................................................................................19 Package Marking Information.....................................................................................................21 Revision History.................................................................................................................................... 26 The Microchip Website.................................................................................................................................27 Product Change Notification Service............................................................................................................27 Customer Support........................................................................................................................................ 27 Product Identification System.......................................................................................................................28 © 2020 Microchip Technology Inc. Datasheet DS20006352A-page 2 AT28HC256 Microchip Devices Code Protection Feature................................................................................................ 29 Legal Notice................................................................................................................................................. 30 Trademarks.................................................................................................................................................. 30 Quality Management System....................................................................................................................... 31 Worldwide Sales and Service.......................................................................................................................32 © 2020 Microchip Technology Inc. Datasheet DS20006352A-page 3 AT28HC256 Package Types (not to scale) Package Types (not to scale) 32-Pad CLCC(1) Top View A7 A12 A14 DC VCC WE A13 28-Lead PGA 4 3 2 1 32 31 30 5 6 7 8 9 10 11 12 13 29 28 27 26 25 24 23 22 21 A8 A9 A11 NC OE A10 CE I/O7 I/O6 14 15 16 17 18 19 20 A6 A5 A4 A3 A2 A1 A0 NC I/O0 Top View I/O1 I/O2 GND DC I/O3 I/O4 I/O5 1. 28-Lead Cerdip/Flatpack Top View A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC WE A13 A8 A9 A11 OE A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 Note:  1. CLCC package pins 1 and 17 are “Don’t Connect”. © 2020 Microchip Technology Inc. Datasheet DS20006352A-page 4 AT28HC256 Pin Descriptions 2. Pin Descriptions The descriptions of the pins are listed in Table 2-1. Table 2-1. Pin Function Table Name 32‑Lead CERDIP 32-Lead CLCC DC A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 NC I/O0 I/O1 I/O2 GND DC I/O3 I/O4 I/O5 I/O6 I/O7 CE A10 OE NC A11 A9 A8 A13 WE VCC — 1 2 3 4 5 6 7 8 9 10 — 11 12 13 14 — 15 16 17 18 19 20 21 22 — 23 24 25 26 27 28 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 © 2020 Microchip Technology Inc. 32-Lead FLATPACK — 1 2 3 4 5 6 7 8 9 10 — 11 12 13 14 — 15 16 17 18 19 20 21 22 — 23 24 25 26 27 28 Datasheet 30‑Pin PGA — 1 2 3 4 5 6 7 8 9 10 — 11 12 13 14 — 15 16 17 18 19 20 21 22 — 23 24 25 26 27 28 Function Don’t Connect Address Address Address Address Address Address Address Address Address Address No Connect Data Input/Output Data Input/Output Data Input/Output Ground Don’t Connect Data Input/Output Data Input/Output Data Input/Output Data Input/Output Data Input/Output Chip Enable Address Output Enable No Connect Address Address Address Address Write Enable Device Power Supply DS20006352A-page 5 AT28HC256 Description 3. Description The AT28HC256 is a high‑performance Electrically Erasable and Programmable Read‑Only Memory (EEPROM). Its 256‑Kb memory is organized as 32,768 words by 8 bits. Manufactured with Microchip’s advanced nonvolatile CMOS technology, the device offers access times to 90 ns with power dissipation of just 440 mW. When the device is deselected, the CMOS standby current is less than 5 mA. The AT28HC256 is accessed like a Static RAM for the read or write cycle without the need for external components. The device contains a 64‑byte page register to allow writing of up to 64 bytes simultaneously. During a write cycle, the address and 1 to 64 bytes of data are internally latched, freeing the address and data bus for other operations. Following the initiation of a write cycle, the device will automatically write the latched data using an internal control timer. The end of a write cycle can be detected by DATA Polling of I/O7. Once the end of a write cycle has been detected, a new access for a read or write can begin. The AT28HC256 has additional features to ensure high quality and manufacturability. The device utilizes internal error correction for extended endurance and improved data retention characteristics. An optional software data protection mechanism is available to guard against inadvertent writes. The device also includes an extra 64 bytes of EEPROM for device identification or tracking. 3.1 Block Diagram VCC Data Inputs/Outputs I/O0-I/O7 GND OE WE OE, CE and WE Logic CE Address Inputs © 2020 Microchip Technology Inc. Data Latch Input/Output Buffers Y-Gating Y Decoder X Decoder Datasheet Cell Matrix Identification DS20006352A-page 6 AT28HC256 Electrical Characteristics 4. Electrical Characteristics 4.1 Absolute Maximum Ratings Temperature under bias -55°C to +125°C Storage temperature -65°C to +150°C All input voltages (including NC pins) with respect to ground -0.6V to +6.25V All output voltages with respect to ground -0.6V to VCC + 0.6V Voltage on OE and A9 with respect to ground -0.6V to +13.5V Note:  Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 4.2 DC and AC Operating Range Table 4-1. DC and AC Operating Range Operating Temperature (Case) Military AT28HC256‑90 AT28HC256‑12 -55°C to +125°C -55°C to +125°C 5V ± 10% 5V ± 10% Test Conditions VCC Power Supply 4.3 DC Characteristics Table 4-2. DC Characteristics Parameter Symbol Minimum Maximum Units Input Load Current ILI — 10 μA VIN = 0V to VCC + 1V Output Leakage Current ILO — 10 μA VI/O = 0V to VCC VCC Standby Current TTL ISB1 — 3 mA CE = 2.0V to VCC + 1V VCC Standby Current CMOS ISB2 — 300 μA CE = VCC - 0.3V to VCC VCC Active Current ICC — 80 mA f = 5 MHz; IOUT = 0 mA Input Low Voltage VIL — 0.8 V Input High Voltage VIH 2.0 — V Output Low Voltage VOL — 0.45 V IOL = 6.0 mA Output High Voltage VOH1 2.4 — V IOH = -4 mA © 2020 Microchip Technology Inc. Datasheet DS20006352A-page 7 AT28HC256 Electrical Characteristics 4.4 Pin Capacitance Table 4-3. Pin Capacitance(1,2) Symbol Typical Maximum Units Conditions CIN 4 6 pF VIN = 0V COUT 8 12 pF VOUT = 0V Note:  1. This parameter is characterized but is not 100% tested in production. 2. f = 1 MHz, TA = 25°C © 2020 Microchip Technology Inc. Datasheet DS20006352A-page 8 AT28HC256 Normalized ICC Graphics Normalized ICC Graphics Figure 5-1. Normalized Supply Current vs. Temperature Normalized ICC 1.3 1.2 1.1 1.0 0.9 0.8 -55 -25 5 35 65 Temperature (°C) 95 125 Figure 5-2. Normalized Supply Current vs. Address Frequency Normalized ICC 1.1 VCC = 5V T = 25°C 1.0 0.9 0.8 0.7 0.6 0 2 4 6 Frequency (MHz) 8 10 Figure 5-3. Normalized Supply Current vs. Supply Voltage 1.4 Normalized ICC 5. 1.2 1.0 0.8 0.6 4.50 © 2020 Microchip Technology Inc. 5.00 5.25 4.75 Supply Voltage(V) Datasheet 5.50 DS20006352A-page 9 AT28HC256 Device Operation 6. Device Operation READ: The AT28HC256 is accessed like a Static RAM. When CE and OE are low and WE is high, the data stored at the memory location determined by the address pins is asserted on the outputs. The outputs are put in the highimpedance state when either CE or OE is high. This dual-line control gives designers flexibility in preventing bus contention in their system. BYTE WRITE: A low pulse on the WE or CE input with CE or WE low (respectively) and OE high initiates a write cycle. The address is latched on the falling edge of CE or WE, whichever occurs last. The data is latched by the first rising edge of CE or WE. Once a byte write is started, it will automatically time itself to completion. Once a programming operation is initiated and for the duration of tWC, a read operation will effectively be a polling operation. PAGE WRITE: The page write operation of the AT28HC256 allows 1 to 64 bytes of data to be written into the device during a single internal programming period. A page write operation is initiated in the same manner as a byte write; the first byte written can then be followed by 1 to 63 additional bytes. Each successive byte must be written within 150 µs (tBLC) of the previous byte. If the tBLC limit is exceeded, the AT28HC256 will cease accepting data and commence the internal programming operation. All bytes during a page write operation must reside on the same page as defined by the state of the A6‑A14 inputs. For each WE high‑to‑low transition during the page write operation, A6‑A14 must be the same. The A0 to A5 inputs are used to specify which bytes within the page are to be written. The bytes may be loaded in any order and may be altered within the same load period. Only bytes which are specified for writing will be written; unnecessary cycling of other bytes within the page does not occur. DATA POLLING: The AT28HC256 features DATA Polling to indicate the end of a write cycle. During a byte or page write cycle, an attempted read of the last byte written will result in the complement of the written data to be presented on I/O7. Once the write cycle has been completed, true data is valid on all outputs, and the next write cycle may begin. DATA Polling may begin at any time during the write cycle. TOGGLE BIT: In addition to DATA Polling, the AT28HC256 provides another method for determining the end of a write cycle. During the write operation, successive attempts to read data from the device will result in I/O6 toggling between one and zero. Once the write has completed, I/O6 will stop toggling and valid data will be read. Reading the toggle bit may begin at any time during the write cycle. DATA PROTECTION: If precautions are not taken, inadvertent writes may occur during transitions of the host system power supply. Microchip incorporated both hardware and software features that will protect the memory against inadvertent writes. HARDWARE PROTECTION: Hardware features protect against inadvertent writes to the AT28HC256 in the following ways: • VCC sense – if VCC is below 3.8V (typical), the write function is inhibited • VCC power‑on delay – once VCC has reached 3.8V, the device will automatically time out 5 ms (typical) before allowing a write • write inhibit – holding any one of OE low, CE high or WE high inhibits write cycles • noise filter – pulses of less than 15 ns (typical) on the WE or CE inputs will not initiate a write cycle SOFTWARE DATA PROTECTION: A software-controlled data protection feature has been implemented on the AT28HC256. When enabled, the software data protection (SDP) will prevent inadvertent writes. The SDP feature may be enabled or disabled by the user; the AT28HC256 is shipped with SDP disabled. SDP is enabled by the host system issuing a series of three write commands; three specific bytes of data are written to three specific addresses (refer to Software Data Protection Algorithm). After writing the 3‑byte command sequence and after tWC, the entire AT28HC256 will be protected against inadvertent write operations. It should be noted that, once protected, the host may still perform a byte or page write to the AT28HC256. This is done by preceding the data to be written by the same 3‑byte command sequence used to enable SDP. Once set, SDP will remain active unless the disable command sequence is issued. Power transitions do not disable SDP and SDP will protect the AT28HC256 during power‑up and power‑down conditions. All command sequences must conform to the page write timing specifications. The data in the enable and disable command sequences is not written to the device and the memory addresses used in the sequence may be written with data in either a byte or page write operation. © 2020 Microchip Technology Inc. Datasheet DS20006352A-page 10 AT28HC256 Device Operation After setting SDP, any attempt to write to the device without the 3‑byte command sequence will start the internal write timers. No data will be written to the device; however, for the duration of tWC, read operations will effectively be polling operations. DEVICE IDENTIFICATION: An extra 64 bytes of EEPROM memory are available to the user for device identification. By raising A9 to 12V ± 0.5V and using address locations 7FC0H to 7FFFH, the bytes may be written to or read from in the same manner as the regular memory array. OPTIONAL CHIP ERASE MODE: The entire device can be erased using a 6‑byte software code. See Software Chip Erase application note for details. 6.1 Operating Modes Table 6-1. Operating Modes Mode CE OE WE I/O Read VIL VIL VIH DOUT Write(1) VIL VIH VIL DIN VIH X(2) X High-Z Write Inhibit X X VIH Write Inhibit X VIL X Output Disable X VIH X High-Z VIL VH(3) VIL High-Z Standby/Write Inhibit Chip Erase Note:  1. Refer to AC Programming Waveforms. 2. X can be VIL or VH. 3. VH = 12.0 V ± 0.5V 6.2 AC Read Characteristics Table 6-2. AC Read Characteristics Parameter Symbol AT28HC256‑90 AT28HC256‑12 Units Min. Max. Min. Max. tACC — 90 — 120 ns CE to Output Delay tCE (1) — 90 — 120 ns OE to Output Delay tOE(2) 0 40 0 50 ns 0 40 0 50 ns 0 — 0 — ns Address to Output Delay CE or OE to Output Float Output Hold from OE or CE, whichever occurred first tDF (3,4) tOH Note:  1. CE may be delayed up to tACC‑tCE after the address transition without impact on tACC. 2. OE may be delayed up to tCE‑tOE after the falling edge of CE without impact on tCE or by tACC‑tOE after an address change without impact in tACC. 3. tDF is specified from OE or CE, whichever occurs first (CL = 5 pF). 4. This parameter is characterized and is not 100% tested. © 2020 Microchip Technology Inc. Datasheet DS20006352A-page 11 AT28HC256 Device Operation 6.3 AC Read Waveforms ADDRESS VALID ADDRESS CE tCE tOE OE tOH tACC High-Z OUTPUT 6.4 tDF OUTPUT VALID Input Test Waveforms and Measurement Level 3.0V AC DRIVING LEVELS AC MEASUREMENT LEVELS 1.5V 0.0V Note:  tR, tF < 5 ns. 6.5 Output Test Load 5.0V 1.8K OUTPUT PIN 1.3K © 2020 Microchip Technology Inc. 100 pF Datasheet DS20006352A-page 12 AT28HC256 Device Operation 6.6 AC Write Characteristics Table 6-3. AC Write Characteristics Parameter Symbol Minimum Maximum Units tAS, tOES 0 — ns Address Hold Time tAH 50 — ns Chip Select Setup Time tCS 0 — ns Chip Select Hold Time tCH 0 — ns Write Pulse Width (WE or CE) tWP 100 — ns Data Setup Time tDS 50 — ns tDH, tOEH 0 — µs tDV NR(1) — Address, OE Setup Time Data, OE Hold Time Time to Data Valid Note:  1. NR = No Restriction 6.7 AC Write Waveforms 6.7.1 WE Controlled OE tOES tOEH ADDRESS tAS CE tAH tCH tCS WE tWPH tWP tDV tDS tDH DATA IN © 2020 Microchip Technology Inc. Datasheet DS20006352A-page 13 AT28HC256 Device Operation 6.7.2 CE Controlled OE tOES tOEH ADDRESS tAS WE tAH tCH tCS CE tWPH tWP tDV tDH tDS DATA IN 6.8 Page Mode Characteristics Table 6-4. Page Mode Characteristics Parameter Write Cycle Time Symbol AT28HC256 AT28HC256F tWC Minimum Maximum Units — 10 ms — 3 ms Address Setup Time tAS 0 — ms Address Hold Time tAH 50 — ns Data Setup Time tDS 50 — ns Data Hold Time tDH 0 — ns Write Pulse Width tWP 100 — ns Byte Load Cycle Time tBLC — 150 µs Write Pulse Width High tWPH 50 — ns © 2020 Microchip Technology Inc. Datasheet DS20006352A-page 14 AT28HC256 Device Operation 6.9 Page Mode Write Waveforms(1,2) OE CE WE A0-A14 tWPH tWP tAS tBLC tDH tAH VALID ADD tDS DATA VALID DATA BYTE 0 BYTE 1 BYTE 2 BYTE 62 BYTE 3 BYTE 63 tWC Note:  1. A6 through A14 must specify the page address during each high-to-low transition of WE (or CE). 2. OE must be high only when WE and CE are both low. 6.10 Chip Erase Waveforms VIH CE VIL VH(3) OE VIH tS(1) tH VIH WE VIL tW(2) Note:  1. tS = tH = 5 µsec (minimum) 2. tW = 10 msec (minimum) 3. VH = 12.0V ± 0.5V © 2020 Microchip Technology Inc. Datasheet DS20006352A-page 15 AT28HC256 Device Operation 6.11 Software Data Protection Enable Algorithm(1) LOAD DATA AA TO ADDRESS 5555 LOAD DATA 55 TO ADDRESS 2AAA LOAD DATA A0 TO ADDRESS 5555 WRITES ENABLED(2) LOAD DATA XX TO ANY ADDRESS(3) LOAD LAST BYTE TO LAST ADDRESS ENTER DATA PROTECT STATE Note:  1. Data format: I/O7-I/O0 (Hex); Address format: A14-A0 (Hex). 2. Write-Protect state will be activated at end of write even if no other data is loaded. 3. 1 to 64 bytes of data are loaded. © 2020 Microchip Technology Inc. Datasheet DS20006352A-page 16 AT28HC256 Device Operation 6.12 Software Data Protection Disable Algorithm(1) LOAD DATA AA TO ADDRESS 5555 LOAD DATA 55 TO ADDRESS 2AAA LOAD DATA 80 TO ADDRESS 5555 LOAD DATA AA TO ADDRESS 5555 LOAD DATA 55 TO ADDRESS 2AAA LOAD DATA 20 TO ADDRESS 5555 EXIT DATA PROTECT STATE(2) LOAD DATA XX TO ANY ADDRESS(3) LOAD LAST BYTE TO LAST ADDRESS Note:  1. Data format: I/O7-I/O0 (Hex); Address format: A14-A0 (Hex). 2. Write-Protect state will be deactivated at end of write period even if no other data is loaded. 3. 1 to 64 bytes of data are loaded. © 2020 Microchip Technology Inc. Datasheet DS20006352A-page 17 AT28HC256 Device Operation 6.13 Software Protected Program Cycle Waveform(1,2) OE CE tWPH tWP WE tAS tBLC tAH BYTE ADDRESS A0-A5 A6-A14 tDS tDH PAGE ADDRESS DATA BYTE 0 BYTE 62 BYTE 63 tWC Note:  1. A6-A14 must specify the same page address during each high-to-low transition of WE (or CE) after the software code has been entered. 2. OE must be high only when WE and CE are both low. 6.14 Data Polling Characteristics(1) Table 6-5. Data Polling Characteristics Parameter Symbol Minimum Typical Maximum Units Data Hold Time tDH 0 — — ns OE Hold Time tOEH 0 — — ns OE to Output Delay(2) tOE — — — ns Write Recovery Time tWR 0 — — ns Note:  1. These parameters are characterized and not 100% tested. 2. See AC Read Characteristics. © 2020 Microchip Technology Inc. Datasheet DS20006352A-page 18 AT28HC256 Device Operation 6.15 Data Polling Waveforms WE CE tOEH OE tDH tOE I/O7 6.16 High-Z AN A0-A14 tWR AN AN AN AN Toggle Bit Characteristics(1) Table 6-6. Toggle Bit Characteristics Parameter Symbol Minimum Typical Maximum Units Data Hold Time tDH 10 — — ns OE Hold Time tOEH 10 — — ns OE to Output Delay(2) tOE — — — ns tOEHP 150 — — ns tWR 0 — — ns OE High Pulse(2) Write Recovery Time Note:  1. These parameters are characterized and not 100% tested. 2. See AC Read Characteristics. 6.17 Toggle Bit Waveforms WE CE tOEH OE tDH I/O6 (2) © 2020 Microchip Technology Inc. tOE High-Z Datasheet tWR DS20006352A-page 19 AT28HC256 Device Operation Note:  1. Toggling either OE or CE or both OE and CE will operate toggle bit. 2. Beginning and ending state of I/O6 will vary. 3. Any address location may be used but the address should not vary. © 2020 Microchip Technology Inc. Datasheet DS20006352A-page 20 AT28HC256 Packaging Information 7. Packaging Information 7.1 Package Marking Information AT28HC256: Package Marking Information (SMD devices) 28-pin CERDIP Topside 32-pad CLCC Backside Δ Topside YWWNNN-19104S 1&&&&&&-$ YYWW ATMEL 5962-88634 ##XA C AT28HC256@ %%DM/883 YQyywwl Δ ATMEL 5962-88634 ##YA YQyywwl AT28HC256@ %%LM/883 C 28-lead FLATPACK Topside Δ ## = SMD Device 03: 90ns, 10ms TWC 01: 120ns, 10ms TWC 04: 90ns, 3ms TWC 02: 120ns, 3ms TWC YWWNNN-19104S 1&&&&&&-$ YYWW %% = Access Time 90: 90 ns 12: 120 ns YWWNNNS 19104 1&&&&&&-$ YYWW 30-pin PGA Backside ATMEL 5962-88634 ##ZA C AT28HC256@ %%FM/883 YQyywwl Backside Topside Edges ATMEL 5962-88634 ##UA YQyywwl AT28HC256@ %%UM/883 C 1&&&&&&-$ YYWW Δ YQNNNN-19104S @ = Write Endurance Rating Blank: Standard (10K at 10ms) E: Extended (100K at 10ms) F: Fast Write (10k at 3ms) $ = Assembly Location F: Philippines N: Thailand Country of Assembly Lot Trace Code Seal Year and Work Week &&&&&&: Country of Assembly YWWNNN: Lot Trace Code YYWW: Seal Year and Work Week Year, Quarter, Seal Year, Seal Week and Group D Coverage (Military Date Code) YQyywwl: Year, Quarter, Seal Year, Seal Week and Group D Coverage (Military Date Code) © 2020 Microchip Technology Inc. Datasheet DS20006352A-page 21 AT28HC256 Packaging Information Dimensions in Millimeters and (Inches). Controlling dimension: Inches. MIL-STD 1835 D-10 Config A (Glass Sealed) 37.85(1.490) 36.58(1.440) PIN 1 15.49(0.610) 12.95(0.510) 5.72(0.225) MAX 33.02(1.300) REF 0.127(0.005)MIN SEA TING PLANE 5.08(0.200) 3.18(0.125) 2.54(0.100)BSC 1.52(0.060) 0.38(0.015) 0.66(0.026) 0.36(0.014) 1.65(0.065) 1.14(0.045) 15.70(0.620) 15.00(0.590) 0.46(0.018) 0.20(0.008) 0º~ 15º REF 17.80(0.700) MAX 10/23/03 TITLE 28D6, 28-lead, 0.600" Wide, Non-windowed, Ceramic Dual Inline Package (Cerdip) DRAWING NO. 28D6 REV. B Note:  For the most current package drawings, please see the Microchip Packaging Specification located at http:// www.microchip.com/packaging. © 2020 Microchip Technology Inc. Datasheet DS20006352A-page 22 AT28HC256 Packaging Information Dimensions in Millimeters and (Inches). Controlling dimension: Inches. MIL-STD 1835 F-12 Config B 9.40(0.370) 6.35(0.250) PIN #1 ID 0.56(0.022) 0.38(0.015) 1.27(0.050) BSC 18.49(0.728) 18.08(0.712) 1.14(0.045) MAX 10.57(0.416) 9.75(0.384) 0.23(0.009) 0.10(0.004) 3.02(0.119) 2.29(0.090) 1.96(0.077) 1.09(0.043) 1.14(0.045) 0.660(0.026) 7.26(0.286) 6.96(0.274) 10/21/03 TITLE 28F, 28-lead, Non-windowed, Ceramic Bottom-brazed Flat Package (FlatPack) DRAWING NO. 28F REV. B Note:  For the most current package drawings, please see the Microchip Packaging Specification located at http:// www.microchip.com/packaging. © 2020 Microchip Technology Inc. Datasheet DS20006352A-page 23 AT28HC256 Packaging Information Dimensions in Millimeters and (Inches). Controlling dimension: Inches. MIL-STD 1835 C-12 11.63(0.458) 11.23(0.442) 2.54(0.100) 2.16(0.085) 14.22(0.560) 13.72(0.540) 1.91(0.075) 1.40(0.055) PIN 1 2.41(0.095) 1.91(0.075) 1.40(0.055) 1.14(0.045) INDEX CORNER 0.635(0.025) X 45° 0.381(0.015) 0.305(0.012) RADIUS 0.178(0.007) 10.16(0.400) BSC 0.737(0.029) 0.533(0.021) 1.27(0.050) TYP 1.02(0.040) X 45° 7.62(0.300) BSC 2.16(0.085) 1.65(0.065) 10/21/03 TITLE 32L, 32-pad, Non-windowed, Ceramic Lid, Leadless Chip Carrier (LCC) DRAWING NO. 32L REV. B Note:  For the most current package drawings, please see the Microchip Packaging Specification located at http:// www.microchip.com/packaging. © 2020 Microchip Technology Inc. Datasheet DS20006352A-page 24 AT28HC256 Packaging Information Dimensions in Millimeters and (Inches). Controlling dimension: Inches. 7.26(0.286) 6.50(0.256) 13.74(0.540) 13.36(0.526) 2.57(0.101) 2.06(0.081) 15.24(0.600) 14.88(0.586) 1.40(0.055) 1.14(0.045) 0.58(0.023) 0.43(0.017) 3.12(0.123) 2.62(0.103) 1.83(0.072) 1.57(0.062) 14.17(0.558) 13.77(0.542) 2.54(0.100) TYP 16.71(0.658) 16.31(0.642) 12.70(0.500) TYP 2.54(0.100) TYP 10.41(0.410) 9.91(0.390) 10/21/03 TITLE 28U, 28-pin, Ceramic Pin Grid Array (PGA) DRAWING NO. 28U REV. B Note:  For the most current package drawings, please see the Microchip Packaging Specification located at http:// www.microchip.com/packaging. © 2020 Microchip Technology Inc. Datasheet DS20006352A-page 25 AT28HC256 Revision History 8. Revision History Revision A (April 2020) Updated to the Microchip template. Microchip DS20006352 replaces Atmel document 0006. Added updated Part Markings to include new trace code format. Atmel Document 0006 Revision M (December 2009) Updated AC Characteristics and ordering information. © 2020 Microchip Technology Inc. Datasheet DS20006352A-page 26 AT28HC256 The Microchip Website Microchip provides online support via our website at http://www.microchip.com/. This website is used to make files and information easily available to customers. Some of the content available includes: • • • Product Support – Data sheets and errata, application notes and sample programs, design resources, user’s guides and hardware support documents, latest software releases and archived software General Technical Support – Frequently Asked Questions (FAQs), technical support requests, online discussion groups, Microchip design partner program member listing Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives Product Change Notification Service Microchip’s product change notification service helps keep customers current on Microchip products. Subscribers will receive email notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, go to http://www.microchip.com/pcn and follow the registration instructions. Customer Support Users of Microchip products can receive assistance through several channels: • • • • Distributor or Representative Local Sales Office Embedded Solutions Engineer (ESE) Technical Support Customers should contact their distributor, representative or ESE for support. Local sales offices are also available to help customers. A listing of sales offices and locations is included in this document. Technical support is available through the website at: http://www.microchip.com/support © 2020 Microchip Technology Inc. Datasheet DS20006352A-page 27 AT28HC256 Product Identification System To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. AT28 HC 256 (E) - 12 D M /883 /883 = MIL-STD-883 Class B Product AT28 = Parallel EEPROM M = -55°C to +125°C Military Temperature Grade, Sn63/Pb37 Terminal Finish C = 4.5V to 5.5V 256 = 256 Kbit Size Blank = 10K Standard Write Endurance E = 100K Extended Write Endurance Option F = 3 ms Fast Write Option D = 28-Lead, 600 mil Wide, Non-Windowed, Ceramic Dual Inline (Cerdip) L = 32-Pad, Non-Windowed, Combo Lid, Leadless Chip Carrier (CLCC) F = 28-Lead, Non-Windowed, Ceramic Bottom-Brazed Flat Package (Flatpack) U = 30-Pin, Ceramic Pin Grid Array (PGA) 12 = 120 ns Speed 90 = 90 ns Speed WM = Die Sales (contact Microchip) DWFM = Wfer Sales (contact Microhip) Examples Table 12-1. AT28HC256 Ordering Information Ordering Code Standard Military Drawing Number (SMD#) Package Number AT28HC256-90DM/883 5962‑88634 03 XA 28D6 AT28HC256-90FM/883 5962‑88634 03 ZA 28F AT28HC256-90LM/883 5962‑88634 03 YA 32L AT28HC256-90UM/883 5962‑88634 03 UA 28U AT28HC256-12DM/883 5962‑88634 01 XA 28D6 AT28HC256-12FM/883 5962‑88634 01 ZA 28F AT28HC256-12LM/883 5962‑88634 01 YA 32L AT28HC256-12UM/883 5962‑88634 01 UA 28U © 2020 Microchip Technology Inc. Datasheet tACC(ns) Operating Range 90 Military/883C Class B, Fully Compliant (-55°C to 125°C) 120 DS20006352A-page 28 AT28HC256 Table 12-2. AT28HC256E Ordering Information (Not Dual Marked Packages) Ordering Code Standard Military Drawing Number (SMD#) Package Number AT28HC256E‑90DM/883 N/A 28D6 AT28HC256E‑90FM/883 N/A 28F AT28HC256E‑90LM/883 N/A 32L AT28HC256E‑90UM/883 N/A 28U AT28HC256E‑12DM/883 N/A 28D6 AT28HC256E‑12FM/883 N/A 28F AT28HC256E‑12LM/883 N/A 32L AT28HC256E‑12UM/883 N/A 28U tACC(ns) Operating Range 90 Military/883C Class B, Fully Compliant (-55°C to 125°C) 120 Table 12-3. AT28HC256F Ordering Information Ordering Code Standard Military Drawing Number (SMD#) Package Number AT28HC256F‑90DM/883 5962‑88634 04 XA 28D6 AT28HC256F‑90FM/883 5962‑88634 04 ZA 28F AT28HC256F‑90LM/883 5962‑88634 04 YA 32L AT28HC256F‑90UM/883 5962‑88634 04 UA 28U AT28HC256F‑12DM/883 5962‑88634 02 XA 28D6 AT28HC256F‑12FM/883 5962‑88634 02 ZA 28F AT28HC256F‑12LM/883 5962‑88634 02 YA 32L AT28HC256F‑12UM/883 5962‑88634 02 UA 28U tACC(ns) Operating Range 90 Military/883C Class B, Fully Compliant (-55°C to 125°C) 120 Package Types 28D6 28-Lead, 0.600" Wide, Non-Windowed, Ceramic Dual Inline (Cerdip) 28F 28-Lead, Non-Windowed, Ceramic Bottom-Brazed Flat Package (Flatpack) 32L 32-Pad, Non-Windowed, Ceramic Leadless Chip Carrier (LCC) 28U 28-Pin, Ceramic Pin Grid Array (PGA) WM Diced Die Military DWFM Die in Wafer Form Military Options Blank Standard Device: Endurance = 10K Write Cycles; Write Time 10 ms E High Endurance Option: Endurance = 100K Write Cycles F Fast Write Option: Write Time = 3 ms Microchip Devices Code Protection Feature Note the following details of the code protection feature on Microchip devices: © 2020 Microchip Technology Inc. Datasheet DS20006352A-page 29 AT28HC256 • • • • • Microchip products meet the specification contained in their particular Microchip Data Sheet. Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. Microchip is willing to work with the customer who is concerned about the integrity of their code. Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Legal Notice Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights unless otherwise stated. Trademarks The Microchip name and logo, the Microchip logo, Adaptec, AnyRate, AVR, AVR logo, AVR Freaks, BesTime, BitCloud, chipKIT, chipKIT logo, CryptoMemory, CryptoRF, dsPIC, FlashFlex, flexPWR, HELDO, IGLOO, JukeBlox, KeeLoq, Kleer, LANCheck, LinkMD, maXStylus, maXTouch, MediaLB, megaAVR, Microsemi, Microsemi logo, MOST, MOST logo, MPLAB, OptoLyzer, PackeTime, PIC, picoPower, PICSTART, PIC32 logo, PolarFire, Prochip Designer, QTouch, SAM-BA, SenGenuity, SpyNIC, SST, SST Logo, SuperFlash, Symmetricom, SyncServer, Tachyon, TempTrackr, TimeSource, tinyAVR, UNI/O, Vectron, and XMEGA are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. APT, ClockWorks, The Embedded Control Solutions Company, EtherSynch, FlashTec, Hyper Speed Control, HyperLight Load, IntelliMOS, Libero, motorBench, mTouch, Powermite 3, Precision Edge, ProASIC, ProASIC Plus, ProASIC Plus logo, Quiet-Wire, SmartFusion, SyncWorld, Temux, TimeCesium, TimeHub, TimePictra, TimeProvider, Vite, WinPath, and ZL are registered trademarks of Microchip Technology Incorporated in the U.S.A. Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut, BlueSky, BodyCom, CodeGuard, CryptoAuthentication, CryptoAutomotive, CryptoCompanion, CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial Programming, ICSP, INICnet, Inter-Chip Connectivity, JitterBlocker, KleerNet, KleerNet logo, memBrain, Mindi, MiWi, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, PowerSmart, PureSilicon, QMatrix, REAL ICE, Ripple Blocker, SAM-ICE, Serial Quad I/O, SMART-I.S., SQI, SuperSwitcher, SuperSwitcher II, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. The Adaptec logo, Frequency on Demand, Silicon Storage Technology, and Symmcom are registered trademarks of Microchip Technology Inc. in other countries. © 2020 Microchip Technology Inc. Datasheet DS20006352A-page 30 AT28HC256 GestIC is a registered trademark of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. © 2020, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. ISBN: 978-1-5224-6095-4 AMBA, Arm, Arm7, Arm7TDMI, Arm9, Arm11, Artisan, big.LITTLE, Cordio, CoreLink, CoreSight, Cortex, DesignStart, DynamIQ, Jazelle, Keil, Mali, Mbed, Mbed Enabled, NEON, POP, RealView, SecurCore, Socrates, Thumb, TrustZone, ULINK, ULINK2, ULINK-ME, ULINK-PLUS, ULINKpro, µVision, Versatile are trademarks or registered trademarks of Arm Limited (or its subsidiaries) in the US and/or elsewhere. Quality Management System For information regarding Microchip’s Quality Management Systems, please visit http://www.microchip.com/quality. © 2020 Microchip Technology Inc. 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