AT28HC256F-12PI

Features • Fast Read Access Time – 70 ns • Automatic Page Write Operation • • • • • • • • • • – Internal Address and Data Latches for 64 Bytes – Internal Control Timer Fast Write Cycle Times – Page Write Cycle Time: 3 ms or 10 ms Maximum – 1 to 64-byte Page Write Operation Low Power Dissipation – 80 mA Active Current – 3 mA Standby Current Hardware and Software Data Protection DATA Polling for End of Write Detection High Reliability CMOS Technology – Endurance: 104 or 105 Cycles – Data Retention: 10 Years Single 5V ± 10% Supply CMOS and TTL Compatible Inputs and Outputs JEDEC Approved Byte-wide Pinout Full Military, Commercial, and Industrial Temperature Ranges Green (Pb/Halide-free) Packaging Option 256 (32K x 8) High-speed Parallel EEPROM AT28HC256 1. Description The AT28HC256 is a high-performance electrically erasable and programmable readonly memory. Its 256K of memory is organized as 32,768 words by 8 bits. Manufactured with Atmel’s advanced nonvolatile CMOS technology, the AT28HC256 offers access times to 70 ns with power dissipation of just 440 mW. When the AT28HC256 is deselected, the standby current is less than 5 mA. The AT28HC256 is accessed like a Static RAM for the read or write cycle without the need for external components. The device contains a 64-byte page register to allow writing of up to 64 bytes simultaneously. During a write cycle, the address and 1 to 64 bytes of data are internally latched, freeing the addresses and data bus for other operations. Following the initiation of a write cycle, the device will automatically write the latched data using an internal control timer. The end of a write cycle can be detected by DATA Polling of I/O7. Once the end of a write cycle has been detected a new access for a read or write can begin. Atmel’s 28HC256 has additional features to ensure high quality and manufacturability. The device utilizes internal error correction for extended endurance and improved data retention characteristics. An optional software data protection mechanism is available to guard against inadvertent writes. The device also includes an extra 64 bytes of EEPROM for device identification or tracking. 0007J–PEEPR–04/05 2. Pin Configurations Pin Name Function A0 - A14 Addresses CE Chip Enable OE Output Enable WE Write Enable I/O0 - I/O7 Data Inputs/Outputs NC No Connect DC Don’t Connect 28-lead PGA Top View A7 A12 A14 DC VCC WE A13 28 27 26 25 24 23 22 21 20 19 18 17 16 15 A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 GND I/O2 I/O1 I/O0 A0 A1 A2 A6 A5 A4 A3 A2 A1 A0 NC I/O0 4 3 2 1 32 31 30 1 2 3 4 5 6 7 8 9 10 11 12 13 14 32-pad LCC, 32-lead PLCC Top View 5 6 7 8 9 10 11 12 13 A8 A9 A11 NC OE A10 CE I/O7 I/O6 Note: PLCC package pins 1 and 17 are Don’t Connect. 2.4 28-lead Cerdip/PDIP/Flatpack/SOIC – Top View A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 GND 2 29 28 27 26 25 24 23 22 21 14 15 16 17 18 19 20 OE A11 A9 A8 A13 WE VCC A14 A12 A7 A6 A5 A4 A3 2.2 2.3 28-lead TSOP Top View I/O1 I/O2 GND DC I/O3 I/O4 I/O5 2.1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC WE A13 A8 A9 A11 OE A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 AT28HC256 0007J–PEEPR–04/05 AT28HC256 3. Block Diagram 4. Device Operation 4.1 Read The AT28HC256 is accessed like a Static RAM. When CE and OE are low and WE is high, the data stored at the memory location determined by the address pins is asserted on the outputs. The outputs are put in the high impedance state when either CE or OE is high. This dual-line control gives designers flexibility in preventing bus contention in their system. 4.2 Byte Write A low pulse on the WE or CE input with CE or WE low (respectively) and OE high initiates a write cycle. The address is latched on the falling edge of CE or WE, whichever occurs last. The data is latched by the first rising edge of CE or WE. Once a byte write has been started it will automatically time itself to completion. Once a programming operation has been initiated and for the duration of tWC, a read operation will effectively be a polling operation. 4.3 Page Write The page write operation of the AT28HC256 allows 1 to 64 bytes of data to be written into the device during a single internal programming period. A page write operation is initiated in the same manner as a byte write; the first byte written can then be followed by 1 to 63 additional bytes. Each successive byte must be written within 150 µs (tBLC) of the previous byte. If the tBLC limit is exceeded the AT28C256 will cease accepting data and commence the internal programming operation. All bytes during a page write operation must reside on the same page as defined by the state of the A6 - A14 inputs. That is, for each WE high to low transition during the page write operation, A6 - A14 must be the same. The A0 to A5 inputs are used to specify which bytes within the page are to be written. The bytes may be loaded in any order and may be altered within the same load period. Only bytes which are specified for writing will be written; unnecessary cycling of other bytes within the page does not occur. 4.4 DATA Polling The AT28HC256 features DATA Polling to indicate the end of a write cycle. During a byte or page write cycle an attempted read of the last byte written will result in the complement of the written data to be presented on I/O7. Once the write cycle has been completed, true data is valid on all outputs, and the next write cycle may begin. DATA Polling may begin at anytime during the write cycle. 3 0007J–PEEPR–04/05 4.5 Toggle Bit In addition to DATA Polling the AT28HC256 provides another method for determining the end of a write cycle. During the write operation, successive attempts to read data from the device will result in I/O6 toggling between one and zero. Once the write has completed, I/O6 will stop toggling and valid data will be read. Testing the toggle bit may begin at any time during the write cycle. 4.6 Data Protection If precautions are not taken, inadvertent writes to any 5-volt-only nonvolatile memory may occur during transition of the host system power supply. Atmel has incorporated both hardware and software features that will protect the memory against inadvertent writes. 4.6.1 Hardware Protection Hardware features protect against inadvertent writes to the AT28HC256 in the following ways: (a) VCC sense – if VCC is below 3.8V (typical) the write function is inhibited; (b) VCC power-on delay – once VCC has reached 3.8V the device will automatically time out 5 ms typical) before allowing a write; (c) write inhibit – holding any one of OE low, CE high or WE high inhibits write cycles; and (d) noise filter – pulses of less than 15 ns (typical) on the WE or CE inputs will not initiate a write cycle. 4.6.2 Software Data Protection A software controlled data protection feature has been implemented on the AT28HC256. When enabled, the software data protection (SDP), will prevent inadvertent writes. The SDP feature may be enabled or disabled by the user; the AT28HC256 is shipped from Atmel with SDP disabled. SDP is enabled by the host system issuing a series of three write commands; three specific bytes of data are written to three specific addresses (refer to “Software Data Protection” algorithm). After writing the 3-byte command sequence and after tWC the entire AT28HC256 will be protected against inadvertent write operations. It should be noted, that once protected the host may still perform a byte or page write to the AT28HC256. This is done by preceding the data to be written by the same 3-byte command sequence. Once set, SDP will remain active unless the disable command sequence is issued. Power transitions do not disable SDP and SDP will protect the AT28HC256 during power-up and power-down conditions. All command sequences must conform to the page write timing specifications. It should also be noted that the data in the enable and disable command sequences is not written to the device and the memory addresses used in the sequence may be written with data in either a byte or page write operation. After setting SDP, any attempt to write to the device without the three byte command sequence will start the internal write timers. No data will be written to the device; however, for the duration of tWC, read operations will effectively be polling operations. 4.7 Device Identification An extra 64 bytes of EEPROM memory are available to the user for device identification. By raising A9 to 12V ± 0.5V and using address locations 7FC0H to 7FFFH the additional bytes may be written to or read from in the same manner as the regular memory array. 4.8 Optional Chip Erase Mode The entire device can be erased using a 6-byte software code. Please see “Software Chip Erase” application note for details. 4 AT28HC256 0007J–PEEPR–04/05 AT28HC256 5. DC and AC Operating Range AT28HC256-70 AT28HC256-90 AT28HC256-12 0°C - 70°C 0°C - 70°C 0°C - 70°C -40°C - 85°C -40°C - 85°C -40°C - 85°C -55°C - 125°C -55°C - 125°C 5V ± 10% 5V ± 10% Com. Operating Temperature (Case) Ind. Mil. 5V ± 10% VCC Power Supply 6. Operating Modes Mode CE Read Write(2) Standby/Write Inhibit OE WE I/O VIL VIL VIH DOUT VIL VIH VIL DIN VIH (1) X High Z Write Inhibit X Write Inhibit Output Disable Chip Erase Notes: 1. X can be VIL or VIH. X X VIH X VIL X X VIH X High Z VIL High Z VIL VH (3) 2. Refer to AC programming waveforms. 3. VH = 12.0V ± 0.5V. 7. Absolute Maximum Ratings* Temperature under Bias ................................ -55°C to +125°C Storage Temperature ..................................... -65°C to +150°C All Input Voltages (including NC Pins) with Respect to Ground ...................................-0.6V to +6.25V All Output Voltages with Respect to Ground .............................-0.6V to VCC + 0.6V *NOTICE: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability Voltage on OE and A9 with Respect to Ground ...................................-0.6V to +13.5V 8. DC Characteristics Symbol Parameter Condition Min Max Units ILI Input Load Current VIN = 0V to VCC + 1V 10 µA ILO Output Leakage Current VI/O = 0V to VCC 10 µA ISB1 VCC Standby Current TTL CE = 2.0V to VCC AT28HC256-90, -12 3 mA AT28HC256-70 60 mA ISB2 VCC Standby Current CMOS CE = VCC - 0.3V to VCC AT28HC256-90, -12 300 µA ICC VCC Active Current f = 5 MHz; IOUT = 0 mA 80 mA VIL Input Low Voltage 0.8 V VIH Input High Voltage VOL Output Low Voltage IOL = 6.0 mA VOH Output High Voltage IOH = -4 mA 2.0 V 0.45 2.4 V V 5 0007J–PEEPR–04/05 9. AC Read Characteristics AT28HC256-70 Symbol tACC Parameter Min Max AT28C256-90 Min Max AT28HC256-12 Min Max Units Address to Output Delay 70 90 120 ns (1) CE to Output Delay 70 90 120 ns tOE(2) OE to Output Delay 0 35 0 40 0 50 ns tDF(3)(4) CE or OE to Output Float 0 35 0 40 0 50 ns tOH Output Hold from OE, CE or Address, whichever occurred first 0 tCE 0 0 ns 10. AC Read Waveforms(1)(2)(3)(4) Notes: 1. CE may be delayed up to tACC - tCE after the address transition without impact on tACC. 2. OE may be delayed up to tCE - tOE after the falling edge of CE without impact on tCE or by tACC - tOE after an address change without impact on tACC. 3. tDF is specified from OE or CE whichever occurs first (CL = 5 pF). 4. This parameter is characterized and is not 100% tested. 6 AT28HC256 0007J–PEEPR–04/05 AT28HC256 11. Input Test Waveforms and Measurement Level tR, tF < 5 ns 12. Output Test Load 13. Pin Capacitance f = 1 MHz, T = 25°C(1) Symbol CIN COUT Note: Typ Max Units Conditions 4 6 pF VIN = 0V 8 12 pF VOUT = 0V 1. This parameter is characterized and is not 100% tested. 7 0007J–PEEPR–04/05 14. AC Write Characteristics Symbol Parameter tAS, tOES Address, OE Setup Time 0 ns tAH Address Hold Time 50 ns tCS Chip Select Setup Time 0 ns tCH Chip Select Hold Time 0 ns tWP Write Pulse Width (WE or CE) 100 ns tDS Data Setup Time 50 ns tDH, tOEH Data, OE Hold Time 0 ns tDV Time to Data Valid Note: Min Max Units NR(1) 1. NR = No Restriction. 15. AC Write Waveforms 15.1 WE Controlled 15.2 CE Controlled 8 AT28HC256 0007J–PEEPR–04/05 AT28HC256 16. Page Mode Write Characteristics Symbol Parameter Min Typ Max Units tWC Write Cycle Time (option available) AT28HC256 5 10 ms AT28HC256F 2 3 ms tAS Address Setup Time 0 ns tAH Address Hold Time 50 ns tDS Data Setup Time 50 ns tDH Data Hold Time 0 ns tWP Write Pulse Width 100 ns tBLC Byte Load Cycle Time tWPH Write Pulse Width High 150 50 µs ns 17. Page Mode Write Waveforms(1)(2) Notes: 1. A6 through A14 must specify the same page address during each high to low transition of WE (or CE). 2. OE must be high only when WE and CE are both low. 18. Chip Erase Waveforms tS = tH = 5 µsec (min.) tW = 10 msec (min.) VH = 12.0V ± 0.5V 9 0007J–PEEPR–04/05 19. Software Data Protection Enable Algorithm(1) Notes: 20. Software Data Protection Disable Algorithm(1) LOAD DATA AA TO ADDRESS 5555 LOAD DATA AA TO ADDRESS 5555 LOAD DATA 55 TO ADDRESS 2AAA LOAD DATA 55 TO ADDRESS 2AAA LOAD DATA A0 TO ADDRESS 5555 LOAD DATA 80 TO ADDRESS 5555 WRITES ENABLED(2) LOAD DATA XX TO ANY ADDRESS(4) LOAD DATA AA TO ADDRESS 5555 LOAD LAST BYTE TO LAST ADDRESS LOAD DATA 55 TO ADDRESS 2AAA ENTER DATA PROTECT STATE 1. Data Format: I/O7 - I/O0 (Hex); Address Format: A14 - A0 (Hex). 2. Write Protect state will be activated at end of write even if no other data is loaded. 3. Write Protect state will be deactivated at end of write period even if no other data is loaded. 4. 1 to 64 bytes of data are loaded. LOAD DATA 20 TO ADDRESS 5555 EXIT DATA PROTECT STATE(3) LOAD DATA XX TO ANY ADDRESS(4) LOAD LAST BYTE TO LAST ADDRESS 21. Software Protected Write Cycle Waveforms(1)(2) Notes: 1. A6 through A14 must specify the same page address during each high to low transition of WE (or CE) after the software code has been entered. 2. OE must be high only when WE and CE are both low. 10 AT28HC256 0007J–PEEPR–04/05 AT28HC256 22. Data Polling Characteristics(1) Symbol Parameter tDH Data Hold Time tOEH OE Hold Time Min Max OE to Output Delay tWR Write Recovery Time Units 0 ns 0 ns (2) tOE Notes: Typ ns 0 ns 1. These parameters are characterized and not 100% tested. 2. See “AC Read Characteristics” on page 6. 23. Data Polling Waveforms 24. Toggle Bit Characteristics(1) Symbol Parameter tDH Data Hold Time 10 ns tOEH OE Hold Time 10 ns tOE OE to Output Delay(2) tOEHP OE High Pulse tWR Write Recovery Time Notes: Min Typ Max Units ns 150 ns 0 ns 1. These parameters are characterized and not 100% tested. 2. See “AC Read Characteristics” on page 6. 25. Toggle Bit Waveforms Notes: 1. Toggling either OE or CE or both OE and CE will operate toggle bit. 2. Beginning and ending state of I/O6 will vary. 3. Any address location may be used but the address should not vary. 11 0007J–PEEPR–04/05 26. Normalized ICC Graphs 12 AT28HC256 0007J–PEEPR–04/05 AT28HC256 27. Ordering Information(1) 27.1 Standard Package ICC (mA) tACC (ns) Active Standby 70 80 90 120 80 Ordering Code Package Operation Range 60 AT28HC256(E,F)-70JC AT28HC256(E,F)-70PC 32J 28P6 Commercial (0°C to 70°C) 0.3 AT28HC256(E,F)-70JI AT28HC256(E,F)-70PI 32J 28P6 Industrial (-40°C to 85°C) 0.3 AT28HC256(E,F)-90JC AT28HC256(E,F)-90PC 32J 28P6 Commercial (0°C to 70°C) AT28HC256(E,F)-90JI AT28HC256(E,F)-90PI 32J 28P6 Industrial (-40°C to 85°C) 80 0.3 AT28HC256(E,F)-90DM/883 AT28HC256(E,F)-90FM/883 AT28HC256(E,F)-90LM/883 AT28HC256(E,F)-90UM/883 28D6 28F 32L 28U Military/883C Class B, Fully Compliant (-55°C to 125°C) 80 0.3 AT28HC256(E,F)-12JC AT28HC256(E,F)-12PC AT28HC256(E,F)-12SC AT28HC256(E,F)-12TC 32J 28P6 28S 28T Commercial (0°C to 70°C) 80 0.3 AT28HC256(E,F)-12JI AT28HC256(E,F)-12PI AT28HC256(E,F)-12SI AT28HC256(E,F)-12TI 32J 28P6 28S 28T Industrial (-40°C to 85°C) 80 0.3 AT28HC256(E,F)-12DM/883 AT28HC256(E,F)-12FM/883 AT28HC256(E,F)-12LM/883 AT28HC256(E,F)-12UM/883 28D6 28F 32L 28U Military/883C Class B, Fully Compliant (-55°C to 125°C) Package Type 28D6 28-lead, 0.600" Wide, Non-windowed, Ceramic Dual Inline Package (Cerdip) 28F 28-lead, Non-windowed, Ceramic Bottom-brazed Flat Package (Flatpack) 32J 32-lead, Plastic J-leaded Chip Carrier (PLCC) 32L 32-pad, Non-windowed, Ceramic Leadless Chip Carrier (LCC) 28P6 28-lead, 0.600" Wide, Plastic Dual Inline Package (PDIP) 28S 28-lead, 0.300" Wide Plastic Gull Wing Small Outline (SOIC) 28T 28-lead, Plastic Thin Small Outline Package (TSOP) 28U 28-pin, Ceramic Pin Grid Array (PGA) W Die Options Blank Standard Device: Endurance = 10K Write Cycles; Write Time = 10 ms E High Endurance Option: Endurance = 100K Write Cycles F Fast Write Option: Write Time = 3 ms 13 0007J–PEEPR–04/05 27.1 Standard Package (Continued) ICC (mA) tACC (ns) Active Standby 90 80 120 Note: Ordering Code Package Operation Range 0.3 5962-88634 03 UX 5962-88634 03 XX 5962-88634 03 YX 5962-88634 03 ZX 28U 28D6 32L 28F Military/883C Class B, Fully Compliant (-55°C to 125°C) 80 0.3 5962-88634 04 UX 5962-88634 04 XX 5962-88634 04 YX 5962-88634 04 ZX 28U 28D6 32L 28F Military/883C Class B, Fully Compliant (-55°C to 125°C) 80 0.3 5962-88634 01 UX 5962-88634 01 XX 5962-88634 01 YX 5962-88634 01 ZX 28U 28D6 32L 28F Military/883C Class B, Fully Compliant (-55°C to 125°C) 80 0.3 5962-88634 02 UX 5962-88634 02 XX 5962-88634 02 YX 5962-88634 02 ZX 28U 28D6 32L 28F Military/883C Class B, Fully Compliant (-55°C to 125°C) 1. See “Valid Part Numbers” on page 16. Package Type 28D6 28-lead, 0.600" Wide, Non-windowed, Ceramic Dual Inline Package (Cerdip) 28F 28-lead, Non-windowed, Ceramic Bottom-brazed Flat Package (Flatpack) 32J 32-lead, Plastic J-leaded Chip Carrier (PLCC) 32L 32-pad, Non-windowed, Ceramic Leadless Chip Carrier (LCC) 28P6 28-lead, 0.600" Wide, Plastic Dual Inline Package (PDIP) 28S 28-lead, 0.300" Wide Plastic Gull Wing Small Outline (SOIC) 28T 28-lead, Plastic Thin Small Outline Package (TSOP) 28U 28-pin, Ceramic Pin Grid Array (PGA) W Die Options Blank Standard Device: Endurance = 10K Write Cycles; Write Time = 10 ms E High Endurance Option: Endurance = 100K Write Cycles F Fast Write Option: Write Time = 3 ms 14 AT28HC256 0007J–PEEPR–04/05 AT28HC256 27.2 Green Package Option (Pb/Halide-free) ICC (mA) tACC (ns) Active Standby 90 80 0.3 Ordering Code Package AT28HC256(F)-90JU AT28HC256(F)-90SU AT28HC256(F)-90TU 32J 28S 28T Operation Range Industrial (-40°C to 85°C) Package Type 32J 32-lead, Plastic J-leaded Chip Carrier (PLCC) 28S 28-lead, 0.300" Wide, Plastic Gull Wing Small Outline (SOIC) 28T 28-lead, Plastic Thin Small Outline Package (TSOP) Options Blank F Standard Device: Endurance = 10K Write Cycles; Write Time = 10 ms Fast Write Option: Write Time = 3 ms 15 0007J–PEEPR–04/05 28. Ordering Information Note Previous datasheets included the low power suffixes L, LE and LF on the At28HC256 for 120 ns and 90 ns speeds. The low power parameters are now standard; therefore, the L, LE and LF suffixes are no longer required. 29. Valid Part Numbers The following table lists standard Atmel products that can be ordered: Device Numbers Speed Package and Temperature Combinations AT28HC256 70 JC, JI, PC, PI AT28HC256 90 JC, JI, JU, PC, PI, TC, SU, TI, TU, DM/883, FM/883, UM/883 AT28HC256E 90 JC, JI, PC, PI, TC, TI, DM/883, FM/883, UM/883 AT28HC256F 90 JC, JI, JU, PC, PI, TC, SU, TI, TU, DM/883, FM/883, UM/883 AT28HC256 12 JC, JI, PC, PI, TC, TI, DM/883, FM/883, UM/883 AT28HC256E 12 JC, JI, PC, PI, TC, TI, DM/883, FM/883, UM/883 AT28HC256F 12 JC, JI, PC, PI, TC, TI, DM/883, FM/883, UM/883 30. Die Products Reference Section: Parallel EEPROM Die Products 16 AT28HC256 0007J–PEEPR–04/05 AT28HC256 31. Packaging Information 31.1 28D6 – Cerdip Dimensions in Millimeters and (Inches). Controlling dimension: Inches. MIL-STD 1835 D-10 Config A (Glass Sealed) 37.85(1.490) 36.58(1.440) PIN 1 15.49(0.610) 12.95(0.510) 33.02(1.300) REF 5.72(0.225) MAX 0.127(0.005)MIN SEATING PLANE 5.08(0.200) 3.18(0.125) 2.54(0.100)BSC 1.65(0.065) 1.14(0.045) 1.52(0.060) 0.38(0.015) 0.66(0.026) 0.36(0.014) 15.70(0.620) 15.00(0.590) 0.46(0.018) 0.20(0.008) 0º~ 15º REF 17.80(0.700) MAX 10/23/03 R 2325 Orchard Parkway San Jose, CA 95131 TITLE 28D6, 28-lead, 0.600" Wide, Non-windowed, Ceramic Dual Inline Package (Cerdip) DRAWING NO. 28D6 REV. B 17 0007J–PEEPR–04/05 31.2 28F – Flatpack Dimensions in Millimeters and (Inches). Controlling dimension: Inches. MIL-STD 1835 F-12 Config B PIN #1 ID 9.40(0.370) 6.35(0.250) 0.56(0.022) 0.38(0.015) 1.27(0.050) BSC 18.49(0.728) 18.08(0.712) 1.14(0.045) MAX 10.57(0.416) 9.75(0.384) 0.23(0.009) 0.10(0.004) 3.02(0.119) 2.29(0.090) 1.96(0.077) 1.09(0.043) 7.26(0.286) 6.96(0.274) 1.14(0.045) 0.660(0.026) 10/21/03 R 18 2325 Orchard Parkway San Jose, CA 95131 TITLE 28F, 28-lead, Non-windowed, Ceramic Bottom-brazed Flat Package (FlatPack) DRAWING NO. REV. 28F B AT28HC256 0007J–PEEPR–04/05 AT28HC256 31.3 32J – PLCC 1.14(0.045) X 45˚ PIN NO. 1 IDENTIFIER 1.14(0.045) X 45˚ 0.318(0.0125) 0.191(0.0075) E1 E2 B1 E B e A2 D1 A1 D A 0.51(0.020)MAX 45˚ MAX (3X) COMMON DIMENSIONS (Unit of Measure = mm) D2 Notes: 1. This package conforms to JEDEC reference MS-016, Variation AE. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is .010"(0.254 mm) per side. Dimension D1 and E1 include mold mismatch and are measured at the extreme material condition at the upper or lower parting line. 3. Lead coplanarity is 0.004" (0.102 mm) maximum. SYMBOL MIN NOM MAX A 3.175 – 3.556 A1 1.524 – 2.413 A2 0.381 – – D 12.319 – 12.573 D1 11.354 – 11.506 D2 9.906 – 10.922 E 14.859 – 15.113 E1 13.894 – 14.046 E2 12.471 – 13.487 B 0.660 – 0.813 B1 0.330 – 0.533 e NOTE Note 2 Note 2 1.270 TYP 10/04/01 R 2325 Orchard Parkway San Jose, CA 95131 TITLE 32J, 32-lead, Plastic J-leaded Chip Carrier (PLCC) DRAWING NO. REV. 32J B 19 0007J–PEEPR–04/05 31.4 32L – LCC Dimensions in Millimeters and (Inches). Controlling dimension: Inches. MIL-STD 1835 C-12 11.63(0.458) 11.23(0.442) 2.54(0.100) 2.16(0.085) 14.22(0.560) 13.72(0.540) 1.91(0.075) 1.40(0.055) PIN 1 2.41(0.095) 1.91(0.075) 1.40(0.055) 1.14(0.045) INDEX CORNER 0.635(0.025) X 45˚ 0.381(0.015) 0.305(0.012) RADIUS 0.178(0.007) 10.16(0.400) BSC 0.737(0.029) 0.533(0.021) 1.27(0.050) TYP 1.02(0.040) X 45˚ 7.62(0.300) BSC 2.16(0.085) 1.65(0.065) 10/21/03 R 20 2325 Orchard Parkway San Jose, CA 95131 TITLE 32L, 32-pad, Non-windowed, Ceramic Lid, Leadless Chip Carrier (LCC) DRAWING NO. REV. 32L B AT28HC256 0007J–PEEPR–04/05 AT28HC256 31.5 28P6 – PDIP D PIN 1 E1 A SEATING PLANE A1 L B B1 e E 0º ~ 15º C COMMON DIMENSIONS (Unit of Measure = mm) REF MIN NOM MAX A – – 4.826 A1 0.381 – – D 36.703 – 37.338 E 15.240 – 15.875 E1 13.462 – 13.970 B 0.356 – 0.559 B1 1.041 – 1.651 L 3.048 – 3.556 C 0.203 – 0.381 eB 15.494 – 17.526 SYMBOL eB Notes: 1. This package conforms to JEDEC reference MS-011, Variation AB. 2. Dimensions D and E1 do not include mold Flash or Protrusion. Mold Flash or Protrusion shall not exceed 0.25 mm (0.010"). e NOTE Note 2 Note 2 2.540 TYP 09/28/01 R 2325 Orchard Parkway San Jose, CA 95131 TITLE 28P6, 28-lead (0.600"/15.24 mm Wide) Plastic Dual Inline Package (PDIP) DRAWING NO. 28P6 REV. B 21 0007J–PEEPR–04/05 31.6 28S – SOIC Dimensions in Millimeters and (Inches). Controlling dimension: Millimeters. 0.51(0.020) 0.33(0.013) 7.60(0.2992) 10.65(0.419) 7.40(0.2914) 10.00(0.394) PIN 1 1.27(0.50) BSC TOP VIEW 18.10(0.7125) 17.70(0.6969) 2.65(0.1043) 2.35(0.0926) 0.30(0.0118) 0.10(0.0040) SIDE VIEWS 0.32(0.0125) 0.23(0.0091) 0º ~ 8º 1.27(0.050) 0.40(0.016) 8/4/03 R 22 2325 Orchard Parkway San Jose, CA 95131 TITLE 28S, 28-lead, 0.300" Body, Plastic Gull Wing Small Outline (SOIC) JEDEC Standard MS-013 DRAWING NO. REV. 28S B AT28HC256 0007J–PEEPR–04/05 AT28HC256 31.7 28T – TSOP PIN 1 0º ~ 5º c Pin 1 Identifier Area D1 D L b e L1 A2 E A GAGE PLANE SEATING PLANE COMMON DIMENSIONS (Unit of Measure = mm) A1 MIN NOM MAX A – – 1.20 A1 0.05 – 0.15 A2 0.90 1.00 1.05 D 13.20 13.40 13.60 D1 11.70 11.80 11.90 Note 2 E 7.90 8.00 8.10 Note 2 L 0.50 0.60 0.70 SYMBOL Notes: 1. This package conforms to JEDEC reference MO-183. 2. Dimensions D1 and E do not include mold protrusion. Allowable protrusion on E is 0.15 mm per side and on D1 is 0.25 mm per side. 3. Lead coplanarity is 0.10 mm maximum. L1 NOTE 0.25 BASIC b 0.17 0.22 0.27 c 0.10 – 0.21 e 0.55 BASIC 12/06/02 R 2325 Orchard Parkway San Jose, CA 95131 TITLE 28T, 28-lead (8 x 13.4 mm) Plastic Thin Small Outline Package, Type I (TSOP) DRAWING NO. REV. 28T C 23 0007J–PEEPR–04/05 31.8 28U – PGA Dimensions in Millimeters and (Inches). Controlling dimension: Inches. 7.26(0.286) 6.50(0.256) 13.74(0.540) 13.36(0.526) 2.57(0.101) 2.06(0.081) 15.24(0.600) 14.88(0.586) 1.40(0.055) 1.14(0.045) 0.58(0.023) 0.43(0.017) 3.12(0.123) 2.62(0.103) 1.83(0.072) 1.57(0.062) 14.17(0.558) 13.77(0.542) 2.54(0.100) TYP 16.71(0.658) 16.31(0.642) 12.70(0.500) TYP 2.54(0.100) TYP 10.41(0.410) 9.91(0.390) 10/21/03 R 24 2325 Orchard Parkway San Jose, CA 95131 TITLE 28U, 28-pin, Ceramic Pin Grid Array (PGA) DRAWING NO. REV. 28U B AT28HC256 0007J–PEEPR–04/05 Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Regional Headquarters Europe Atmel Sarl Route des Arsenaux 41 Case Postale 80 CH-1705 Fribourg Switzerland Tel: (41) 26-426-5555 Fax: (41) 26-426-5500 Asia Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong Kong Tel: (852) 2721-9778 Fax: (852) 2722-1369 Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581 Atmel Operations Memory 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 RF/Automotive Theresienstrasse 2 Postfach 3535 74025 Heilbronn, Germany Tel: (49) 71-31-67-0 Fax: (49) 71-31-67-2340 Microcontrollers 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 La Chantrerie BP 70602 44306 Nantes Cedex 3, France Tel: (33) 2-40-18-18-18 Fax: (33) 2-40-18-19-60 ASIC/ASSP/Smart Cards 1150 East Cheyenne Mtn. Blvd. Colorado Springs, CO 80906, USA Tel: 1(719) 576-3300 Fax: 1(719) 540-1759 Biometrics/Imaging/Hi-Rel MPU/ High Speed Converters/RF Datacom Avenue de Rochepleine BP 123 38521 Saint-Egreve Cedex, France Tel: (33) 4-76-58-30-00 Fax: (33) 4-76-58-34-80 Zone Industrielle 13106 Rousset Cedex, France Tel: (33) 4-42-53-60-00 Fax: (33) 4-42-53-60-01 1150 East Cheyenne Mtn. Blvd. Colorado Springs, CO 80906, USA Tel: 1(719) 576-3300 Fax: 1(719) 540-1759 Scottish Enterprise Technology Park Maxwell Building East Kilbride G75 0QR, Scotland Tel: (44) 1355-803-000 Fax: (44) 1355-242-743 Literature Requests www.atmel.com/literature Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. 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