AT32UC3B1256-AUR

Features • High Performance, Low Power 32-Bit Atmel® AVR®Microcontroller • • • • • • • • • • • • • • • – Compact Single-cycle RISC Instruction Set Including DSP Instruction Set – Read-Modify-Write Instructions and Atomic Bit Manipulation – Performing up to 1.39 DMIPS / MHz • Up to 83 DMIPS Running at 60 MHz from Flash • Up to 46 DMIPS Running at 30 MHz from Flash – Memory Protection Unit Multi-hierarchy Bus System – High-Performance Data Transfers on Separate Buses for Increased Performance – 7 Peripheral DMA Channels Improves Speed for Peripheral Communication Internal High-Speed Flash – 512K Bytes, 256K Bytes, 128K Bytes, 64K Bytes Versions – Single Cycle Access up to 30 MHz – Prefetch Buffer Optimizing Instruction Execution at Maximum Speed – 4ms Page Programming Time and 8ms Full-Chip Erase Time – 100,000 Write Cycles, 15-year Data Retention Capability – Flash Security Locks and User Defined Configuration Area Internal High-Speed SRAM, Single-Cycle Access at Full Speed – 96K Bytes (512KB Flash), 32K Bytes (256KB and 128KB Flash), 16K Bytes (64KB Flash) Interrupt Controller – Autovectored Low Latency Interrupt Service with Programmable Priority System Functions – Power and Clock Manager Including Internal RC Clock and One 32KHz Oscillator – Two Multipurpose Oscillators and Two Phase-Lock-Loop (PLL) allowing Independant CPU Frequency from USB Frequency – Watchdog Timer, Real-Time Clock Timer Universal Serial Bus (USB) – Device 2.0 and Embedded Host Low Speed and Full Speed – Flexible End-Point Configuration and Management with Dedicated DMA Channels – On-chip Transceivers Including Pull-Ups – USB Wake Up from Sleep Functionality One Three-Channel 16-bit Timer/Counter (TC) – Three External Clock Inputs, PWM, Capture and Various Counting Capabilities One 7-Channel 20-bit Pulse Width Modulation Controller (PWM) Three Universal Synchronous/Asynchronous Receiver/Transmitters (USART) – Independant Baudrate Generator, Support for SPI, IrDA and ISO7816 interfaces – Support for Hardware Handshaking, RS485 Interfaces and Modem Line One Master/Slave Serial Peripheral Interfaces (SPI) with Chip Select Signals One Synchronous Serial Protocol Controller – Supports I2S and Generic Frame-Based Protocols One Master/Slave Two-Wire Interface (TWI), 400kbit/s I2C-compatible One 8-channel 10-bit Analog-To-Digital Converter, 384ks/s 16-bit Stereo Audio Bitstream DAC – Sample Rate Up to 50 KHz QTouch® Library Support – Capacitive Touch Buttons, Sliders, and Wheels – QTouch and QMatrix Acquisition 32-bit ATMEL AVR Microcontroller AT32UC3B0512 AT32UC3B0256 AT32UC3B0128 AT32UC3B064 AT32UC3B1512 AT32UC3B1256 AT32UC3B1128 AT32UC3B164 32059L–01/2012 AT32UC3B • On-Chip Debug System (JTAG interface) – Nexus Class 2+, Runtime Control, Non-Intrusive Data and Program Trace • 64-pin TQFP/QFN (44 GPIO pins), 48-pin TQFP/QFN (28 GPIO pins) • 5V Input Tolerant I/Os, including 4 high-drive pins • Single 3.3V Power Supply or Dual 1.8V-3.3V Power Supply 2 32059L–AVR32–01/2012 AT32UC3B 1. Description The AT32UC3B is a complete System-On-Chip microcontroller based on the AVR32 UC RISC processor running at frequencies up to 60 MHz. AVR32 UC is a high-performance 32-bit RISC microprocessor core, designed for cost-sensitive embedded applications, with particular emphasis on low power consumption, high code density and high performance. The processor implements a Memory Protection Unit (MPU) and a fast and flexible interrupt controller for supporting modern operating systems and real-time operating systems. Higher computation capability is achieved using a rich set of DSP instructions. The AT32UC3B incorporates on-chip Flash and SRAM memories for secure and fast access. The Peripheral Direct Memory Access controller enables data transfers between peripherals and memories without processor involvement. PDCA drastically reduces processing overhead when transferring continuous and large data streams between modules within the MCU. The Power Manager improves design flexibility and security: the on-chip Brown-Out Detector monitors the power supply, the CPU runs from the on-chip RC oscillator or from one of external oscillator sources, a Real-Time Clock and its associated timer keeps track of the time. The Timer/Counter includes three identical 16-bit timer/counter channels. Each channel can be independently programmed to perform frequency measurement, event counting, interval measurement, pulse generation, delay timing and pulse width modulation. The PWM modules provides seven independent channels with many configuration options including polarity, edge alignment and waveform non overlap control. One PWM channel can trigger ADC conversions for more accurate close loop control implementations. The AT32UC3B also features many communication interfaces for communication intensive applications. In addition to standard serial interfaces like USART, SPI or TWI, other interfaces like flexible Synchronous Serial Controller and USB are available. The USART supports different communication modes, like SPI mode. The Synchronous Serial Controller provides easy access to serial communication protocols and audio standards like I2S, UART or SPI. The Full-Speed USB 2.0 Device interface supports several USB Classes at the same time thanks to the rich End-Point configuration. The Embedded Host interface allows device like a USB Flash disk or a USB printer to be directly connected to the processor. Atmel offers the QTouch library for embedding capacitive touch buttons, sliders, and wheels functionality into AVR microcontrollers. The patented charge-transfer signal acquisition offers robust sensing and included fully debounced reporting of touch keys and includes Adjacent Key Suppression® (AKS®) technology for unambiguous detection of key events. The easy-to-use QTouch Suite toolchain allows you to explore, develop, and debug your own touch applications. AT32UC3B integrates a class 2+ Nexus 2.0 On-Chip Debug (OCD) System, with non-intrusive real-time trace, full-speed read/write memory access in addition to basic runtime control. The Nanotrace interface enables trace feature for JTAG-based debuggers. 3 32059L–AVR32–01/2012 AT32UC3B 2. Overview 2.1 Blockdiagram Figure 2-1. Block diagram NEXUS CLASS 2+ OCD MCKO MDO[5..0] MSEO[1..0] EVTI_N EVTO_N VBUS D+ DID VBOF M USB INTERFACE MEMORY PROTECTION UNIT INSTR INTERFACE DATA INTERFACE M M S HSB HSB-PB BRIDGE B REGISTERS BUS HSB PERIPHERAL DMA CONTROLLER HSB-PB BRIDGE A GENERAL PURPOSE IOs XIN32 XOUT32 XIN0 XOUT0 XIN1 XOUT1 32 KHz OSC CLOCK GENERATOR OSC0 OSC1 PLL0 PLL1 GCLK[3..0] RESET_N A[2..0] B[2..0] CLK[2..0] PDC PDC POWER MANAGER PDC 115 kHz RCOSC SYNCHRONOUS SERIAL CONTROLLER PDC WATCHDOG TIMER SERIAL PERIPHERAL INTERFACE TWO-WIRE INTERFACE PDC REAL TIME COUNTER USART0 USART2 ANALOG TO DIGITAL CONVERTER PDC NMI EXTERNAL INTERRUPT CONTROLLER USART1 PDC INTERRUPT CONTROLLER EXTINT[7..0] KPS[7..0] AUDIO BITSTREAM DAC CLOCK CONTROLLER SLEEP CONTROLLER RESET CONTROLLER TIMER/COUNTER 64/128/ 256/512 KB FLASH M PB PA PB FAST GPIO 16/32/96 KB SRAM S S CONFIGURATION PB LOCAL BUS INTERFACE S HIGH SPEED BUS MATRIX S M DMA AVR32 UC CPU PULSE WIDTH MODULATION CONTROLLER RXD TXD CLK RTS, CTS DSR, DTR, DCD, RI RXD TXD CLK RTS, CTS GENERAL PURPOSE IOs JTAG INTERFACE FLASH CONTROLLER TDO TDI TMS MEMORY INTERFACE TCK PA PB SCK MISO, MOSI NPCS[3..0] TX_CLOCK, TX_FRAME_SYNC TX_DATA RX_CLOCK, RX_FRAME_SYNC RX_DATA SCL SDA AD[7..0] ADVREF DATA[1..0] DATAN[1..0] PWM[6..0] 4 32059L–AVR32–01/2012 AT32UC3B 3. Configuration Summary The table below lists all AT32UC3B memory and package configurations: Table 3-1. Feature Configuration Summary AT32UC3B0512 AT32UC3B0256/128/64 AT32UC3B1512 AT32UC3B1256/128/64 Flash 512 KB 256/128/64 KB 512 KB 256/128/64 KB SRAM 96KB 32/32/16KB 96KB 32/16/16KB GPIO 44 28 External Interrupts 8 6 TWI 1 USART 3 Peripheral DMA Channels 7 SPI 1 Full Speed USB SSC Audio Bitstream DAC Mini-Host + Device Device 1 0 1 0 1 Timer/Counter Channels 3 PWM Channels 7 Watchdog Timer 1 Real-Time Clock Timer 1 Power Manager 1 0 PLL 80-240 MHz (PLL0/PLL1) Crystal Oscillators 0.4-20 MHz (OSC0) Crystal Oscillator 32 KHz (OSC32K) RC Oscillator 115 kHz (RCSYS) Oscillators Crystal Oscillators 0.4-20 MHz (OSC1) 10-bit ADC number of channels 8 JTAG 1 Max Frequency Package 6 60 MHz TQFP64, QFN64 TQFP48, QFN48 5 32059L–AVR32–01/2012 AT32UC3B 4. Package and Pinout 4.1 Package The device pins are multiplexed with peripheral functions as described in the Peripheral Multiplexing on I/O Line section. TQFP64 / QFN64 Pinout 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 VDDIO PA23 PA22 PA21 PA20 PB07 PA29 PA28 PA19 PA18 PB06 PA17 PA16 PA15 PA14 PA13 Figure 4-1. GND DP DM VBUS VDDPLL PB08 PB09 VDDCORE PB10 PB11 PA24 PA25 PA26 PA27 RESET_N VDDIO 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VDDIO PA12 PA11 PA10 PA09 PB05 PB04 PB03 PB02 GND VDDCORE VDDIN VDDOUT VDDANA ADVREF GNDANA 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 PA31 PA30 PA08 PA07 PA06 PA05 PA04 PA03 VDDCORE PB01 PB00 PA02 PA01 PA00 TCK GND 6 32059L–AVR32–01/2012 AT32UC3B TQFP48 / QFN48 Pinout 36 35 34 33 32 31 30 29 28 27 26 25 VDDIO PA23 PA22 PA21 PA20 PA19 PA18 PA17 PA16 PA15 PA14 PA13 Figure 4-2. GND DP DM VBUS VDDPLL VDDCORE PA24 PA25 PA26 PA27 RESET_N VDDIO 37 38 39 40 41 42 43 44 45 46 47 48 24 23 22 21 20 19 18 17 16 15 14 13 VDDIO PA12 PA11 PA10 PA09 GND VDDCORE VDDIN VDDOUT VDDANA ADVREF GNDANA 12 11 10 9 8 7 6 5 4 3 2 1 PA08 PA07 PA06 PA05 PA04 PA03 VDDCORE PA02 PA01 PA00 TCK GND Note: 4.2 The exposed pad is not connected to anything internally, but should be soldered to ground to increase board level reliability. Peripheral Multiplexing on I/O lines 4.2.1 Table 4-1. Multiplexed signals Each GPIO line can be assigned to one of 4 peripheral functions; A, B, C or D (D is only available for UC3Bx512 parts). The following table define how the I/O lines on the peripherals A, B,C or D are multiplexed by the GPIO. GPIO Controller Function Multiplexing Function D 48-pin 64-pin PIN GPIO Pin Function A Function B Function C (only for UC3Bx512) 3 3 PA00 GPIO 0 4 4 PA01 GPIO 1 5 5 PA02 GPIO 2 7 9 PA03 GPIO 3 ADC - AD[0] PM - GCLK[0] USBB - USB_ID ABDAC - DATA[0] 8 10 PA04 GPIO 4 ADC - AD[1] PM - GCLK[1] USBB - USB_VBOF ABDAC - DATAN[0] 9 11 PA05 GPIO 5 EIC - EXTINT[0] ADC - AD[2] USART1 - DCD ABDAC - DATA[1] 7 32059L–AVR32–01/2012 AT32UC3B Table 4-1. GPIO Controller Function Multiplexing 10 12 PA06 GPIO 6 EIC - EXTINT[1] ADC - AD[3] USART1 - DSR ABDAC - DATAN[1] 11 13 PA07 GPIO 7 PWM - PWM[0] ADC - AD[4] USART1 - DTR SSC RX_FRAME_SYNC 12 14 PA08 GPIO 8 PWM - PWM[1] ADC - AD[5] USART1 - RI SSC - RX_CLOCK 20 28 PA09 GPIO 9 TWI - SCL SPI0 - NPCS[2] USART1 - CTS 21 29 PA10 GPIO 10 TWI - SDA SPI0 - NPCS[3] USART1 - RTS 22 30 PA11 GPIO 11 USART0 - RTS TC - A2 PWM - PWM[0] SSC - RX_DATA 23 31 PA12 GPIO 12 USART0 - CTS TC - B2 PWM - PWM[1] USART1 - TXD 25 33 PA13 GPIO 13 EIC - NMI PWM - PWM[2] USART0 - CLK SSC - RX_CLOCK 26 34 PA14 GPIO 14 SPI0 - MOSI PWM - PWM[3] EIC - EXTINT[2] PM - GCLK[2] 27 35 PA15 GPIO 15 SPI0 - SCK PWM - PWM[4] USART2 - CLK 28 36 PA16 GPIO 16 SPI0 - NPCS[0] TC - CLK1 PWM - PWM[4] 29 37 PA17 GPIO 17 SPI0 - NPCS[1] TC - CLK2 SPI0 - SCK USART1 - RXD 30 39 PA18 GPIO 18 USART0 - RXD PWM - PWM[5] SPI0 - MISO SSC RX_FRAME_SYNC 31 40 PA19 GPIO 19 USART0 - TXD PWM - PWM[6] SPI0 - MOSI SSC - TX_CLOCK 32 44 PA20 GPIO 20 USART1 - CLK TC - CLK0 USART2 - RXD SSC - TX_DATA 33 45 PA21 GPIO 21 PWM - PWM[2] TC - A1 USART2 - TXD SSC TX_FRAME_SYNC 34 46 PA22 GPIO 22 PWM - PWM[6] TC - B1 ADC - TRIGGER ABDAC - DATA[0] 35 47 PA23 GPIO 23 USART1 - TXD SPI0 - NPCS[1] EIC - EXTINT[3] PWM - PWM[0] 43 59 PA24 GPIO 24 USART1 - RXD SPI0 - NPCS[0] EIC - EXTINT[4] PWM - PWM[1] 44 60 PA25 GPIO 25 SPI0 - MISO PWM - PWM[3] EIC - EXTINT[5] 45 61 PA26 GPIO 26 USBB - USB_ID USART2 - TXD TC - A0 ABDAC - DATA[1] 46 62 PA27 GPIO 27 USBB - USB_VBOF USART2 - RXD TC - B0 ABDAC - DATAN[1] 41 PA28 GPIO 28 USART0 - CLK PWM - PWM[4] SPI0 - MISO ABDAC - DATAN[0] 42 PA29 GPIO 29 TC - CLK0 TC - CLK1 SPI0 - MOSI 15 PA30 GPIO 30 ADC - AD[6] EIC - SCAN[0] PM - GCLK[2] 16 PA31 GPIO 31 ADC - AD[7] EIC - SCAN[1] PWM - PWM[6] 6 PB00 GPIO 32 TC - A0 EIC - SCAN[2] USART2 - CTS 7 PB01 GPIO 33 TC - B0 EIC - SCAN[3] USART2 - RTS 24 PB02 GPIO 34 EIC - EXTINT[6] TC - A1 USART1 - TXD 25 PB03 GPIO 35 EIC - EXTINT[7] TC - B1 USART1 - RXD 26 PB04 GPIO 36 USART1 - CTS SPI0 - NPCS[3] TC - CLK2 27 PB05 GPIO 37 USART1 - RTS SPI0 - NPCS[2] PWM - PWM[5] 38 PB06 GPIO 38 SSC - RX_CLOCK USART1 - DCD EIC - SCAN[4] ABDAC - DATA[0] 43 PB07 GPIO 39 SSC - RX_DATA USART1 - DSR EIC - SCAN[5] ABDAC - DATAN[0] 54 PB08 GPIO 40 SSC RX_FRAME_SYNC USART1 - DTR EIC - SCAN[6] ABDAC - DATA[1] 8 32059L–AVR32–01/2012 AT32UC3B Table 4-1. 4.2.2 GPIO Controller Function Multiplexing 55 PB09 GPIO 41 SSC - TX_CLOCK USART1 - RI EIC - SCAN[7] 57 PB10 GPIO 42 SSC - TX_DATA TC - A2 USART0 - RXD 58 PB11 GPIO 43 SSC TX_FRAME_SYNC TC - B2 USART0 - TXD JTAG Port Connections If the JTAG is enabled, the JTAG will take control over a number of pins, irrespective of the I/O Controller configuration. Table 4-2. 64QFP/QFN 4.2.3 JTAG Pinout 48QFP/QFN Pin name JTAG pin 2 2 TCK TCK 3 3 PA00 TDI 4 4 PA01 TDO 5 5 PA02 TMS Nexus OCD AUX port connections If the OCD trace system is enabled, the trace system will take control over a number of pins, irrespectively of the PIO configuration. Two different OCD trace pin mappings are possible, depending on the configuration of the OCD AXS register. For details, see the AVR32 UC Technical Reference Manual. Table 4-3. 4.2.4 ABDAC - DATAN[1] Nexus OCD AUX port connections Pin AXS=0 AXS=1 EVTI_N PB05 PA14 MDO[5] PB04 PA08 MDO[4] PB03 PA07 MDO[3] PB02 PA06 MDO[2] PB01 PA05 MDO[1] PB00 PA04 MDO[0] PA31 PA03 EVTO_N PA15 PA15 MCKO PA30 PA13 MSEO[1] PB06 PA09 MSEO[0] PB07 PA10 Oscillator Pinout The oscillators are not mapped to the normal A, B or C functions and their muxings are controlled by registers in the Power Manager (PM). Please refer to the power manager chapter for more information about this. 9 32059L–AVR32–01/2012 AT32UC3B Table 4-4. Oscillator pinout QFP48 pin QFP64 pin Pad Oscillator pin 30 39 PA18 XIN0 41 PA28 XIN1 22 30 PA11 XIN32 31 40 PA19 XOUT0 42 PA29 XOUT1 31 PA12 XOUT32 23 4.3 High Drive Current GPIO Ones of GPIOs can be used to drive twice current than other GPIO capability (see Electrical Characteristics section). Table 4-5. High Drive Current GPIO GPIO Name PA20 PA21 PA22 PA23 5. Signals Description The following table gives details on the signal name classified by peripheral. Table 5-1. Signal Description List Signal Name Function Type Active Level Comments Power VDDPLL PLL Power Supply Power Input 1.65V to 1.95 V VDDCORE Core Power Supply Power Input 1.65V to 1.95 V VDDIO I/O Power Supply Power Input 3.0V to 3.6V VDDANA Analog Power Supply Power Input 3.0V to 3.6V VDDIN Voltage Regulator Input Supply Power Input 3.0V to 3.6V 10 32059L–AVR32–01/2012 AT32UC3B Table 5-1. Signal Description List (Continued) Signal Name Function Type VDDOUT Voltage Regulator Output Power Output GNDANA Analog Ground Ground GND Ground Ground Active Level Comments 1.65V to 1.95 V Clocks, Oscillators, and PLL’s XIN0, XIN1, XIN32 Crystal 0, 1, 32 Input Analog XOUT0, XOUT1, XOUT32 Crystal 0, 1, 32 Output Analog JTAG TCK Test Clock Input TDI Test Data In Input TDO Test Data Out TMS Test Mode Select Output Input Auxiliary Port - AUX MCKO Trace Data Output Clock Output MDO0 - MDO5 Trace Data Output Output MSEO0 - MSEO1 Trace Frame Control Output EVTI_N Event In Output Low EVTO_N Event Out Output Low Power Manager - PM GCLK0 - GCLK2 Generic Clock Pins RESET_N Reset Pin Output Input Low External Interrupt Controller - EIC EXTINT0 - EXTINT7 External Interrupt Pins KPS0 - KPS7 Keypad Scan Pins NMI Non-Maskable Interrupt Pin Input Output Input Low General Purpose I/O pin- GPIOA, GPIOB PA0 - PA31 Parallel I/O Controller GPIOA I/O PB0 - PB11 Parallel I/O Controller GPIOB I/O 11 32059L–AVR32–01/2012 AT32UC3B Table 5-1. Signal Description List (Continued) Signal Name Function Type Active Level Comments Serial Peripheral Interface - SPI0 MISO Master In Slave Out I/O MOSI Master Out Slave In I/O NPCS0 - NPCS3 SPI Peripheral Chip Select I/O SCK Clock Low Output Synchronous Serial Controller - SSC RX_CLOCK SSC Receive Clock I/O RX_DATA SSC Receive Data Input RX_FRAME_SYNC SSC Receive Frame Sync I/O TX_CLOCK SSC Transmit Clock I/O TX_DATA SSC Transmit Data Output TX_FRAME_SYNC SSC Transmit Frame Sync I/O Timer/Counter - TIMER A0 Channel 0 Line A I/O A1 Channel 1 Line A I/O A2 Channel 2 Line A I/O B0 Channel 0 Line B I/O B1 Channel 1 Line B I/O B2 Channel 2 Line B I/O CLK0 Channel 0 External Clock Input Input CLK1 Channel 1 External Clock Input Input CLK2 Channel 2 External Clock Input Input Two-wire Interface - TWI SCL Serial Clock I/O SDA Serial Data I/O Universal Synchronous Asynchronous Receiver Transmitter - USART0, USART1, USART2 CLK Clock CTS Clear To Send I/O Input 12 32059L–AVR32–01/2012 AT32UC3B Table 5-1. Signal Description List (Continued) Type Active Level Signal Name Function Comments DCD Data Carrier Detect Only USART1 DSR Data Set Ready Only USART1 DTR Data Terminal Ready Only USART1 RI Ring Indicator Only USART1 RTS Request To Send RXD Receive Data Input TXD Transmit Data Output Output Analog to Digital Converter - ADC AD0 - AD7 Analog input pins Analog input ADVREF Analog positive reference voltage input Analog input 2.6 to 3.6V Audio Bitstream DAC - ABDAC DATA0 - DATA1 D/A Data out Output DATAN0 - DATAN1 D/A Data inverted out Output Pulse Width Modulator - PWM PWM0 - PWM6 PWM Output Pins Output Universal Serial Bus Device - USBB DDM USB Device Port Data - Analog DDP USB Device Port Data + Analog VBUS USB VBUS Monitor and Embedded Host Negociation Analog Input USBID ID Pin of the USB Bus Input USB_VBOF USB VBUS On/off: bus power control port output 5.1 JTAG pins TMS and TDI pins have pull-up resistors. TDO pin is an output, driven at up to VDDIO, and has no pull-up resistor. These 3 pins can be used as GPIO-pins. At reset state, these pins are in GPIO mode. TCK pin cannot be used as GPIO pin. JTAG interface is enabled when TCK pin is tied low. 13 32059L–AVR32–01/2012 AT32UC3B 5.2 RESET_N pin The RESET_N pin is a schmitt input and integrates a permanent pull-up resistor to VDDIO. As the product integrates a power-on reset cell, the RESET_N pin can be left unconnected in case no reset from the system needs to be applied to the product. 5.3 TWI pins When these pins are used for TWI, the pins are open-drain outputs with slew-rate limitation and inputs with inputs with spike-filtering. When used as GPIO-pins or used for other peripherals, the pins have the same characteristics as GPIO pins. 5.4 GPIO pins All the I/O lines integrate a pull-up resistor. Programming of this pull-up resistor is performed independently for each I/O line through the GPIO Controllers. After reset, I/O lines default as inputs with pull-up resistors disabled, except when indicated otherwise in the column “Reset Value” of the GPIO Controller user interface table. 5.5 High drive pins The four pins PA20, PA21, PA22, PA23 have high drive output capabilities. 5.6 5.6.1 Power Considerations Power Supplies The AT32UC3B has several types of power supply pins: • • • • • VDDIO: Powers I/O lines. Voltage is 3.3V nominal. VDDANA: Powers the ADC Voltage is 3.3V nominal. VDDIN: Input voltage for the voltage regulator. Voltage is 3.3V nominal. VDDCORE: Powers the core, memories, and peripherals. Voltage is 1.8V nominal. VDDPLL: Powers the PLL. Voltage is 1.8V nominal. The ground pins GND are common to VDDCORE, VDDIO and VDDPLL. The ground pin for VDDANA is GNDANA. Refer to Electrical Characteristics section for power consumption on the various supply pins. The main requirement for power supplies connection is to respect a star topology for all electrical connection. 14 32059L–AVR32–01/2012 AT32UC3B Figure 5-1. Power Supply Dual Power Supply Single Power Supply 3.3V 3.3V VDDANA VDDANA VDDIO VDDIO ADVREF ADVREF VDDIN VDDIN 1.8V Regulator VDDOUT VDDOUT 1.8 V VDDCORE VDDCORE VDDPLL VDDPLL 5.6.2 5.6.2.1 1.8V Regulator Voltage Regulator Single Power Supply The AT32UC3B embeds a voltage regulator that converts from 3.3V to 1.8V. The regulator takes its input voltage from VDDIN, and supplies the output voltage on VDDOUT that should be externally connected to the 1.8V domains. Adequate input supply decoupling is mandatory for VDDIN in order to improve startup stability and reduce source voltage drop. Two input decoupling capacitors must be placed close to the chip. Adequate output supply decoupling is mandatory for VDDOUT to reduce ripple and avoid oscillations. The best way to achieve this is to use two capacitors in parallel between VDDOUT and GND as close to the chip as possible Figure 5-2. Supply Decoupling 3.3V VDDIN CIN2 CIN1 1.8V 1.8V Regulator VDDOUT COUT2 COUT1 15 32059L–AVR32–01/2012 AT32UC3B Refer to Section 28.3 on page 610 for decoupling capacitors values and regulator characteristics. For decoupling recommendations for VDDIO, VDDANA, VDDCORE and VDDPLL, please refer to the Schematic checklist. 5.6.2.2 Dual Power Supply In case of dual power supply, VDDIN and VDDOUT should be connected to ground to prevent from leakage current. To avoid over consumption during the power up sequence, VDDIO and VDDCORE voltage difference needs to stay in the range given Figure 5-3. Figure 5-3. VDDIO versus VDDCORE during power up sequence 4 Extra consumption on VDDIO 3.5 3 VDDIO (V) 2.5 2 1.5 1 0.5 Extra consumption on VDDCORE 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 VDDCORE (V) 5.6.3 Analog-to-Digital Converter (ADC) reference. The ADC reference (ADVREF) must be provided from an external source. Two decoupling capacitors must be used to insure proper decoupling. Figure 5-4. ADVREF Decoupling 3.3V ADVREF C VREF2 C VREF1 Refer to Section 28.4 on page 610 for decoupling capacitors values and electrical characteristics. In case ADC is not used, the ADVREF pin should be connected to GND to avoid extra consumption. 16 32059L–AVR32–01/2012 AT32UC3B 6. Processor and Architecture Rev: 1.0.0.0 This chapter gives an overview of the AVR32UC CPU. AVR32UC is an implementation of the AVR32 architecture. A summary of the programming model, instruction set, and MPU is presented. For further details, see the AVR32 Architecture Manual and the AVR32UC Technical Reference Manual. 6.1 Features • 32-bit load/store AVR32A RISC architecture – – – – – 15 general-purpose 32-bit registers 32-bit Stack Pointer, Program Counter and Link Register reside in register file Fully orthogonal instruction set Privileged and unprivileged modes enabling efficient and secure Operating Systems Innovative instruction set together with variable instruction length ensuring industry leading code density – DSP extention with saturating arithmetic, and a wide variety of multiply instructions • 3-stage pipeline allows one instruction per clock cycle for most instructions – Byte, halfword, word and double word memory access – Multiple interrupt priority levels • MPU allows for operating systems with memory protection 6.2 AVR32 Architecture AVR32 is a high-performance 32-bit RISC microprocessor architecture, designed for cost-sensitive embedded applications, with particular emphasis on low power consumption and high code density. In addition, the instruction set architecture has been tuned to allow a variety of microarchitectures, enabling the AVR32 to be implemented as low-, mid-, or high-performance processors. AVR32 extends the AVR family into the world of 32- and 64-bit applications. Through a quantitative approach, a large set of industry recognized benchmarks has been compiled and analyzed to achieve the best code density in its class. In addition to lowering the memory requirements, a compact code size also contributes to the core’s low power characteristics. The processor supports byte and halfword data types without penalty in code size and performance. Memory load and store operations are provided for byte, halfword, word, and double word data with automatic sign- or zero extension of halfword and byte data. The C-compiler is closely linked to the architecture and is able to exploit code optimization features, both for size and speed. In order to reduce code size to a minimum, some instructions have multiple addressing modes. As an example, instructions with immediates often have a compact format with a smaller immediate, and an extended format with a larger immediate. In this way, the compiler is able to use the format giving the smallest code size. Another feature of the instruction set is that frequently used instructions, like add, have a compact format with two operands as well as an extended format with three operands. The larger format increases performance, allowing an addition and a data move in the same instruction in a single cycle. Load and store instructions have several different formats in order to reduce code size and speed up execution. 17 32059L–AVR32–01/2012 AT32UC3B The register file is organized as sixteen 32-bit registers and includes the Program Counter, the Link Register, and the Stack Pointer. In addition, register R12 is designed to hold return values from function calls and is used implicitly by some instructions. 6.3 The AVR32UC CPU The AVR32UC CPU targets low- and medium-performance applications, and provides an advanced OCD system, no caches, and a Memory Protection Unit (MPU). Java acceleration hardware is not implemented. AVR32UC provides three memory interfaces, one High Speed Bus master for instruction fetch, one High Speed Bus master for data access, and one High Speed Bus slave interface allowing other bus masters to access data RAMs internal to the CPU. Keeping data RAMs internal to the CPU allows fast access to the RAMs, reduces latency, and guarantees deterministic timing. Also, power consumption is reduced by not needing a full High Speed Bus access for memory accesses. A dedicated data RAM interface is provided for communicating with the internal data RAMs. A local bus interface is provided for connecting the CPU to device-specific high-speed systems, such as floating-point units and fast GPIO ports. This local bus has to be enabled by writing the LOCEN bit in the CPUCR system register. The local bus is able to transfer data between the CPU and the local bus slave in a single clock cycle. The local bus has a dedicated memory range allocated to it, and data transfers are performed using regular load and store instructions. Details on which devices that are mapped into the local bus space is given in the Memories chapter of this data sheet. Figure 6-1 on page 19 displays the contents of AVR32UC. 18 32059L–AVR32–01/2012 AT32UC3B OCD interface Reset interface Overview of the AVR32UC CPU Interrupt controller interface Figure 6-1. OCD system Power/ Reset control AVR32UC CPU pipeline MPU 6.3.1 CPU Local Bus master Data RAM interface High Speed Bus slave CPU Local Bus High Speed Bus master High Speed Bus High Speed Bus High Speed Bus master High Speed Bus Data memory controller Instruction memory controller Pipeline Overview AVR32UC has three pipeline stages, Instruction Fetch (IF), Instruction Decode (ID), and Instruction Execute (EX). The EX stage is split into three parallel subsections, one arithmetic/logic (ALU) section, one multiply (MUL) section, and one load/store (LS) section. Instructions are issued and complete in order. Certain operations require several clock cycles to complete, and in this case, the instruction resides in the ID and EX stages for the required number of clock cycles. Since there is only three pipeline stages, no internal data forwarding is required, and no data dependencies can arise in the pipeline. Figure 6-2 on page 20 shows an overview of the AVR32UC pipeline stages. 19 32059L–AVR32–01/2012 AT32UC3B Figure 6-2. The AVR32UC Pipeline Multiply unit MUL IF ID Pref etch unit Decode unit Regf ile Read A LU LS 6.3.2 Regf ile w rite A LU unit Load-store unit AVR32A Microarchitecture Compliance AVR32UC implements an AVR32A microarchitecture. The AVR32A microarchitecture is targeted at cost-sensitive, lower-end applications like smaller microcontrollers. This microarchitecture does not provide dedicated hardware registers for shadowing of register file registers in interrupt contexts. Additionally, it does not provide hardware registers for the return address registers and return status registers. Instead, all this information is stored on the system stack. This saves chip area at the expense of slower interrupt handling. Upon interrupt initiation, registers R8-R12 are automatically pushed to the system stack. These registers are pushed regardless of the priority level of the pending interrupt. The return address and status register are also automatically pushed to stack. The interrupt handler can therefore use R8-R12 freely. Upon interrupt completion, the old R8-R12 registers and status register are restored, and execution continues at the return address stored popped from stack. The stack is also used to store the status register and return address for exceptions and scall. Executing the rete or rets instruction at the completion of an exception or system call will pop this status register and continue execution at the popped return address. 6.3.3 Java Support AVR32UC does not provide Java hardware acceleration. 6.3.4 Memory Protection The MPU allows the user to check all memory accesses for privilege violations. If an access is attempted to an illegal memory address, the access is aborted and an exception is taken. The MPU in AVR32UC is specified in the AVR32UC Technical Reference manual. 6.3.5 Unaligned Reference Handling AVR32UC does not support unaligned accesses, except for doubleword accesses. AVR32UC is able to perform word-aligned st.d and ld.d. Any other unaligned memory access will cause an address exception. Doubleword-sized accesses with word-aligned pointers will automatically be performed as two word-sized accesses. 20 32059L–AVR32–01/2012 AT32UC3B The following table shows the instructions with support for unaligned addresses. All other instructions require aligned addresses. Table 6-1. 6.3.6 Instructions with Unaligned Reference Support Instruction Supported alignment ld.d Word st.d Word Unimplemented Instructions The following instructions are unimplemented in AVR32UC, and will cause an Unimplemented Instruction Exception if executed: • All SIMD instructions • All coprocessor instructions if no coprocessors are present • retj, incjosp, popjc, pushjc • tlbr, tlbs, tlbw • cache 6.3.7 CPU and Architecture Revision Three major revisions of the AVR32UC CPU currently exist. The Architecture Revision field in the CONFIG0 system register identifies which architecture revision is implemented in a specific device. AVR32UC CPU revision 3 is fully backward-compatible with revisions 1 and 2, ie. code compiled for revision 1 or 2 is binary-compatible with revision 3 CPUs. 21 32059L–AVR32–01/2012 AT32UC3B 6.4 6.4.1 Programming Model Register File Configuration The AVR32UC register file is shown below. Figure 6-3. The AVR32UC Register File Application Supervisor INT0 Bit 31 Bit 31 Bit 31 Bit 0 Bit 0 INT1 Bit 0 INT2 Bit 31 Bit 0 INT3 Bit 31 Bit 0 Bit 31 Bit 0 Exception NMI Bit 31 Bit 31 Bit 0 Secure Bit 0 Bit 31 Bit 0 PC LR SP_APP R12 R11 R10 R9 R8 INT0PC R7 INT1PC R6 FINTPC R5 SMPC R4 R3 R2 R1 R0 PC LR SP_SYS R12 R11 R10 R9 R8 INT0PC R7 INT1PC R6 FINTPC R5 SMPC R4 R3 R2 R1 R0 PC LR SP_SYS R12 R11 R10 R9 R8 INT0PC R7 INT1PC R6 FINTPC R5 SMPC R4 R3 R2 R1 R0 PC LR SP_SYS R12 R11 R10 R9 R8 INT0PC R7 INT1PC R6 FINTPC R5 SMPC R4 R3 R2 R1 R0 PC LR SP_SYS R12 R11 R10 R9 R8 INT0PC R7 INT1PC R6 FINTPC R5 SMPC R4 R3 R2 R1 R0 PC LR SP_SYS R12 R11 R10 R9 R8 INT0PC R7 INT1PC R6 FINTPC R5 SMPC R4 R3 R2 R1 R0 PC LR SP_SYS R12 R11 R10 R9 R8 INT0PC R7 INT1PC R6 FINTPC R5 SMPC R4 R3 R2 R1 R0 PC LR SP_SYS R12 R11 R10 R9 R8 INT0PC R7 INT1PC R6 FINTPC R5 SMPC R4 R3 R2 R1 R0 PC LR SP_SEC R12 R11 R10 R9 R8 INT0PC R7 INT1PC R6 FINTPC R5 SMPC R4 R3 R2 R1 R0 SR SR SR SR SR SR SR SR SR SS_STATUS SS_ADRF SS_ADRR SS_ADR0 SS_ADR1 SS_SP_SYS SS_SP_APP SS_RAR SS_RSR 6.4.2 Status Register Configuration The Status Register (SR) is split into two halfwords, one upper and one lower, see Figure 6-4 on page 22 and Figure 6-5 on page 23. The lower word contains the C, Z, N, V, and Q condition code flags and the R, T, and L bits, while the upper halfword contains information about the mode and state the processor executes in. Refer to the AVR32 Architecture Manual for details. Figure 6-4. The Status Register High Halfword Bit 31 Bit 16 - LC 1 - - DM D - M2 M1 M0 EM I3M I2M FE I1M I0M GM 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 Bit name Initial value Global Interrupt Mask Interrupt Level 0 Mask Interrupt Level 1 Mask Interrupt Level 2 Mask Interrupt Level 3 Mask Exception Mask Mode Bit 0 Mode Bit 1 Mode Bit 2 Reserved Debug State Debug State Mask Reserved 22 32059L–AVR32–01/2012 AT32UC3B Figure 6-5. The Status Register Low Halfword Bit 15 Bit 0 - T - - - - - - - - L Q V N Z C Bit name 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Initial value Carry Zero Sign Overflow Saturation Lock Reserved Scratch Reserved 6.4.3 6.4.3.1 Processor States Normal RISC State The AVR32 processor supports several different execution contexts as shown in Table 6-2 on page 23. Table 6-2. Overview of Execution Modes, their Priorities and Privilege Levels. Priority Mode Security Description 1 Non Maskable Interrupt Privileged Non Maskable high priority interrupt mode 2 Exception Privileged Execute exceptions 3 Interrupt 3 Privileged General purpose interrupt mode 4 Interrupt 2 Privileged General purpose interrupt mode 5 Interrupt 1 Privileged General purpose interrupt mode 6 Interrupt 0 Privileged General purpose interrupt mode N/A Supervisor Privileged Runs supervisor calls N/A Application Unprivileged Normal program execution mode Mode changes can be made under software control, or can be caused by external interrupts or exception processing. A mode can be interrupted by a higher priority mode, but never by one with lower priority. Nested exceptions can be supported with a minimal software overhead. When running an operating system on the AVR32, user processes will typically execute in the application mode. The programs executed in this mode are restricted from executing certain instructions. Furthermore, most system registers together with the upper halfword of the status register cannot be accessed. Protected memory areas are also not available. All other operating modes are privileged and are collectively called System Modes. They have full access to all privileged and unprivileged resources. After a reset, the processor will be in supervisor mode. 6.4.3.2 Debug State The AVR32 can be set in a debug state, which allows implementation of software monitor routines that can read out and alter system information for use during application development. This implies that all system and application registers, including the status registers and program counters, are accessible in debug state. The privileged instructions are also available. 23 32059L–AVR32–01/2012 AT32UC3B All interrupt levels are by default disabled when debug state is entered, but they can individually be switched on by the monitor routine by clearing the respective mask bit in the status register. Debug state can be entered as described in the AVR32UC Technical Reference Manual. Debug state is exited by the retd instruction. 6.4.4 System Registers The system registers are placed outside of the virtual memory space, and are only accessible using the privileged mfsr and mtsr instructions. The table below lists the system registers specified in the AVR32 architecture, some of which are unused in AVR32UC. The programmer is responsible for maintaining correct sequencing of any instructions following a mtsr instruction. For detail on the system registers, refer to the AVR32UC Technical Reference Manual. Table 6-3. System Registers Reg # Address Name Function 0 0 SR Status Register 1 4 EVBA Exception Vector Base Address 2 8 ACBA Application Call Base Address 3 12 CPUCR CPU Control Register 4 16 ECR Exception Cause Register 5 20 RSR_SUP Unused in AVR32UC 6 24 RSR_INT0 Unused in AVR32UC 7 28 RSR_INT1 Unused in AVR32UC 8 32 RSR_INT2 Unused in AVR32UC 9 36 RSR_INT3 Unused in AVR32UC 10 40 RSR_EX Unused in AVR32UC 11 44 RSR_NMI Unused in AVR32UC 12 48 RSR_DBG Return Status Register for Debug mode 13 52 RAR_SUP Unused in AVR32UC 14 56 RAR_INT0 Unused in AVR32UC 15 60 RAR_INT1 Unused in AVR32UC 16 64 RAR_INT2 Unused in AVR32UC 17 68 RAR_INT3 Unused in AVR32UC 18 72 RAR_EX Unused in AVR32UC 19 76 RAR_NMI Unused in AVR32UC 20 80 RAR_DBG Return Address Register for Debug mode 21 84 JECR Unused in AVR32UC 22 88 JOSP Unused in AVR32UC 23 92 JAVA_LV0 Unused in AVR32UC 24 96 JAVA_LV1 Unused in AVR32UC 25 100 JAVA_LV2 Unused in AVR32UC 24 32059L–AVR32–01/2012 AT32UC3B Table 6-3. System Registers (Continued) Reg # Address Name Function 26 104 JAVA_LV3 Unused in AVR32UC 27 108 JAVA_LV4 Unused in AVR32UC 28 112 JAVA_LV5 Unused in AVR32UC 29 116 JAVA_LV6 Unused in AVR32UC 30 120 JAVA_LV7 Unused in AVR32UC 31 124 JTBA Unused in AVR32UC 32 128 JBCR Unused in AVR32UC 33-63 132-252 Reserved Reserved for future use 64 256 CONFIG0 Configuration register 0 65 260 CONFIG1 Configuration register 1 66 264 COUNT Cycle Counter register 67 268 COMPARE Compare register 68 272 TLBEHI Unused in AVR32UC 69 276 TLBELO Unused in AVR32UC 70 280 PTBR Unused in AVR32UC 71 284 TLBEAR Unused in AVR32UC 72 288 MMUCR Unused in AVR32UC 73 292 TLBARLO Unused in AVR32UC 74 296 TLBARHI Unused in AVR32UC 75 300 PCCNT Unused in AVR32UC 76 304 PCNT0 Unused in AVR32UC 77 308 PCNT1 Unused in AVR32UC 78 312 PCCR Unused in AVR32UC 79 316 BEAR Bus Error Address Register 80 320 MPUAR0 MPU Address Register region 0 81 324 MPUAR1 MPU Address Register region 1 82 328 MPUAR2 MPU Address Register region 2 83 332 MPUAR3 MPU Address Register region 3 84 336 MPUAR4 MPU Address Register region 4 85 340 MPUAR5 MPU Address Register region 5 86 344 MPUAR6 MPU Address Register region 6 87 348 MPUAR7 MPU Address Register region 7 88 352 MPUPSR0 MPU Privilege Select Register region 0 89 356 MPUPSR1 MPU Privilege Select Register region 1 90 360 MPUPSR2 MPU Privilege Select Register region 2 91 364 MPUPSR3 MPU Privilege Select Register region 3 25 32059L–AVR32–01/2012 AT32UC3B Table 6-3. 6.5 System Registers (Continued) Reg # Address Name Function 92 368 MPUPSR4 MPU Privilege Select Register region 4 93 372 MPUPSR5 MPU Privilege Select Register region 5 94 376 MPUPSR6 MPU Privilege Select Register region 6 95 380 MPUPSR7 MPU Privilege Select Register region 7 96 384 MPUCRA Unused in this version of AVR32UC 97 388 MPUCRB Unused in this version of AVR32UC 98 392 MPUBRA Unused in this version of AVR32UC 99 396 MPUBRB Unused in this version of AVR32UC 100 400 MPUAPRA MPU Access Permission Register A 101 404 MPUAPRB MPU Access Permission Register B 102 408 MPUCR MPU Control Register 103-191 448-764 Reserved Reserved for future use 192-255 768-1020 IMPL IMPLEMENTATION DEFINED Exceptions and Interrupts AVR32UC incorporates a powerful exception handling scheme. The different exception sources, like Illegal Op-code and external interrupt requests, have different priority levels, ensuring a welldefined behavior when multiple exceptions are received simultaneously. Additionally, pending exceptions of a higher priority class may preempt handling of ongoing exceptions of a lower priority class. When an event occurs, the execution of the instruction stream is halted, and execution control is passed to an event handler at an address specified in Table 6-4 on page 29. Most of the handlers are placed sequentially in the code space starting at the address specified by EVBA, with four bytes between each handler. This gives ample space for a jump instruction to be placed there, jumping to the event routine itself. A few critical handlers have larger spacing between them, allowing the entire event routine to be placed directly at the address specified by the EVBA-relative offset generated by hardware. All external interrupt sources have autovectored interrupt service routine (ISR) addresses. This allows the interrupt controller to directly specify the ISR address as an address relative to EVBA. The autovector offset has 14 address bits, giving an offset of maximum 16384 bytes. The target address of the event handler is calculated as (EVBA | event_handler_offset), not (EVBA + event_handler_offset), so EVBA and exception code segments must be set up appropriately. The same mechanisms are used to service all different types of events, including external interrupt requests, yielding a uniform event handling scheme. An interrupt controller does the priority handling of the external interrupts and provides the autovector offset to the CPU. 6.5.1 System Stack Issues Event handling in AVR32UC uses the system stack pointed to by the system stack pointer, SP_SYS, for pushing and popping R8-R12, LR, status register, and return address. Since event code may be timing-critical, SP_SYS should point to memory addresses in the IRAM section, since the timing of accesses to this memory section is both fast and deterministic. 26 32059L–AVR32–01/2012 AT32UC3B The user must also make sure that the system stack is large enough so that any event is able to push the required registers to stack. If the system stack is full, and an event occurs, the system will enter an UNDEFINED state. 6.5.2 Exceptions and Interrupt Requests When an event other than scall or debug request is received by the core, the following actions are performed atomically: 1. The pending event will not be accepted if it is masked. The I3M, I2M, I1M, I0M, EM, and GM bits in the Status Register are used to mask different events. Not all events can be masked. A few critical events (NMI, Unrecoverable Exception, TLB Multiple Hit, and Bus Error) can not be masked. When an event is accepted, hardware automatically sets the mask bits corresponding to all sources with equal or lower priority. This inhibits acceptance of other events of the same or lower priority, except for the critical events listed above. Software may choose to clear some or all of these bits after saving the necessary state if other priority schemes are desired. It is the event source’s responsability to ensure that their events are left pending until accepted by the CPU. 2. When a request is accepted, the Status Register and Program Counter of the current context is stored to the system stack. If the event is an INT0, INT1, INT2, or INT3, registers R8-R12 and LR are also automatically stored to stack. Storing the Status Register ensures that the core is returned to the previous execution mode when the current event handling is completed. When exceptions occur, both the EM and GM bits are set, and the application may manually enable nested exceptions if desired by clearing the appropriate bit. Each exception handler has a dedicated handler address, and this address uniquely identifies the exception source. 3. The Mode bits are set to reflect the priority of the accepted event, and the correct register file bank is selected. The address of the event handler, as shown in Table 6-4, is loaded into the Program Counter. The execution of the event handler routine then continues from the effective address calculated. The rete instruction signals the end of the event. When encountered, the Return Status Register and Return Address Register are popped from the system stack and restored to the Status Register and Program Counter. If the rete instruction returns from INT0, INT1, INT2, or INT3, registers R8-R12 and LR are also popped from the system stack. The restored Status Register contains information allowing the core to resume operation in the previous execution mode. This concludes the event handling. 6.5.3 Supervisor Calls The AVR32 instruction set provides a supervisor mode call instruction. The scall instruction is designed so that privileged routines can be called from any context. This facilitates sharing of code between different execution modes. The scall mechanism is designed so that a minimal execution cycle overhead is experienced when performing supervisor routine calls from timecritical event handlers. The scall instruction behaves differently depending on which mode it is called from. The behaviour is detailed in the instruction set reference. In order to allow the scall routine to return to the correct context, a return from supervisor call instruction, rets, is implemented. In the AVR32UC CPU, scall and rets uses the system stack to store the return address and the status register. 6.5.4 Debug Requests The AVR32 architecture defines a dedicated Debug mode. When a debug request is received by the core, Debug mode is entered. Entry into Debug mode can be masked by the DM bit in the 27 32059L–AVR32–01/2012 AT32UC3B status register. Upon entry into Debug mode, hardware sets the SR[D] bit and jumps to the Debug Exception handler. By default, Debug mode executes in the exception context, but with dedicated Return Address Register and Return Status Register. These dedicated registers remove the need for storing this data to the system stack, thereby improving debuggability. The mode bits in the status register can freely be manipulated in Debug mode, to observe registers in all contexts, while retaining full privileges. Debug mode is exited by executing the retd instruction. This returns to the previous context. 6.5.5 Entry Points for Events Several different event handler entry points exists. In AVR32UC, the reset address is 0x8000_0000. This places the reset address in the boot flash memory area. TLB miss exceptions and scall have a dedicated space relative to EVBA where their event handler can be placed. This speeds up execution by removing the need for a jump instruction placed at the program address jumped to by the event hardware. All other exceptions have a dedicated event routine entry point located relative to EVBA. The handler routine address identifies the exception source directly. AVR32UC uses the ITLB and DTLB protection exceptions to signal a MPU protection violation. ITLB and DTLB miss exceptions are used to signal that an access address did not map to any of the entries in the MPU. TLB multiple hit exception indicates that an access address did map to multiple TLB entries, signalling an error. All external interrupt requests have entry points located at an offset relative to EVBA. This autovector offset is specified by an external Interrupt Controller. The programmer must make sure that none of the autovector offsets interfere with the placement of other code. The autovector offset has 14 address bits, giving an offset of maximum 16384 bytes. Special considerations should be made when loading EVBA with a pointer. Due to security considerations, the event handlers should be located in non-writeable flash memory, or optionally in a privileged memory protection region if an MPU is present. If several events occur on the same instruction, they are handled in a prioritized way. The priority ordering is presented in Table 6-4. If events occur on several instructions at different locations in the pipeline, the events on the oldest instruction are always handled before any events on any younger instruction, even if the younger instruction has events of higher priority than the oldest instruction. An instruction B is younger than an instruction A if it was sent down the pipeline later than A. The addresses and priority of simultaneous events are shown in Table 6-4. Some of the exceptions are unused in AVR32UC since it has no MMU, coprocessor interface, or floating-point unit. 28 32059L–AVR32–01/2012 AT32UC3B Table 6-4. Priority and Handler Addresses for Events Priority Handler Address Name Event source Stored Return Address 1 0x8000_0000 Reset External input Undefined 2 Provided by OCD system OCD Stop CPU OCD system First non-completed instruction 3 EVBA+0x00 Unrecoverable exception Internal PC of offending instruction 4 EVBA+0x04 TLB multiple hit MPU 5 EVBA+0x08 Bus error data fetch Data bus First non-completed instruction 6 EVBA+0x0C Bus error instruction fetch Data bus First non-completed instruction 7 EVBA+0x10 NMI External input First non-completed instruction 8 Autovectored Interrupt 3 request External input First non-completed instruction 9 Autovectored Interrupt 2 request External input First non-completed instruction 10 Autovectored Interrupt 1 request External input First non-completed instruction 11 Autovectored Interrupt 0 request External input First non-completed instruction 12 EVBA+0x14 Instruction Address CPU PC of offending instruction 13 EVBA+0x50 ITLB Miss MPU 14 EVBA+0x18 ITLB Protection MPU PC of offending instruction 15 EVBA+0x1C Breakpoint OCD system First non-completed instruction 16 EVBA+0x20 Illegal Opcode Instruction PC of offending instruction 17 EVBA+0x24 Unimplemented instruction Instruction PC of offending instruction 18 EVBA+0x28 Privilege violation Instruction PC of offending instruction 19 EVBA+0x2C Floating-point UNUSED 20 EVBA+0x30 Coprocessor absent Instruction PC of offending instruction 21 EVBA+0x100 Supervisor call Instruction PC(Supervisor Call) +2 22 EVBA+0x34 Data Address (Read) CPU PC of offending instruction 23 EVBA+0x38 Data Address (Write) CPU PC of offending instruction 24 EVBA+0x60 DTLB Miss (Read) MPU 25 EVBA+0x70 DTLB Miss (Write) MPU 26 EVBA+0x3C DTLB Protection (Read) MPU PC of offending instruction 27 EVBA+0x40 DTLB Protection (Write) MPU PC of offending instruction 28 EVBA+0x44 DTLB Modified UNUSED 29 32059L–AVR32–01/2012 AT32UC3B 6.6 Module Configuration All AT32UC3B parts do not implement the same CPU and Architecture Revision. Table 6-5. CPU and Architecture Revision Part Name Architecture Revision AT32UC3Bx512 2 AT32UC3Bx256 1 AT32UC3Bx128 1 AT32UC3Bx64 1 30 32059L–AVR32–01/2012 AT32UC3B 7. Memories 7.1 Embedded Memories • Internal High-Speed Flash – – – – 512KBytes (AT32UC3B0512, AT32UC3B1512) 256 KBytes (AT32UC3B0256, AT32UC3B1256) 128 KBytes (AT32UC3B0128, AT32UC3B1128) 64 KBytes (AT32UC3B064, AT32UC3B164) • - 0 Wait State Access at up to 30 MHz in Worst Case Conditions • - 1 Wait State Access at up to 60 MHz in Worst Case Conditions • - Pipelined Flash Architecture, allowing burst reads from sequential Flash locations, hiding penalty of 1 wait state access • - 100 000 Write Cycles, 15-year Data Retention Capability • - 4 ms Page Programming Time, 8 ms Chip Erase Time • - Sector Lock Capabilities, Bootloader Protection, Security Bit • - 32 Fuses, Erased During Chip Erase • - User Page For Data To Be Preserved During Chip Erase • Internal High-Speed SRAM, Single-cycle access at full speed – 96KBytes ((AT32UC3B0512, AT32UC3B1512) – 32KBytes (AT32UC3B0256, AT32UC3B0128, AT32UC3B1256 and AT32UC3B1128) – 16KBytes (AT32UC3B064 and AT32UC3B164) 7.2 Physical Memory Map The system bus is implemented as a bus matrix. All system bus addresses are fixed, and they are never remapped in any way, not even in boot. Note that AVR32 UC CPU uses unsegmented translation, as described in the AVR32UC Technical Architecture Manual. The 32-bit physical address space is mapped as follows: Table 7-1. Embedded SRAM Embedded Flash USB Data HSB-PB Bridge A HSB-PB Bridge B 0x0000_0000 0x8000_0000 0xD000_0000 0xFFFF_0000 0xFFFE_0000 AT32UC3B0512 AT32UC3B1512 96 Kbytes 512 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes AT32UC3B0256 AT32UC3B1256 32 Kbytes 256 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes AT32UC3B0128 AT32UC3B1128 32 Kbytes 128 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes AT32UC3B064 AT32UC3B164 16 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes Device Start Address Size AT32UC3B Physical Memory Map 31 32059L–AVR32–01/2012 AT32UC3B 7.3 Peripheral Address Map Table 7-2. Peripheral Address Mapping Address 0xFFFE0000 0xFFFE1000 0xFFFE1400 0xFFFF0000 0xFFFF0800 0xFFFF0C00 0xFFFF0D00 0xFFFF0D30 0xFFFF0D80 0xFFFF1000 0xFFFF1400 0xFFFF1800 0xFFFF1C00 0xFFFF2400 0xFFFF2C00 0xFFFF3000 0xFFFF3400 0xFFFF3800 Peripheral Name USB USB 2.0 Interface - USB HMATRIX HSB Matrix - HMATRIX HFLASHC Flash Controller - HFLASHC PDCA Peripheral DMA Controller - PDCA INTC Interrupt controller - INTC PM Power Manager - PM RTC Real Time Counter - RTC WDT Watchdog Timer - WDT EIM External Interrupt Controller - EIM GPIO General Purpose Input/Output Controller - GPIO USART0 Universal Synchronous/Asynchronous Receiver/Transmitter - USART0 USART1 Universal Synchronous/Asynchronous Receiver/Transmitter - USART1 USART2 Universal Synchronous/Asynchronous Receiver/Transmitter - USART2 SPI0 Serial Peripheral Interface - SPI0 TWI Two-wire Interface - TWI PWM Pulse Width Modulation Controller - PWM SSC Synchronous Serial Controller - SSC TC Timer/Counter - TC 32 32059L–AVR32–01/2012 AT32UC3B Table 7-2. Peripheral Address Mapping 0xFFFF3C00 ADC 0xFFFF4000 7.4 ABDAC Analog to Digital Converter - ADC Audio Bitstream DAC - ABDAC CPU Local Bus Mapping Some of the registers in the GPIO module are mapped onto the CPU local bus, in addition to being mapped on the Peripheral Bus. These registers can therefore be reached both by accesses on the Peripheral Bus, and by accesses on the local bus. Mapping these registers on the local bus allows cycle-deterministic toggling of GPIO pins since the CPU and GPIO are the only modules connected to this bus. Also, since the local bus runs at CPU speed, one write or read operation can be performed per clock cycle to the local busmapped GPIO registers. The following GPIO registers are mapped on the local bus: Table 7-3. Local bus mapped GPIO registers Port Register Mode Local Bus Address Access 0 Output Driver Enable Register (ODER) WRITE 0x4000_0040 Write-only SET 0x4000_0044 Write-only CLEAR 0x4000_0048 Write-only TOGGLE 0x4000_004C Write-only WRITE 0x4000_0050 Write-only SET 0x4000_0054 Write-only CLEAR 0x4000_0058 Write-only TOGGLE 0x4000_005C Write-only Pin Value Register (PVR) - 0x4000_0060 Read-only Output Driver Enable Register (ODER) WRITE 0x4000_0140 Write-only SET 0x4000_0144 Write-only CLEAR 0x4000_0148 Write-only TOGGLE 0x4000_014C Write-only WRITE 0x4000_0150 Write-only SET 0x4000_0154 Write-only CLEAR 0x4000_0158 Write-only TOGGLE 0x4000_015C Write-only - 0x4000_0160 Read-only Output Value Register (OVR) 1 Output Value Register (OVR) Pin Value Register (PVR) 33 32059L–AVR32–01/2012 AT32UC3B 8. Boot Sequence This chapter summarizes the boot sequence of the AT32UC3B. The behaviour after power-up is controlled by the Power Manager. For specific details, refer to section Power Manager (PM). 8.1 Starting of clocks After power-up, the device will be held in a reset state by the Power-On Reset circuitry, until the power has stabilized throughout the device. Once the power has stabilized, the device will use the internal RC Oscillator as clock source. On system start-up, the PLLs are disabled. All clocks to all modules are running. No clocks have a divided frequency, all parts of the system recieves a clock with the same frequency as the internal RC Oscillator. 8.2 Fetching of initial instructions After reset has been released, the AVR32 UC CPU starts fetching instructions from the reset address, which is 0x8000_0000. This address points to the first address in the internal Flash. The code read from the internal Flash is free to configure the system to use for example the PLLs, to divide the frequency of the clock routed to some of the peripherals, and to gate the clocks to unused peripherals. When powering up the device, there may be a delay before the voltage has stabilized, depending on the rise time of the supply used. The CPU can start executing code as soon as the supply is above the POR threshold, and before the supply is stable. Before switching to a high-speed clock source, the user should use the BOD to make sure the VDDCORE is above the minimum level. 34 32059L–AVR32–01/2012 AT32UC3B 9. Power Manager (PM) Rev: 2.3.0.2 9.1 Features • • • • • • • • • • • • • 9.2 Controls integrated oscillators and PLLs Generates clocks and resets for digital logic Supports 2 crystal oscillators 0.4-20 MHz Supports 2 PLLs 80-240 MHz Supports 32 KHz ultra-low power oscillator Integrated low-power RC oscillator On-the fly frequency change of CPU, HSB, PBA, and PBB clocks Sleep modes allow simple disabling of logic clocks, PLLs, and oscillators Module-level clock gating through maskable peripheral clocks Wake-up from internal or external interrupts Generic clocks with wide frequency range provided Automatic identification of reset sources Controls brownout detector (BOD), RC oscillator, and bandgap voltage reference through control and calibration registers Description The Power Manager (PM) controls the oscillators and PLLs, and generates the clocks and resets in the device. The PM controls two fast crystal oscillators, as well as two PLLs, which can multiply the clock from either oscillator to provide higher frequencies. Additionally, a low-power 32 KHz oscillator is used to generate the real-time counter clock for high accuracy real-time measurements. The PM also contains a low-power RC oscillator with fast start-up time, which can be used to clock the digital logic. The provided clocks are divided into synchronous and generic clocks. The synchronous clocks are used to clock the main digital logic in the device, namely the CPU, and the modules and peripherals connected to the HSB, PBA, and PBB buses. The generic clocks are asynchronous clocks, which can be tuned precisely within a wide frequency range, which makes them suitable for peripherals that require specific frequencies, such as timers and communication modules. The PM also contains advanced power-saving features, allowing the user to optimize the power consumption for an application. The synchronous clocks are divided into three clock domains, one for the CPU and HSB, one for modules on the PBA bus, and one for modules on the PBB bus.The three clocks can run at different speeds, so the user can save power by running peripherals at a relatively low clock, while maintaining a high CPU performance. Additionally, the clocks can be independently changed on-the-fly, without halting any peripherals. This enables the user to adjust the speed of the CPU and memories to the dynamic load of the application, without disturbing or re-configuring active peripherals. Each module also has a separate clock, enabling the user to switch off the clock for inactive modules, to save further power. Additionally, clocks and oscillators can be automatically switched off during idle periods by using the sleep instruction on the CPU. The system will return to normal on occurrence of interrupts. The Power Manager also contains a Reset Controller, which collects all possible reset sources, generates hard and soft resets, and allows the reset source to be identified by software. 35 32059L–AVR32–01/2012 AT32UC3B 9.3 Block Diagram Figure 9-1. Power Manager block diagram RCOSC Oscillator 0 Synchronous Clock Generator Synchronous clocks CPU, HSB, PBA, PBB Generic Clock Generator G eneric clocks PLL0 PLL1 Oscillator 1 32 KHz Oscillator O SC/PLL Control signals 32 KHz clock for RTC RC Oscillator Slow clock Oscillator and PLL Control Startup Counter Voltage Regulator Interrupts fuses Sleep Controller Sleep instruction Calibration Registers Brown-Out Detector Reset Controller resets Power-On Detector O ther reset sources External Reset Pad 36 32059L–AVR32–01/2012 AT32UC3B 9.4 9.4.1 Product Dependencies I/O Lines The PM provides a number of generic clock outputs, which can be connected to output pins, multiplexed with GPIO lines. The programmer must first program the GPIO controller to assign these pins to their peripheral function. If the I/O pins of the PM are not used by the application, they can be used for other purposes by the GPIO controller. 9.4.2 Interrupt The PM interrupt line is connected to one of the internal sources of the interrupt controller. Using the PM interrupt requires the interrupt controller to be programmed first. 9.4.3 9.5 9.5.1 Clock implementation In AT32UC3B, the HSB shares the source clock with the CPU. This means that writing to the HSBDIV and HSBSEL bits in CKSEL has no effect. These bits will always read the same as CPUDIV and CPUSEL. Functional Description Slow clock The slow clock is generated from an internal RC oscillator which is always running, except in Static mode. The slow clock can be used for the main clock in the device, as described in ”Synchronous clocks” on page 39. The slow clock is also used for the Watchdog Timer and measuring various delays in the Power Manager. The RC oscillator has a 3 cycles startup time, and is always available when the CPU is running. The RC oscillator operates at approximately 115 kHz, and can be calibrated to a narrow range by the RCOSCCAL fuses. Software can also change RC oscillator calibration through the use of the RCCR register. Please see the Electrical Characteristics section for details. RC oscillator can also be used as the RTC clock when crystal accuracy is not required. 9.5.2 Oscillator 0 and 1 operation The two main oscillators are designed to be used with an external crystal and two biasing capacitors, as shown in Figure 9-2. Oscillator 0 can be used for the main clock in the device, as described in ”Synchronous clocks” on page 39. Both oscillators can be used as source for the generic clocks, as described in ”Generic clocks” on page 43. The oscillators are disabled by default after reset. When the oscillators are disabled, the XIN and XOUT pins can be used as general purpose I/Os. When the oscillators are configured to use an external clock, the clock must be applied to the XIN pin while the XOUT pin can be used as a general purpose I/O. The oscillators can be enabled by writing to the OSCnEN bits in MCCTRL. Operation mode (external clock or crystal) is chosen by writing to the MODE field in OSCCTRLn. Oscillators are automatically switched off in certain sleep modes to reduce power consumption, as described in Section 9.5.7 on page 42. After a hard reset, or when waking up from a sleep mode that disabled the oscillators, the oscillators may need a certain amount of time to stabilize on the correct frequency. This start-up time can be set in the OSCCTRLn register. 37 32059L–AVR32–01/2012 AT32UC3B The PM masks the oscillator outputs during the start-up time, to ensure that no unstable clocks propagate to the digital logic. The OSCnRDY bits in POSCSR are automatically set and cleared according to the status of the oscillators. A zero to one transition on these bits can also be configured to generate an interrupt, as described in ”MODE: Oscillator Mode” on page 57. Figure 9-2. Oscillator connections C2 XO UT XIN C1 9.5.3 32 KHz oscillator operation The 32 KHz oscillator operates as described for Oscillator 0 and 1 above. The 32 KHz oscillator is used as source clock for the Real-Time Counter. The oscillator is disabled by default, but can be enabled by writing OSC32EN in OSCCTRL32. The oscillator is an ultra-low power design and remains enabled in all sleep modes except Static mode. While the 32 KHz oscillator is disabled, the XIN32 and XOUT32 pins are available as general purpose I/Os. When the oscillator is configured to work with an external clock (MODE field in OSCCTRL32 register), the external clock must be connected to XIN32 while the XOUT32 pin can be used as a general purpose I/O. The startup time of the 32 KHz oscillator can be set in the OSCCTRL32, after which OSC32RDY in POSCSR is set. An interrupt can be generated on a zero to one transition of OSC32RDY. As a crystal oscillator usually requires a very long startup time (up to 1 second), the 32 KHz oscillator will keep running across resets, except Power-On-Reset. 9.5.4 PLL operation The device contains two PLLs, PLL0 and PLL1. These are disabled by default, but can be enabled to provide high frequency source clocks for synchronous or generic clocks. The PLLs can take either Oscillator 0 or 1 as reference clock. The PLL output is divided by a multiplication factor, and the PLL compares the resulting clock to the reference clock. The PLL will adjust its output frequency until the two compared clocks are equal, thus locking the output frequency to a multiple of the reference clock frequency. The Voltage Controlled Oscillator inside the PLL can generate frequencies from 80 to 240 MHz. To make the PLL output frequencies under 80 MHz the OTP[1] bitfield could be set. This will divide the output of the PLL by two and bring the clock in range of the max frequency of the CPU. 38 32059L–AVR32–01/2012 AT32UC3B When the PLL is switched on, or when changing the clock source or multiplication factor for the PLL, the PLL is unlocked and the output frequency is undefined. The PLL clock for the digital logic is automatically masked when the PLL is unlocked, to prevent connected digital logic from receiving a too high frequency and thus become unstable. Figure 9-3. PLL with control logic and filters PLLM UL P L L O P T [1 ] fvco O u tp u t D iv id e r 0 1 /2 O sc0 c lo c k 0 O sc1 c lo c k In p u t D iv id e r 1 PLLO SC 9.5.4.1 Phase D e te c to r VCO Lock D e te c to r fP LL M ask P L L c lo c k 1 L o c k b it PLLO PT P L L D IV Enabling the PLL PLLn is enabled by writing the PLLEN bit in the PLLn register. PLLOSC selects Oscillator 0 or 1 as clock source. The PLLMUL and PLLDIV bitfields must be written with the multiplication and division factors, respectively, creating the voltage controlled ocillator frequency fVCO and the PLL frequency fPLL : fVCO = (PLLMUL+1)/(PLLDIV) • fOSC if PLLDIV > 0. fVCO = 2*(PLLMUL+1) • fOSC if PLLDIV = 0. If PLLOPT[1] field is set to 0: fPLL = fVCO. If PLLOPT[1] field is set to 1: fPLL = fVCO / 2. The PLLn:PLLOPT field should be set to proper values according to the PLL operating frequency. The PLLOPT field can also be set to divide the output frequency of the PLLs by 2. The lock signal for each PLL is available as a LOCKn flag in POSCSR. An interrupt can be generated on a 0 to 1 transition of these bits. 9.5.5 Synchronous clocks The slow clock (default), Oscillator 0, or PLL0 provide the source for the main clock, which is the common root for the synchronous clocks for the CPU/HSB, PBA, and PBB modules. The main clock is divided by an 8-bit prescaler, and each of these four synchronous clocks can run from 39 32059L–AVR32–01/2012 AT32UC3B any tapping of this prescaler, or the undivided main clock, as long as fCPU fPBA,B,. The synchronous clock source can be changed on-the fly, responding to varying load in the application. The clock domains can be shut down in sleep mode, as described in ”Sleep modes” on page 42. Additionally, the clocks for each module in the four domains can be individually masked, to avoid power consumption in inactive modules. Figure 9-4. Synchronous clock generation Sleep Controller Sleep instruction 0 Main clock Slow clock Osc0 clock PLL0 clock Prescaler CPUDIV MCSEL Mask 1 CPU clocks HSB clocks CPUMASK PBAclocks PBB clocks CPUSEL 9.5.5.1 Selecting PLL or oscillator for the main clock The common main clock can be connected to the slow clock, Oscillator 0, or PLL0. By default, the main clock will be connected to the slow clock. The user can connect the main clock to Oscillator 0 or PLL0 by writing the MCSEL bitfield in the Main Clock Control Register (MCCTRL). This must only be done after that unit has been enabled, otherwise a deadlock will occur. Care should also be taken that the new frequency of the synchronous clocks does not exceed the maximum frequency for each clock domain. 9.5.5.2 Selecting synchronous clock division ratio The main clock feeds an 8-bit prescaler, which can be used to generate the synchronous clocks. By default, the synchronous clocks run on the undivided main clock. The user can select a prescaler division for the CPU clock by writing CKSEL:CPUDIV to 1 and CPUSEL to the prescaling value, resulting in a CPU clock frequency: fCPU = fmain / 2(CPUSEL+1) 40 32059L–AVR32–01/2012 AT32UC3B Similarly, the clock for the PBA, and PBB can be divided by writing their respective bitfields. To ensure correct operation, frequencies must be selected so that fCPU fPBA,B. Also, frequencies must never exceed the specified maximum frequency for each clock domain. CKSEL can be written without halting or disabling peripheral modules. Writing CKSEL allows a new clock setting to be written to all synchronous clocks at the same time. It is possible to keep one or more clocks unchanged by writing the same value a before to the xxxDIV and xxxSEL bitfields. This way, it is possible to e.g. scale CPU and HSB speed according to the required performance, while keeping the PBA and PBB frequency constant. For modules connected to the HSB bus, the PB clock frequency must be set to the same frequency than the CPU clock. 9.5.5.3 9.5.6 Clock Ready flag There is a slight delay from CKSEL is written and the new clock setting becomes effective. During this interval, the Clock Ready (CKRDY) flag in ISR will read as 0. If IER:CKRDY is written to 1, the Power Manager interrupt can be triggered when the new clock setting is effective. CKSEL must not be re-written while CKRDY is 0, or the system may become unstable or hang. Peripheral clock masking By default, the clock for all modules are enabled, regardless of which modules are actually being used. It is possible to disable the clock for a module in the CPU, HSB, PBA, or PBB clock domain by writing the corresponding bit in the Clock Mask register (CPU/HSB/PBA/PBB) to 0. When a module is not clocked, it will cease operation, and its registers cannot be read or written. The module can be re-enabled later by writing the corresponding mask bit to 1. A module may be connected to several clock domains, in which case it will have several mask bits. Table 9-6 contains a list of implemented maskable clocks. 9.5.6.1 Cautionary note Note that clocks should only be switched off if it is certain that the module will not be used. Switching off the clock for the internal RAM will cause a problem if the stack is mapped there. Switching off the clock to the Power Manager (PM), which contains the mask registers, or the corresponding PBx bridge, will make it impossible to write the mask registers again. In this case, they can only be re-enabled by a system reset. 9.5.6.2 Mask Ready flag Due to synchronization in the clock generator, there is a slight delay from a mask register is written until the new mask setting goes into effect. When clearing mask bits, this delay can usually be ignored. However, when setting mask bits, the registers in the corresponding module must not be written until the clock has actually be re-enabled. The status flag MSKRDY in ISR provides the required mask status information. When writing either mask register with any value, this bit is cleared. The bit is set when the clocks have been enabled and disabled according to the new mask setting. Optionally, the Power Manager interrupt can be enabled by writing the MSKRDY bit in IER. 41 32059L–AVR32–01/2012 AT32UC3B 9.5.7 Sleep modes In normal operation, all clock domains are active, allowing software execution and peripheral operation. When the CPU is idle, it is possible to switch off the CPU clock and optionally other clock domains to save power. This is activated by the sleep instruction, which takes the sleep mode index number as argument. 9.5.7.1 Entering and exiting sleep modes The sleep instruction will halt the CPU and all modules belonging to the stopped clock domains. The modules will be halted regardless of the bit settings of the mask registers. Oscillators and PLLs can also be switched off to save power. Some of these modules have a relatively long start-up time, and are only switched off when very low power consumption is required. The CPU and affected modules are restarted when the sleep mode is exited. This occurs when an interrupt triggers. Note that even if an interrupt is enabled in sleep mode, it may not trigger if the source module is not clocked. 9.5.7.2 Supported sleep modes The following sleep modes are supported. These are detailed in Table 9-1. •Idle: The CPU is stopped, the rest of the chip is operating. Wake-up sources are any interrupt. •Frozen: The CPU and HSB modules are stopped, peripherals are operating. Wake-up sources are any interrupts from PB modules. •Standby: All synchronous clocks are stopped, but oscillators and PLLs are running, allowing quick wake-up to normal mode. Wake-up sources are RTC or external interrupt (EIC), external reset or any asynchronous interrupts from PB modules. •Stop: As Standby, but Oscillator 0 and 1, and the PLLs are stopped. 32 KHz (if enabled) and RC oscillators and RTC/WDT will still operate. Wake-up are the same as for Standby mode. •DeepStop: All synchronous clocks, Oscillator 0 and 1 and PLL 0 and 1 are stopped. 32 KHz oscillator can run if enabled. RC oscillator still operates. Bandgap voltage reference and BOD is turned off. Wake-up sources are RTC, external interrupt in asynchronous mode, external reset or any asynchronous interrupts from PB modules. •Static: All oscillators, including 32 KHz and RC oscillator are stopped. Bandgap voltage reference BOD detector is turned off. Wake-up sources are external interrupt (EIC) in asynchronous mode only, external reset pin or any asynchronous interrupts from PB modules. Table 9-1. Sleep modes Osc0,1 PLL0,1, SYSTIMER Osc32 Sleep Mode CPU HSB PBA,B GCLK 0 Idle Stop Run Run Run Run Run On Full power 1 Frozen Stop Stop Run Run Run Run On Full power 2 Standby Stop Stop Stop Run Run Run On Full power 3 Stop Stop Stop Stop Stop Run Run On Low power 4 DeepStop Stop Stop Stop Stop Run Run Off Low power 5 Static Stop Stop Stop Stop Stop Stop Off Low power Index RCOsc BOD & Bandgap Voltage Regulator 42 32059L–AVR32–01/2012 AT32UC3B The power level of the internal voltage regulator is also adjusted according to the sleep mode to reduce the internal regulator power consumption. 9.5.7.3 Precautions when entering sleep mode Modules communicating with external circuits should normally be disabled before entering a sleep mode that will stop the module operation. This prevents erratic behavior when entering or exiting sleep mode. Please refer to the relevant module documentation for recommended actions. Communication between the synchronous clock domains is disturbed when entering and exiting sleep modes. This means that bus transactions are not allowed between clock domains affected by the sleep mode. The system may hang if the bus clocks are stopped in the middle of a bus transaction. The CPU is automatically stopped in a safe state to ensure that all CPU bus operations are complete when the sleep mode goes into effect. Thus, when entering Idle mode, no further action is necessary. When entering a sleep mode (except Idle mode), all HSB masters must be stopped before entering the sleep mode. Also, if there is a chance that any PB write operations are incomplete, the CPU should perform a read operation from any register on the PB bus before executing the sleep instruction. This will stall the CPU while waiting for any pending PB operations to complete. When entering a sleep mode deeper or equal to DeepStop, the VBus asynchronous interrupt should be disabled (USBCON.VBUSTE = 0). 9.5.7.4 Wake Up The USB can be used to wake up the part from sleep modes through register AWEN of the Power Manager. 9.5.8 Generic clocks Timers, communication modules, and other modules connected to external circuitry may require specific clock frequencies to operate correctly. The Power Manager contains an implementation defined number of generic clocks that can provide a wide range of accurate clock frequencies. Each generic clock module runs from either Oscillator 0 or 1, or PLL0 or 1. The selected source can optionally be divided by any even integer up to 512. Each clock can be independently enabled and disabled, and is also automatically disabled along with peripheral clocks by the Sleep Controller. 43 32059L–AVR32–01/2012 AT32UC3B Figure 9-5. Generic clock generation Sleep Controller 0 Osc0 clock Osc1 clock PLL0 clock PLL1 clock Divider Generic Clock 1 1 PLLSEL OSCSEL 9.5.8.1 Mask 0 DIV DIVEN CEN Enabling a generic clock A generic clock is enabled by writing the CEN bit in GCCTRL to 1. Each generic clock can use either Oscillator 0 or 1 or PLL0 or 1 as source, as selected by the PLLSEL and OSCSEL bits. The source clock can optionally be divided by writing DIVEN to 1 and the division factor to DIV, resulting in the output frequency: fGCLK = fSRC / (2*(DIV+1)) 9.5.8.2 Disabling a generic clock The generic clock can be disabled by writing CEN to 0 or entering a sleep mode that disables the PB clocks. In either case, the generic clock will be switched off on the first falling edge after the disabling event, to ensure that no glitches occur. If CEN is written to 0, the bit will still read as 1 until the next falling edge occurs, and the clock is actually switched off. When writing CEN to 0, the other bits in GCCTRL should not be changed until CEN reads as 0, to avoid glitches on the generic clock. When the clock is disabled, both the prescaler and output are reset. 9.5.8.3 Changing clock frequency When changing generic clock frequency by writing GCCTRL, the clock should be switched off by the procedure above, before being re-enabled with the new clock source or division setting. This prevents glitches during the transition. 44 32059L–AVR32–01/2012 AT32UC3B 9.5.8.4 Generic clock implementation In AT32UC3B, there are 5 generic clocks. These are allocated to different functions as shown in Table 9-2. Table 9-2. Generic clock allocation Clock number 9.5.9 Function 0 GCLK0 pin 1 GCLK1 pin 2 GCLK2 pin 3 USBB 4 ABDAC Divided PB clocks The clock generator in the Power Manager provides divided PBA and PBB clocks for use by peripherals that require a prescaled PBx clock. This is described in the documentation for the relevant modules. The divided clocks are not directly maskable, but are stopped in sleep modes where the PBx clocks are stopped. 9.5.10 Debug operation During a debug session, the user may need to halt the system to inspect memory and CPU registers. The clocks normally keep running during this debug operation, but some peripherals may require the clocks to be stopped, e.g. to prevent timer overflow, which would cause the program to fail. For this reason, peripherals on the PBA and PBB buses may use “debug qualified” PBx clocks. This is described in the documentation for the relevant modules. The divided PBx clocks are always debug qualified clocks. Debug qualified PB clocks are stopped during debug operation. The debug system can optionally keep these clocks running during the debug operation. This is described in the documentation for the On-Chip Debug system. 9.5.11 Reset Controller The Reset Controller collects the various reset sources in the system and generates hard and soft resets for the digital logic. The device contains a Power-On Detector, which keeps the system reset until power is stable. This eliminates the need for external reset circuitry to guarantee stable operation when powering up the device. It is also possible to reset the device by asserting the RESET_N pin. This pin has an internal pullup, and does not need to be driven externally when negated. Table 9-4 lists these and other reset sources supported by the Reset Controller. 45 32059L–AVR32–01/2012 AT32UC3B Figure 9-6. Reset Controller block diagram R C _R C AU S E RESET_N P o w e r-O n D e te c to r CPU, HSB, PBA, PBB R eset C o n tro lle r B ro w n o u t D e te c to r O C D , R T C /W D T C lo c k G e n e ra to JTAG OCD W a tc h d o g R e s e t In addition to the listed reset types, the JTAG can keep parts of the device statically reset through the JTAG Reset Register. See JTAG documentation for details. Table 9-3. Reset description Reset source Description Power-on Reset Supply voltage below the power-on reset detector threshold voltage External Reset RESET_N pin asserted Brownout Reset Supply voltage below the brownout reset detector threshold voltage CPU Error Caused by an illegal CPU access to external memory while in Supervisor mode Watchdog Timer See watchdog timer documentation. OCD See On-Chip Debug documentation When a Reset occurs, some parts of the chip are not necessarily reset, depending on the reset source. Only the Power On Reset (POR) will force a reset of the whole chip. 46 32059L–AVR32–01/2012 AT32UC3B Table 9-4 lists parts of the device that are reset, depending on the reset source. Table 9-4. Effect of the different reset events Power-On Reset External Reset Watchdog Reset BOD Reset CPU Error Reset OCD Reset CPU/HSB/PBA/PBB (excluding Power Manager) Y Y Y Y Y Y 32 KHz oscillator Y N N N N N RTC control register Y N N N N N GPLP registers Y N N N N N Watchdog control register Y Y N Y Y Y Voltage Calibration register Y N N N N N RC Oscillator Calibration register Y N N N N N BOD control register Y Y N N N N Bandgap control register Y Y N N N N Clock control registers Y Y Y Y Y Y Osc0/Osc1 and control registers Y Y Y Y Y Y PLL0/PLL1 and control registers Y Y Y Y Y Y OCD system and OCD registers Y Y N Y Y N The cause of the last reset can be read from the RCAUSE register. This register contains one bit for each reset source, and can be read during the boot sequence of an application to determine the proper action to be taken. 9.5.11.1 Power-On Detector The Power-On Detector monitors the VDDCORE supply pin and generates a reset when the device is powered on. The reset is active until the supply voltage from the linear regulator is above the power-on threshold level. The reset will be re-activated if the voltage drops below the power-on threshold level. See Electrical Characteristics for parametric details. 9.5.11.2 Brown-Out Detector The Brown-Out Detector (BOD) monitors the VDDCORE supply pin and compares the supply voltage to the brown-out detection level, as set in BOD.LEVEL. The BOD is disabled by default, but can be enabled either by software or by flash fuses. The Brown-Out Detector can either generate an interrupt or a reset when the supply voltage is below the brown-out detection level. In any case, the BOD output is available in bit POSCR.BODET bit. Note 1 : Any change to the BOD.LEVEL field of the BOD register should be done with the BOD deactivated to avoid spurious reset or interrupt. Note 2 : If the BOD level is set to a value higher than VDDCORE and enabled by fuses, the part will be in constant reset. In order to leave reset state, an external voltage higher than the BOD level should be applied. Thus, it is possible to disable BOD. 47 32059L–AVR32–01/2012 AT32UC3B See Electrical Characteristics for parametric details. 9.5.11.3 9.5.12 External Reset The external reset detector monitors the state of the RESET_N pin. By default, a low level on this pin will generate a reset. Calibration registers The Power Manager controls the calibration of the RC oscillator, voltage regulator, bandgap voltage reference through several calibration registers. Those calibration registers are loaded after a Power On Reset with default values stored in factory-programmed flash fuses. Although it is not recommended to override default factory settings, it is still possible to override these default values by writing to those registers. To prevent unexpected writes due to software bugs, write access to these registers is protected by a “key”. First, a write to the register must be made with the field “KEY” equal to 0x55 then a second write must be issued with the “KEY” field equal to 0xAA 48 32059L–AVR32–01/2012 AT32UC3B 9.6 User Interface Table 9-5. PM Register Memory Map Offset Register Register Name Access Reset 0x0000 Main Clock Control Register MCCTRL Read/Write 0x00000000 0x0004 Clock Select Register CKSEL Read/Write 0x00000000 0x0008 CPU Mask Register CPUMASK Read/Write 0x00000003 0x000C HSB Mask Register HSBMASK Read/Write 0x0000007F 0x0010 PBA Mask Register PBAMASK Read/Write 0x00007FFF 0x0014 PBB Mask Register PBBMASK Read/Write 0x0000003F 0x0020 PLL0 Control Register PLL0 Read/Write 0x00000000 0x0024 PLL1 Control Register PLL1 Read/Write 0x00000000 0x0028 Oscillator 0 Control Register OSCCTRL0 Read/Write 0x00000000 0x002C Oscillator 1 Control Register OSCCTRL1 Read/Write 0x00000000 0x0030 Oscillator 32 Control Register OSCCTRL32 Read/Write 0x00010000 0x0040 Interrupt Enable Register IER Write-Only 0x00000000 0x0044 Interrupt Disable Register IDR Write-Only 0x00000000 0x0048 Interrupt Mask Register IMR Read-Only 0x00000000 0x004C Interrupt Status Register ISR Read-Only 0x00000000 0x0050 Interrupt Clear Register ICR Write-Only 0x00000000 0x0054 Power and Oscillators Status Register POSCSR Read/Write 0x00000000 0x0060-0x070 Generic Clock Control Register GCCTRL Read/Write 0x00000000 0x00C0 RC Oscillator Calibration Register RCCR Read/Write Factory settings 0x00C4 Bandgap Calibration Register BGCR Read/Write Factory settings 0x00C8 Linear Regulator Calibration Register VREGCR Read/Write Factory settings 0x00D0 BOD Level Register BOD Read/Write BOD fuses in Flash 0x0140 Reset Cause Register RCAUSE Read-Only Latest Reset Source 0x0144 Asynchronous Wake Up Enable Register AWEN Read/Write 0x00000000 0x0200 General Purpose Low-Power Register 0 GPLP0 Read/Write 0x00000000 0x0204 General Purpose Low-Power Register 1 GPLP1 Read/Write 0x00000000 49 32059L–AVR32–01/2012 AT32UC3B 9.6.1 Name: Main Clock Control Register MCCTRL Access Type: Read/Write Offset: 0x000 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - OSC1EN OSC0EN MCSEL • OSC1EN: Oscillator 1 Enable 0: Oscillator 1 is disabled. 1: Oscillator 1 is enabled. • OSC0EN: Oscillator 0 Enable 0: Oscillator 0 is disabled. 1: Oscillator 0 is enabled. • MCSEL: Main Clock Select 0: The slow clock is the source for the main clock. 1: Oscillator 0 is the source for the main clock. 2: PLL0 is the source for the main clock. 3: Reserved. • 50 32059L–AVR32–01/2012 AT32UC3B 9.6.2 Name: Clock Select Register CKSEL Access Type: Read/Write Offset: 0x004 Reset Value: 0x00000000 31 30 29 28 27 PBBDIV - - - - 23 22 21 20 19 PBADIV - - - - 15 14 13 12 11 HSBDIV - - - - 7 6 5 4 3 CPUDIV - - - - 26 25 24 PBBSEL 18 17 16 PBASEL 10 9 8 HSBSEL 2 1 0 CPUSEL • PBBDIV, PBBSEL: PBB Division and Clock Select PBBDIV = 0: PBB clock equals main clock. PBBDIV = 1: PBB clock equals main clock divided by 2(PBBSEL+1). • PBADIV, PBASEL: PBA Division and Clock Select PBADIV = 0: PBA clock equals main clock. PBADIV = 1: PBA clock equals main clock divided by 2(PBASEL+1). • HSBDIV, HSBSEL: HSB Division and Clock Select For the AT32UC3B, HSBDIV always equals CPUDIV, and HSBSEL always equals CPUSEL, as the HSB clock is always equal to the CPU clock. • CPUDIV, CPUSEL: CPU Division and Clock Select CPUDIV = 0: CPU clock equals main clock. CPUDIV = 1: CPU clock equals main clock divided by 2(CPUSEL+1). Note that if xxxDIV is written to 0, xxxSEL should also be written to 0 to ensure correct operation. Also note that writing this register clears POSCSR:CKRDY. The register must not be re-written until CKRDY goes high. 51 32059L–AVR32–01/2012 AT32UC3B 9.6.3 Name: Clock Mask Register CPU/HSB/PBA/PBBMASK Access Type: Read/Write Offset: 0x008, 0x00C, 0x010, 0x014 Reset Value: - 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 MASK[31:24] 23 22 21 20 MASK[23:16] 15 14 13 12 MASK[15:8] 7 6 5 4 MASK[7:0] 52 32059L–AVR32–01/2012 AT32UC3B • MASK: Clock Mask If bit n is cleared, the clock for module n is stopped. If bit n is set, the clock for module n is enabled according to the current power mode. The number of implemented bits in each mask register, as well as which module clock is controlled by each bit, is shown in Table 9-6. Table 9-6. Maskable module clocks in AT32UC3B. Bit CPUMASK HSBMASK PBAMASK PBBMASK 0 - FLASHC INTC HMATRIX 1 OCD(1) PBA bridge GPIO USBB 2 - PBB bridge PDCA FLASHC 3 - USBB PM/RTC/EIC - 4 - PDCA ADC - 5 - - SPI - 6 - - TWI - 7 - - USART0 - 8 - - USART1 - 9 - - USART2 - 10 - - PWM - 11 - - SSC - 12 - - TC - 13 - - ABDAC - 14 - - - - 15 - - - - 16 SYSTIMER (COMPARE/COUNT REGISTERS CLK) - - - 31: 17 - - - - Note: 1. This bit must be one if the user wishes to debug the device with a JTAG debugger. 53 32059L–AVR32–01/2012 AT32UC3B 9.6.4 Name: PLL Control Register PLL0,1 Access Type: Read/Write Offset: 0x020, 0x024 Reset Value: 0x00000000 31 30 29 28 - - 23 22 21 20 - - - - 15 14 13 12 - - - - 7 6 5 4 - - - 27 26 25 24 18 17 16 9 8 1 0 PLLOSC PLLEN PLLCOUNT 19 PLLMUL 11 10 PLLDIV 3 PLLOPT 2 • PLLCOUNT: PLL Count Specifies the number of slow clock cycles before ISR:LOCKn will be set after PLLn has been written, or after PLLn has been automatically re-enabled after exiting a sleep mode. • PLLMUL: PLL Multiply Factor • PLLDIV: PLL Division Factor These fields determine the ratio of the ouput frequency of the internal VCO of the PLL (fVCO) to the source oscillator frequency: • fVCO = (PLLMUL+1)/(PLLDIV) * fOSC if PLLDIV > 0. • fVCO = 2 * (PLLMUL+1) * fOSC if PLLDIV = 0. If PLLOPT[1] bit is set to 0: fPLL = fVCO. If PLLOPT[1] bit is set to 1: fPLL = fVCO / 2. Note that the PLLMUL field cannot be equal to 0 or 1, or the behavior of the PLL will be undefined. PLLDIV gives also the input frequency of the PLL (fIN): if the PLLDIV field is set to 0: fIN = fOSC. if the PLLDIV field is greater than 0: fIN = fOSC / (2 * PLLDIV). • PLLOPT: PLL Option Select the operating range for the PLL. PLLOPT[0]: Select the VCO frequency range. PLLOPT[1]: Enable the extra output divider. PLLOPT[2]: Disable the Wide-Bandwidth mode (Wide-Bandwidth mode allows a faster startup time and out-of-lock time). • 54 32059L–AVR32–01/2012 AT32UC3B • Table 9-7. PLLOPT Fields Description in AT32UC3B Description PLLOPT[0]: VCO frequency 0 160MHz