Features
• Permanent and reversible software write protection for the first-half of the array
– Software procedure to verify write protect status
• Hardware write protection for the entire array
• Low-voltage and standard-voltage operation
•
•
•
•
•
•
•
•
•
•
•
– 1.7 (VCC = 1.7V to 5.5V)
Internally organized 256 x 8
Two-wire serial interface
Schmitt trigger, filtered inputs for noise suppression
Bidirectional data transfer protocol
100kHz (1.7V) and 400kHz (2.7V and 5.0V) compatibility
16-byte page write modes
Partial page writes are allowed
Self-timed write cycle (5ms max)
High-reliability
– Endurance: 1 million write cycles
– Data retention: 100 years
8-lead JEDEC SOIC, 8-lead UDFN, 8-lead TSSOP, and 8-ball VFBGA packages
Die sales: wafer form, tape and reel, and bumped wafers
2K (256 x 8)
Description
The Atmel® AT34C02C provides 2048 bits of serial electrically-erasable and programmable
read only memory (EEPROM) organized as 256 words of eight bits each. The first-half of
the device incorporates a permanent and a reversible software write protection feature
while hardware write protection for the entire array is available via an external pin. Once the
permanent software write protection is enabled, by sending a special command to the
device, it cannot be reversed. However, the reversible software write protection is enabled
and can be reversed by sending a special command. The hardware write protection is controlled with the WP pin and can be used to protect the entire array, whether or not the
software write protection has been enabled. This allows the user to protect none, first-half,
or all of the array depending on the application. The device is optimized for use in many
industrial and commercial applications where low-power and low-voltage operations are
essential. The AT34C02C is available in space saving 8-lead JEDEC SOIC, 8-lead UDFN,
8-lead TSSOP, and 8-ball VFBGA packages and is accessed via a Two-wire serial interface. It
is available in 1.7V (1.7V to 5.5V).
8-ball dBGA2
8-lead TSSOP
1
2
3
4
A0
A1
A2
GND
8
7
6
5
8-lead SOIC
A0
A1
A2
GND
1
2
3
4
Two-wire Serial
Electrically-erasable
and Programmable
Read Only Memory
with Permanent
and Reversible
Software Write
Protect
8
7
6
5
VCC
WP
SCL
SDA
VCC
WP
SCL
SDA
8
1
7
2
6
3
5
4
A0
A1
A2
GND
Bottom View
VCC
WP
SCL
SDA
Atmel AT34C02C
Not Recommended for
New Design
Replaced by AT34C02D
8-lead UDFN
VCC
WP
SCL
SDA
8
7
6
5
1
2
3
4
A0
A1
A2
GND
Bottom View
5185F–SEEPROM–102014
Table 0-1.
1.
Pin Configurations
Pin Name
Function
A0 - A2
Address inputs
SDA
Serial data
SCL
Serial clock input
WP
Write protect
Absolute Maximum Ratings*
*NOTICE:
Operating temperature . . . . . . . . . . . . . . –55°C to +125°C
Storage temperature . . . . . . . . . . . . . . . . –65 °C to +150°C
Voltage on any pin
with respect to ground . . . . . . . . . . . . . . . . .–1.0V to +7.0V
Maximum operating voltage . . . . . . . . . . . . . . . . . . . . 6.25V
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these
or any other conditions beyond those indicated
in the operational sections of this specification
is not implied. Exposure to absolute maximum
rating conditions for extended periods may
affect device reliability.
DC output current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.0mA
Figure 1-1.
Block Diagram
VCC
GND
WP
START
STOP
LOGIC
SCL
SDA
SERIAL
CONTROL
LOGIC
WRITE PROTECT
CIRCUITRY
EN
H.V. PUMP/TIMING
LOAD
A2
A1
A0
R/W
COMP
LOAD
DATA WORD
ADDR/COUNTER
DATA RECOVERY
SOFTWARE WRITE
PROTECTED AREA
(00H - 7FH)
INC
X DEC
DEVICE
ADDRESS
COMPARATOR
EEPROM
Y DEC
DIN
SERIAL MUX
DOUT/ACK
LOGIC
DOUT
2
AT34C02C
5185F–SEEPROM–102014
AT34C02C
2.
Pin Description
SERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into each EEPROM device and negative edge
clock data out of each device.
SERIAL DATA (SDA): The SDA pin is bidirectional for serial data transfer. This pin is open-drain driven and may be wireORed with any number of other open-drain or open collector devices.
DEVICE/PAGE ADDRESSES (A2, A1, A0): The A2, A1, and A0 pins are device address inputs that are hardwired
(directly to GND or to Vcc) for compatibility with other Atmel AT24Cxx devices. When the pins are hardwired, as many as
eight 2K devices may be addressed on a single bus system. (Device addressing is discussed in detail under “Device
Addressing,” page 9.) A device is selected when a corresponding hardware and software match is true. If these pins are
left floating, the A2, A1, and A0 pins will be internally pulled down to GND. However, due to capacitive coupling that may
appear during customer applications, Atmel recommends always connecting the address pins to a known state. When
using a pull-up resistor, Atmel recommends using 10k or less.
WRITE PROTECT (WP): The write protect input, when connected to GND, allows normal write operations. When WP is
connected directly to Vcc, all write operations to the memory are inhibited. If the pin is left floating, the WP pin will be
internally pulled down to GND. However, due to capacitive coupling that may appear during customer applications, Atmel
recommends always connecting the WP pins to a known state. When using a pull-up resistor, Atmel recommends using
10k or less.
Table 2-1.
AT34C02C Write Protection Modes
WP pin status
Permanent write protect
register
Reversible write protect
register
Part of the array write protected
VCC
–
–
Full array (2K)
GND or floating
Not programmed
Not programmed
Normal read/write
GND or floating
Programmed
–
First-half of array
(1K: 00H - 7FH)
GND or floating
–
Programmed
First-half of array
(1K: 00H - 7FH)
Table 2-2.
Pin Capacitance(1)
Applicable over recommended operating range from TA = 25C, f = 100 kHz, VCC = +1.7V
Symbol
Test condition
CI/O
CIN
Note:
Max
Units
Conditions
Input/output capacitance (SDA)
8
pF
VI/O = 0V
Input capacitance (A0, A1, A2, SCL)
6
pF
VIN = 0V
1. This parameter is characterized and is not 100% tested
3
5185F–SEEPROM–102014
Table 2-3.
DC Characteristics
Applicable over recommended operating range from: TAI = –40°C to +85°C, VCC = +1.7V to +5.5V, (unless otherwise noted)
Symbol
Parameter
Test Condition
VCC
Supply voltage
ICC
Supply current VCC = 5.0V
READ at 100kHz
ICC
Supply current VCC = 5.0V
ISB1
Max
Units
5.5
V
0.4
1.0
mA
WRITE at 100kHz
2.0
3.0
mA
Standby current VCC = 1.7V
VIN = VCC or VSS
0.6
3.0
µA
ISB2
Standby current VCC = 3.6V
VIN = VCC or VSS
1.6
4.0
µA
ISB3
Standby current VCC = 5.5V
VIN = VCC or VSS
8.0
18.0
µA
ILI
Input leakage current
VIN = VCC or VSS
0.10
3.0
µA
ILO
Output leakage current
Typ
VOUT = VCC or VSS
0.05
3.0
µA
–0.6
VCC x 0.3
V
VCC x 0.7
VCC + 0.5
V
1.7
(1)
Input low level
VIL
Min
(1)
VIH
Input high level
VOL2
Output low level VCC = 3.0V
IOL = 2.1mA
0.4
V
VOL1
Output low level VCC = 1.7V
IOL = 0.15mA
0.2
V
Note:
1. VIL min and VIH max are reference only and are not tested
Table 2-4.
AC Characteristics
Applicable over recommended operating range from TAI = –40C to +85C, VCC = +1.7V to +5.5V, CL = 1 TTL Gate and
100pF (unless otherwise noted)
1.7V
Symbol
Parameter
Min
fSCL
Clock frequency, SCL
tLOW
Clock pulse width low
tHIGH
Clock pulse width high
2.7V, 5.0V
Max
Min
100
Max
Units
400
kHz
4.7
1.2
µs
4.0
0.6
µs
(1)
tI
Noise suppression time
100
tAA
Clock low to data out valid
0.1
tBUF
Time the bus must be free before a new
transmission can start(1)
4.7
1.2
µs
tHD.STA
Start hold time
4.0
0.6
µs
tSU.STA
Start set-up time
4.7
0.6
µs
tHD.DAT
Data in hold time
0
0
µs
tSU.DAT
Data In set-up time
200
100
ns
(1)
Inputs rise time
tR
(1)
4.5
0.1
50
ns
0.9
µs
1.0
0.3
µs
300
300
ns
tF
Inputs fall time
tSU.STO
Stop set-up time
4.7
0.6
µs
tDH
Data out hold time
100
50
ns
tWR
Write cycle time
Endurance(1)
25C, page mode
Note:
4
5
1M
5
1M
ms
Write
cycles
1. This parameter is characterized and is not 100% tested.
AT34C02C
5185F–SEEPROM–102014
AT34C02C
3.
Memory Organization
Atmel AT34C02C, 2K Serial EEPROM: The 2K is internally organized with 16 pages of 16 bytes each. Random word
addressing requires a 8-bit data word address.
4.
Device Operation
CLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an external device. Data on the SDA pin may
change only during SCL low time periods (see Figure 4-3 on page 6). Data changes during SCL high periods will indicate
a start or stop condition as defined below.
START CONDITION: A high-to-low transition of SDA with SCL high is a start condition which must precede any
other command (see Figure 4-4 on page 6).
STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition. After a read sequence, the stop
command will place the EEPROM in a standby power mode (see Figure 4-4 on page 6).
ACKNOWLEDGE: All addresses and data words are serially transmitted to and from the EEPROM in 8-bit words. The
EEPROM sends a zero to acknowledge that it has received each word. This happens during the ninth clock cycle.
STANDBY MODE: The Atmel AT34C02C features a low-power standby mode which is enabled:
• Upon power-up or
• After the receipt of the STOP bit and the completion of any internal operations
MEMORY RESET: After an interruption in protocol, power loss or system reset, any Two-wire part can be reset by
following these steps:
• Clock up to nine cycles,
• Look for SDA high in each cycle while SCL is high, and then
• Create a Start condition.
Figure 4-1.
Bus Timing SCL: Serial Clock SDA: Serial Data I/O
tHIGH
tF
tR
tLOW
SCL
tSU.STA
tHD.STA
tHD.DAT
tSU.DAT
tSU.STO
SDA In
tAA
tDH
tBUF
SDA Out
5
5185F–SEEPROM–102014
Figure 4-2.
Write cycle Timing SCL: Serial Clock SDA: Serial Data I/O
SCL
8th bit
SDA
AC
WORDn
twr(1)
Start
Condition
Stop
Condition
Note:
1. The write cycle time tWR is the time from a valid stop condition of a write sequence to the end of the internal clear/write
cycle.
Figure 4-3.
Data Validity
SDA
SCL
Data Stable
Data Stable
Data
Change
Figure 4-4.
Start and Stop Condition
SDA
SCL
Start
6
Stop
AT34C02C
5185F–SEEPROM–102014
AT34C02C
Figure 4-5.
Output Acknowledge
1
SCL
8
9
Data In
Data Out
Start
5.
Acknowledge
Device Addressing
The 2K EEPROM device requires an 8-bit device address word following a start condition to enable the chip for a read or
write operation (see Figure 8-1 on page 12).
The device address word consists of a mandatory one-zero sequence for the first four most-significant bits (1010) for
normal read and write operations and 0110 for writing to the write protect register.
The next three bits are the A2, A1, and A0 device address bits for the Atmel AT34C02C EEPROM. These three bits must
compare to their corresponding hard-wired input pins.
The eighth bit of the device address is the read/write operation select bit. A read operation is initiated if this bit is high and
a write operation is initiated if this bit is low.
Upon a compare of the device address, the EEPROM will output a zero. If a compare is not made, the chip will return to a
standby state. The device will not acknowledge if the write protect register has been programmed and the control code is
0110.
6.
Write Operations
BYTE WRITE: A write operation requires an 8-bit data word address following the device address word and
acknowledgment. Upon receipt of this address, the EEPROM will again respond with a zero and then clock in the first 8-bit
data word. Following receipt of the 8-bit data word, the EEPROM will output a zero and the addressing device, such as a
microcontroller, must terminate the write sequence with a stop condition. At this time the EEPROM enters an internallytimed write cycle, tWR, to the nonvolatile memory. All inputs are disabled during this write cycle and the EEPROM will not
respond until the write is complete (see Figure 8-2 on page 12).
The device will acknowledge a write command, but not write the data, if the software or hardware write protection has
been enabled. The write cycle time must be observed even when the write protection is enabled.
PAGE WRITE: The 2K device is capable of 16-byte page write.
A page write is initiated the same as a byte write, but the microcontroller does not send a stop condition after the first data
word is clocked in. Instead, after the EEPROM acknowledges receipt of the first data word, the microcontroller can transmit
up to fifteen more data words. The EEPROM will respond with a zero after each data word received. The microcontroller
must terminate the page write sequence with a stop condition (see Figure 8-3 on page 12).
7
5185F–SEEPROM–102014
The data word address lower four bits are internally incremented following the receipt of each data word. The higher data
word address bits are not incremented, retaining the memory page row location. When the word address, internally
generated, reaches the page boundary, the following byte is placed at the beginning of the same page. If more than
sixteen data words are transmitted to the EEPROM, the data word address will “roll over” and previous data will be
overwritten. The address “roll over” during write is from the last byte of the current page to the first byte of the same
page.
The device will acknowledge a write command, but not write the data, if the software or hardware write protection has
been enabled. The write cycle time must be observed even when the write protection is enabled.
ACKNOWLEDGE POLLING: Once the internally-timed write cycle has started and the EEPROM inputs are disabled,
acknowledge polling can be initiated. This involves sending a start condition followed by the device address word. The
read/write bit is representative of the operation desired. Only if the internal write cycle has completed will the EEPROM
respond with a zero allowing the read or write sequence to continue.
7.
Write Protection
The software write protection, once enabled, write protects only the first-half of the array (00H - 7FH) while the hardware
write protection, via the WP pin, is used to protect the entire array.
PERMANENT SOFTWARE WRITE PROTECTION: The software write protection is enabled by sending a command,
similar to a normal write command, to the device which programs the permanent write protect register. This must be done
with the WP pin low. The write protect register is programmed by sending a write command with the device address of
0110 instead of 1010 with the address and data bit being don’t cares (see Figure 7-1 on page 8). Once the software
write protection has been enabled, the device will no longer acknowledge the 0110 control byte. The software write
protection cannot be reversed even if the device is powered down. The write cycle time must be observed.
REVERSIBLE SOFTWARE WRITE PROTECTION: The reversible software write protection is enabled by sending a
command, similar to a normal write command, to the device which programs the reversible write protect register. This
must be done with the WP pin low. The write protect register is programmed by sending a write command 01100010
with pins A2 and A1 tied to ground or don't connect and pin A0 connected to VHV (see Figure 7-2). The reversible write
protection can be reversed by sending a command 01100110 with pin A2 tied to ground or no connect, pin A1 tied to VCC
and pin A0 tied to VHV (see Figure 7-3).
HARDWARE WRITE PROTECTION: The WP pin can be connected to VCC, GND, or left floating. Connecting the WP pin to
VCC will write protect the entire array, regardless of whether or not the software write protection has been enabled. The
software write protection register cannot be programmed when the WP pin is connected to VCC. If the WP pin is connected
to GND or left floating, the write protection mode is determined by the status of the software write protect register.
Figure 7-1.
Setting Permanent Write Protect Register (PSWP)
S
T
A
R
T
SDA LINE
CONTROL
BYTE
WORD
ADDRESS
S
T
O
P
DATA
0 1 1 0 A2 A1 A0 0
A
C
K
A
C
K
A
C
K
= Don't Care
8
AT34C02C
5185F–SEEPROM–102014
AT34C02C
Figure 7-2.
Setting Reversible Write Protect Register (RSWP)
S
T
A
R
T
SDA LINE
CONTROL
BYTE
WORD
ADDRESS
S
T
O
P
DATA
0 1 1 0 0 0 1 0
A
C
K
A
C
K
A
C
K
= Don't Care
Figure 7-3.
Clearing Reversible Write Protect Register (RSWP)
S
T
A
R
T
SDA LINE
CONTROL
BYTE
WORD
ADDRESS
S
T
O
P
DATA
0 1 1 0 0 1 1 0
A
C
K
A
C
K
A
C
K
= Don't Care
Table 7-1.
Write Protection
Pin
Preamble
RW
Command
A2
A1
A0
B7
B6
B5
B4
B3
B2
B1
B0
Set PSWP
A2
A1
A0
0
1
1
0
A2
A1
A0
0
Set RSWP
0
0
VHV
0
1
1
0
0
0
1
0
Clear RSWP
0
1
VHV
0
1
1
0
0
1
1
0
Table 7-2.
VHV
VHV
Note:
Min
Max
Units
7
10
V
VHV - VCC > 4.8V
9
5185F–SEEPROM–102014
Table 7-3.
WP Connected to GND or Floating
WP Connected to GND or Floating
10
Command
R/W bit
Permanent write
protect register
PSWP
Reversible write
protect register
RSWP
Acknowledgment
from device
1010
R
X
X
ACK
1010
W
Programmed
X
ACK
Can write to second Half (80H - FFH) only
1010
W
X
Programmed
ACK
Can write to second Half (80H - FFH) only
1010
W
Not programmed
Not programmed
ACK
Can write to full array
Read PSWP
R
Programmed
X
No ACK
Read PSWP
R
Not programmed
X
ACK
Set PSWP
W
Programmed
X
No ACK
Set PSWP
W
Not programmed
X
ACK
Read RSWP
R
X
Programmed
No ACK
Read RSWP
R
X
Not programmed
ACK
Set RSWP
W
X
Programmed
No ACK
Set RSWP
W
X
Not programmed
ACK
Program reversible write protect register (reversible)
Clear RSWP
W
Programmed
X
No ACK
STOP - Indicates permanent write protect register is
programmed
Clear RSWP
W
Not programmed
X
ACK
Clear (unprogram) reversible write protect register
(reversible)
Action from device
STOP - Indicates permanent write protect register is
programmed
Read out data don't care. Indicates PSWP register is not
programmed
STOP - Indicates permanent write protect register is
programmed
Program permanent write protect register
(irreversible)
STOP - Indicates reversible write protect register is
programmed
Read out data don't care. Indicates RSWP register is not
programmed
STOP - Indicates reversible write protect register is
programmed
AT34C02C
5185F–SEEPROM–102014
AT34C02C
Table 7-4.
WP connected to Vcc
WP Connected to Vcc
Command
R/W bit
Permanent write
protect register
PSWP
1010
R
X
X
ACK
Read array
1010
W
X
X
ACK
Device write protect
Read PSWP
R
Programmed
X
No ACK
Read PSWP
R
Not programmed
X
ACK
Set PSWP
W
Programmed
X
No ACK
Set PSWP
W
Not programmed
X
ACK
Read RSWP
R
X
Programmed
No ACK
Read RSWP
R
X
Not programmed
ACK
Set RSWP
W
X
Programmed
No ACK
Set RSWP
W
X
Not programmed
ACK
Clear RSWP
W
Programmed
X
No ACK
Clear RSWP
W
Not programmed
X
ACK
8.
Reversible write
protect register
RSWP
Acknowledgment
from device
Action from device
STOP - Indicates permanent write protect register is
programmed
Read out data don't care. Indicates PSWP register is not
programmed
STOP - Indicates permanent write protect register is
programmed
Cannot program write protect registers
STOP - Indicates reversible write protect register is
programmed
Read out data don't care. Indicates RSWP register is not
programmed
STOP - Indicates reversible write protect register is
programmed
Cannot program write protect registers
STOP - Indicates permanent write protect register is
programmed
Cannot write to write protect registers
Read Operations
Read operations are initiated the same way as write operations with the exception that the read/write select bit in the
device address word is set to one. There are three read operations:
• Current address read
• Random address read
• Sequential read.
CURRENT ADDRESS READ: The internal data word address counter maintains the last address accessed during the last
read or write operation, incremented by one. This address stays valid between operations as long as the chip power is
maintained. The address “roll over” during read is from the last byte of the last memory page to the first byte of the first
page.
Once the device address with the read/write select bit set to one is clocked in and acknowledged by the EEPROM, the
current address data word is serially clocked out. To end the command, the microcontroller does not respond with an input
zero but does generate a following stop condition (see Figure 8-4 on page 13).
RANDOM READ: A random read requires a “dummy” byte write sequence to load in the data word address. Once the
device address word and data word address are clocked in and acknowledged by the EEPROM, the microcontroller must
generate another start condition. The microcontroller now initiates a current address read by sending a device address with
the read/write select bit high. The EEPROM acknowledges the device address and serially clocks out the data word. To end
the command, the microcontroller does not respond with a zero but does generate a following stop condition (see Figure
8-5 on page 13).
11
5185F–SEEPROM–102014
SEQUENTIAL READ: Sequential reads are initiated by either a current address read or a random address read. After the
microcontroller receives a data word, it responds with an acknowledge. As long as the EEPROM receives an acknowledge,
it will continue to increment the data word address and serially clock out sequential data words. When the memory
address limit is reached, the data word address will “roll over” and the sequential read will continue. The sequential read
operation is terminated when the microcontroller does not respond with a zero but does generate a following stop
condition (see Figure 8-6 on page 13).
PERMANENT WRITE PROTECT REGISTER (PSWP) STATUS: To find out if the register has been programmed, the
same procedure is used as to program the register except that the R/W bit is set to one. If the device sends an
acknowledge, then the permanent write protect register has not been programmed. Otherwise, it has been
programmed and the device is permanently write protected at the first half of the array.
Table 8-1.
PSWP Status
Pin
Preamble
RW
Command
A2
A1
A0
B7
B6
B5
B4
B3
B2
B1
B0
Read PSWP
A2
A1
A0
0
1
1
0
A2
A1
A0
1
REVERSIBLE WRITE PROTECT REGISTER(RSWP) STATUS: To find out if the register has been programmed, the
same procedure is used as to program the register except that the R/W bit is set to one. If the sends an device
acknowledge, then the reversible write protect register has not been programmed. Otherwise, it has been programmed
and the device is write protected (reversible) at the first half of the array.
12
Figure 8-1.
Device Address
Figure 8-2.
Byte Write
Figure 8-3.
Page Write
AT34C02C
5185F–SEEPROM–102014
AT34C02C
Figure 8-4.
Current Address Read
Figure 8-5.
Random Read
Figure 8-6.
Sequential Read
13
5185F–SEEPROM–102014
9.
Atmel AT34C02C Ordering Information
Atmel Ordering Code
Lead Finish
Package
Voltage
Operation Range
1.7V to 5.5V
Industrial Temperature
(-40C to 85C)
(1)
AT34C02CN-SH-B
8S1
AT34C02CN-SH-T(2)
AT34C02C-TH-B(1)
NiPdAu
(Lead-free/Halogen-free)
AT34C02C-TH-T(2)
AT34C02CY6-YH-T(2)
8MA2
AT34C02CY6-YH-E(3)
AT34C02CU3-UU-T(2)
Notes:
8X
—
8U3-1
1. -B = Bulk
SOIC and TSSOP = 100 units per tube.
2. -T = Tape and Reel, Standard Quantity Option:
SOIC = 4,000 per reel.
TSSOP, UDFN, and VFBGA = 5,000 per reel.
3. -E = Tape and Reel, Expanded Quantity Option:
UDFN = 15,000 units per reel.
Package type
8S1
14
8-lead, 0.150" wide, Plastic Gull Wing Small Outline (JEDEC SOIC)
8X
8-lead, 4.40mm body, Plastic Thin Shrink Small Outline Package (TSSOP)
8MA2
8-pad, 2.00mm x 3.00mm body, 0.50mm Pitch, Ultra Thin Dual Flat No Lead (UDFN)
8U3-1
8-ball, 1.50mm x 2.00mm body, 0.5mm pitch, Very thin Fine Ball Grid Array (VFBGA)
AT34C02C
5185F–SEEPROM–102014
AT34C02C
10.
Part Markings
8 lead TSSOP
2 Rows/Top & Bottom
4/5 Top-7/7 Bottom Characters
8 lead SOIC
3 Rows of 8 Characters
HYWW
34C 1
Top
ATMLHYWW
34C1
AAAAAAAA
LOA
AAAAAAA
Bottom
8 lead UDFN - 2.0x3.0mm
3 Rows of 3 Characters
8-ball VFBGA - 1.5x2.0mm
34C
H1@
YXX
2 Rows of 4 Characters
34CU
YMXX
PIN 1
PIN 1
Catalog Truncation: 34C
Catalog Number: AT34C02C
Date Codes
Y = Year
0: 2010
1: 2011
2: 2012
3: 2013
4:
5:
6:
7:
Voltages
2014
2015
2016
2017
M = Month
A: January
B: February
“
”
“
L: December
WW
02:
04:
”
52:
= Work Week of Assembly
Week 2
Week 4
“ ”
Week 52
Trace Code
XX = Trace Code (ATMEL Lot Numbers to Correspond to Code)
(e.g. XX:
AA, AB...YZ, ZZ)
1:
1.7v min
Grade/Lead Finish Material
U: Industrial/Matt Tin
H: Industrial/NiPdAu
Lot Number
AAAAAAA = ATMEL Wafer Lot Number
Location of Assembly
@ = Location of Assembly
ATMEL Truncation
AT: ATMEL
ATM: ATMEL
ATML: ATMEL
3/17/11
Package Drawing Contact:
packagedrawings@atmel.com
TITLE
34C02CSM, AT34C02C Standard Marking Information
for Package Offering
DRAWING NO.
34C02CSM
REV.
A
15
5185F–SEEPROM–102014
11.
Packaging Information
8S1 — 8-lead JEDEC SOIC
C
1
E
E1
L
N
Ø
TOP VIEW
END VIEW
e
b
COMMON DIMENSIONS
(Unit of Measure = mm)
A
A1
D
SIDE VIEW
Notes: This drawing is for general information only.
Refer to JEDEC Drawing MS-012, Variation AA
for proper dimensions, tolerances, datums, etc.
SYMBOL MIN
A
1.35
NOM
MAX
–
1.75
A1
0.10
–
0.25
b
0.31
–
0.51
C
0.17
–
0.25
D
4.80
–
5.05
E1
3.81
–
3.99
E
5.79
–
6.20
e
NOTE
1.27 BSC
L
0.40
–
1.27
Ø
0°
–
8°
6/22/11
Package Drawing Contact:
packagedrawings@atmel.com
16
TITLE
8S1, 8-lead (0.150” Wide Body), Plastic Gull Wing
Small Outline (JEDEC SOIC)
GPC
SWB
DRAWING NO.
REV.
8S1
G
AT34C02C
5185F–SEEPROM–102014
AT34C02C
8X — 8-lead TSSOP
C
1
Pin 1 indicator
this corner
E1
E
L1
N
L
Top View
End View
A
b
A1
e
D
SYMBOL
Side View
Notes:
COMMON DIMENSIONS
(Unit of Measure = mm)
A2
1. This drawing is for general information only.
Refer to JEDEC Drawing MO-153, Variation AA, for proper
dimensions, tolerances, datums, etc.
2. Dimension D does not include mold Flash, protrusions or gate
burrs. Mold Flash, protrusions and gate burrs shall not exceed
0.15mm (0.006in) per side.
3. Dimension E1 does not include inter-lead Flash or protrusions.
Inter-lead Flash and protrusions shall not exceed 0.25mm
(0.010in) per side.
4. Dimension b does not include Dambar protrusion.
Allowable Dambar protrusion shall be 0.08mm total in excess
of the b dimension at maximum material condition. Dambar
cannot be located on the lower radius of the foot. Minimum
space between protrusion and adjacent lead is 0.07mm.
5. Dimension D and E1 to be determined at Datum Plane H.
MIN
NOM
MAX
A
-
-
1.20
A1
0.05
-
0.15
NOTE
A2
0.80
1.00
1.05
D
2.90
3.00
3.10
2, 5
E
6.40 BSC
E1
4.30
4.40
4.50
3, 5
b
0.19
0.25
0.30
4
e
L
0.65 BSC
0.45
L1
C
0.60
0.75
1.00 REF
0.09
-
0.20
2/27/14
TITLE
Package Drawing Contact:
packagedrawings@atmel.com
8X, 8-lead 4.4mm Body, Plastic Thin
Shrink Small Outline Package (TSSOP)
GPC
TNR
DRAWING NO.
8X
REV.
E
17
5185F–SEEPROM–102014
8MA2 — 8-pad UDFN
E
1
8
Pin 1 ID
2
7
3
6
4
5
D
C
TOP VIEW
A2
SIDE VIEW
A
A1
E2
b (8x)
8
1
7
D2
6
3
5
4
e (6x)
K
L (8x)
BOTTOM VIEW
Notes:
COMMON DIMENSIONS
(Unit of Measure = mm)
2
Pin#1 ID
1. This drawing is for general information only. Refer to
Drawing MO-229, for proper dimensions, tolerances,
datums, etc.
2. The Pin #1 ID is a laser-marked feature on Top View.
3. Dimensions b applies to metallized terminal and is
measured between 0.15 mm and 0.30 mm from the
terminal tip. If the terminal has the optional radius on
the other end of the terminal, the dimension should
not be measured in that radius area.
4. The Pin #1 ID on the Bottom View is an orientation
feature on the thermal pad.
SYMBOL
MIN
NOM
MAX
A
0.50
0.55
0.60
A1
0.0
0.02
0.05
A2
-
-
0.55
D
1.90
2.00
2.10
D2
1.20
-
1.60
E
2.90
3.00
3.10
E2
1.20
-
1.60
b
0.18
0.25
0.30
C
L
3
1.52 REF
0.30
e
K
NOTE
0.35
0.40
0.50 BSC
0.20
-
-
6/6/14
Package Drawing Contact:
packagedrawings@atmel.com
18
TITLE
8MA2, 8-pad 2 x 3 x 0.6mm Body, Thermally
Enhanced Plastic Ultra Thin Dual Flat No-Lead
Package (UDFN)
GPC
DRAWING NO.
REV.
YNZ
8MA2
F
AT34C02C
5185F–SEEPROM–102014
AT34C02C
8U3-1 — 8-ball VFBGA
E
D
2. b
PIN 1 BALL PAD CORNER
A1
A2
TOP VIEW
A
SIDE VIEW
PIN 1 BALL PAD CORNER
3
1
2
4
d
(d1)
8
7
6
5
COMMON DIMENSIONS
(Unit of Measure - mm)
e
(e1)
SYMBOL
MIN
NOM
MAX
BOTTOM VIEW
A
0.73
0.79
0.85
8 SOLDER BALLS
A1
0.09
0.14
0.19
A2
0.40
0.45
0.50
Notes:
b
0.20
0.25
0.30
1. This drawing is for general information only.
D
2. Dimension ‘b’ is measured at maximum solder ball diameter.
3. Solder ball composition shall be 95.5Sn-4.0Ag-.5Cu.
NOTE
2
1.50 BSC
E
2.0 BSC
e
0.50 BSC
e1
0.25 REF
d
1.00 BSC
d1
0.25 REF
6/11/13
Package Drawing Contact:
packagedrawings@atmel.com
TITLE
GPC
DRAWING NO.
8U3-1, 8-ball, 1.50mm x 2.00mm body, 0.50mm pitch,
Very Thin, Fine-Pitch Ball Grid Array Package (VFBGA)
GXU
8U3-1
REV.
F
19
5185F–SEEPROM–102014
12.
20
Revision history
Doc. Rev.
Date
Comments
5185F
10/2014
Updated package drawings to newer versions: 8A2 to 8X, 8Y6 to 8MA2-UDFN, and 8U3-1 dBGA2 to
VFBGA.
Updated the Atmel logos and disclaimer page.
5185E
09/2013
Not recommended for new design. Replaced by AT34C02D.
5185E
03/2011
Replaced part markings to single page part markings
Updated template
5185D
01/2008
Removed ‘preliminary’ status
5185C
08/2007
Updated to new template
Added package marking tables
5185B
03/2007
Implemented revision history
AT34C02C
5185F–SEEPROM–102014
XXXXXX
Atmel Corporation
1600 Technology Drive, San Jose, CA 95110 USA
T: (+1)(408) 441.0311
F: (+1)(408) 436.4200
|
www.atmel.com
© 2014 Atmel Corporation. / Rev.: Atmel-8827E-SEEPROM-AT34C04-Datasheet_102014.
Atmel®, Atmel logo and combinations thereof, Enabling Unlimited Possibilities®, and others are registered trademarks or trademarks of Atmel Corporation in U.S. and
other countries. Other terms and product names may be trademarks of others.
DISCLAIMER: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right
is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN THE ATMEL TERMS AND CONDITIONS OF SALES LOCATED ON THE
ATMEL WEBSITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS
INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT
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FOR LOSS AND PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS
BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this
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