Features
•
•
•
•
•
•
•
•
•
•
•
Single Supply for Read and Write: 2.7 to 3.6V
Fast Read Access Time – 70 ns
Internal Program Control and Timer
Sector Architecture
– One 16K Bytes Boot Block with Programming Lockout
– Two 8K Bytes Parameter Blocks
– Eight Main Memory Blocks (One 32K Bytes, Seven 64K Bytes)
Fast Erase Cycle Time – 7 Seconds
Byte-by-Byte Programming – 30 µs/Byte Typical
Hardware Data Protection
DATA Polling for End of Program Detection
Low Power Dissipation
– 15 mA Active Current
– 50 µA CMOS Standby Current
Typical 10,000 Write Cycles
Green (Pb/Halide-free) Packaging Option
1. Description
The AT49BV040A is a 2.7-volt-only in-system reprogrammable Flash Memory. Its
4 megabits of memory is organized as 524,288 words by 8 bits. Manufactured with
Atmel’s advanced nonvolatile CMOS technology, the device offers access times to
70 ns with power dissipation of just 54 mW over the commercial temperature range.
When the device is deselected, the CMOS standby current is less than 50 µA. To
allow for simple in-system reprogrammability, the AT49BV040A does not require high
input voltages for programming. Three-volt-only commands determine the read and
programming operation of the device. Reading data out of the device is similar to
reading from an EPROM; it has standard CE, OE, and WE inputs to avoid bus contention. Reprogramming the AT49BV040A is performed by erasing a block of data and
then programming on a byte by byte basis. The byte programming time is a fast 30 µs.
The end of a program cycle can be optionally detected by the DATA polling feature.
Once the end of a byte program cycle has been detected, a new access for a read or
program can begin. The typical number of program and erase cycles is in excess of
10,000 cycles.
4-megabit
(512K x 8)
Single 2.7-volt
Battery-Voltage
Flash Memory
AT49BV040A
Not Recommended
for New Design
Contact Atmel to discuss
the latest design in trends
and options
The device is erased by executing the erase command sequence; the device internally controls the erase operations. There are two 8K byte parameter block sections,
eight main memory blocks, and one boot block.
The device has the capability to protect the data in the boot block; this feature is
enabled by a command sequence. The 16K-byte boot block section includes a reprogramming lock out feature to provide data integrity. The boot sector is designed to
contain user secure code, and when the feature is enabled, the boot sector is permanently protected from being reprogrammed.
3358C–FLASH–3/05
2. Pin Configurations
Function
A0 - A18
Addresses
CE
Chip Enable
OE
Output Enable
WE
Write Enable
I/O0 - I/O7
Data Inputs/Outputs
32-lead PLCC Top View
29
28
27
26
25
24
23
22
21
14
15
16
17
18
19
20
5
6
7
8
9
10
11
12
13
A14
A13
A8
A9
A11
OE
A10
CE
I/O7
I/O1
I/O2
GND
I/O3
I/O4
I/O5
I/O6
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
4
3
2
1
32
31
30
A12
A15
A16
A18
VCC
WE
A17
2.1
Pin Name
2.2
32-lead VSOP (8 x 14 mm) or 32-lead TSOP, Type 1 (8 x 20 mm) – Top View
A11
A9
A8
A13
A14
A17
WE
VCC
A18
A16
A15
A12
A7
A6
A5
A4
2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
A1
A2
A3
AT49BV040A
3358C–FLASH–3/05
AT49BV040A
3. Block Diagram
AT49BV040A
DATA INPUTS/OUTPUTS
I/O7 - I/O0
VCC
GND
OE
WE
CE
RESET
ADDRESS
INPUTS
8
CONTROL
LOGIC
INPUT/OUTPUT
BUFFERS
PROGRAM
DATA LATCHES
Y DECODER
Y-GATING
X DECODER
MAIN MEMORY
BLOCK 8
(64K BYTES)
MAIN MEMORY
BLOCK 7
(64K BYTES)
MAIN MEMORY
BLOCK 6
(64K BYTES)
MAIN MEMORY
BLOCK 5
(64K BYTES)
MAIN MEMORY
BLOCK 4
(64K BYTES)
MAIN MEMORY
BLOCK 3
(64K BYTES)
MAIN MEMORY
BLOCK 2
(64K BYTES)
MAIN MEMORY
BLOCK 1
(32K BYTES)
PARAMETER
BLOCK 2
(8K BYTES)
PARAMETER
BLOCK 1
(8K BYTES)
BOOT BLOCK
(16K BYTES)
7FFFF
70000
6FFFF
60000
5FFFF
50000
4FFFF
40000
3FFFF
30000
2FFFF
20000
1FFFF
10000
0FFFF
08000
07FFF
06000
05FFF
04000
03FFF
00000
4. Device Operation
4.1
Read
The AT49BV040A is accessed like an EPROM. When CE and OE are low and WE is high, the
data stored at the memory location determined by the address pins is asserted on the outputs.
The outputs are put in the high impedance state whenever CE or OE is high. This dual-line control gives designers flexibility in preventing bus contention.
3
3358C–FLASH–3/05
4.2
Command Sequences
When the device is first powered on it will be reset to the read or standby mode depending upon
the state of the control line inputs. In order to perform other device functions, a series of command sequences are entered into the device. The command sequences are shown in the
“Command Definition Table” on page 6. The command sequences are written by applying a low
pulse on the WE or CE input with CE or WE low (respectively) and OE high. The address is
latched on the falling edge of CE or WE (except for the sixth cycle of the Sector Erase command), whichever occurs last. The data is latched by the first rising edge of CE or WE. Standard
microprocessor write timings are used. The address locations used in the command sequences
are not affected by entering the command sequences.
4.3
Erasure
Before a byte can be reprogrammed, the main memory blocks or parameter blocks which contains the byte must be erased. The erased state of the memory bits is a logical “1”. The entire
device can be erased at one time by using a 6-byte software code. The software chip erase
code consists of 6-byte load commands to specific address locations with a specific data pattern
(please refer to the Chip Erase Cycle Waveforms).
After the software chip erase has been initiated, the device will internally time the erase operation so that no external clocks are required. The maximum time needed to erase the whole chip
is tEC. If the boot block lockout feature has been enabled, the data in the boot sector will not be
erased.
4.3.1
Chip Erase
If the boot block lockout has been enabled, the Chip Erase function will erase Parameter Block
1, Parameter Block 2, Main Memory Block 1 - 8, but not the boot block. If the Boot Block Lockout
has not been enabled, the Chip Erase function will erase the entire chip. After the full chip erase
the device will return back to read mode. Any command during chip erase will be ignored.
4.3.2
Sector Erase
As an alternative to a full chip erase, the device is organized into sectors that can be individually
erased. There are two 8K-byte parameter block sections and eight main memory blocks. The
8K-byte parameter block sections and the eight main memory blocks can be independently
erased and reprogrammed. The Sector Erase command is a six bus cycle operation. The sector
address is latched on the rising WE edge of the sixth cycle while the 30H data input command is
also latched at the rising edge of WE. The sector erase starts after the rising edge of WE of the
sixth cycle. The erase operation is internally controlled; it will automatically time to completion.
4.4
Byte Programming
Once the memory array is erased, the device is programmed (to a logical “0”) on a byte-by-byte
basis. Please note that a data “0” cannot be programmed back to a “1”; only erase operations
can convert “0”s to “1”s. Programming is accomplished via the internal device command register
and is a 4 bus cycle operation (please refer to the “Command Definition Table” on page 6). The
device will automatically generate the required internal program pulses.
The program cycle has addresses latched on the falling edge of WE or CE, whichever occurs
last, and the data latched on the rising edge of WE or CE, whichever occurs first. Programming
is completed after the specified tBP cycle time. The DATA polling feature may also be used to
indicate the end of a program cycle.
4
AT49BV040A
3358C–FLASH–3/05
AT49BV040A
4.5
Boot Block Programming Lockout
The device has one designated block that has a programming lockout feature. This feature prevents programming of data in the designated block once the feature has been enabled. The size
of the block is 16K bytes. This block, referred to as the boot block, can contain secure code that
is used to bring up the system. Enabling the lockout feature will allow the boot code to stay in the
device while data in the rest of the device is updated. This feature does not have to be activated;
the boot block’s usage as a write protected region is optional to the user. The address range of
the boot block is 00000 to 03FFF.
Once the feature is enabled, the data in the boot block can no longer be erased or programmed.
Data in the main memory block can still be changed through the regular programming method.
To activate the lockout feature, a series of six program commands to specific addresses with
specific data must be performed. Please refer to the “Command Definition Table” on page 6.
4.5.1
4.6
Boot Block Lockout Detection
A software method is available to determine if programming of the boot block section is locked
out. When the device is in the software product identification mode (see “Software Product Identification Entry and Exit” sections) a read from address location 00002H will show if
programming the boot block is locked out. If the data on I/O0 is low, the boot block can be programmed; if the data on I/O0 is high, the program lockout feature has been activated and the
block cannot be programmed. The software product identification code should be used to return
to standard operation.
Product Identification
The product identification mode identifies the device and manufacturer as Atmel. It may be
accessed by hardware or software operation. The hardware operation mode can be used by an
external programmer to identify the correct programming algorithm for the Atmel product.
For details, see Operating Modes (for hardware operation) or Software Product Identification.
The manufacturer and device code is the same for both modes.
4.7
DATA Polling
The AT49BV040A features DATA polling to indicate the end of a program cycle. During a program cycle an attempted read of the last byte loaded will result in the complement of the loaded
data on I/O7. Once the program cycle has been completed, true data is valid on all outputs and
the next cycle may begin. DATA polling may begin at any time during the program cycle.
4.8
Toggle Bit
In addition to DATA polling the AT49BV040A provides another method for determining the end
of a program or erase cycle. During a program or erase operation, successive attempts to read
data from the device will result in I/O6 toggling between one and zero. Once the program cycle
has completed, I/O6 will stop toggling and valid data will be read. Examining the toggle bit may
begin at any time during a program cycle.
4.9
Hardware Data Protection
Hardware features protect against inadvertent programs to the AT49BV040A in the following
ways: (a) VCC sense: if VCC is below 1.8V (typical), the program function is inhibited. (b) Program
inhibit: holding any one of OE low, CE high or WE high inhibits program cycles. (c) Noise filter:
pulses of less than 15 ns (typical) on the WE or CE inputs will not initiate a program cycle.
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3358C–FLASH–3/05
5. Command Definition Table
Command
Sequence
1st Bus
Cycle
Bus
Cycles
Addr
Data
Read
1
Addr
DOUT
Chip Erase
6
555
AA
Sector Erase
2nd Bus
Cycle
3rd Bus
Cycle
4th Bus
Cycle
Data
Addr
Data
Addr
Data
Addr
Data
Addr
Data
AAA(2)
55
555
80
555
AA
AAA
55
555
10
555
AA
AAA
55
555
80
555
AA
4
555
AA
AAA
55
555
A0
Addr
DIN
6
555
AA
AAA
55
555
80
555
AA
Product ID Entry
3
555
AA
AAA
55
555
90
(4)
Product ID Exit
3
555
AA
AAA
55
555
F0
Product ID Exit(4)
1
XXX
F0
Boot Block Lockout
Notes:
(3)
6th Bus
Cycle
Addr
6
Byte Program
5th Bus
Cycle
(5)
AAA
55
SA
30
AAA
55
555
40
1. The DATA FORMAT in each bus cycle is as follows: I/O7 - I/O0 (Hex). The address format in each bus cycle is as follows:
A11 - A0 (Hex); A11 - A18 (don’t care).
2. Since A11 is don’t care, AAA can be replaced with 2AA.
3. The 16K byte boot sector has the address range 00000H to 03FFFH.
4. Either one of the Product ID Exit commands can be used.
5. SA = sector addresses:
SA = 00000 to 03FFF for BOOT BLOCK
SA = 04000 to 05FFF for PARAMETER BLOCK 1
SA = 06000 to 07FFF for PARAMETER BLOCK 2
SA = 08000 to FFFF for MAIN MEMORY ARRAY BLOCK 1
SA = 10000 to 1FFFF for MAIN MEMORY ARRAY BLOCK 2
SA = 20000 to 2FFFF for MAIN MEMORY ARRAY BLOCK 3
SA = 30000 to 3FFFF for MAIN MEMORY ARRAY BLOCK 4
SA = 40000 to 4FFFF for MAIN MEMORY ARRAY BLOCK 5
SA = 50000 to 5FFFF for MAIN MEMORY ARRAY BLOCK 6
SA = 60000 to 6FFFF for MAIN MEMORY ARRAY BLOCK 7
SA = 70000 to 7FFFF for MAIN MEMORY ARRAY BLOCK 8
6. Absolute Maximum Ratings
Temperature Under Bias................................ -55°C to +125°C
Storage Temperature ..................................... -65°C to +150°C
All Input Voltages
(including NC Pins)
with Respect to Ground ...................................-0.6V to +6.25V
*NOTICE:
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended
periods may affect device reliability.
All Output Voltages
with Respect to Ground .............................-0.6V to VCC + 0.6V
Voltage on OE
with Respect to Ground ...................................-0.6V to +13.5V
6
AT49BV040A
3358C–FLASH–3/05
AT49BV040A
7. DC and AC Operating Range
Operating Temperature (Case)
Ind.
VCC Power Supply
AT49BV040A-70
AT49BV040A-90
-40°C - 85°C
-40°C - 85°C
2.7V - 3.6V
2.7V - 3.6V
8. Operating Modes
Mode
CE
OE
WE
Ai
I/O
VIL
VIL
VIH
Ai
DOUT
Program/Erase
VIL
VIH
VIL
Ai
DIN
Standby/Write Inhibit
VIH
X(1)
X
X
High Z
Program Inhibit
X
X
VIH
Program Inhibit
X
VIL
X
Output Disable
X
VIH
X
Reset
X
X
X
VIL
VIL
VIH
Read
(2)
High Z
X
High Z
A1 - A18 = VIL, A9 = VH,(3), A0 = VIL
Manufacturer Code(4)
A1 - A18 = VIL, A9 = VH,(3), A0 = VIH
Device Code(4)
A0 = VIL, A1 - A18 = VIL
Manufacturer Code(4)
A0 = VIH, A1 - A18 = VIL
Device Code(4)
Product Identification
Hardware
Software(5)
Notes:
1.
2.
3.
4.
5.
X can be VIL or VIH.
Refer to AC Programming Waveforms.
VH = 12.0V ± 0.5V.
Manufacturer Code: 1FH, Device Code: 13H.
See details under “Software Product Identification Entry/Exit”.
9. DC Characteristics
Symbol
Parameter
Condition
ILI
Input Load Current
ILO
Max
Units
VIN = 0V to VCC
10
µA
Output Leakage Current
VI/O = 0V to VCC
10
µA
ISB1
VCC Standby Current CMOS
CE = VCC - 0.3V to VCC
50
µA
ISB2
VCC Standby Current TTL
CE = 2.0V to VCC
1
mA
VCC Active Current
f = 5 MHz; IOUT = 0 mA
15
mA
0.6
V
ICC
(1)
VIL
Input Low Voltage
VIH
Input High Voltage
VOL
Output Low Voltage
IOL = 2.1 mA
VOH
Output High Voltage
IOH = -400 µA
Note:
Min
2.0
V
0.45
2.4
V
V
1. In the erase mode, ICC is 70 mA.
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3358C–FLASH–3/05
10. AC Read Characteristics
AT49BV040A-70
Symbol
Parameter
tACC
Min
AT49BV040A-90
Max
Min
Max
Units
Address to Output Delay
70
90
ns
(1)
CE to Output Delay
70
90
ns
tOE(2)
OE to Output Delay
0
35
0
40
ns
tDF(3)(4)
CE or OE to Output Float
0
25
0
25
ns
tOH
Output Hold from OE, CE or
Address, whichever occurred first
0
tCE
0
ns
11. AC Read Waveforms (1)(2)(3)(4)
ADDRESS
ADDRESS
VALID
CE
OE
tCE
tOE
t DF
tACC
OUTPUT
Notes:
8
HIGH Z
tOH
OUTPUT
VALID
1. CE may be delayed up to tACC - tCE after the address transition without impact on tACC.
2. OE may be delayed up to tCE - tOE after the falling edge of CE without impact on tCE or by tACC - tOE after an address change
without impact on tACC.
3. tDF is specified from OE or CE whichever occurs first (CL = 5 pF).
4. This parameter is characterized and is not 100% tested.
AT49BV040A
3358C–FLASH–3/05
AT49BV040A
12. Input Test Waveform and Measurement Level
2.4V
AC
DRIVING
LEVELS
AC
MEASUREMENT
LEVEL
1.5V
0.4V
tR, tF < 5 ns
13. Output Load Test
3.0V
1.8K
OUTPUT
PIN
1.3K
30 pF
14. Pin Capacitance
f = 1 MHz, T = 25°C(1)
Symbol
Typ
Max
Units
Conditions
CIN
4
6
pF
VIN = 0V
COUT
8
12
pF
VOUT = 0V
Note:
1. This parameter is characterized and is not 100% tested.
9
3358C–FLASH–3/05
15. AC Byte Load Characteristics
Symbol
Parameter
Min
Max
Units
tAS, tOES
Address, OE Set-up Time
0
ns
tAH
Address Hold Time
40
ns
tCS
Chip Select Set-up Time
0
ns
tCH
Chip Select Hold Time
0
ns
tWP
Write Pulse Width (WE or CE)
30
ns
tDS
Data Set-up Time
40
ns
tDH, tOEH
Data, OE Hold Time
0
ns
tWPH
Write Pulse Width High
30
ns
16. AC Byte Load Waveforms
16.1
WE Controlled
OE
tOES
tOEH
ADDRESS
CE
WE
tAS
tAH
tCH
tCS
tWPH
tWP
tDH
tDS
DATA IN
16.2
CE Controlled
OE
tOES
tOEH
ADDRESS
tAS
tAH
tCH
WE
tCS
CE
tWPH
tWP
tDS
tDH
DATA IN
10
AT49BV040A
3358C–FLASH–3/05
AT49BV040A
17. Program Cycle Characteristics
Symbol
Parameter
Min
Typ
Max
Units
tBP
Byte Programming Time
30
50
µs
tAS
Address Set-up Time
0
ns
tAH
Address Hold Time
40
ns
tDS
Data Set-up Time
40
ns
tDH
Data Hold Time
0
ns
tWP
Write Pulse Width
30
ns
tWPH
Write Pulse Width High
30
ns
tEC
Chip Erase Cycle Time
12
seconds
18. Program Cycle Waveforms
A0 - A18
19. Sector or Chip Erase Cycle Waveforms
OE
(1)
CE
tWP
tWPH
WE
tAS
A0 - A18
tAH
tDH
555
555
555
AAA
Note 2
AAA
tEC
tDS
DATA
AA
BYTE 0
Notes:
55
BYTE 1
80
BYTE 2
AA
BYTE 3
55
BYTE 4
Note 3
BYTE 5
1. OE must be high only when WE and CE are both low.
2. For chip erase, the address should be 555. For sector erase, the address depends on what sector is to be erased.
(See note 4 under “Command Definition Table” on page 6.)
3. For chip erase, the data should be 10H, and for sector erase, the data should be 30H.
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3358C–FLASH–3/05
20. Data Polling Characteristics
Symbol
Parameter
Min
tDH
Data Hold Time
10
ns
tOEH
OE Hold Time
10
ns
Max
(2)
tOE
OE to Output Delay
tWR
Write Recovery Time
Notes:
Typ
Units
ns
0
ns
1. These parameters are characterized and not 100% tested.
2. See tOE spec in “AC Read Characteristics” on page 8.
21. Data Polling Waveforms
WE
CE
tOEH
OE
tDH
tOE
I/O7
A0-A18
An
tWR
HIGH Z
An
An
An
An
22. Toggle Bit Characteristics
Symbol
Parameter
Min
tDH
Data Hold Time
10
ns
tOEH
OE Hold Time
10
ns
tOE
OE to Output Delay(2)
tOEHP
OE High Pulse
50
ns
tWR
Write Recovery Time
0
ns
Notes:
Typ
Max
Units
ns
1. These parameters are characterized and not 100% tested.
2. See tOE spec in “AC Read Characteristics” on page 8.
23. Toggle Bit Waveforms(1)(2)(3)
WE
CE
tOEH
tOEHP
OE
tDH
I/O6
Notes:
12
tOE
HIGH Z
tWR
1. Toggling either OE or CE or both OE and CE will operate toggle bit.
The tOEHP specification must be met by the toggling input(s).
2. Beginning and ending state of I/O6 will vary.
3. Any address location may be used but the address should not vary.
AT49BV040A
3358C–FLASH–3/05
AT49BV040A
24. Software Product Identification
Entry(1)
26. Boot Block Lockout Feature Enable
Algorithm(1)
LOAD DATA AA
TO
ADDRESS 555
LOAD DATA AA
TO
ADDRESS 555
LOAD DATA 55
TO
ADDRESS AAA
LOAD DATA 55
TO
ADDRESS AAA
LOAD DATA 80
TO
ADDRESS 555
LOAD DATA 90
TO
ADDRESS 555
LOAD DATA AA
TO
ADDRESS 555
ENTER PRODUCT
IDENTIFICATION
MODE(2)(3)(5)
LOAD DATA 55
TO
ADDRESS AAA
LOAD DATA 40
TO
ADDRESS 555
25. Software Product Identification
Exit(1)
LOAD DATA AA
TO
ADDRESS 555
LOAD DATA 55
TO
ADDRESS AAA
OR
LOAD DATA F0
TO
ANY ADDRESS
EXIT PRODUCT
IDENTIFICATION
MODE(4)
PAUSE 1 second(2)
Notes:
1. Data Format: I/O7 - I/O0 (Hex);
Address Format: A11 - A0 (Hex).
2. Boot block lockout feature enabled.
LOAD DATA F0
TO
ADDRESS 555
EXIT PRODUCT
IDENTIFICATION
MODE(4)
Notes:
1. Data Format: I/O7 - I/O0 (Hex);
Address Format: A11 - A0 (Hex).
2. A1 - A18 = VIL.
Manufacture Code is read for A0 = VIL;
Device Code is read for A0 = VIH.
Additional Device Code is read for address 0003H
3. The device does not remain in identification mode if
powered down.
4. The device returns to standard operation mode.
5. Manufacturer Code: 1FH
Device Code: 13H.
Additional Device Code: 0FH.
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3358C–FLASH–3/05
27. Ordering Information
27.1
tACC
(ns)
Standard Package
ICC (mA)
Active
Standby
Ordering Code
Package
32J
32T
32V
Industrial
(-40° to 85°C)
32J
32T
32V
Industrial
(-40° to 85°C)
70
15
0.05
AT49BV040A-70JI
AT49BV040A-70TI
AT49BV040A-70VI
90
15
0.05
AT49BV040A-90JI
AT49BV040A-90TI
AT49BV040A-90VI
27.2
Operation Range
Green Package Option (Pb/Halide-free)
ICC (mA)
tACC
(ns)
Active
Standby
70
15
90
15
Ordering Code
Package
Operation Range
0.05
AT49BV040A-70JU
AT49BV040A-70TU
32J
32T
Industrial
(-40° to 85°C)
0.05
AT49BV040A-90TU
AT49BV040A-90VU
32T
32V
Industrial
(-40° to 85°C)
Package Type
32J
32-Lead, Plastic, J-Leaded Chip Carrier Package (PLCC)
32T
32-Lead, Thin Small Outline Package (TSOP)
32V
32-Lead, Thin Small Outline Package (VSOP) (8 x 14 mm)
14
AT49BV040A
3358C–FLASH–3/05
AT49BV040A
28. Packaging Information
28.1
32J – PLCC
1.14(0.045) X 45˚
PIN NO. 1
IDENTIFIER
1.14(0.045) X 45˚
0.318(0.0125)
0.191(0.0075)
E1
E2
B1
E
B
e
A2
D1
A1
D
A
0.51(0.020)MAX
45˚ MAX (3X)
COMMON DIMENSIONS
(Unit of Measure = mm)
D2
Notes:
1. This package conforms to JEDEC reference MS-016, Variation AE.
2. Dimensions D1 and E1 do not include mold protrusion.
Allowable protrusion is .010"(0.254 mm) per side. Dimension D1
and E1 include mold mismatch and are measured at the extreme
material condition at the upper or lower parting line.
3. Lead coplanarity is 0.004" (0.102 mm) maximum.
SYMBOL
MIN
NOM
MAX
A
3.175
–
3.556
A1
1.524
–
2.413
A2
0.381
–
–
D
12.319
–
12.573
D1
11.354
–
11.506
D2
9.906
–
10.922
E
14.859
–
15.113
E1
13.894
–
14.046
E2
12.471
–
13.487
B
0.660
–
0.813
B1
0.330
–
0.533
e
NOTE
Note 2
Note 2
1.270 TYP
10/04/01
R
2325 Orchard Parkway
San Jose, CA 95131
TITLE
32J, 32-lead, Plastic J-leaded Chip Carrier (PLCC)
DRAWING NO.
REV.
32J
B
15
3358C–FLASH–3/05
28.2
32T – TSOP
PIN 1
0º ~ 8º
c
Pin 1 Identifier
D1 D
L
b
e
L1
A2
E
A
GAGE PLANE
SEATING PLANE
COMMON DIMENSIONS
(Unit of Measure = mm)
A1
MIN
NOM
MAX
A
–
–
1.20
A1
0.05
–
0.15
A2
0.95
1.00
1.05
D
19.80
20.00
20.20
D1
18.30
18.40
18.50
Note 2
E
7.90
8.00
8.10
Note 2
L
0.50
0.60
0.70
SYMBOL
Notes:
1. This package conforms to JEDEC reference MO-142, Variation BD.
2. Dimensions D1 and E do not include mold protrusion. Allowable
protrusion on E is 0.15 mm per side and on D1 is 0.25 mm per side.
3. Lead coplanarity is 0.10 mm maximum.
L1
0.25 BASIC
b
0.17
0.22
0.27
c
0.10
–
0.21
e
NOTE
0.50 BASIC
10/18/01
R
16
2325 Orchard Parkway
San Jose, CA 95131
TITLE
32T, 32-lead (8 x 20 mm Package) Plastic Thin Small Outline
Package, Type I (TSOP)
DRAWING NO.
REV.
32T
B
AT49BV040A
3358C–FLASH–3/05
AT49BV040A
28.3
32V – VSOP
PIN 1
0º ~ 8º
c
Pin 1 Identifier
D1 D
L
b
e
L1
A2
E
A
GAGE PLANE
SEATING PLANE
COMMON DIMENSIONS
(Unit of Measure = mm)
A1
MIN
NOM
MAX
A
–
–
1.20
A1
0.05
–
0.15
A2
0.95
1.00
1.05
D
13.80
14.00
14.20
D1
12.30
12.40
12.50
Note 2
E
7.90
8.00
8.10
Note 2
L
0.50
0.60
0.70
SYMBOL
Notes:
1. This package conforms to JEDEC reference MO-142, Variation BA.
2. Dimensions D1 and E do not include mold protrusion. Allowable
protrusion on E is 0.15 mm per side and on D1 is 0.25 mm per side.
3. Lead coplanarity is 0.10 mm maximum.
L1
0.25 BASIC
b
0.17
0.22
0.27
c
0.10
–
0.21
e
NOTE
0.50 BASIC
10/18/01
R
2325 Orchard Parkway
San Jose, CA 95131
TITLE
32V, 32-lead (8 x 14 mm Package) Plastic Thin Small Outline
Package, Type I (VSOP)
DRAWING NO.
REV.
32V
B
17
3358C–FLASH–3/05
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