Features
• Single-voltage Operation
•
•
•
•
•
•
•
•
•
– 5V Read
– 5V Reprogramming
Fast Read Access Time - 55 ns
Internal Program Control and Timer
Sector Architecture
– One 16K Byte Boot Block with Programming Lockout
– Two 8K Byte Parameter Blocks
– Two Main Memory Blocks (96K, 128K Bytes)
Fast Erase Cycle Time - 10 seconds
Byte-by-byte Programming - 10 µs/Byte Typical
Hardware Data Protection
DATA Polling for End of Program Detection
Low Power Dissipation
– 50 mA Active Current
– 100 µA CMOS Standby Current
Typical 10,000 Write Cycles
2-megabit
(256K x 8)
5-volt Only
Flash Memory
Description
The AT49F002(N)(T) is a 5-volt only in-system reprogrammable Flash memory. Its 2
megabits of memory is organized as 262,144 words by 8 bits. Manufactured with
Atmel’s advanced nonvolatile CMOS technology, the device offers access times to 55
ns with power dissipation of just 275 mW over the commercial temperature range.
(continued)
Pin Configurations
Pin Name
Function
A0 - A17
Addresses
CE
Chip Enable
OE
Output Enable
WE
Write Enable
RESET
RESET
I/O0 - I/O7
Data Inputs/Outputs
DC
Don’t Connect
4
3
2
1
32
31
30
29
28
27
26
25
24
23
22
21
14
15
16
17
18
19
20
5
6
7
8
9
10
11
12
13
A14
A13
A8
A9
A11
OE
A10
CE
I/O7
I/O1
I/O2
GND
I/O3
I/O4
I/O5
I/O6
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
* RESET
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VCC
WE
A17
A14
A13
A8
A9
A11
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
VSOP Top View (8 x 14 mm) or
TSOP Top View (8 x 20 mm)
Type 1
A12
A15
A16
RESET *
VCC
WE
A17
PLCC Top View
DIP Top View
AT49F002
AT49F002N
AT49F002T
AT49F002NT
A11
A9
A8
A13
A14
A17
WE
VCC
* RESET
A16
A15
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
A1
A2
A3
Rev. 1017D–10/99
*Note: This pin is a DC on the AT49F002(N)(T).
1
When the device is deselected, the CMOS standby current
is less than 100 µA. For the AT49F002N(T) pin 1 for the
DIP and PLCC packages and pin 9 for the TSOP package
are don’t connect pins.
To allow for simple in-system reprogrammability, the
AT49F002(N)(T) does not require high input voltages for
programming. Five-volt-only commands determine the read
and programming operation of the device. Reading data
out of the device is similar to reading from an EPROM; it
has standard CE, OE, and WE inputs to avoid bus contention. Reprogramming the AT49F002(N)(T) is performed by
erasing a block of data and then programming on a byte by
byte basis. The byte programming time is a fast 50 µs. The
end of a program cycle can be optionally detected by the
DATA polling feature. Once the end of a byte program
cycle has been detected, a new access for a read or program can begin. The typical number of program and erase
cycles is in excess of 10,000 cycles.
The device is erased by executing the erase command
sequence; the device internally controls the erase operations. There are two 8K byte parameter block sections and
two main memory blocks.
The device has the capability to protect the data in the boot
block; this feature is enabled by a command sequence.
The 16K-byte boot block section includes a reprogramming
lock out feature to provide data integrity. The boot sector is
designed to contain user secure code, and when the feature is enabled, the boot sector is protected from being
reprogrammed.
In the AT49F002(N)(T), once the boot block programming
lockout feature is enabled, the contents of the boot block
are permanent and cannot be changed. In the
AT49F002(T), once the boot block programming lockout
feature is enabled, the contents of the boot block cannot be
changed with input voltage levels of 5.5 volts or less.
Block Diagram
AT49F002(N)T
DATA INPUTS/OUTPUTS
I/O7 - I/O0
AT49F002(N)
DATA INPUTS/OUTPUTS
I/O7 - I/O0
VCC
GND
OE
WE
CE
RESET
CONTROL
LOGIC
Y DECODER
ADDRESS
INPUTS
8
8
INPUT/OUTPUT
BUFFERS
INPUT/OUTPUT
BUFFERS
PROGRAM
DATA LATCHES
PROGRAM
DATA LATCHES
Y-GATING
Y-GATING
X DECODER
MAIN MEMORY
BLOCK 2
(128K BYTES)
MAIN MEMORY
BLOCK 1
(96K BYTES)
PARAMETER
BLOCK 2
(8K BYTES)
PARAMETER
BLOCK 1
(8K BYTES)
BOOT BLOCK
(16K BYTES)
BOOT BLOCK
(16K BYTES)
20000
1FFFF
08000
07FFF
06000
05FFF
04000
03FFF
00000
2
3FFFF
3FFFF
AT49F002(N)(T)
PARAMETER
BLOCK 1
(8K BYTES)
PARAMETER
BLOCK 2
(8K BYTES)
MAIN MEMORY
BLOCK 1
(96K BYTES)
MAIN MEMORY
BLOCK 2
(128K BYTES)
3C000
3BFFF
3A000
39FFF
38000
37FFF
20000
1FFFF
00000
AT49F002(N)(T)
Device Operation
READ: The AT49F002(N)(T) is accessed like an EPROM.
When CE and OE are low and WE is high, the data stored
at the memory location determined by the address pins is
asserted on the outputs. The outputs are put in the high
impedance state whenever CE or OE is high. This dual-line
control gives designers flexibility in preventing bus contention.
COMMAND SEQUENCES: When the device is first powered on it will be reset to the read or standby mode
depending upon the state of the control line inputs. In order
to perform other device functions, a series of command
sequences are entered into the device. The command
sequences are shown in the Command Definitions table.
The command sequences are written by applying a low
pulse on the WE or CE input with CE or WE low (respectively) and OE high. The address is latched on the falling
edge of CE or WE, whichever occurs last. The data is
latched by the first rising edge of CE or WE. Standard
microprocessor write timings are used. The address locations used in the command sequences are not affected by
entering the command sequences.
RESET: A RESET input pin is provided to ease some system applications. When RESET is at a logic high level, the
device is in its standard operating mode. A low level on the
RESET input halts the present device operation and puts
the outputs of the device in a high impedance state. If the
RESET pin makes a high to low transition during a program
or erase operation, the operation may not be successfully
completed and the operation will have to be repeated after
a high level is applied to the RESET pin. When a high level
is reasserted on the RESET pin, the device returns to the
read or standby mode, depending upon the state of the
control inputs. By applying a 12V ± 0.5V input signal to the
RESET pin, the boot block array can be reprogrammed
even if the boot block lockout feature has been enabled
(see Boot Block Programming Lockout Override section).
The RESET feature is not available for the AT49F002N(T).
ERASURE: Before a byte can be reprogrammed, the main
memory block or parameter block which contains the byte
must be erased. The erased state of the memory bits is a
logical “1”. The entire device can be erased at one time by
using a 6-byte software code. The software chip erase
code consists of 6-byte load commands to specific address
locations with a specific data pattern (please refer to the
Chip Erase Cycle Waveforms).
After the software chip erase has been initiated, the device
will internally time the erase operation so that no external
clocks are required. The maximum time needed to erase
the whole chip is tEC. If the boot block lockout feature has
been enabled, the data in the boot sector will not be
erased.
CHIP ERASE: If the boot block lockout has been enabled,
the Chip Erase function will erase Parameter Block 1,
Parameter Block 2, Main Memory Block 1, and Main Memory Block 2 but not the boot block. If the Boot Block Lockout
has not been enabled, the Chip Erase function will erase
the entire chip. After the full chip erase the device will
return back to read mode. Any command during chip erase
will be ignored.
SECTOR ERASE: As an alternative to a full chip erase, the
device is organized into sectors that can be individually
erased. There are two 8K-byte parameter block sections
and two main memory blocks. The 8K-byte parameter
block sections can be independently erased and reprogrammed. The two main memory sections are designed to
be used as alternative memory sectors. That is, whenever
one of the blocks has been erased and reprogrammed, the
other block should be erased and reprogrammed before
the first block is again erased. The Sector Erase command
is a six bus cycle operation. The sector address is latched
on the falling WE edge of the sixth cycle while the 30H data
input command is latched at the rising edge of WE. The
sector erase starts after the rising edge of WE of the sixth
cycle. The erase operation is internally controlled; it will
automatically time to completion.
BYTE PROGRAMMING: Once the memory array is
erased, the device is programmed (to a logical “0”) on a
byte-by-byte basis. Please note that a data “0” cannot be
programmed back to a “1”; only erase operations can convert “0”s to “1”s. Programming is accomplished via the
internal device command register and is a 4 bus cycle
operation (please refer to the Command Definitions table).
The device will automatically generate the required internal
program pulses.
The program cycle has addresses latched on the falling
edge of WE or CE, whichever occurs last, and the data
latched on the rising edge of WE or CE, whichever occurs
first. Programming is completed after the specified tBP cycle
time. The DATA polling feature may also be used to indicate
the end of a program cycle.
BOOT BLOCK PROGRAMMING LOCKOUT: The device
has one designated block that has a programming lockout
feature. This feature prevents programming of data in the
designated block once the feature has been enabled. The
size of the block is 16K bytes. This block, referred to as the
boot block, can contain secure code that is used to bring up
the system. Enabling the lockout feature will allow the boot
code to stay in the device while data in the rest of the
device is updated. This feature does not have to be activated; the boot block’s usage as a write protected region is
optional to the user. The address range of the boot block is
00000 to 03FFF for the AT49F002(N) while the address
3
range of the boot block is 3C000 to 3FFFF for the
AT49F002(N)T.
Once the feature is enabled, the data in the boot block can
no longer be erased or programmed with input voltage levels of 5.5V or less. Data in the main memory block can still
be changed through the regular programming method. To
activate the lockout feature, a series of six program commands to specific addresses with specific data must be
performed. Please refer to the Command Definitions table.
BOOT BLOCK LOCKOUT DETECTION: A software
method is available to determine if programming of the boot
block section is locked out. When the device is in the software product identification mode (see Software Product
Identification Entry and Exit sections) a read from address
location 00002H will show if programming the boot block is
locked out for the AT49F002(N), and a read from address
location 3C002H will show if programming the boot block is
locked out for AT49F002(N)T. If the data on I/O0 is low, the
boot block can be programmed; if the data on I/O0 is high,
the program lockout feature has been activated and the
block cannot be programmed. The software product identification exit code should be used to return to standard
operation.
BOOT BLOCK PROGRAMMING LOCKOUT OVERRIDE:
The user can override the boot block programming lockout
by taking the RESET pin to 12 volts. By doing this, protected boot block data can be altered through a chip erase,
sector erase or word programming. When the RESET pin is
brought back to TTL levels the boot block programming
lockout feature is again active. This feature is not available
on the AT49F002N(T).
4
AT49F002(N)(T)
PRODUCT IDENTIFICATION: The product identification
mode identifies the device and manufacturer as Atmel. It
may be accessed by hardware or software operation. The
hardware operation mode can be used by an external programmer to identify the correct programming algorithm for
the Atmel product.
For details, see Operating Modes (for hardware operation)
or Software Product Identification. The manufacturer and
device code is the same for both modes.
DATA POLLING: The AT49F002(N)(T) features DATA polling to indicate the end of a program cycle. During a program cycle an attempted read of the last byte loaded will
result in the complement of the loaded data on I/O7. Once
the program cycle has been completed, true data is valid
on all outputs and the next cycle may begin. DATA polling
may begin at any time during the program cycle.
T O G G L E B I T : I n a d d i t i o n t o DATA p o l l i n g t h e
AT49F002(N)(T) provides another method for determining
the end of a program or erase cycle. During a program or
erase operation, successive attempts to read data from the
device will result in I/O6 toggling between one and zero.
Once the program cycle has completed, I/O6 will stop toggling and valid data will be read. Examining the toggle bit
may begin at any time during a program cycle.
HARDWARE DATA PROTECTION: Hardware features
protect against inadvertent programs to the
AT49F002(N)(T) in the following ways: (a) V CC sense: if
VCC is below 3.8V (typical), the program function is inhibited. (b) Program inhibit: holding any one of OE low, CE
high or WE high inhibits program cycles. (c) Noise filter:
pulses of less than 15 ns (typical) on the WE or CE inputs
will not initiate a program cycle.
AT49F002(N)(T)
Command Definition (in Hex)(1)
Command
Sequence
1st Bus
Cycle
Bus
Cycles
Addr
Data
Read
1
Addr
DOUT
Chip Erase
6
5555
AA
2nd Bus
Cycle
3rd Bus
Cycle
4th Bus
Cycle
6th Bus
Cycle
Addr
Data
Addr
Data
Addr
Data
Addr
Data
Addr
Data
2AAA
55
5555
80
5555
AA
2AAA
55
5555
10
2AAA
55
SA
(4)
30
2AAA
55
5555
40
Sector Erase
6
5555
AA
2AAA
55
5555
80
5555
AA
Byte Program
4
5555
AA
2AAA
55
5555
A0
Addr
DIN
Boot Block Lockout(2)
6
5555
AA
2AAA
55
5555
80
5555
AA
Product ID Entry
3
5555
AA
2AAA
55
5555
90
Product ID Exit
(3)
3
5555
AA
2AAA
55
5555
F0
Product ID Exit
(3)
1
XXXX
F0
Notes:
5th Bus
Cycle
1. The DATA FORMAT in each bus cycle is as follows: I/O7 - I/O0 (Hex)
2. The 16K byte boot sector has the address range 00000H to 03FFFH for the AT49F002(N) and 3C000H to 3FFFFH for the
AT49F002(N)T
3. Either one of the Product ID Exit commands can be used.
4. SA = sector addresses:
For the AT49F002(N):
SA = 00000 to 03FFF for BOOT BLOCK
Nothing will happen and the device goes back to the read mode in 100 ns
SA = 04000 to 05FFF for PARAMETER BLOCK 1
SA = 06000 to 07FFF for PARAMETER BLOCK 2
SA = 08000 to 1FFFF for MAIN MEMORY ARRAY BLOCK 1
This command will erase - PB1, PB2 and MMB1
SA = 20000 to 3FFFF for MAIN MEMORY ARRAY BLOCK 2
For the AT49F002(N)T:
SA = 3C000 to 3FFFF for BOOT BLOCK
Nothing will happen and the device goes back to the read mode in 100 ns
SA = 3A000 to 3BFFF for PARAMETER BLOCK 1
SA = 38000 to 39FFF for PARAMETER BLOCK 2
SA = 20000 to 37FFF for MAIN MEMORY ARRAY BLOCK 1
This command will erase - PB1, PB2 and MMB1
SA = 00000 to IFFFF for MAIN MEMORY ARRAY BLOCK 2
Absolute Maximum Ratings*
Temperature Under Bias................................ -55°C to +125°C
Storage Temperature ..................................... -65°C to +150°C
All Input Voltages
(including NC Pins)
with Respect to Ground ...................................-0.6V to +6.25V
*NOTICE:
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended
periods may affect device reliability.
All Output Voltages
with Respect to Ground .............................-0.6V to VCC + 0.6V
Voltage on OE
with Respect to Ground ...................................-0.6V to +13.5V
5
DC and AC Operating Range
Operating
Temperature (Case)
AT49F002(N)(T)-55
AT49F002(N)(T)-70
AT49F002(N)(T)-90
AT49F002(N)(T)-12
0°C - 70°C
0°C - 70°C
0°C - 70°C
0°C - 70°C
-40°C - 85°C
-40°C - 85°C
-40°C - 85°C
-40°C - 85°C
5V ± 10%
5V ± 10%
5V ± 10%
5V ± 10%
Com.
Ind.
VCC Power Supply
Operating Modes
Mode
Read
Program/Erase
(2)
Standby/Write Inhibit
CE
OE
WE
RESET(6)
Ai
VIL
VIL
VIH
VIH
Ai
DOUT
VIL
VIH
VIL
VIH
Ai
DIN
X
VIH
X
High Z
VIH
X
(1)
X
X
VIH
VIH
X
VIL
X
VIH
Output Disable
X
VIH
X
VIH
Reset
X
X
X
VIL
VIL
VIL
VIH
Program Inhibit
I/O
High Z
X
High Z
Product Identification
Hardware
Software(5)
Notes:
A1 - A17 = VIL, A9 = VH,(3) A0 = VIL
Manufacturer Code(4)
A1 - A17 = VIL, A9 = VH,(3) A0 = VIH
Device Code(4)
A0 = VIL, A1 - A17=VIL
Manufacturer Code(4)
A0 = VIH, A1 - A17=VIL
Device Code(4)
1. X can be VIL or VIH.
2. Refer to AC Programming Waveforms.
3. VH = 12.0V ± 0.5V.
4. Manufacturer Code: 1FH, Device Code: 07H - AT49F002(N), 08H - AT49F002(N)T
5. See details under Software Product Identification Entry/Exit.
6. This pin is not available on the AT49F002N(T).
DC Characteristics
Symbol
Parameter
Condition
ILI
Input Load Current
ILO
Max
Units
VIN = 0V to VCC
10
µA
Output Leakage Current
VI/O = 0V to VCC
10
µA
Com.
100
µA
ISB1
VCC Standby Current CMOS
CE = VCC - 0.3V to VCC
Ind.
300
µA
ISB2
VCC Standby Current TTL
CE = 2.0V to VCC
3
mA
ICC(1)
VCC Active Current
f = 5 MHz; IOUT = 0 mA
50
mA
VIL
Input Low Voltage
0.8
V
VIH
Input High Voltage
VOL
Output Low Voltage
IOL = 2.1 mA
VOH1
Output High Voltage
IOH = -400 µA
2.4
V
VOH2
Output High Voltage CMOS
IOH = -100 µA; VCC = 4.5V
4.2
V
Note:
6
Min
2.0
1. In the erase mode, ICC is 90 mA.
AT49F002(N)(T)
V
0.45
V
AT49F002(N)(T)
AC Read Characteristics
AT49F002(N)(T)
-55
Symbol
Parameter
tACC
Min
-70
Max
Min
-90
Max
Min
-12
Max
Min
Max
Units
Address to Output Delay
55
70
90
120
ns
(1)
CE to Output Delay
55
70
90
120
ns
tOE(2)
OE to Output Delay
0
30
0
35
0
40
0
50
ns
CE or OE to Output Float
0
25
0
25
0
25
0
30
ns
Output Hold from OE, CE
or Address, whichever
occurred first
0
tCE
tDF
(3)(4)
tOH
0
0
0
ns
AC Read Waveforms (1)(2)(3)(4)
ADDRESS
ADDRESS
VALID
CE
tCE
tOE
OE
t DF
tOH
tACC
HIGH Z
OUTPUT
Notes:
OUTPUT
VALID
1. CE may be delayed up to tACC - tCE after the address transition without impact on tACC.
2. OE may be delayed up to tCE - tOE after the falling edge of CE without impact on tCE or by tACC - tOE after an address change
without impact on tACC.
3. tDF is specified from OE or CE whichever occurs first (CL = 5 pF).
4. This parameter is characterized and is not 100% tested.
Input Test Waveform and
Measurement Level
Output Load Test
50 ns
70/90/120 ns
5.0V
5.0V
tR, tF < 5 ns
1.3K
1.8K
OUTPUT
PIN
30 pF
1.8K
1.3K
OUTPUT
PIN
100 pF
Pin Capacitance
f = 1 MHz, T = 25°C(1)
Symbol
Typ
Max
Units
Conditions
CIN
4
6
pF
VIN = 0V
COUT
8
12
pF
VOUT = 0V
Note:
1. This parameter is characterized and is not 100% tested.
7
AC Byte Load Characteristics
Symbol
Parameter
Min
tAS, tOES
Address, OE Set-up Time
0
ns
tAH
Address Hold Time
50
ns
tCS
Chip Select Set-up Time
0
ns
tCH
Chip Select Hold Time
0
ns
tWP
Write Pulse Width (WE or CE)
90
ns
tDS
Data Set-up Time
50
ns
tDH, tOEH
Data, OE Hold Time
0
ns
tWPH
Write Pulse Width High
90
ns
AC Byte Load Waveforms
WE Controlled
OE
tOES
tOEH
ADDRESS
CE
WE
tAS
tAH
tCH
tCS
tWPH
tWP
tDH
tDS
DATA IN
CE Controlled
OE
tOES
tOEH
ADDRESS
tAS
tAH
tCH
WE
tCS
CE
tWPH
tWP
tDS
DATA IN
8
AT49F002(N)(T)
tDH
Max
Units
AT49F002(N)(T)
Program Cycle Characteristics
Symbol
Parameter
Min
Typ
Max
Units
tBP
Byte Programming Time
10
50
µs
tAS
Address Set-up Time
0
ns
tAH
Address Hold Time
50
ns
tDS
Data Set-up Time
50
ns
tDH
Data Hold Time
0
ns
tWP
Write Pulse Width
90
ns
tWPH
Write Pulse Width High
90
ns
tEC
Erase Cycle Time
10
seconds
Program Cycle Waveforms
Sector or Chip Erase Cycle Waveforms
Notes:
1. OE must be high only when WE and CE are both low.
2. For chip erase, the address should be 5555. For sector erase, the address depends on what sector is to be erased.
(See note 4 under command definitions.)
3. For chip erase, the data should be 10H, and for sector erase, the data should be 30H.
9
Data Polling Characteristics(1)
Symbol
Parameter
Min
tDH
Data Hold Time
10
ns
tOEH
OE Hold Time
10
ns
Max
(2)
tOE
OE to Output Delay
tWR
Write Recovery Time
Notes:
Typ
Units
ns
0
ns
1. These parameters are characterized and not 100% tested.
2. See tOE spec in AC Read Characteristics.
Data Polling Waveforms
WE
CE
tOEH
OE
tDH
tOE
I/O7
A0-A17
An
tWR
HIGH Z
An
An
An
An
Toggle Bit Characteristics(1)
Symbol
Parameter
Min
tDH
Data Hold Time
10
ns
tOEH
OE Hold Time
10
ns
(2)
tOE
OE to Output Delay
tOEHP
OE High Pulse
tWR
Write Recovery Time
Notes:
Typ
Max
Units
ns
150
ns
0
ns
1. These parameters are characterized and not 100% tested.
2. See tOE spec in AC Read Characteristics.
Toggle Bit Waveforms(1)(2)(3)
WE
CE
tOEH
tOEHP
OE
tDH
tOE
I/O6
Notes:
HIGH Z
1. Toggling either OE or CE or both OE and CE will operate toggle bit. The tOEHP specification must be met by the toggling
input(s).
2. Beginning and ending state of I/O6 will vary.
3. Any address location may be used but the address should not vary.
10
tWR
AT49F002(N)(T)
AT49F002(N)(T)
Software Product Identification Entry(1)
LOAD DATA AA
TO
ADDRESS 5555
LOAD DATA AA
TO
ADDRESS 5555
LOAD DATA 55
TO
ADDRESS 2AAA
LOAD DATA 55
TO
ADDRESS 2AAA
LOAD DATA 90
TO
ADDRESS 5555
LOAD DATA 80
TO
ADDRESS 5555
ENTER PRODUCT
IDENTIFICATION
MODE(2)(3)(5)
LOAD DATA AA
TO
ADDRESS 5555
Software Product Identification Exit(1)
LOAD DATA AA
TO
ADDRESS 5555
LOAD DATA 55
TO
ADDRESS 2AAA
OR
Boot Block Lockout Feature Enable
Algorithm(1)
LOAD DATA F0
TO
ANY ADDRESS
EXIT PRODUCT
IDENTIFICATION
MODE(4)
LOAD DATA F0
TO
ADDRESS 5555
EXIT PRODUCT
IDENTIFICATION
MODE(4)
Notes for software product identification
1. Data Format: I/O7 - I/O0 (Hex);
Address Format: A14 - A0 (Hex).
2. A1 - A17 = VIL.
Manufacture Code is read for A0 = VIL;
Device Code is read for A0 = VIH.
3. The device does not remain in identification mode if
powered down.
4. The device returns to standard operation mode.
5. Manufacturer Code: 1FH
Device Code: 07H - AT49F002(N)
08H - AT49F002(N)T
LOAD DATA 55
TO
ADDRESS 2AAA
LOAD DATA 40
TO
ADDRESS 5555
PAUSE 1 second(2)
Notes for boot block lockout feature enable:
1. Data Format: I/O7 - I/O0 (Hex);
Address Format: A14 - A0 (Hex).
2. Boot block lockout feature enabled.
11
AT49F002 Ordering Information
ICC (mA)
tACC
(ns)
Active
Standby
Ordering Code
Package
55
50
0.1
AT49F002-55JC
AT49F002-55PC
AT49F002-55TC
AT49F002-55VC
32J
32P6
32T
32V
Commercial
(0° to 70°C)
50
0.3
AT49F002-55JI
AT49F002-55PI
AT49F002-55TI
AT49F002-55VI
32J
32P6
32T
32V
Industrial
(-40° to 85°C)
50
0.1
AT49F002-70JC
AT49F002-70PC
AT49F002-70TC
AT49F002-70VC
32J
32P6
32T
32V
Commercial
(0° to 70°C)
50
0.3
AT49F002-70JI
AT49F002-70PI
AT49F002-70TI
AT49F002-70VI
32J
32P6
32T
32V
Industrial
(-40° to 85°C)
50
0.1
AT49F002-90JC
AT49F002-90PC
AT49F002-90TC
AT49F002-90VC
32J
32P6
32T
32V
Commercial
(0° to 70°C)
50
0.3
AT49F002-90JI
AT49F002-90PI
AT49F002-90TI
AT49F002-90VI
32J
32P6
32T
32V
Industrial
(-40° to 85°C)
50
0.1
AT49F002-12JC
AT49F002-12PC
AT49F002-12TC
AT49F002-12VC
32J
32P6
32T
32V
Commercial
(0° to 70°C)
50
0.3
AT49F002-12JI
AT49F002-12PI
AT49F002-12TI
AT49F002-12VI
32J
32P6
32T
32V
Industrial
(-40° to 85°C)
70
90
120
Package Type
32J
32-lead, Plastic J-leaded Chip Carrier Package (PLCC)
32P6
32-pin, 0.600" Wide, Plastic Dual Inline Package (PDIP)
32T
32-lead, Plastic Thin Small Outline Package (TSOP) (8 x 20 mm)
32V
32-lead, Plastic Thin Small Outline Package (VSOP) (8 x 14 mm)
12
AT49F002(N)(T)
Operation Range
AT49F002(N)(T)
AT49F002N Ordering Information
ICC (mA)
tACC
(ns)
Active
Standby
Ordering Code
Package
55
50
0.1
AT49F002N-55JC
AT49F002N-55PC
AT49F002N-55TC
AT49F002N-55VC
32J
32P6
32T
32V
Commercial
(0° to 70°C)
50
0.3
AT49F002N-55JI
AT49F002N-55PI
AT49F002N-55TI
AT49F002N-55VI
32J
32P6
32T
32V
Industrial
(-40° to 85°C)
50
0.1
AT49F002N-70JC
AT49F002N-70PC
AT49F002N-70TC
AT49F002N-70VC
32J
32P6
32T
32V
Commercial
(0° to 70°C)
50
0.3
AT49F002N-70JI
AT49F002N-70PI
AT49F002N-70TI
AT49F002N-70VI
32J
32P6
32T
32V
Industrial
(-40° to 85°C)
50
0.1
AT49F002N-90JC
AT49F002N-90PC
AT49F002N-90TC
AT49F002N-90VC
32J
32P6
32T
32V
Commercial
(0° to 70°C)
50
0.3
AT49F002N-90JI
AT49F002N-90PI
AT49F002N-90TI
AT49F002N-90VI
32J
32P6
32T
32V
Industrial
(-40° to 85°C)
50
0.1
AT49F002N-12JC
AT49F002N-12PC
AT49F002N-12TC
AT49F002N-12VC
32J
32P6
32T
32V
Commercial
(0° to 70°C)
50
0.3
AT49F002N-12JI
AT49F002N-12PI
AT49F002N-12TI
AT49F002N-12VI
32J
32P6
32T
32V
Industrial
(-40° to 85°C)
70
90
120
Operation Range
Package Type
32J
32-lead, Plastic J-leaded Chip Carrier Package (PLCC)
32P6
32-pin, 0.600" Wide, Plastic Dual Inline Package (PDIP)
32T
32-lead, Plastic Thin Small Outline Package (TSOP) (8 x 20 mm)
32V
32-lead, Plastic Thin Small Outline Package (VSOP) (8 x 14 mm)
13
AT49F002T Ordering Information
ICC (mA)
tACC
(ns)
Active
Standby
Ordering Code
Package
55
50
0.1
AT49F002T-55JC
AT49F002T-55PC
AT49F002T-55TC
AT49F002T-55VC
32J
32P6
32T
32V
Commercial
(0° to 70°C)
50
0.3
AT49F002T-55JI
AT49F002T-55PI
AT49F002T-55TI
AT49F002T-55VI
32J
32P6
32T
32V
Industrial
(-40° to 85°C)
50
0.1
AT49F002T-70JC
AT49F002T-70PC
AT49F002T-70TC
AT49F002T-70VC
32J
32P6
32T
32V
Commercial
(0° to 70°C)
50
0.3
AT49F002T-70JI
AT49F002T-70PI
AT49F002T-70TI
AT49F002T-70VI
32J
32P6
32T
32V
Industrial
(-40° to 85°C)
50
0.1
AT49F002T-90JC
AT49F002T-90PC
AT49F002T-90TC
AT49F002T-90VC
32J
32P6
32T
32V
Commercial
(0° to 70°C)
50
0.3
AT49F002T-90JI
AT49F002T-90PI
AT49F002T-90TI
AT49F002T-90VI
32J
32P6
32T
32V
Industrial
(-40° to 85°C)
50
0.1
AT49F002T-12JC
AT49F002T-12PC
AT49F002T-12TC
AT49F002T-12VC
32J
32P6
32T
32V
Commercial
(0° to 70°C)
50
0.3
AT49F002T-12JI
AT49F002T-12PI
AT49F002T-12TI
AT49F002T-12VI
32J
32P6
32T
32V
Industrial
(-40° to 85°C)
70
90
120
Package Type
32J
32-lead, Plastic J-leaded Chip Carrier Package (PLCC)
32P6
32-pin, 0.600" Wide, Plastic Dual Inline Package (PDIP)
32T
32-lead, Plastic Thin Small Outline Package (TSOP) (8 x 20 mm)
32V
32-lead, Plastic Thin Small Outline Package (VSOP) (8 x 14 mm)
14
AT49F002(N)(T)
Operation Range
AT49F002(N)(T)
AT49F002NT Ordering Information
ICC (mA)
tACC
(ns)
Active
Standby
Ordering Code
Package
55
50
0.1
AT49F002NT-55JC
AT49F002NT-55PC
AT49F002NT-55TC
AT49F002NT-55VC
32J
32P6
32T
32V
Commercial
(0° to 70°C)
50
0.3
AT49F002NT-55JI
AT49F002NT-55PI
AT49F002NT-55TI
AT49F002NT-55VI
32J
32P6
32T
32V
Industrial
(-40° to 85°C)
50
0.1
AT49F002NT-70JC
AT49F002NT-70PC
AT49F002NT-70TC
AT49F002NT-70VC
32J
32P6
32T
32V
Commercial
(0° to 70°C)
50
0.3
AT49F002NT-70JI
AT49F002NT-70PI
AT49F002NT-70TI
AT49F002NT-70VI
32J
32P6
32T
32V
Industrial
(-40° to 85°C)
50
0.1
AT49F002NT-90JC
AT49F002NT-90PC
AT49F002NT-90TC
AT49F002NT-90VC
32J
32P6
32T
32V
Commercial
(0° to 70°C)
50
0.3
AT49F002NT-90JI
AT49F002NT-90PI
AT49F002NT-90TI
AT49F002NT-90VI
32J
32P6
32T
32V
Industrial
(-40° to 85°C)
50
0.1
AT49F002NT-12JC
AT49F002NT-12PC
AT49F002NT-12TC
AT49F002NT-12VC
32J
32P6
32T
32V
Commercial
(0° to 70°C)
50
0.3
AT49F002NT-12JI
AT49F002NT-12PI
AT49F002NT-12TI
AT49F002NT-12VI
32J
32P6
32T
32V
Industrial
(-40° to 85°C)
70
90
120
Operation Range
Package Type
32J
32-lead, Plastic J-leaded Chip Carrier Package (PLCC)
32P6
32-pin, 0.600" Wide, Plastic Dual Inline Package (PDIP)
32T
32-lead, Plastic Thin Small Outline Package (TSOP) (8 x 20 mm)
32V
32-lead, Plastic Thin Small Outline Package (VSOP) (8 x 14 mm)
15
Packaging Information
32J, 32-lead, Plastic J-leaded Chip Carrier (PLCC)
Dimensions in Inches and (Millimeters)
JEDEC STANDARD MS-016 AE
.045(1.14) X 45˚
PIN NO. 1
IDENTIFY
.050(1.27) TYP
1.67(42.4)
1.64(41.7)
.025(.635) X 30˚ - 45˚
.012(.305)
.008(.203)
.553(14.0)
.547(13.9)
.595(15.1)
.585(14.9)
.032(.813)
.026(.660)
32P6, 32-pin, 0.600" Wide,
Plastic Dual Inline Package (PDIP)
Dimensions in Inches and (Millimeters)
.300(7.62) REF
.430(10.9)
.390(9.90)
AT CONTACT
POINTS
PIN
1
.530(13.5)
.490(12.4)
.566(14.4)
.530(13.5)
.021(.533)
.013(.330)
.030(.762)
.015(.381)
.095(2.41)
.060(1.52)
.140(3.56)
.120(3.05)
.090(2.29)
MAX
1.500(38.10) REF
.220(5.59)
MAX
.005(.127)
MIN
SEATING
PLANE
.065(1.65)
.015(.381)
.022(.559)
.014(.356)
.161(4.09)
.125(3.18)
.022(.559) X 45˚ MAX (3X)
.453(11.5)
.447(11.4)
.495(12.6)
.485(12.3)
INDEX
MARK
0 REF
15
.690(17.5)
.610(15.5)
32V, 32-lead, Plastic Thin Small Outline Package
(TSOP)
Dimensions in Millimeters and (Inches)
INDEX
MARK
18.5(.728)
18.3(.720)
7.50(.295)
REF
20.2(.795)
19.8(.780)
12.5(.492)
12.3(.484)
0.50(.020)
BSC
0.25(.010)
0.15(.006)
8.20(.323)
7.80(.307)
7.50(.295)
REF
14.2(.559)
13.8(.543)
0.25(.010)
0.15(.006)
8.10(.319)
7.90(.311)
1.20(.047) MAX
0.15(.006)
0.05(.002)
1.20(.047) MAX
0.15(.006)
0.05(.002)
0
5 REF
0.20(.008)
0.10(.004)
0.70(.028)
0.50(.020)
*Controlling dimension: millimeters
16
.630(16.0)
.590(15.0)
.012(.305)
.008(.203)
32T, 32-lead, Plastic Thin Small Outline Package
(TSOP)
Dimensions in Millimeters and (Inches)*
0.50(.020)
BSC
.065(1.65)
.041(1.04)
.110(2.79)
.090(2.29)
AT49F002(N)(T)
0
5 REF
0.20(.008)
0.10(.004)
0.70(.028)
0.50(.020)
Atmel Headquarters
Atmel Operations
Corporate Headquarters
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© Atmel Corporation 1999.
Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warranty which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for
any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without
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