Features
• Single Voltage Operation
•
•
•
•
•
•
•
•
•
– 5V Read
– 5V Programming
Fast Read Access Time - 70 ns
Internal Erase/Program Control
Sector Architecture
– One 8K Words (16K bytes) Boot Block with Programming Lockout
– Two 4K Words (8K bytes) Parameter Blocks
– One 496K Words (992K bytes) Main Memory Array Block
Fast Sector Erase Time - 10 seconds
Byte-by-byte or Word-by-word Programming - 10 µs Typical
Hardware Data Protection
DATA Polling For End Of Program Detection
Low Power Dissipation
– 50 mA Active Current
– 300 µA CMOS Standby Current
Typical 10,000 Write Cycles
8-megabit
(1M x 8/
512K x 16)
Flash Memory
Description
The AT49F008A(T) and AT49F8192A(T) are 5-volt, 8-megabit Flash memories organized as 1,048,576 words of 8 bits each or 512K words of 16 bits each. Manufactured
with Atmel’s advanced nonvolatile CMOS technology, the devices offer access times
to 70 ns with power dissipation of just 275 mW. When deselected, the CMOS standby
current is less than 300 µA.
The device contains a user-enabled “boot block” protection feature. Two versions of
the feature are available: the AT49F008A/8192A locates the boot block at lowest
order addresses (“bottom boot”); the AT49F008AT/8192AT locates it at highest order
addresses (“top boot”).
To allow for simple in-system reprogrammability, the AT49F008A(T)/8192A(T) does
not require high input voltages for programming. Reading data out of the device is
similar to reading from an EPROM; it has standard CE, OE, and WE inputs to avoid
bus contention. Reprogramming the AT49F008A(T)/8192A(T) is performed by first
erasing a block of data and then programming on a byte-by-byte or word-by-word
basis.
(continued)
AT49F008A
AT49F008AT
AT49F8192A
AT49F8192AT
Pin Configurations
Pin Name
Function
A0 - A18
Addresses
CE
Chip Enable
OE
Output Enable
WE
Write Enable
RESET
Reset
RDY/BUSY
Ready/Busy Output
I/O0 - I/O14
Data Inputs/Outputs
I/O15 (A-1)
I/O15 (Data Input/Output, Word Mode)
A-1 (LSB Address Input, Byte Mode)
BYTE
Selects Byte or Word Mode
NC
No Connect
Rev. 1199D–08/99
1
AT49F8192A(T) TSOP Top View
Type 1
A15
A14
A13
A12
A11
A10
A9
A8
NC
NC
WE
RESET
NC
NC
NC
A18
A17
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
2
3
4
5
6
7
8
A8
NC
NC
NC
A7
A4
A
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
B
AT49F008A(T) Standard Pin Definition
CBGA Top View (Ball Down)
3
4
5
6
7
8
A8
NC
NC
NC
A7
A4
A14 A10 WE RST A18 A17
A5
A2
1
2
A14 A10 WE RST A18 A17
A5
A15 A12
A9
NC
NC
A6
A3
A9
NC
NC
A6
A3
A16 I/O14 I/O5 I/O11 I/O2 I/O8 CE
CE
BYTE I/O15 I/O6 I/O12 I/O3 I/O9 I/O0 GND
GND I/O7 I/O13 I/O4 VCC I/O10 I/O1 OE
2
A14 A12
A0
E
F
1
3
4
5
6
7
8
A8
NC
NC
NC
A7
A4
A15 A10 WE RST A19 A18
A5
A2
A16 A13
A6
A3
A1
A17 NC I/O5 NC I/O2 NC
CE
A0
A9
NC
NC
D
A16 NC I/O5 NC I/O2 NC
A0
AT49F008A(T) Alternate Pin Definition
CBGA Top View (Ball Down)
A1
D
E
A17
GND
NC
A-1
A10
I/O7
I/O6
I/O5
I/O4
VCC
VCC
NC
I/O3
I/O2
I/O1
I/O0
OE
GND
CE
A0
C
A15 A12
A1
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
B
C
D
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
A
A13 A11
A2
AT49F008A(T) TSOP Top View
Type 1
A16
A15
A14
A13
A12
A11
A9
A8
WE
RESET
NC
RDY/BUSY
A18
A7
A6
A5
A4
A3
A2
A1
B
C
NC
A-1 I/O6 NC I/O3 NC I/O0 GND
F
GND I/O7 NC I/O4 VCC NC I/O1 OE
E
NC
A11 I/O6 NC I/O3 NC I/O0 GND
F
GND I/O7 NC I/O4 VCC NC I/O1 OE
“•” denotes a white dot marked on the package.
The device is erased by executing the erase command
sequence; the device internally controls the erase operation. The memory is divided into four blocks for erase operations. There are two 4K word parameter block sections,
the boot block, and the main memory array block. The typical number of program and erase cycles is in excess of
10,000 cycles.
The optional 8K word boot block section includes a reprogramming lock out feature to provide data integrity. This
feature is enabled by a command sequence. Once the boot
block programming lockout feature is enabled, the data in
the boot block cannot be changed when input levels of 3.6
2
RESET
WE
A8
A9
A10
A11
A12
A13
A14
A15
A16
BYTE
GND
I/O15
I/O7
I/O14
I/O6
I/O13
I/O5
I/O12
I/O4
VCC
A
A13 A11
Note:
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
NC
A18
A17
A7
A6
A5
A4
A3
A2
A1
A0
CE
GND
OE
I/O0
I/O8
I/O1
I/O9
I/O2
I/O10
I/O3
I/O11
A16
BYTE
GND
I/O15 / A-1
I/O7
I/O14
I/O6
I/O13
I/O5
I/O12
I/O4
VCC
I/O11
I/O3
I/O10
I/O2
I/O9
I/O1
I/O8
I/O0
OE
GND
CE
A0
AT49F8192A(T)
CBGA Top View (Ball Down)
1
AT49F8192A(T) SOIC (SOP) Top View
AT49F008A(T)/8192A(T)
volts or less are used. The boot sector is designed to contain user secure code.
For the AT49F8192A(T), the BYTE pin controls whether
the device data I/O pins operate in the byte or word configuration. If the BYTE pin is set at a logic “1” or left open, the
device is in word configuration, I/O0 - I/O15 are active and
controlled by CE and OE.
If the BYTE pin is set at logic “0”, the device is in byte configuration, and only data I/O pins I/O0 - I/O7 are active and
controlled by CE and OE. The data I/O pins I/O8 - I/O14
are tri-stated and the I/O15 pin is used as an input for the
LSB (A-1) address function.
AT49F008A(T)/8192A(T)
AT49F008A(T) Block Diagram
AT49F008A
VCC
AT49F008AT
DATA INPUTS/OUTPUTS
I/O0 - I/O7
DATA INPUTS/OUTPUTS
I/O0 - I/O7
INPUT/OUTPUT
BUFFERS
INPUT/OUTPUT
BUFFERS
PROGRAM DATA
LATCHES
PROGRAM DATA
LATCHES
GND
OE
WE
CE
RESET
CONTROL
LOGIC
Y DECODER
ADDRESS
INPUTS
X DECODER
Y-GATING
MAIN MEMORY
(992K BYTES)
PARAMETER
BLOCK 2
8K BYTES
PARAMETER
BLOCK 1
8K BYTES
BOOT BLOCK
16K BYTES
Y-GATING
FFFFF
08000
07FFF
06000
05FFF
04000
03FFF
00000
BOOT BLOCK
16K BYTES
PARAMETER
BLOCK 1
8K BYTES
PARAMETER
BLOCK 2
8K BYTES
MAIN MEMORY
(992K BYTES)
FFFFF
FC000
FBFFF
7A000
79FFF
78000
77FFF
00000
AT49F8192A(T) Block Diagram
AT49F8192A
VCC
AT49F8192AT
DATA INPUTS/OUTPUTS
I/O0 - I/O15
DATA INPUTS/OUTPUTS
I/O0 - I/O15
INPUT/OUTPUT
BUFFERS
INPUT/OUTPUT
BUFFERS
PROGRAM DATA
LATCHES
PROGRAM DATA
LATCHES
GND
OE
WE
CE
RESET
CONTROL
LOGIC
Y DECODER
ADDRESS
INPUTS
X DECODER
Y-GATING
Y-GATING
MAIN MEMORY
(496K WORDS)
PARAMETER
BLOCK 2
4K WORDS
PARAMETER
BLOCK 1
4K WORDS
BOOT BLOCK
8K WORDS
7FFFF
04000
03FFF
03000
02FFF
02000
01FFF
00000
BOOT BLOCK
8K WORDS
PARAMETER
BLOCK 1
4K WORDS
PARAMETER
BLOCK 2
4K WORDS
MAIN MEMORY
(496K WORDS)
7FFFF
7E000
7DFFF
7D000
7CFFF
7C000
7BFFF
00000
Device Operation
READ: The AT49F008A(T)/8192A(T) is accessed like an
EPROM. When CE and OE are low and WE is high, the
data stored at the memory location determined by the
address pins is asserted on the outputs. The outputs are
put in the high impedance state whenever CE or OE is
high. This dual-line control gives designers flexibility in preventing bus contention.
COMMAND SEQUENCES: When the device is first powered on it will be reset to the read or standby mode
depending upon the state of the control line inputs. In order
to perform other device functions, a series of command
sequences are entered into the device. The command
sequences are shown in the Command Definitions table
(I/O8 - I/O15 are don’t care inputs for the command codes).
The command sequences are written by applying a low
pulse on the WE or CE input with CE or WE low (respectively) and OE high. The address is latched on the falling
edge of CE or WE, whichever occurs last. The data is
latched by the first rising edge of CE or WE. Standard
microprocessor write timings are used. The address locations used in the command sequences are not affected by
entering the command sequences.
RESET: A RESET input pin is provided to ease some system applications. When RESET is at a logic high level, the
3
device is in its standard operating mode. A low level on the
RESET input halts the present device operation and puts
the outputs of the device in a high impedance state. When
a high level is reasserted on the RESET pin, the device
returns to the Read or Standby mode, depending upon the
state of the control inputs. By applying a 12V ± 0.5V input
signal to the RESET pin the boot block array can be reprogrammed even if the boot block program lockout feature
has been enabled (see Boot Block Programming Lockout
Override section).
ERASURE: Before a byte or word can be reprogrammed, it
must be erased. The erased state of memory bits is a logical “1”. The entire device can be erased by using the Chip
Erase command or individual sectors can be erased by
using the Sector Erase commands.
CHIP ERASE: The entire device can be erased at one time
by using the 6-byte chip erase software code. After the chip
erase has been initiated, the device will internally time the
erase operation so that no external clocks are required.
The maximum time to erase the chip is tEC.
If the boot block lockout has been enabled, the Chip Erase
will not erase the data in the boot block; it will erase the
main memory block and the parameter blocks only. After
the chip erase, the device will return to the read or standby
mode.
SECTOR ERASE: As an alternative to a full chip erase, the
device is organized into four sectors that can be individually
erased. There are two 4K word parameter block sections,
one boot block, and the main memory array block. The
Sector Erase command is a six bus cycle operation. The
sector address is latched on the falling WE edge of the
sixth cycle while the 30H data input command is latched at
the rising edge of WE. The sector erase starts after the rising edge of WE of the sixth cycle. The erase operation is
internally controlled; it will automatically time to completion.
Whenever the main memory block is erased and reprogrammed, the two parameter blocks should be erased and
reprogrammed before the main memory block is erased
again. Whenever a parameter block is erased and reprogrammed, the other parameter block should be erased and
reprogrammed before the first parameter block is erased
again. Whenever the boot block is erased and reprogrammed, the main memory block and the parameter
blocks should be erased and reprogrammed before the
boot block is erased again.
BYTE/WORD PROGRAMMING: Once a memory block is
erased, it is programmed (to a logical “0”) on a byte-by-byte
or word-by-word basis. Programming is accomplished via
the internal device command register and is a 4 bus cycle
operation. The device will automatically generate the
required internal program pulses.
Any commands written to the chip during the embedded
programming cycle will be ignored. If a hardware reset hap-
4
AT49F008A(T)/8192A(T)
pens during programming, the data at the location being
programmed will be corrupted. Please note that a data “0”
cannot be programmed back to a “1”; only erase operations
can convert “0”s to “1”s. Programming is completed after
the specified tBP cycle time. The DATA polling feature may
also be used to indicate the end of a program cycle.
BOOT BLOCK PROGRAMMING LOCKOUT: The device
has one designated block that has a programming lockout
feature. This feature prevents programming of data in the
designated block once the feature has been enabled. The
size of the block is 8K words. This block, referred to as the
boot block, can contain secure code that is used to bring up
the system. Enabling the lockout feature will allow the boot
code to stay in the device while data in the rest of the
device is updated. This feature does not have to be activated; the boot block’s usage as a write protected region is
optional to the user. The address range of the boot block is
00000H to 03FFFH for the AT49F008A; FC000H to
FFFFFH for the AT49F008AT; 00000H to 01FFFH for the
AT49F8192A; and 7E000H to 7FFFFH for the
AT49F8192AT.
Once the feature is enabled, the data in the boot block can
no longer be erased or programmed when input levels of
5.5V or less are used. Data in the main memory block can
still be changed through the regular programming method.
To activate the lockout feature, a series of six program
commands to specific addresses with specific data must be
performed. Please refer to the Command Definitions table.
BOOT BLOCK LOCKOUT DETECTION: A software
method is available to determine if programming of the boot
block section is locked out. When the device is in the software product identification mode (see Software Product
Identification Entry and Exit sections) a read from the following address location will show if programming the boot
block is locked out—00002H for the AT49F008A and
AT49F8192A; FC002H for the AT49F008AT; and 7E002H
for the AT49F8192AT. If the data on I/O0 is low, the boot
block can be programmed; if the data on I/O0 is high, the
program lockout feature has been enabled and the block
cannot be programmed. The software product identification
exit code should be used to return to standard operation.
BOOT BLOCK PROGRAMMING LOCKOUT OVERRIDE:
The user can override the boot block programming lockout
by taking the RESET pin to 12 volts during the entire chip
erase, sector erase or word programming operation. When
the RESET pin is brought back to TTL levels the boot block
programming lockout feature is again active.
PRODUCT IDENTIFICATION: The product identification
mode identifies the device and manufacturer as Atmel. It
may be accessed by hardware or software operation. The
hardware operation mode can be used by an external programmer to identify the correct programming algorithm for
the Atmel product.
AT49F008A(T)/8192A(T)
For details, see Operating Modes (for hardware operation)
or Software Product Identification. The manufacturer and
device code is the same for both modes.
DATA POLLING: The AT49F008A(T)/8192A(T) features
DATA polling to indicate the end of a program cycle. During
a program cycle an attempted read of the last byte loaded
will result in the complement of the loaded data on I/O7.
Once the program cycle has been completed, true data is
valid on all outputs and the next cycle may begin. During a
chip or sector erase operation, an attempt to read the
device will give a “0” on I/O7. Once the program or erase
cycle has completed, true data will be read from the device.
DATA polling may begin at any time during the program
cycle.
T O G G L E B I T : I n a d d i t i o n t o D ATA p o l l i n g t h e
AT49F008A(T)/8192A(T) provides another method for
determining the end of a program or erase cycle. During a
program or erase operation, successive attempts to read
data from the device will result in I/O6 toggling between
one and zero. Once the program cycle has completed, I/O6
will stop toggling and valid data will be read. Examining the
toggle bit may begin at any time during a program cycle.
READY/BUSY: For the AT49F008A(T), pin 12 is an open
drain READY/BUSY output pin which provides another
method of detecting the end of a program or erase operation. RDY/BUSY is actively pulled low during the internal
program and erase cycles and it is released at the completion of the cycle. The open drain connection allows for ORtying of several devices to the same RDY/BUSY line.
HARDWARE DATA PROTECTION: Hardware features
protect against inadvertent programs to the
AT49F008A(T)/8192A(T) in the following ways: (a) V CC
sense: if VCC is below 3.8V (typical), the program function
is inhibited. (b) VCC power on delay: once VCC has reached
the VCC sense level, the device will automatically time out
10 ms (typical) before programming. (c) Program inhibit:
holding any one of OE low, CE high or WE high inhibits
program cycles. (d) Noise filter: pulses of less than 15 ns
(typical) on the WE or CE inputs will not initiate a program
cycle.
AT49F008A(T) ALTERNATE PIN DEFINITION: Two
AT49F008A(T) BGA pin definitions are shown. The standard pin definition allows use of the JEDEC standard programming algorithm. If the alternate pin definition is used,
the programming algorithm must be modified as shown in
the Command Definition for Alternate Pin Definition Table
on page 7.
5
Command Definition in Hex(1)
Command
Sequence
1st Bus
Cycle
Bus
Cycles
Addr
Data
Read
1
Addr
DOUT
Chip Erase
6
5555
AA
2nd Bus
Cycle
3rd Bus
Cycle
4th Bus
Cycle
Data
Addr
Data
Addr
Data
Addr
Data
Addr
Data
2AAA
55
5555
80
5555
AA
2AAA
55
5555
10
2AAA
55
(4)
SA
30
2AAA
55
5555
40
6
5555
AA
2AAA
55
5555
80
5555
AA
Byte/Word Program
4
5555
AA
2AAA
55
5555
A0
Addr
DIN
Boot Block Lockout(2)
6
5555
AA
2AAA
55
5555
80
5555
AA
Product ID Entry
3
5555
AA
2AAA
55
5555
90
(3)
3
5555
AA
2AAA
55
5555
F0
(3)
1
xxxx
F0
Product ID Exit
Notes:
6th Bus
Cycle
Addr
Sector Erase
Product ID Exit
5th Bus
Cycle
1. The DATA FORMAT in each bus cycle is as follows: I/O15 - I/O8 (Don’t Care); I/O7 - I/O0 (Hex)
The ADDRESS FORMAT in each bus cycle is as follows: A15 - A0 (Hex), A-1, and A15 - A18 (Don’t Care)
2. The boot sector has the address range 00000H to 03FFFH for the AT49F008A; FC000H to FFFFFH for the
AT49F008AT; 00000H to 01FFFH for the AT49F8192A; and 7E000H to 7FFFFH for the AT49F8192AT.
3. Either one of the Product ID Exit commands can be used.
4. SA = sector addresses: (A0 - A18)
For the AT49F008A/8192A
SA = 01XXX for BOOT BLOCK
SA = 02XXX for PARAMETER BLOCK 1
SA = 03XXX for PARAMETER BLOCK 2
SA = 7FXXX for MAIN MEMORY ARRAY
For the AT49F008AT/8192AT
SA = 7FXXX for BOOT BLOCK
SA = 7DXXX for PARAMETER BLOCK 1
SA = 7CXXX for PARAMETER BLOCK 2
SA = 7BXXX for MAIN MEMORY ARRAY
Absolute Maximum Ratings*
Temperature Under Bias................................ -55°C to +125°C
Storage Temperature ..................................... -65°C to +150°C
All Input Voltages
(including NC Pins)
with Respect to Ground ...................................-0.6V to +6.25V
All Output Voltages
with Respect to Ground .............................-0.6V to VCC + 0.6V
Voltage on RESET
with Respect to Ground ...................................-0.6V to +13.5V
6
AT49F008A(T)/8192A(T)
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
AT49F008A(T)/8192A(T)
Command Definition (in Hex) for Alternate Pin Definition of AT49F008A(T)(1)
Command
Sequence
1st Bus
Cycle
Bus
Cycles
Addr
Data
Read
1
Addr
DOUT
Chip Erase
6
A555
AA
2nd Bus
Cycle
3rd Bus
Cycle
4th Bus
Cycle
Data
Addr
Data
Addr
Data
Addr
Data
Addr
Data
5AAA
55
A555
80
A555
AA
5AAA
55
A555
10
5AAA
55
(4)
SA
30
5AAA
55
A555
40
6
A555
AA
5AAA
55
A555
80
A555
AA
Byte/Word Program
4
A555
AA
5AAA
55
A555
A0
Addr
DIN
Boot Block Lockout(2)
6
A555
AA
5AAA
55
A555
80
A555
AA
Product ID Entry
3
A555
AA
5AAA
55
A555
90
(3)
3
A555
AA
5AAA
55
A555
F0
(3)
1
xxxx
F0
Product ID Exit
Notes:
6th Bus
Cycle
Addr
Sector Erase
Product ID Exit
5th Bus
Cycle
1. The DATA FORMAT in each bus cycle is as follows: I/O15 - I/O8 (Don’t Care); I/O7 - I/O0 (Hex)
The ADDRESS FORMAT in each bus cycle is as follows: A15 - A0 (Hex), A-1, and A15 - A18 (Don’t Care)
2. The boot sector has the address range 00000H to 03FFFH for the AT49F008A; FC000H to FFFFFH for the
AT49F008AT; 00000H to 01FFFH for the AT49F8192A; and 7E000H to 7FFFFH for the AT49F8192AT.
3. Either one of the Product ID Exit commands can be used.
4. SA = sector addresses: (A0 - A18)
For the AT49F008A/8192A
SA = 02XXX for BOOT BLOCK
SA = 04XXX for PARAMETER BLOCK 1
SA = 06XXX for PARAMETER BLOCK 2
SA = FEXXX for MAIN MEMORY ARRAY
For the AT49F008AT/8192AT
SA = FEXXX for BOOT BLOCK
SA = FAXXX for PARAMETER BLOCK 1
SA = 78XXX for PARAMETER BLOCK 2
SA = 76XXX for MAIN MEMORY ARRAY
Absolute Maximum Ratings*
Temperature Under Bias................................ -55°C to +125°C
Storage Temperature ..................................... -65°C to +150°C
All Input Voltages
(including NC Pins)
with Respect to Ground ...................................-0.6V to +6.25V
All Output Voltages
with Respect to Ground .............................-0.6V to VCC + 0.6V
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
Voltage on RESET
with Respect to Ground ...................................-0.6V to +13.5V
7
DC and AC Operating Range
Operating
Temperature (Case)
AT49F008A(T)/8192A(T)-70
AT49F008A(T)/8192A(T)-90
AT49F008A(T)/8192A(T)-120
0°C - 70°C
0°C - 70°C
0°C - 70°C
-40°C - 85°C
-40°C - 85°C
-40°C - 85°C
Com.
Ind.
5V ± 10%
VCC Power Supply
5V
± 10%
5V ± 10%
Operating Modes
Mode
CE
OE
WE
RESET
Ai
I/O
VIL
VIL
VIH
VIH
Ai
DOUT
VIL
VIH
VIL
VIH
Ai
DIN
VIH
X(1)
X
VIH
X
High Z
Program Inhibit
X
X
VIH
VIH
Program Inhibit
X
VIL
X
VIH
Output Disable
X
VIH
X
VIH
Reset
X
X
X
VIL
Read
Program/Erase
(2)
Standby/Program
Inhibit
High Z
X
High Z
Product Identification
Hardware
VIL
VIL
VIH
Software(5)
Notes:
VIH
VIH
A1 - A18 = VIL, A9 = VH,(3)
A0 = VIL
Manufacturer Code(4)
A1 - A18 = VIL, A9 = VH,(3)
A0 = VIH
Device Code(4)
A0 = VIL, A1 - A18 = VIL
Manufacturer Code(4)
A0 = VIH, A1 - A18 = VIL
Device Code(4)
1. X can be VIL or VIH.
2. Refer to AC Programming Waveforms.
3. VH = 12.0V ± 0.5V.
4. Manufacturer Code: 1FH
Device Code: 22H (AT49F008A), A0H (AT49F8192A), 21H (AT49F008AT), A3H (AT49F8192AT).
5. See details under Software Product Identification Entry/Exit.
DC Characteristics
Symbol
Parameter
Condition
ILI
Input Load Current
ILO
Max
Units
VIN = 0V to VCC
10
µA
Output Leakage Current
VI/O = 0V to VCC
10
µA
ISB1
VCC Standby Current CMOS
CE = VCC - 0.3V to VCC
300
µA
ISB2
VCC Standby Current TTL
CE = 2.0V to VCC
3
mA
ICC(1)
VCC Active Current
f = 5 MHz; IOUT = 0 mA
50
mA
VIL
Input Low Voltage
0.8
V
VIH
Input High Voltage
VOL
Output Low Voltage
IOL = 2.1 mA
VOH
Output High Voltage
IOH = -400 µA
Note:
1. In the erase mode, ICC is 90 mA.
8
AT49F008A(T)/8192A(T)
Min
2.0
V
0.45
2.4
V
V
AT49F008A(T)/8192A(T)
AC Read Characteristics
AT49F008A(T)/8192A(T)-70
Min
AT49F008A(T)/8192A(T)-90
Symbol
Parameter
Max
Min
tACC
Address to
Output Delay
70
tCE(1)
CE to Output Delay
70
tOE(2)
OE to Output Delay
0
30
0
40
tDF(3)(4)
CE or OE to Output Float
0
25
0
25
tOH
Output Hold from OE,
CE or Address,
whichever occurred first
0
tRO
RESET to Output Delay
AT49F008A(T)/8192A(T)-120
Max
Min
Max
Units
90
120
ns
90
120
ns
0
50
ns
0
30
ns
0
0
800
ns
800
800
ns
AC Read Waveforms(1)(2)(3)(4)
ADDRESS
ADDRESS VALID
CE
t
CE
t
OE
OE
t
DF
t
t
OH
ACC
t
RO
RESET
OUTPUT
Notes:
HIGH Z
OUTPUT
VALID
1.
CE may be delayed up to tACC - tCE after the address transition without impact on tACC.
2.
OE may be delayed up to tCE - tOE after the falling edge of CE without impact on tCE or by tACC - tOE after an address change
without impact on tACC.
3.
tDF is specified from OE or CE whichever occurs first (CL = 5 pF).
4.
This parameter is characterized and is not 100% tested.
Input Test Waveforms and Measurement Level
Output Test Load
3.0V
5.0V
0.0V
tR, tF < 5 ns
Pin Capacitance
f = 1 MHz, T = 25°C(1)
Typ
Max
Units
CIN
4
6
pF
VIN = 0V
COUT
8
12
pF
VOUT = 0V
Note:
Conditions
1. This parameter is characterized and is not 100% tested.
9
AC Word Load Characteristics
Symbol
Parameter
tAS, tOES
Address, OE Set-up Time
10
ns
tAH
Address Hold Time
100
ns
tCS
Chip Select Set-up Time
0
ns
tCH
Chip Select Hold Time
0
ns
tWP
Write Pulse Width (WE or CE)
100
ns
tDS
Data Set-up Time
100
ns
tDH, tOEH
Data, OE Hold Time
10
ns
tWPH
Write Pulse Width High
50
ns
AC Byte/Word Load Waveforms
WE Controlled
CE Controlled
10
AT49F008A(T)/8192A(T)
Min
Max
Units
AT49F008A(T)/8192A(T)
Program Cycle Characteristics
Symbol
Parameter
Min
tBP
Byte/Word Programming Time
tAS
Address Set-up Time
tAH
Typ
Max
Units
10
50
µs
0
ns
Address Hold Time
100
ns
tDS
Data Set-up Time
100
ns
tDH
Data Hold Time
0
ns
tWP
Write Pulse Width
100
ns
tWPH
Write Pulse Width High
50
ns
tEC
Erase Cycle Time
10
seconds
Program Cycle Waveforms
PROGRAM CYCLE
OE
CE
t WP
t BP
t WPH
WE
t
AS
A0-A18
t DH
t AH
5555
5555
2AAA
5555
ADDRESS
t DS
55
AA
DATA
A0
AA
INPUT DATA
Sector or Chip Erase Cycle Waveforms
OE
(1)
CE
t WP
t WPH
WE
t AS
A0-A18
t DH
t AH
5555
5555
5555
2AAA
Note 2
2AAA
t EC
t DS
DATA
AA
BYTE/
WORD 0
Notes:
55
BYTE/
WORD 1
80
BYTE/
WORD 2
AA
BYTE/
WORD 3
55
Note 3
BYTE/
WORD 4
BYTE/
WORD 5
1.
OE must be high only when WE and CE are both low.
2.
For chip erase, the address should be 5555. For sector erase, the address depends on what sector is to be erased.
(See note 4 under command definitions.)
3.
For chip erase, the data should be 10H, and for sector erase, the data should be 30H.
11
Data Polling Characteristics(1)
Symbol
Parameter
tDH
Data Hold Time
tOEH
OE Hold Time
Min
Max
OE to Output Delay
tWR
Write Recovery Time
Units
10
ns
10
ns
(2)
tOE
Notes:
Typ
ns
0
ns
1. These parameters are characterized and not 100% tested.
2. See tOE spec in AC Read Characteristics.
Data Polling Waveforms
Toggle Bit Characteristics(1)
Symbol
Parameter
tDH
Data Hold Time
tOEH
OE Hold Time
Min
OE to Output Delay
tOEHP
OE High Pulse
tWR
Notes:
Write Recovery Time
Max
Units
10
ns
10
ns
(2)
tOE
Typ
ns
150
ns
0
ns
1. These parameters are characterized and not 100% tested.
2. See tOE spec in AC Read Characteristics.
Toggle Bit Waveforms(1)(2)(3)
Notes:
12
1.
Toggling either OE or CE or both OE and CE will operate toggle bit. The tOEHP specification must be met by the toggling
input(s).
2.
Beginning and ending state of I/O6 will vary.
3.
Any address location may be used but the address should not vary.
AT49F008A(T)/8192A(T)
AT49F008A(T)/8192A(T)
Software Product Identification Entry(1)
LOAD DATA AA
TO
ADDRESS 5555(7)
Boot Block
Lockout Enable Algorithm(1)
LOAD DATA AA
TO
ADDRESS 5555(3)
LOAD DATA 55
TO
ADDRESS 2AAA(7)
LOAD DATA 55
TO
ADDRESS 2AAA(3)
LOAD DATA 90
TO
ADDRESS 5555(7)
LOAD DATA 80
TO
ADDRESS 5555(3)
ENTER PRODUCT
IDENTIFICATION
MODE(2)(3)(5)
LOAD DATA AA
TO
ADDRESS 5555(3)
Software Product Identification Exit(1)(6)
LOAD DATA AA
TO
ADDRESS 5555(7)
LOAD DATA 55
TO
ADDRESS 2AAA(7)
OR
LOAD DATA 55
TO
ADDRESS 2AAA(3)
LOAD DATA F0
TO
ANY ADDRESS
LOAD DATA 40
TO
ADDRESS 5555(3)
EXIT PRODUCT
IDENTIFICATION
MODE(4)
PAUSE 1 second(2)
LOAD DATA F0
TO
ADDRESS 5555(7)
EXIT PRODUCT
IDENTIFICATION
MODE(4)
Notes:
1.
Data Format: I/O15 - I/O8 (Don’t Care); I/O7 - I/O0 (Hex)
Address Format: A15 - A0 (Hex), A-1, and A15 - A18
(Don’t Care).
2.
A1 - A18 = VIL.
Manufacture Code is read for A0 = VIL;
Device Code is read for A0 = VIH.
3.
The device does not remain in identification mode if
powered down.
4.
The device returns to standard operation mode.
5.
Manufacturer Code: 1FH
Device Code: 22H (AT49F008A), A0H (AT49F8192A),
21H (AT49F008AT), A3H (AT49F8192AT)
6.
Either one of the Product ID Exit commands can be used.
7.
If the alternate pin definition is used,
5555 should be replaced with A555,
2AAA should be replaced with 5AAA.
Notes:
1.
Data Format: I/O15 - I/O8 (Don’t Care); I/O7 - I/O0 (Hex)
Address Format: A15 - A0 (Hex), A-1, and A15 - A18
(Don’t Care).
2.
Boot block lockout feature enabled.
3.
If the alternate pin definition is used,
5555 should be replaced with A555,
2AAA should be replaced with 5AAA.
13
AT49F008A(T) Ordering Information
tACC
(ns)
70
90
120
70
90
120
ICC (mA)
Standby
Active
50
50
50
50
50
50
0.3
0.3
0.3
0.3
0.3
0.3
Ordering Code
Package
AT49F008A-70TC
AT49F008A-70CC
40T
48C1
Commercial
(0° to 70°C)
AT49F008A-70TI
AT49F008A-70CI
40T
48C1
Industrial
(-40° to 85°C)
AT49F008A-90TC
AT49F008A-90CC
40T
48C1
Commercial
(0° to 70°C)
AT49F008A-90TI
AT49F008A-90CI
40T
48C1
Industrial
(-40° to 85°C)
AT49F008A-12TC
AT49F008A-12CC
40T
48C1
Commercial
(0° to 70°C)
AT49F008A-12TI
AT49F008A-12CI
40T
48C1
Industrial
(-40° to 85°C)
AT49F008AT-70TC
AT49F008AT-70CC
40T
48C1
Commercial
(0° to 70°C)
AT49F008AT-70TI
AT49F008AT-70CI
40T
48C1
Industrial
(-40° to 85°C)
AT49F008AT-90TC
AT49F008AT-90CC
40T
48C1
Commercial
(0° to 70°C)
AT49F008AT-90TI
AT49F008AT-90CI
40T
48C1
Industrial
(-40° to 85°C)
AT49F008AT-12TC
AT49F008AT-12CC
40T
48C1
Commercial
(0° to 70°C)
AT49F008AT-12TI
AT49F008AT-12CI
40T
48C1
Industrial
(-40° to 85°C)
Package Type
40T
40-Lead, Plastic Thin Small Outline Package (TSOP)
48C1
48-Ball, Chip-Size Ball Grid Array Package (CBGA)
14
AT49F008A(T)/8192A(T)
Operation Range
AT49F008A(T)/8192A(T)
AT49F8192A(T) Ordering Information
ICC (mA)
tACC
(ns)
Active
Standby
70
50
0.3
90
120
70
90
120
50
50
50
50
50
0.3
0.3
0.3
0.3
0.3
Ordering Code
Package
AT49F8192A-70TC
AT49F8192A-70CC
AT49F8192A-70RC
48T
48C1
44R
Operation Range
Commercial
(0° to 70°C)
AT49F8192A-70TI
AT49F8192A-70CI
AT49F8192A-70RI
48T
48C1
44R
Industrial
(-40° to 85°C)
AT49F8192A-90TC
AT49F8192A-90CC
AT49F8192A-90RC
48T
48C1
44R
Commercial
(0° to 70°C)
AT49F8192A-90TI
AT49F8192A-90CI
AT49F8192A-90RI
48T
48C1
44R
Industrial
(-40° to 85°C)
AT49F8192A-12TC
AT49F8192A-12CC
AT49F8192A-12RC
48T
48C1
44R
Commercial
(0° to 70°C)
AT49F8192A-12TI
AT49F8192A-12CI
AT49F8192A-12RI
48T
48C1
44R
Industrial
(-40° to 85°C)
AT49F8192AT-70TC
AT49F8192AT-70CC
AT49F8192AT-70RC
48T
48C1
44R
Commercial
(0° to 70°C)
AT49F8192AT-70TI
AT49F8192AT-70CI
AT49F8192AT-70RI
48T
48C1
44R
Industrial
(-40° to 85°C)
AT49F8192AT-90TC
AT49F8192AT-90CC
AT49F8192AT-90RC
48T
48C1
44R
Commercial
(0° to 70°C)
AT49F8192AT-90TI
AT49F8192AT-90CI
AT49F8192AT-90RI
48T
48C1
44R
Industrial
(-40° to 85°C)
AT49F8192AT-12TC
AT49F8192AT-12CC
AT49F8192AT-12RC
48T
48C1
44R
Commercial
(0° to 70°C)
AT49F8192AT-12TI
AT49F8192AT-12CI
AT49F8192AT-12RI
48T
48C1
44R
Industrial
(-40° to 85°C)
Package Type
48T
48-Lead, Plastic Thin Small Outline Package (TSOP)
48C1
48-Ball, Chip-Size Ball Grid Array Package (CBGA)
44R
44-lead, 0.525" Wide, Plastic Gull Wing Small Outline Package (SOIC)
15
Packaging Information
40T, 40-Lead, Plastic Thin Small Outline Package
(TSOP)
Dimensions in Inches and (Millimeters)*
48T, 48-Lead, Plastic Thin Small Outline Package
(TSOP)
Dimensions in Millimeters and (Inches)*
JEDEC OUTLINE MO-142 D
*Controlling dimension: millimeters
*Controlling dimension: millimeters
48C1, 48-Ball, Chip-Size Ball Grid Array Package
(CBGA)
Dimensions in Millimeters
44R, 44-lead, 0.525" Wide, Plastic Gull Wing Small
Outline Package (SOIC)
Dimensions in Inches and (Millimeters)
7.2 (0.283)
6.8 (0.268)
7.2 (0.283)
6.8 (0.268)
0.25 (0.010)
1.25 (0.049) MAX
1.0 (0.040)
0.74 (0.029)
5.25 (0.207)
8
7
6
5
4
3
2
1
1.75 (0.69)
1.48 (0.58)
A
B
C
3.75 (0.148)
D
E
F
0.75 (0.030) BSC
NON-ACCUMULATIVE
16
0.30 (0.012)
DIA BALL TYP
AT49F008A(T)/8192A(T)
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© Atmel Corporation 1999.
Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warranty which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for
any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without
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