Features
• Single Voltage Operation
•
•
•
•
•
•
•
•
•
•
– 5V Read
– 5V Reprogramming
Fast Read Access Time – 55 ns
Internal Program Control and Timer
8K Bytes Boot Block With Lockout
Fast Erase Cycle Time – 10 Seconds
Byte-by-byte Programming – 10 µs/Byte
Hardware Data Protection
DATA Polling For End of Program Detection
Low Power Dissipation
– 30 mA Active Current
– 100 µA CMOS Standby Current
Typical 10,000 Write Cycles
Green (Pb/Halide-free) Packaging Option
512K (64K x 8)
5-volt Only
Flash Memory
AT49F512
1. Description
The AT49F512 is a 5-volt-only in-system programmable and erasable Flash memory.
Its 512K of memory is organized as 65,536 words by 8 bits. Manufactured with
Atmel’s advanced nonvolatile CMOS technology, the devices offer access times to
55 ns with a power dissipation of just 165 mW over the commercial temperature
range. When the device is deselected, the CMOS standby current is less than 100 µA.
To allow for simple in-system reprogrammability, the AT49F512 does not require high
input voltages for programming. Five-volt-only commands determine the read and
programming operation of the device. Reading data out of the device is similar to
reading from an EPROM. Reprogramming the AT49F512 is performed by erasing the
entire 512K of memory and then programming on a byte-by-byte basis. The typical
byte programming time is a fast 10 µs. The end of a program cycle can be optionally
detected by the DATA polling feature. Once the end of a byte program cycle has been
detected, a new access for a read or program can begin. The typical number of program and erase cycles is in excess of 10,000 cycles.
The optional 8K bytes boot block section includes a reprogramming write lock out feature to provide data integrity. The boot sector is designed to contain user secure code,
and when the feature is enabled, the boot sector is permanently protected from being
reprogrammed.
1027F–FLASH–3/05
2. Pin Configurations
Function
A0 - A15
Addresses
CE
Chip Enable
OE
Output Enable
WE
Write Enable
I/O0 - I/O7
Data Inputs/Outputs
NC
No Connect
32-lead PLCC Top View
29
28
27
26
25
24
23
22
21
14
15
16
17
18
19
20
5
6
7
8
9
10
11
12
13
A14
A13
A8
A9
A11
OE
A10
CE
I/O7
I/O1
I/O2
GND
I/O3
I/O4
I/O5
I/O6
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
4
3
2
1
32
31
30
A12
A15
NC
NC
VCC
WE
NC
2.1
Pin Name
2.2
32-lead VSOP Top View (8 x 14 mm) or 32-lead TSOP (Type 1)Top View (8 x 20 mm)
A11
A9
A8
A13
A14
NC
WE
VCC
NC
NC
A15
A12
A7
A6
A5
A4
2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
A1
A2
A3
AT49F512
1027F–FLASH–3/05
AT49F512
3. Block Diagram
FFFFH
2000H
1FFFH
0000H
4. Device Operation
4.1
Read
The AT49F512 is accessed like an EPROM. When CE and OE are low and WE is high, the data
stored at the memory location determined by the address pins is asserted on the outputs. The
outputs are put in the high impedance state whenever CE or OE is high. This dual-line control
gives designers flexibility in preventing bus contention.
4.2
Erasure
Before a byte can be reprogrammed, the 64K bytes memory array (or 56K bytes if the boot block
featured is used) must be erased. The erased state of the memory bits is a logical “1”. The entire
device can be erased at one time by using a 6-byte software code. The chip erase code consists
of 6-byte load commands to specific address locations with a specific data pattern (please refer
to the Chip Erase Cycle Waveforms).
After the chip erase has been initiated, the device will internally time the erase operation so that
no external clocks are required. The maximum time needed to erase the whole chip is tEC. If the
boot block lockout feature has been enabled, the data in the boot sector will not be erased.
4.3
Byte Programming
Once the memory array is erased, the device is programmed (to a logical “0”) on a byte-by-byte
basis. Please note that a data “0” cannot be programmed back to a “1”; only erase operations
can convert “0”s to “1”s. Programming is accomplished via the internal device command register
and is a 4 bus cycle operation (please refer to the Command Definitions table). The device will
automatically generate the required internal program pulses.
The program cycle has addresses latched on the falling edge of WE or CE, whichever occurs
last, and the data latched on the rising edge of WE or CE, whichever occurs first. Programming
is completed after the specified tBP cycle time. The DATA polling feature may also be used to
indicate the end of a program cycle.
3
1027F–FLASH–3/05
4.4
Boot Block Programming Lockout
The device has one designated block that has a programming lockout feature. This feature prevents programming of data in the designated block once the feature has been enabled. The size
of the block is 8K bytes. This block, referred to as the boot block, can contain secure code that is
used to bring up the system. Enabling the lockout feature will allow the boot code to stay in the
device while data in the rest of the device is updated. This feature does not have to be activated;
the boot block’s usage as a write protected region is optional to the user. The address range of
the boot block is 0000H to 1FFFH.
Once the feature is enabled, the data in the boot block can no longer be erased or programmed.
Data in the main memory block can still be changed through the regular programming method.
To activate the lockout feature, a series of six program commands to specific addresses with
specific data must be performed. Please refer to the Command Definitions table.
4.4.1
4.5
Boot Block Lockout Detection
A software method is available to determine if programming of the boot block section is locked
out. When the device is in the software product identification mode (see Software Product Identification Entry and Exit sections) a read from address location 00002H will show if programming
the boot block is locked out. If the data on I/O0 is low, the boot block can be programmed; if the
data on I/O0 is high, the program lockout feature has been activated and the block cannot be
programmed. The software product identification code should be used to return to standard
operation.
Product Identification
The product identification mode identifies the device and manufacturer as Atmel. It may be
accessed by hardware or software operation. The hardware operation mode can be used by an
external programmer to identify the correct programming algorithm for the Atmel product.
For details, see Operating Modes (for hardware operation) or Software Product Identification.
The manufacturer and device code is the same for both modes.
4.6
DATA Polling
The AT49F512 features DATA polling to indicate the end of a program cycle. During a program
cycle an attempted read of the last byte loaded will result in the complement of the loaded data
on I/O7. Once the program cycle has been completed, true data is valid on all outputs and the
next cycle may begin. DATA polling may begin at any time during the program cycle.
4.7
Toggle Bit
In addition to DATA polling the AT49F512 provides another method for determining the end of a
program or erase cycle. During a program or erase operation, successive attempts to read data
from the device will result in I/O6 toggling between one and zero. Once the program cycle has
completed, I/O6 will stop toggling and valid data will be read. Examining the toggle bit may begin
at any time during a program cycle.
4.8
Hardware Data Protection
Hardware features protect against inadvertent programs to the AT49F512 in the following ways:
(a) V CC sense: if VCC is below 3.8V (typical), the program function is inhibited. (b) Program
inhibit: holding any one of OE low, CE high or WE high inhibits program cycles. (c) Noise filter:
Pulses of less than 15 ns (typical) on the WE or CE inputs will not initiate a program cycle.
4
AT49F512
1027F–FLASH–3/05
AT49F512
5. Command Definition Table
Command
Sequence
1st Bus
Cycle
Bus
Cycles
Addr
Data
Read
1
Addr
DOUT
Chip Erase
6
5555
Byte Program
4
Boot Block
Lockout(1)
2nd Bus
Cycle
3rd Bus
Cycle
4th Bus
Cycle
5th Bus
Cycle
6th Bus
Cycle
Addr
Data
Addr
Data
Addr
Data
Addr
Data
Addr
Data
AA
2AAA
55
5555
80
5555
AA
2AAA
55
5555
10
5555
AA
2AAA
55
5555
A0
Addr
DIN
6
5555
AA
2AAA
55
5555
80
5555
AA
2AAA
55
5555
40
Product ID
Entry
3
5555
AA
2AAA
55
5555
90
Product ID
Exit(2)
3
5555
AA
2AAA
55
5555
F0
Product ID
Exit(2)
1
XXXX
F0
Notes:
1. The 8K byte boot sector has the address range 0000H to 1FFFH.
2. Either one of the Product ID exit commands can be used.
6. Absolute Maximum Ratings*
Temperature Under Bias................................ -55°C to +125°C
Storage Temperature ..................................... -65°C to +150°C
All Input Voltages
(including NC pins)
with Respect to Ground ...................................-0.6V to +6.25V
All Output Voltages
with Respect to Ground .............................-0.6V to VCC + 0.6V
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
Voltage on OE
with Respect to Ground ...................................-0.6V to +13.5V
5
1027F–FLASH–3/05
7. DC and AC Operating Range
AT49F512-55
Industrial Operating Temperature (Case)
-40°C - 85°C
VCC Power Supply
5V ± 10%
8. Operating Modes
Mode
Read
Program
(2)
Standby/Write Inhibit
CE
OE
WE
Ai
I/O
VIL
VIL
VIH
Ai
DOUT
VIL
VIH
VIL
Ai
DIN
X
High Z
(1)
VIH
X
X
Program Inhibit
X
X
VIH
Program Inhibit
X
VIL
X
Output Disable
X
VIH
X
VIL
VIL
VIH
High Z
Product Identification
Hardware
A1 - A15 = VIL, A9 = VH, A0 = VIL(3)
Manufacturer Code(4)
A1 - A15 = VIL, A9 = VH, A0 = VIH(3)
Device Code(4)
A0 = VIL, A1 - A15 = VIL
Manufacturer Code(4)
A0 = VIH, A1 - A15 = VIL
Device Code(4)
Software(5)
Notes:
1. X can be VIL or VIH.
2. Refer to AC Programming Waveforms.
3. VH = 12.0V ± 0.5V.
4. Manufacturer Code: 1FH, Device Code: 03H
5. See details under Software Product Identification Entry/Exit.
9. DC Characteristics
Symbol
Parameter
Condition
ILI
Input Load Current
ILO
Max
Units
VIN = 0V to VCC
10
µA
Output Leakage Current
VI/O = 0V to VCC
10
µA
Com.
100
µA
ISB1
VCC Standby Current CMOS
CE = VCC - 0.3V to VCC
Ind.
300
µA
ISB2
VCC Standby Current TTL
CE = 2.0V to VCC
3
mA
ICC(1)
Com.
30
mA
VCC Active Current
f = 5 MHz; IOUT = 0 mA
Ind.
40
mA
VIL
Input Low Voltage
0.8
V
VIH
Input High Voltage
VOL
Output Low Voltage
IOL = 2.1 mA
VOH1
Output High Voltage
IOH = -400 µA
2.4
V
VOH2
Output High Voltage CMOS
IOH = -100 µA; VCC = 4.5V
4.2
V
Note:
6
Min
2.0
V
0.45
V
1. In the erase mode, ICC is 90 mA.
AT49F512
1027F–FLASH–3/05
AT49F512
10. AC Read Characteristics
AT49F512-55
Symbol
Parameter
tACC
Min
Max
Units
Address to Output Delay
55
ns
(1)
CE to Output Delay
55
ns
tOE(2)
OE to Output Delay
30
ns
tDF(3)(4)
CE or OE to Output Float
0
25
ns
tOH
Output Hold from OE, CE or Address, whichever occurred first
0
tCE
ns
11. AC Read Waveforms(1)(2)(3)(4)
Notes:
1. CE may be delayed up to tACC - tCE after the address transition without impact on tACC.
2. OE may be delayed up to tCE - tOE, after the falling edge of CE without impact on tCE or by tACC - tOE after an address change
without impact on tACC.
3. tDF is specified from OE or CE whichever occurs first (CL = 5 pF).
4. This parameter is characterized and is not 100% tested.
7
1027F–FLASH–3/05
12. Input Test Waveforms and Measurement Level
tR, tF < 5 ns
13. Output Test Load
14. Pin Capacitance
f = 1 MHz, T= 25°C(1)
Symbol
Typ
Max
Units
Conditions
CIN
4
6
pF
VIN = 0V
COUT
8
12
pF
VOUT = 0V
Note:
8
1. This parameter is characterized and is not 100% tested.
AT49F512
1027F–FLASH–3/05
AT49F512
15. AC Word Load Characteristics
Symbol
Parameter
Min
Max
Units
tAS, tOES
Address, OE Set-up Time
0
ns
tAH
Address Hold Time
50
ns
tCS
Chip Select Set-up Time
0
ns
tCH
Chip Select Hold Time
0
ns
tWP
Write Pulse Width (WE or CE)
90
ns
tDS
Data Set-up Time
50
ns
tDH, tOEH
Data, OE Hold Time
0
ns
tWPH
Write Pulse Width High
90
ns
16. AC Byte Load Waveforms
16.1
WE Controlled
16.2
CE Controlled
9
1027F–FLASH–3/05
17. Program Cycle Characteristics
Symbol
Parameter
Min
Typ
Max
Units
tBP
Byte Programming Time
10
50
µs
tAS
Address Set-up Time
0
ns
tAH
Address Hold Time
50
ns
tDS
Data Set-up Time
50
ns
tDH
Data Hold Time
0
ns
tWP
Write Pulse Width
90
ns
tWPH
Write Pulse Width High
90
ns
tEC
Erase Cycle Time
10
seconds
18. Program Cycle Waveforms
PROGRAM CYCLE
OE
CE
t
t
WP
t
WPH
BP
WE
t
t
AH
AS
A0-A15
t
5555
5555
2AAA
t
DATA
DH
ADDRESS
DS
55
AA
INPUT
DATA
A0
19. Chip Erase Cycle Waveforms
OE
CE
t
t
WP
WPH
WE
t
AS
A0-A15
t
t
AH
5555
AA
BYTE 0
Note:
10
5555
5555
2AAA
t
DATA
DH
5555
2AAA
t
DS
55
BYTE 1
80
AA
BYTE 2
BYTE 3
55
10
BYTE 4
BYTE 5
EC
1. OE must be high only when WE and CE are both low.
AT49F512
1027F–FLASH–3/05
AT49F512
20. Data Polling Characteristics(1)
Symbol
Parameter
Min
tDH
Data Hold Time
10
ns
tOEH
OE Hold Time
10
ns
Max
(2)
tOE
OE to Output Delay
tWR
Write Recovery Time
Notes:
Typ
Units
ns
0
ns
1. These parameters are characterized and not 100% tested.
2. See tOE spec in AC Read Characteristics.
21. Data Polling Waveforms
WE
CE
tOEH
OE
tDH
tOE
I/O7
A0-A15
tWR
HIGH Z
An
An
An
An
An
22. Toggle Bit Characteristics(1)
Symbol
Parameter
Min
tDH
Data Hold Time
10
ns
tOEH
OE Hold Time
10
ns
(2)
tOE
OE to Output Delay
tOEHP
OE High Pulse
tWR
Notes:
Write Recovery Time
Typ
Max
Units
ns
150
ns
0
ns
1. These parameters are characterized and not 100% tested.
2. See tOE spec in AC Read Characteristics.
23. Toggle Bit Waveforms(1)(2)(3)
Notes:
1. Toggling either OE or CE or both OE and CE will operate toggle bit. The tOEHP specification must be met by the toggling
input(s)
2. Beginning and ending state of I/O6 will vary.
3. Any address location may be used but the address should not vary.
11
1027F–FLASH–3/05
AT49F512
24. Software Product Identification
Entry(1)
26. Boot Block Lockout Enable
Algorithm(1)
LOAD DATA AA
TO
ADDRESS 5555
LOAD DATA AA
TO
ADDRESS 5555
LOAD DATA 55
TO
ADDRESS 2AAA
LOAD DATA 55
TO
ADDRESS 2AAA
LOAD DATA 90
TO
ADDRESS 5555
LOAD DATA 80
TO
ADDRESS 5555
ENTER PRODUCT
IDENTIFICATION
MODE(2)(3)(5)
LOAD DATA AA
TO
ADDRESS 5555
25. Software Product Identification
Exit(1)
LOAD DATA AA
TO
ADDRESS 5555
OR
LOAD DATA 55
TO
ADDRESS 2AAA
LOAD DATA 55
TO
ADDRESS 2AAA
LOAD DATA F0
TO
ANY ADDRESS
LOAD DATA 40
TO
ADDRESS 5555
EXIT PRODUCT
IDENTIFICATION
MODE(4)
LOAD DATA F0
TO
ADDRESS 5555
PAUSE 1 second(2)
Notes:
1. Data Format: I/O7 - I/O0 (Hex);
Address Format: A14 - A0 (Hex).
2. Boot block lockout feature enabled.
EXIT PRODUCT
IDENTIFICATION
MODE(4)
Notes:
1. Data Format: I/O7 - I/O0 (Hex);
Address Format: A14 - A0 (Hex).
2. A1 - A15 = VIL.
Manufacture Code is read for A0 = VIL;
Device Code is read for A0 = VIH.
3. The device does not remain in identification mode if powered down.
4. The device returns to standard operation mode.
5. Manufacturer Code: 1FH
Device Code: 03H
12
1027F–FLASH–3/05
AT49F512
27. Ordering Information
27.1
Standard Package
ICC (mA)
tACC
(ns)
Active
Standby
Ordering Code
Package
55
40
0.3
AT49F512-55JI
AT49F512-55TI
AT49F512-55VI
32J
32T
32V
Operation Range
Industrial
(-40° to 85°C)
Note:
1. The AT49F512 has as optional boot block feature. The part number shown in the Ordering Information table is for devices
with the boot block in the lower address range (i.e., 0000H to 1FFFH). Users requiring the boot block to be in the higher
address range should contact Atmel.
27.2
Green Package Option (Pb/Halide-free)
ICC (mA)
tACC
(ns)
Active
Standby
Ordering Code
Package
55
40
0.3
AT49F512-55JU
32J
Industrial
(-40° to 85°C)
70
40
0.3
AT49F512-70TU
32T
Industrial
(-40° to 85°C)
55
40
0.3
AT49F512-55VU
32V
Industrial
(-40° to 85°C)
70
40
0.3
AT49F512-70VU
32V
Industrial
(-40° to 85°C)
Operation Range
Package Type
32J
32-lead, Plastic, J-leaded Chip Carrier Package (PLCC)
32T
32-lead, Thin Small Outline Package (TSOP) (8 x 20 mm)
32V
32-lead, Thin Small Outline Package (VSOP) (8 x 14 mm)
13
1027F–FLASH–3/05
28. Packaging Information
28.1
32J – PLCC
1.14(0.045) X 45˚
PIN NO. 1
IDENTIFIER
1.14(0.045) X 45˚
0.318(0.0125)
0.191(0.0075)
E1
E2
B1
E
B
e
A2
D1
A1
D
A
0.51(0.020)MAX
45˚ MAX (3X)
COMMON DIMENSIONS
(Unit of Measure = mm)
D2
Notes:
1. This package conforms to JEDEC reference MS-016, Variation AE.
2. Dimensions D1 and E1 do not include mold protrusion.
Allowable protrusion is .010"(0.254 mm) per side. Dimension D1
and E1 include mold mismatch and are measured at the extreme
material condition at the upper or lower parting line.
3. Lead coplanarity is 0.004" (0.102 mm) maximum.
SYMBOL
MIN
NOM
MAX
A
3.175
–
3.556
A1
1.524
–
2.413
A2
0.381
–
–
D
12.319
–
12.573
D1
11.354
–
11.506
D2
9.906
–
10.922
E
14.859
–
15.113
E1
13.894
–
14.046
E2
12.471
–
13.487
B
0.660
–
0.813
B1
0.330
–
0.533
e
NOTE
Note 2
Note 2
1.270 TYP
10/04/01
R
14
2325 Orchard Parkway
San Jose, CA 95131
TITLE
32J, 32-lead, Plastic J-leaded Chip Carrier (PLCC)
DRAWING NO.
REV.
32J
B
AT49F512
1027F–FLASH–3/05
AT49F512
28.2
32T – TSOP
PIN 1
0º ~ 8º
c
Pin 1 Identifier
D1 D
L
b
e
L1
A2
E
A
GAGE PLANE
SEATING PLANE
COMMON DIMENSIONS
(Unit of Measure = mm)
A1
MIN
NOM
MAX
A
–
–
1.20
A1
0.05
–
0.15
A2
0.95
1.00
1.05
D
19.80
20.00
20.20
D1
18.30
18.40
18.50
Note 2
E
7.90
8.00
8.10
Note 2
L
0.50
0.60
0.70
SYMBOL
Notes:
1. This package conforms to JEDEC reference MO-142, Variation BD.
2. Dimensions D1 and E do not include mold protrusion. Allowable
protrusion on E is 0.15 mm per side and on D1 is 0.25 mm per side.
3. Lead coplanarity is 0.10 mm maximum.
L1
0.25 BASIC
b
0.17
0.22
0.27
c
0.10
–
0.21
e
NOTE
0.50 BASIC
10/18/01
R
2325 Orchard Parkway
San Jose, CA 95131
TITLE
32T, 32-lead (8 x 20 mm Package) Plastic Thin Small Outline
Package, Type I (TSOP)
DRAWING NO.
REV.
32T
B
15
1027F–FLASH–3/05
28.3
32V – VSOP
PIN 1
0º ~ 8º
c
Pin 1 Identifier
D1 D
L
b
e
L1
A2
E
A
GAGE PLANE
SEATING PLANE
COMMON DIMENSIONS
(Unit of Measure = mm)
A1
MIN
NOM
MAX
A
–
–
1.20
A1
0.05
–
0.15
A2
0.95
1.00
1.05
D
13.80
14.00
14.20
D1
12.30
12.40
12.50
Note 2
E
7.90
8.00
8.10
Note 2
L
0.50
0.60
0.70
SYMBOL
Notes:
1. This package conforms to JEDEC reference MO-142, Variation BA.
2. Dimensions D1 and E do not include mold protrusion. Allowable
protrusion on E is 0.15 mm per side and on D1 is 0.25 mm per side.
3. Lead coplanarity is 0.10 mm maximum.
L1
0.25 BASIC
b
0.17
0.22
0.27
c
0.10
–
0.21
e
NOTE
0.50 BASIC
10/18/01
R
16
2325 Orchard Parkway
San Jose, CA 95131
TITLE
32V, 32-lead (8 x 14 mm Package) Plastic Thin Small Outline
Package, Type I (VSOP)
DRAWING NO.
REV.
32V
B
AT49F512
1027F–FLASH–3/05
AT49F512
29. Revision History
Revision No.
History
•
Added a 55 ns speed option and removed the 50, 70, and 90 ns
speed options for the die shrink redesign. The PDIP package was
also eliminated. The die shrink redesign will have a marketing
revision letter “A” marked after the date code on the topside
of the device.
•
•
Converted datasheet to New Template.
Added Green Package (Pb/Halide-free) Option in the
Ordering Information section.
Revision E – August 2004
Revision F – March 2005
17
1027F–FLASH–3/05
Atmel Corporation
2325 Orchard Parkway
San Jose, CA 95131, USA
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