Features
•
•
•
•
•
•
•
•
•
•
Single Supply for Read and Write: 2.7 to 3.6V (BV), 3.0 to 3.6V (LV)
Fast Read Access Time – 70 ns
Internal Program Control and Timer
Sector Architecture
– One 16K Bytes Boot Block with Programming Lockout
– Two 8K Bytes Parameter Blocks
– Two Main Memory Blocks (96K, 128K Bytes)
Fast Erase Cycle Time – 10 Seconds
Byte-by-Byte Programming – 30 µs/Byte Typical
Hardware Data Protection
DATA Polling for End of Program Detection
Low Power Dissipation
– 25 mA Active Current
– 50 µA CMOS Standby Current
Typical 10,000 Write Cycles
2-megabit
(256K x 8)
Single 2.7-volt
Battery-Voltage™
Description
The AT49BV/LV002(N)(T) is a 3-volt-only in-system reprogrammable Flash Memory.
Its 2 megabits of memory is organized as 262,144 words by 8 bits. Manufactured with
Atmel’s advanced nonvolatile CMOS technology, the device offers access times to
70 ns with power dissipation of just 90 mW over the commercial temperature range.
DIP Top View
Pin Configurations
Pin Name
Function
A0 - A17
Addresses
CE
Chip Enable
OE
Output Enable
WE
Write Enable
RESET
RESET
I/O0 - I/O7
Data Inputs/Outputs
DC
Don’t Connect
A12
A15
A16
RESET*
VCC
WE
A17
4
3
2
1
32
31
30
29
28
27
26
25
24
23
22
21
I/O1
I/O2
GND
I/O3
I/O4
I/O5
I/O6
14
15
16
17
18
19
20
5
6
7
8
9
10
11
12
13
Note:
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VCC
WE
A17
A14
A13
A8
A9
A11
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
VSOP Top View (8 x 14 mm) or
TSOP Top View (8 x 20 mm)
Type 1
PLCC Top View
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
*RESET
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
GND
A14
A13
A8
A9
A11
OE
A10
CE
I/O7
A11
A9
A8
A13
A14
A17
WE
VCC
*RESET
A16
A15
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
*This pin is a DC on the AT49BV002N(T) and AT49LV002N(T).
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
A1
A2
A3
Flash Memory
AT49BV002
AT49LV002
AT49BV002N
AT49LV002N
AT49BV002T
AT49LV002T
AT49BV002NT
AT49LV002NT
Not Recommended
for New Design
Contact Atmel to discuss
the latest design in trends
and options
Rev. 0982D–FLASH–02/03
1
When the device is deselected, the CMOS standby current is less than 50 µA. For the
AT49BV/LV002N(T) pin 1 for the DIP and PLCC packages and pin 9 for the TSOP package
a r e d o n’ t c o n n e c t pi n s . T o al l o w f o r s i m p l e i n - s y s t e m r e p r o g r a m m a bi l i ty , t h e
AT49BV/LV002(N)(T) does not require high input voltages for programming. Five-volt-only
commands determine the read and programming operation of the device. Reading data out of
the device is similar to reading from an EPROM; it has standard CE, OE, and WE inputs to
avoid bus contention. Reprogramming the AT49BV/LV002(N)(T) is performed by erasing a
block of data and then programming on a byte by byte basis. The byte programming time is a
fast 50 µs. The end of a program cycle can be optionally detected by the DATA polling feature.
Once the end of a byte program cycle has been detected, a new access for a read or program
can begin. The typical number of program and erase cycles is in excess of 10,000 cycles.
The device is erased by executing the erase command sequence; the device internally controls the erase operations. There are two 8K byte parameter block sections and two main
memory blocks.
The device has the capability to protect the data in the boot block; this feature is enabled by a
command sequence. The 16K-byte boot block section includes a reprogramming lock out feature to provide data integrity. The boot sector is designed to contain user secure code, and
when the feature is enabled, the boot sector is protected from being reprogrammed.
In the AT49BV/LV002N(T), once the boot block programming lockout feature is enabled, the
contents of the boot block are permanent and cannot be changed. In the AT49BV/LV002(T),
once the boot block programming lockout feature is enabled, the contents of the boot block
cannot be changed with input voltage levels of 5.5 volts or less.
Block Diagram
AT49BV/LV002(N)
DATA INPUTS/OUTPUTS
I/O7 - I/O0
VCC
GND
OE
WE
CE
RESET
8
CONTROL
LOGIC
Y DECODER
ADDRESS
INPUTS
AT49BV/LV002(N)T
DATA INPUTS/OUTPUTS
I/O7 - I/O0
8
INPUT/OUTPUT
BUFFERS
INPUT/OUTPUT
BUFFERS
PROGRAM
DATA LATCHES
PROGRAM
DATA LATCHES
Y-GATING
Y-GATING
3FFFF
X DECODER
MAIN MEMORY
BLOCK 2
(128K BYTES)
MAIN MEMORY
BLOCK 1
(96K BYTES)
PARAMETER
BLOCK 2
(8K BYTES)
PARAMETER
BLOCK 1
(8K BYTES)
BOOT BLOCK
(16K BYTES)
20000
1FFFF
08000
07FFF
06000
05FFF
04000
03FFF
00000
2
3FFFF
BOOT BLOCK
(16K BYTES)
PARAMETER
BLOCK 1
(8K BYTES)
PARAMETER
BLOCK 2
(8K BYTES)
MAIN MEMORY
BLOCK 1
(96K BYTES)
MAIN MEMORY
BLOCK 2
(128K BYTES)
3C000
3BFFF
3A000
39FFF
38000
37FFF
20000
1FFFF
00000
AT49BV/LV002(N)(T)
0982D–FLASH–02/03
AT49BV/LV002(N)(T)
Device
Operation
READ: The AT49BV/LV002(N)(T) is accessed like an EPROM. When CE and OE are low and
WE is high, the data stored at the memory location determined by the address pins is asserted
on the outputs. The outputs are put in the high impedance state whenever CE or OE is high.
This dual-line control gives designers flexibility in preventing bus contention.
COMMAND SEQUENCES: When the device is first powered on it will be reset to the read or
standby mode depending upon the state of the control line inputs. In order to perform other
device functions, a series of command sequences are entered into the device. The command
sequences are shown in the Command Definitions table. The command sequences are written
by applying a low pulse on the WE or CE input with CE or WE low (respectively) and OE high.
The address is latched on the falling edge of CE or WE, whichever occurs last. The data is
latched by the first rising edge of CE or WE. Standard microprocessor write timings are used.
The address locations used in the command sequences are not affected by entering the command sequences.
RESET: A RESET input pin is provided to ease some system applications. When RESET is at
a logic high level, the device is in its standard operating mode. A low level on the RESET input
halts the present device operation and puts the outputs of the device in a high impedance
state. If the RESET pin makes a high to low transition during a program or erase operation, the
operation may not be successfully completed and the operation will have to be repeated after
a high level is applied to the RESET pin. When a high level is reasserted on the RESET pin,
the device returns to the read or standby mode, depending upon the state of the control inputs.
By applying a 12V ± 0.5V input signal to the RESET pin, the boot block array can be reprogrammed even if the boot block lockout feature has been enabled (see Boot Block
Programming Lockout Override section). The RESET feature is not available on the
AT49BV/LV002N(T).
ERASURE: Before a byte can be reprogrammed, the main memory block or parameter block
which contains the byte must be erased. The erased state of the memory bits is a logical “1”.
The entire device can be erased at one time by using a 6-byte software code. The software
chip erase code consists of 6-byte load commands to specific address locations with a specific
data pattern (please refer to the Chip Erase Cycle Waveforms).
After the software chip erase has been initiated, the device will internally time the erase operation so that no external clocks are required. The maximum time needed to erase the whole
chip is tEC. If the boot block lockout feature has been enabled, the data in the boot sector will
not be erased.
CHIP ERASE: If the boot block lockout has been enabled, the Chip Erase function will erase
Parameter Block 1, Parameter Block 2, Main Memory Block 1, and Main Memory Block 2 but
not the boot block. If the Boot Block Lockout has not been enabled, the Chip Erase function
will erase the entire chip. After the full chip erase the device will return back to read mode. Any
command during chip erase will be ignored.
SECTOR ERASE: As an alternative to a full chip erase, the device is organized into sectors
that can be individually erased. There are two 8K-byte parameter block sections and two main
memory blocks. The 8K-byte parameter block sections can be independently erased and
reprogrammed. The two main memory sections are designed to be used as alternative memory sectors. That is, whenever one of the blocks has been erased and reprogrammed, the
other block should be erased and reprogrammed before the first block is again erased. The
Sector Erase command is a six bus cycle operation. The sector address is latched on the falling WE edge of the sixth cycle while the 30H data input command is latched at the rising edge
of WE. The sector erase starts after the rising edge of WE of the sixth cycle. The erase operation is internally controlled; it will automatically time to completion.
3
0982D–FLASH–02/03
BYTE PROGRAMMING: Once the memory array is erased, the device is programmed (to a
logical “0”) on a byte-by-byte basis. Please note that a data “0” cannot be programmed back to
a “1”; only erase operations can convert “0”s to “1”s. Programming is accomplished via the
internal device command register and is a 4 bus cycle operation (please refer to the Command
Definitions table). The device will automatically generate the required internal program pulses.
The program cycle has addresses latched on the falling edge of WE or CE, whichever occurs
last, and the data latched on the rising edge of WE or CE, whichever occurs first. Programming is completed after the specified tBP cycle time. The DATA polling feature may also be
used to indicate the end of a program cycle.
BOOT BLOCK PROGRAMMING LOCKOUT: The device has one designated block that has
a programming lockout feature. This feature prevents programming of data in the designated
block once the feature has been enabled. The size of the block is 16K bytes. This block,
referred to as the boot block, can contain secure code that is used to bring up the system.
Enabling the lockout feature will allow the boot code to stay in the device while data in the rest
of the device is updated. This feature does not have to be activated; the boot block’s usage as
a write protected region is optional to the user. The address range of the boot block is 00000
to 03FFF for the AT49BV/LV002(N) while the address range of the boot block is 3C000 to
3FFFF for the AT49BV/LV002(N)T.
Once the feature is enabled, the data in the boot block can no longer be erased or programmed with input voltage of 5.5V or less. Data in the main memory block can still be
changed through the regular programming method. To activate the lockout feature, a series of
six program commands to specific addresses with specific data must be performed. Please
refer to the Command Definitions table.
BOOT BLOCK LOCKOUT DETECTION: A software method is available to determine if programming of the boot block section is locked out. When the device is in the software product
identification mode (see Software Product Identification Entry and Exit sections) a read from
address location 00002H will show if programming the boot block is locked out for the
AT49BV/LV002(N), and a read from address location 3C002H will show if programming the
bootblock is locked out for AT49BV/LV002(N)T. If the data on I/O0 is low, the boot block can
be programmed; if the data on I/O0 is high, the program lockout feature has been activated
and the block cannot be programmed. The software product identification code should be
used to return to standard operation.
BOOT BLOCK PROGRAMMING LOCKOUT OVERRIDE: The user can override the boot
block programming lockout by taking the RESET pin to 12 volts during the entire chip erase,
sector erase or byte programming operation. When the RESET pin is brought back to TTL levels the boot block programming lockout feature is again active. This feature is not available on
the AT49BV/LV002N(T).
PRODUCT IDENTIFICATION: The product identification mode identifies the device and manufacturer as Atmel. It may be accessed by hardware or software operation. The hardware
operation mode can be used by an external programmer to identify the correct programming
algorithm for the Atmel product.
For details, see Operating Modes (for hardware operation) or Software Product Identification.
The manufacturer and device code is the same for both modes.
4
AT49BV/LV002(N)(T)
0982D–FLASH–02/03
AT49BV/LV002(N)(T)
DATA POLLING: The AT49BV/LV002(N)(T) features DATA polling to indicate the end of a
program cycle. During a program cycle an attempted read of the last byte loaded will result in
the complement of the loaded data on I/O7. Once the program cycle has been completed, true
data is valid on all outputs and the next cycle may begin. DATA polling may begin at any time
during the program cycle.
TOGGLE BIT: In addition to DATA polling the AT49BV/LV002(N)(T) provides another method
for determining the end of a program or erase cycle. During a program or erase operation,
successive attempts to read data from the device will result in I/O6 toggling between one and
zero. Once the program cycle has completed, I/O6 will stop toggling and valid data will be
read. Examining the toggle bit may begin at any time during a program cycle.
HARDWARE DATA PROTECTION: Hardware features protect against inadvertent programs
to the AT49BV/LV002(N)(T) in the following ways: (a) VCC sense: if VCC is below 1.8V (typical),
the program function is inhibited. (b) Program inhibit: holding any one of OE low, CE high or
WE high inhibits program cycles. (c) Noise filter: pulses of less than 15 ns (typical) on the WE
or CE inputs will not initiate a program cycle.
5
0982D–FLASH–02/03
Command Definition (in Hex)(1)
Command
Sequence
1st Bus
Cycle
Bus
Cycles
Addr
Data
Read
1
Addr
DOUT
Chip Erase
6
5555
AA
2nd Bus
Cycle
3rd Bus
Cycle
4th Bus
Cycle
Data
Addr
Data
Addr
Data
Addr
Data
Addr
Data
2AAA
55
5555
80
5555
AA
2AAA
55
5555
10
2AAA
55
SA
(4)
30
2AAA
55
5555
40
6
5555
AA
2AAA
55
5555
80
5555
AA
Byte Program
4
5555
AA
2AAA
55
5555
A0
Addr
DIN
Boot Block Lockout(2)
6
5555
AA
2AAA
55
5555
80
5555
AA
Product ID Entry
3
5555
AA
2AAA
55
5555
90
(3)
3
5555
AA
2AAA
55
5555
F0
(3)
1
XXXX
F0
Product ID Exit
Notes:
6th Bus
Cycle
Addr
Sector Erase
Product ID Exit
5th Bus
Cycle
1. The DATA FORMAT in each bus cycle is as follows: I/O7 - I/O0 (Hex)
2. The 16K byte boot sector has the address range 00000H to 03FFFH for the AT49BV/LV002(N) and 3C000H to 3FFFFH for
the AT49BV/LV002(N)T
3. Either one of the Product ID Exit commands can be used.
4. SA = sector addresses:
For the AT49BV/LV002(N):
SA = 00000 to 03FFF for BOOT BLOCK
Nothing will happen and the device goes back to the read mode in 100 ns
SA = 04000 to 05FFF for PARAMETER BLOCK 1
SA = 06000 to 07FFF for PARAMETER BLOCK 2
SA = 08000 to 1FFFF for MAIN MEMORY ARRAY BLOCK 1
This command will erase - PB1, PB2 and MMB1
SA = 20000 to 3FFFF for MAIN MEMORY ARRAY BLOCK 2
For the AT49BV/LV002(N)T:
SA = 3C000 to 3FFFF for BOOT BLOCK
Nothing will happen and the device goes back to the read mode in 100 ns
SA = 3A000 to 3BFFF for PARAMETER BLOCK 1
SA = 38000 to 39FFF for PARAMETER BLOCK 2
SA = 20000 to 37FFF for MAIN MEMORY ARRAY BLOCK 1
This command will erase - PB1, PB2 and MMB1
SA = 00000 to IFFFF for MAIN MEMORY ARRAY BLOCK 2
Absolute Maximum Ratings
Temperature Under Bias................................ -55°C to +125°C
Storage Temperature ..................................... -65°C to +150°C
All Input Voltages
(including NC Pins)
with Respect to Ground ...................................-0.6V to +6.25V
*NOTICE:
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended
periods may affect device reliability.
All Output Voltages
with Respect to Ground .............................-0.6V to VCC + 0.6V
Voltage on OE
with Respect to Ground ...................................-0.6V to +13.5V
6
AT49BV/LV002(N)(T)
0982D–FLASH–02/03
AT49BV/LV002(N)(T)
DC and AC Operating Range
Operating
Temperature (Case)
AT49LV002(N)(T)-70
AT49BV/LV002(N)(T)-90
AT49BV/LV002(N)(T)-12
0°C - 70°C
0°C - 70°C
0°C - 70°C
-40°C - 85°C
-40°C - 85°C
-40°C - 85°C
3.0V - 3.6V
2.7V - 3.6V/3.0V - 3.6V
2.7V - 3.6V/3.0V - 3.6V
Com.
Ind.
VCC Power Supply
Operating Modes
Mode
Read
(2)
Program/Erase
Standby/Write Inhibit
CE
OE
WE
RESET(6)
Ai
I/O
VIL
VIL
VIH
VIH
Ai
DOUT
VIL
VIH
VIL
VIH
Ai
DIN
X
VIH
X
High Z
(1)
VIH
X
Program Inhibit
X
X
VIH
VIH
Program Inhibit
X
VIL
X
VIH
Output Disable
X
VIH
X
VIH
Reset
X
X
X
VIL
High Z
X
High Z
Product Identification
Hardware
VIL
VIL
VIH
Software(5)
Notes:
1.
2.
3.
4.
5.
6.
A1 - A17 = VIL, A9 = VH,(3), A0 = VIL
Manufacturer Code(4)
A1 - A17 = VIL, A9 = VH,(3), A0 = VIH
Device Code(4)
A0 = VIL, A1 - A17=VIL
Manufacturer Code(4)
A0 = VIH, A1 - A17=VIL
Device Code(4)
X can be VIL or VIH.
Refer to AC Programming Waveforms.
VH = 12.0V ± 0.5V.
Manufacturer Code: 1FH, Device Code: 07H - AT49BV/LV002(N), 08H - AT49BV/LV002(N)T
See details under Software Product Identification Entry/Exit.
This pin is not available on the AT49BV/LV002N(T).
DC Characteristics
Symbol
Parameter
Condition
ILI
Input Load Current
ILO
Max
Units
VIN = 0V to VCC
10
µA
Output Leakage Current
VI/O = 0V to VCC
10
µA
ISB1
VCC Standby Current CMOS
CE = VCC - 0.3V to VCC
50
µA
ISB2
VCC Standby Current TTL
CE = 2.0V to VCC
3
mA
VCC Active Current
f = 5 MHz; IOUT = 0 mA
25
mA
0.6
V
ICC
(1)
VIL
Input Low Voltage
VIH
Input High Voltage
VOL
Output Low Voltage
IOL = 2.1 mA
VOH
Output High Voltage
IOH = -400 µA
Note:
Min
2.0
V
0.45
2.4
V
V
1. In the erase mode, ICC is 50 mA.
7
0982D–FLASH–02/03
AC Read Characteristics
AT49LV002(N)(T)-70
Symbol
Parameter
tACC
Min
AT49BV/LV002(N)(T)-90
Max
Min
Max
AT49BV/LV002(N)(T)-12
Min
Max
Unit
s
Address to Output Delay
70
90
120
ns
(1)
CE to Output Delay
70
90
120
ns
tOE(2)
OE to Output Delay
0
35
0
40
0
50
ns
CE or OE to Output Float
0
25
0
25
0
30
ns
Output Hold from OE, CE or
Address, whichever
occurred first
0
tCE
tDF
(3)(4)
tOH
0
0
ns
AC Read Waveforms (1)(2)(3)(4)
ADDRESS
ADDRESS
VALID
CE
OE
tCE
tOE
t DF
tACC
OUTPUT
Notes:
8
HIGH Z
tOH
OUTPUT
VALID
1. CE may be delayed up to tACC - tCE after the address transition without impact on tACC.
2. OE may be delayed up to tCE - tOE after the falling edge of CE without impact on tCE or by tACC - tOE after an address change
without impact on tACC.
3. tDF is specified from OE or CE whichever occurs first (CL = 5 pF).
4. This parameter is characterized and is not 100% tested.
AT49BV/LV002(N)(T)
0982D–FLASH–02/03
AT49BV/LV002(N)(T)
Input Test Waveform and Measurement Level
2.4V
AC
DRIVING
LEVELS
AC
MEASUREMENT
LEVEL
1.5V
0.4V
tR, tF < 5
Output Load Test
3.0V
1.8K
OUTPUT
PIN
1.3K
30 pF
Pin Capacitance
f = 1 MHz, T = 25°C(1)
Symbol
Typ
Max
Units
Conditions
CIN
4
6
pF
VIN = 0V
COUT
8
12
pF
VOUT = 0V
Note:
1. This parameter is characterized and is not 100% tested.
9
0982D–FLASH–02/03
AC Byte Load Characteristics
Symbol
Parameter
Min
Max
Units
tAS, tOES
Address, OE Set-up Time
0
ns
tAH
Address Hold Time
70
ns
tCS
Chip Select Set-up Time
0
ns
tCH
Chip Select Hold Time
0
ns
tWP
Write Pulse Width (WE or CE)
90
ns
tDS
Data Set-up Time
70
ns
tDH, tOEH
Data, OE Hold Time
0
ns
tWPH
Write Pulse Width High
90
ns
AC Byte Load Waveforms
WE Controlled
OE
tOES
tOEH
ADDRESS
CE
WE
tAS
tAH
tCH
tCS
tWPH
tWP
tDH
tDS
DATA IN
CE Controlled
OE
tOES
tOEH
ADDRESS
tAS
tAH
tCH
WE
tCS
CE
tWPH
tWP
tDS
tDH
DATA IN
10
AT49BV/LV002(N)(T)
0982D–FLASH–02/03
AT49BV/LV002(N)(T)
Program Cycle Characteristics
Symbol
Parameter
Min
Typ
Max
Units
tBP
Byte Programming Time
30
50
µs
tAS
Address Set-up Time
0
ns
tAH
Address Hold Time
70
ns
tDS
Data Set-up Time
70
ns
tDH
Data Hold Time
0
ns
tWP
Write Pulse Width
90
ns
tWPH
Write Pulse Width High
90
ns
tEC
Erase Cycle Time
10
seconds
Program Cycle Waveforms
A0 - A17
Sector or Chip Erase Cycle Waveforms
OE
(1)
CE
tWP
tWPH
WE
tAS
A0 - A17
tAH
tDH
5555
5555
5555
2AAA
Note 2
2AAA
tEC
tDS
DATA
AA
BYTE 0
Notes:
55
BYTE 1
80
BYTE 2
AA
BYTE 3
55
BYTE 4
Note 3
BYTE 5
1. OE must be high only when WE and CE are both low.
2. For chip erase, the address should be 5555. For sector erase, the address depends on what sector is to be erased.
(See note 4 under command definitions.)
3. For chip erase, the data should be 10H, and for sector erase, the data should be 30H.
11
0982D–FLASH–02/03
Data Polling Characteristics
Symbol
Parameter
Min
tDH
Data Hold Time
10
ns
tOEH
OE Hold Time
10
ns
Max
(2)
tOE
OE to Output Delay
tWR
Write Recovery Time
Notes:
Typ
Units
ns
0
ns
1. These parameters are characterized and not 100% tested.
2. See tOE spec in AC Read Characteristics.
Data Polling Waveforms
WE
CE
tOEH
OE
tDH
tOE
I/O7
A0-A17
An
tWR
HIGH Z
An
An
An
An
Toggle Bit Characteristics
Symbol
Parameter
Min
tDH
Data Hold Time
10
ns
tOEH
OE Hold Time
10
ns
(2)
tOE
OE to Output Delay
tOEHP
OE High Pulse
tWR
Write Recovery Time
Notes:
Typ
Max
Units
ns
150
ns
0
ns
1. These parameters are characterized and not 100% tested.
2. See tOE spec in AC Read Characteristics.
Toggle Bit Waveforms(1)(2)(3)
WE
CE
tOEH
tOEHP
OE
tDH
tOE
I/O6
Notes:
12
HIGH Z
tWR
1. Toggling either OE or CE or both OE and CE will operate toggle bit.
The tOEHP specification must be met by the toggling input(s).
2. Beginning and ending state of I/O6 will vary.
3. Any address location may be used but the address should not vary.
AT49BV/LV002(N)(T)
0982D–FLASH–02/03
AT49BV/LV002(N)(T)
Software Product Identification Entry(1)
Boot Block Lockout Feature Enable
Algorithm(1)
LOAD DATA AA
TO
ADDRESS 5555
LOAD DATA AA
TO
ADDRESS 5555
LOAD DATA 55
TO
ADDRESS 2AAA
LOAD DATA 55
TO
ADDRESS 2AAA
LOAD DATA 90
TO
ADDRESS 5555
LOAD DATA 80
TO
ADDRESS 5555
ENTER PRODUCT
IDENTIFICATION
MODE(2)(3)(5)
LOAD DATA AA
TO
ADDRESS 5555
LOAD DATA 55
TO
ADDRESS 2AAA
Software ProductIdentification Exit(1)
LOAD DATA AA
TO
ADDRESS 5555
LOAD DATA 55
TO
ADDRESS 2AAA
OR
LOAD DATA 40
TO
ADDRESS 5555
LOAD DATA F0
TO
ANY ADDRESS
EXIT PRODUCT
IDENTIFICATION
MODE(4)
PAUSE 1 second(2)
Notes:
LOAD DATA F0
TO
ADDRESS 5555
1. Data Format: I/O7 - I/O0 (Hex);
Address Format: A14 - A0 (Hex).
2. Boot block lockout feature enabled.
EXIT PRODUCT
IDENTIFICATION
MODE(4)
Notes:
1. Data Format: I/O7 - I/O0 (Hex);
Address Format: A14 - A0 (Hex).
2. A1 - A17 = VIL.
Manufacture Code is read for A0 = VIL;
Device Code is read for A0 = VIH.
3. The device does not remain in identification mode if
powered down.
4. The device returns to standard operation mode.
5. Device Code:
07H - AT49BV/LV002(N)
08H - AT49BV/LV002(N)T
13
0982D–FLASH–02/03
AT49BV002 Ordering Information
ICC (mA)
tACC
(ns)
Active
Standby
90
50
120
Ordering Code
Package
Operation Range
0.1
AT49BV002-90JC
AT49BV002-90PC
AT49BV002-90TC
AT49BV002-90VC
32J
32P6
32T
32V
Commercial
(0° to 70°C)
50
0.3
AT49BV002-90JI
AT49BV002-90PI
AT49BV002-90TI
AT49LV002-90VI
32J
32P6
32T
32V
Industrial
(-40° to 85°C)
50
0.1
AT49BV002-12JC
AT49BV002-12PC
AT49BV002-12TC
AT49BV002-12VC
32J
32P6
32T
32V
Commercial
(0° to 70°C)
50
0.3
AT49BV002-12JI
AT49BV002-12PI
AT49BV002-12TI
AT49BV002-12VI
32J
32P6
32T
32V
Industrial
(-40° to 85°C)
Package Type
32J
32-Lead, Plastic, J-Leaded Chip Carrier Package (PLCC)
32P6
32-Lead, 0.600" Wide, Plastic Dual In-line Package (PDIP)
32T
32-Lead, Thin Small Outline Package (TSOP)
32V
32-Lead, Thin Small Outline Package (VSOP) (8 x 14 mm)
14
AT49BV/LV002(N)(T)
0982D–FLASH–02/03
AT49BV/LV002(N)(T)
AT49LV002 Ordering Information
ICC (mA)
tACC
(ns)
Active
Standby
70
50
90
120
Ordering Code
Package
Operation Range
0.1
AT49LV002-70JC
AT49LV002-70PC
AT49LV002-70TC
AT49LV002-70VC
32J
32P6
32T
32V
Commercial
(0° to 70°C)
50
0.3
AT49LV002-70JI
AT49LV002-70PI
AT49LV002-70TI
AT49LV002-70VI
32J
32P6
32T
32V
Industrial
(-40° to 85°C)
50
0.1
AT49LV002-90JC
AT49LV002-90PC
AT49LV002-90TC
AT49LV002-90VC
32J
32P6
32T
32V
Commercial
(0° to 70°C)
50
0.3
AT49LV002-90JI
AT49LV002-90PI
AT49LV002-90TI
AT49LV002-90VI
32J
32P6
32T
32V
Industrial
(-40° to 85°C)
50
0.1
AT49LV002-12JC
AT49LV002-12PC
AT49LV002-12TC
AT49LV002-12VC
32J
32P6
32T
32V
Commercial
(0° to 70°C)
50
0.3
AT49LV002-12JI
AT49LV002-12PI
AT49LV002-12TI
AT49LV002-12VI
32J
32P6
32T
32V
Industrial
(-40° to 85°C)
Package Type
32J
32-Lead, Plastic, J-Leaded Chip Carrier Package (PLCC)
32P6
32-Lead, 0.600" Wide, Plastic Dual In-line Package (PDIP)
32T
32-Lead, Thin Small Outline Package (TSOP)
32V
32-Lead, Thin Small Outline Package (VSOP) (8 x 14 mm)
15
0982D–FLASH–02/03
AT49BV002N Ordering Information
ICC (mA)
tACC
(ns)
Active
Standby
90
50
120
Ordering Code
Package
Operation Range
0.1
AT49BV002N-90JC
AT49BV002N-90PC
AT49BV002N-90TC
AT49BV002N-90VC
32J
32P6
32T
32V
Commercial
(0° to 70°C)
50
0.3
AT49BV002N-90JI
AT49BV002N-90PI
AT49BV002N-90TI
AT49BV002N-90VI
32J
32P6
32T
32V
Industrial
(-40° to 85°C)
50
0.1
AT49BV002N-12JC
AT49BV002N-12PC
AT49BV002N-12TC
AT49BV002N-12VC
32J
32P6
32T
32V
Commercial
(0° to 70°C)
50
0.3
AT49BV002N-12JI
AT49BV002N-12PI
AT49BV002N-12TI
AT49BV002N-12VI
32J
32P6
32T
32V
Industrial
(-40° to 85°C)
Package Type
32J
32-Lead, Plastic, J-Leaded Chip Carrier Package (PLCC)
32P6
32-Lead, 0.600" Wide, Plastic Dual In-line Package (PDIP)
32T
32-Lead, Thin Small Outline Package (TSOP)
32V
32-Lead, Thin Small Outline Package (VSOP) (8 x 14 mm)
16
AT49BV/LV002(N)(T)
0982D–FLASH–02/03
AT49BV/LV002(N)(T)
AT49LV002N Ordering Information
ICC (mA)
tACC
(ns)
Active
Standby
70
50
90
120
Ordering Code
Package
Operation Range
0.1
AT49LV002N-70JC
AT49LV002N-70PC
AT49LV002N-70TC
AT49LV002N-70VC
32J
32P6
32T
32V
Commercial
(0° to 70°C)
50
0.3
AT49LV002N-70JI
AT49LV002N-70PI
AT49LV002N-70TI
AT49LV002N-70VI
32J
32P6
32T
32V
Industrial
(-40° to 85°C)
50
0.1
AT49LV002N-90JC
AT49LV002N-90PC
AT49LV002N-90TC
AT49LV002N-90VC
32J
32P6
32T
32V
Commercial
(0° to 70°C)
50
0.3
AT49LV002N-90JI
AT49LV002N-90PI
AT49LV002N-90TI
AT49LV002N-90VI
32J
32P6
32T
32V
Industrial
(-40° to 85°C)
50
0.1
AT49LV002N-12JC
AT49LV002N-12PC
AT49LV002N-12TC
AT49LV002N-12VC
32J
32P6
32T
32V
Commercial
(0° to 70°C)
50
0.3
AT49LV002N-12JI
AT49LV002N-12PI
AT49LV002N-12TI
AT49LV002N-12VI
32J
32P6
32T
32V
Industrial
(-40° to 85°C)
Package Type
32J
32-Lead, Plastic, J-Leaded Chip Carrier Package (PLCC)
32P6
32-Lead, 0.600" Wide, Plastic Dual In-line Package (PDIP)
32T
32-Lead, Thin Small Outline Package (TSOP)
32V
32-Lead, Thin Small Outline Package (VSOP) (8 x 14 mm)
17
0982D–FLASH–02/03
AT49BV002T Ordering Information
ICC (mA)
tACC
(ns)
Active
Standby
90
50
120
Ordering Code
Package
Operation Range
0.1
AT49BV002T-90JC
AT49BV002T-90PC
AT49BV002T-90TC
AT49BV002T-90VC
32J
32P6
32T
32V
Commercial
(0° to 70°C)
50
0.3
AT49BV002T-90JI
AT49BV002T-90PI
AT49BV002T-90TI
AT49BV002T-90VI
32J
32P6
32T
32V
Industrial
(-40° to 85°C)
50
0.1
AT49BV002T-12JC
AT49BV002T-12PC
AT49BV002T-12TC
AT49BV002T-12VC
32J
32P6
32T
32V
Commercial
(0° to 70°C)
50
0.3
AT49BV002T-12JI
AT49BV002T-12PI
AT49BV002T-12TI
AT49BV002T-12VI
32J
32P6
32T
32V
Industrial
(-40° to 85°C)
Package Type
32J
32-Lead, Plastic, J-Leaded Chip Carrier Package (PLCC)
32P6
32-Lead, 0.600" Wide, Plastic Dual In-line Package (PDIP)
32T
32-Lead, Thin Small Outline Package (TSOP)
32V
32-Lead, Thin Small Outline Package (VSOP) (8 x 14 mm)
18
AT49BV/LV002(N)(T)
0982D–FLASH–02/03
AT49BV/LV002(N)(T)
AT49LV002T Ordering Information
ICC (mA)
tACC
(ns)
Active
Standby
70
50
90
120
Ordering Code
Package
Operation Range
0.1
AT49LV002T-70JC
AT49LV002T-70PC
AT49LV002T-70TC
AT49LV002T-70VC
32J
32P6
32T
32V
Commercial
(0° to 70°C)
50
0.3
AT49LV002T-70JI
AT49LV002T-70PI
AT49LV002T-70TI
AT49LV002T-70VI
32J
32P6
32T
32V
Industrial
(-40° to 85°C)
50
0.1
AT49LV002T-90JC
AT49LV002T-90PC
AT49LV002T-90TC
AT49LV002T-90VC
32J
32P6
32T
32V
Commercial
(0° to 70°C)
50
0.3
AT49LV002T-90JI
AT49LV002T-90PI
AT49LV002T-90TI
AT49LV002T-90VI
32J
32P6
32T
32V
Industrial
(-40° to 85°C)
50
0.1
AT49LV002T-12JC
AT49LV002T-12PC
AT49LV002T-12TC
AT49LV002T-12VC
32J
32P6
32T
32V
Commercial
(0° to 70°C)
50
0.3
AT49LV002T-12JI
AT49LV002T-12PI
AT49LV002T-12TI
AT49LV002T-12VI
32J
32P6
32T
32V
Industrial
(-40° to 85°C)
Package Type
32J
32-Lead, Plastic, J-Leaded Chip Carrier Package (PLCC)
32P6
32-Lead, 0.600" Wide, Plastic Dual In-line Package (PDIP)
32T
32-Lead, Thin Small Outline Package (TSOP)
32V
32-Lead, Thin Small Outline Package (VSOP) (8 x 14 mm)
19
0982D–FLASH–02/03
AT49BV002NT Ordering Information
tACC
(ns)
90
120
ICC (mA)
Ordering Code
Package
Operation Range
50
0.1
AT49BV002NT-90JC
AT49BV002NT-90PC
AT49BV002NT-90TC
AT49BV002NT-90VC
32J
32P6
32T
32V
Commercial
(0° to 70°C)
50
0.3
AT49BV002NT-90JI
AT49BV002NT-90PI
AT49BV002NT-90TI
AT49BV002NT-90VI
32J
32P6
32T
32V
Industrial
(-40° to 85°C)
50
0.1
AT49BV002NT-12JC
AT49BV002NT-12PC
AT49BV002NT-12TC
AT49BV002NT-12VC
32J
32P6
32T
32V
Commercial
(0° to 70°C)
50
0.3
AT49BV002NT-12JI
AT49BV002NT-12PI
AT49BV002NT-12TI
AT49BV002NT-12VI
32J
32P6
32T
32V
Industrial
(-40° to 85°C)
Package Type
32J
32-Lead, Plastic, J-Leaded Chip Carrier Package (PLCC)
32P6
32-Lead, 0.600" Wide, Plastic Dual In-line Package (PDIP)
32T
32-Lead, Thin Small Outline Package (TSOP)
32V
32-Lead, Thin Small Outline Package (VSOP) (8 x 14 mm)
20
AT49BV/LV002(N)(T)
0982D–FLASH–02/03
AT49BV/LV002(N)(T)
AT49LV002NT Ordering Information
tACC
(ns)
70
90
120
ICC (mA)
Ordering Code
Package
Operation Range
50
0.1
AT49LV002NT-70JC
AT49LV002NT-70PC
AT49LV002NT-70TC
AT49LV002NT-70VC
32J
32P6
32T
32V
Commercial
(0° to 70°C)
50
0.3
AT49LV002NT-70JI
AT49LV002NT-70PI
AT49LV002NT-70TI
AT49LV002NT-70VI
32J
32P6
32T
32V
Industrial
(-40° to 85°C)
50
0.1
AT49LV002NT-90JC
AT49LV002NT-90PC
AT49LV002NT-90TC
AT49LV002NT-90VC
32J
32P6
32T
32V
Commercial
(0° to 70°C)
50
0.3
AT49LV002NT-90JI
AT49LV002NT-90PI
AT49LV002NT-90TI
AT49LV002NT-90VI
32J
32P6
32T
32V
Industrial
(-40° to 85°C)
50
0.1
AT49LV002NT-12JC
AT49LV002NT-12PC
AT49LV002NT-12TC
AT49LV002NT-12VC
32J
32P6
32T
32V
Commercial
(0° to 70°C)
50
0.3
AT49LV002NT-12JI
AT49LV002NT-12PI
AT49LV002NT-12TI
AT49LV002NT-12VI
32J
32P6
32T
32V
Industrial
(-40° to 85°C)
Package Type
32J
32-Lead, Plastic, J-Leaded Chip Carrier Package (PLCC)
32P6
32-Lead, 0.600" Wide, Plastic Dual In-line Package (PDIP)
32T
32-Lead, Thin Small Outline Package (TSOP)
32V
32-Lead, Thin Small Outline Package (VSOP) (8 x 14 mm)
21
0982D–FLASH–02/03
Packaging Information
32J – PLCC
1.14(0.045) X 45˚
PIN NO. 1
IDENTIFIER
1.14(0.045) X 45˚
0.318(0.0125)
0.191(0.0075)
E1
E2
B1
E
B
e
A2
D1
A1
D
A
0.51(0.020)MAX
45˚ MAX (3X)
COMMON DIMENSIONS
(Unit of Measure = mm)
D2
Notes:
1. This package conforms to JEDEC reference MS-016, Variation AE.
2. Dimensions D1 and E1 do not include mold protrusion.
Allowable protrusion is .010"(0.254 mm) per side. Dimension D1
and E1 include mold mismatch and are measured at the extreme
material condition at the upper or lower parting line.
3. Lead coplanarity is 0.004" (0.102 mm) maximum.
SYMBOL
MIN
NOM
MAX
A
3.175
–
3.556
A1
1.524
–
2.413
A2
0.381
–
–
D
12.319
–
12.573
D1
11.354
–
11.506
D2
9.906
–
10.922
E
14.859
–
15.113
E1
13.894
–
14.046
E2
12.471
–
13.487
B
0.660
–
0.813
B1
0.330
–
0.533
e
NOTE
Note 2
Note 2
1.270 TYP
10/04/01
R
22
2325 Orchard Parkway
San Jose, CA 95131
TITLE
32J, 32-lead, Plastic J-leaded Chip Carrier (PLCC)
DRAWING NO.
REV.
32J
B
AT49BV/LV002(N)(T)
0982D–FLASH–02/03
AT49BV/LV002(N)(T)
32P6 – PDIP
D
PIN
1
E1
A
SEATING PLANE
A1
L
B
B1
e
E
0º ~ 15º
C
COMMON DIMENSIONS
(Unit of Measure = mm)
REF
MIN
NOM
MAX
A
–
–
4.826
A1
0.381
–
–
D
41.783
–
42.291
E
15.240
–
15.875
E1
13.462
–
13.970
B
0.356
–
0.559
B1
1.041
–
1.651
L
3.048
–
3.556
C
0.203
–
0.381
eB
15.494
–
17.526
SYMBOL
eB
Note:
1. Dimensions D and E1 do not include mold Flash or Protrusion.
Mold Flash or Protrusion shall not exceed 0.25 mm (0.010").
e
NOTE
Note 1
Note 1
2.540 TYP
09/28/01
R
2325 Orchard Parkway
San Jose, CA 95131
TITLE
32P6, 32-lead (0.600"/15.24 mm Wide) Plastic Dual
Inline Package (PDIP)
DRAWING NO.
32P6
REV.
B
23
0982D–FLASH–02/03
32T – TSOP
PIN 1
0º ~ 8º
c
Pin 1 Identifier
D1 D
L
b
e
L1
A2
E
A
GAGE PLANE
SEATING PLANE
COMMON DIMENSIONS
(Unit of Measure = mm)
A1
MIN
NOM
MAX
A
–
–
1.20
A1
0.05
–
0.15
A2
0.95
1.00
1.05
D
19.80
20.00
20.20
D1
18.30
18.40
18.50
Note 2
E
7.90
8.00
8.10
Note 2
L
0.50
0.60
0.70
SYMBOL
Notes:
1. This package conforms to JEDEC reference MO-142, Variation BD.
2. Dimensions D1 and E do not include mold protrusion. Allowable
protrusion on E is 0.15 mm per side and on D1 is 0.25 mm per side.
3. Lead coplanarity is 0.10 mm maximum.
L1
0.25 BASIC
b
0.17
0.22
0.27
c
0.10
–
0.21
e
NOTE
0.50 BASIC
10/18/01
R
24
2325 Orchard Parkway
San Jose, CA 95131
TITLE
32T, 32-lead (8 x 20 mm Package) Plastic Thin Small Outline
Package, Type I (TSOP)
DRAWING NO.
REV.
32T
B
AT49BV/LV002(N)(T)
0982D–FLASH–02/03
AT49BV/LV002(N)(T)
32V – VSOP
PIN 1
0º ~ 8º
c
Pin 1 Identifier
D1 D
L
b
e
L1
A2
E
A
GAGE PLANE
SEATING PLANE
COMMON DIMENSIONS
(Unit of Measure = mm)
A1
MIN
NOM
MAX
A
–
–
1.20
A1
0.05
–
0.15
A2
0.95
1.00
1.05
D
13.80
14.00
14.20
D1
12.30
12.40
12.50
Note 2
E
7.90
8.00
8.10
Note 2
L
0.50
0.60
0.70
SYMBOL
Notes:
1. This package conforms to JEDEC reference MO-142, Variation BA.
2. Dimensions D1 and E do not include mold protrusion. Allowable
protrusion on E is 0.15 mm per side and on D1 is 0.25 mm per side.
3. Lead coplanarity is 0.10 mm maximum.
L1
0.25 BASIC
b
0.17
0.22
0.27
c
0.10
–
0.21
e
NOTE
0.50 BASIC
10/18/01
R
2325 Orchard Parkway
San Jose, CA 95131
TITLE
32V, 32-lead (8 x 14 mm Package) Plastic Thin Small Outline
Package, Type I (VSOP)
DRAWING NO.
REV.
32V
B
25
0982D–FLASH–02/03
Atmel Headquarters
Atmel Operations
Corporate Headquarters
Memory
2325 Orchard Parkway
San Jose, CA 95131
USA
TEL 1(408) 441-0311
FAX 1(408) 487-2600
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FAX 1(408) 436-4314
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e-mail
literature@atmel.com
Web Site
http://www.atmel.com
© Atmel Corporation 2003.
Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warranty
which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any errors
which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does
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