Features
• High performance, low power Atmel®AVR® 8-bit Microcontroller
• Advanced RISC architecture
•
•
•
•
– 131 powerful instructions - most single clock cycle execution
– 32 × 8 general purpose working registers
– Fully static operation
– Up to 1 MIPS throughput per MHz
– On-chip 2-cycle multiplier
Data and non-volatile program memory
– 8/16Kbytes of in-system programmable program memory flash
• Endurance: 10,000 write/erase cycles
• Lock bits protection
• Optional 2/4Kbytes boot code section with independent lock bits
• In-system programming by on-chip boot program
• True read-while-write operation
– 512 Bytes of in-system programmable EEPROM
• Four bytes page size
– 256/1024 Bytes Internal SRAM
On-chip debug support (debugWIRE)
Peripheral features
– One 12-bit high speed PSC (Power Stage Controllers with extended PSC2 features)
• Non overlapping inverted PWM output pins with flexible dead-time
• Variable PWM duty cycle and frequency
• Synchronous update of all PWM registers
• Enhanced resolution mode (16 bits)
• Additional register for ADC synchronization
• Input capture
• Four output pins and output matrix
– One 12-bit high speed PSC (Power Stage Controller)
• Auto-stop function for event driven PFC implementation
• Non overlapping inverted PWM output pins with flexible dead-time
• Variable PWM duty cycle and frequency
• Synchronous update of all PWM registers
• Enhanced resolution mode (16 bits)
• Input capture
– One 16-bit simple general purpose timer/counter
– 10-bit ADC
• Up to 11 single ended channels and one fully differential ADC channel pair
• Programmable gain (5×, 10×, 20×, 40× on differential channel)
• Internal reference voltage
– One 10-bit DAC
– Three analog comparators with
• Resistor-array to adjust comparison voltage
• DAC to adjust comparison voltage
– One SPI
– Three external interrupts
– Programmable watchdog timer with separate on-chip oscillator
Special microcontroller features
– Low power idle, noise reduction, and power down modes
8-bit Atmel
Microcontroller
with 8/16K
Bytes In-System
Programmable
Flash
AT90PWM81
AT90PWM161
7734Q–AVR–02/12
AT90PWM81/161
– Power-on reset and programmable brown-out detection
– Flag array in bit-programmable I/O space (three bytes)
– In-system programmable via SPI port
– Internal low power calibrated RC oscillator (8MHz or 1MHz, low jitter)
– On chip PLL for fast PWM (32MHz, 48MHz, 64MHz) and CPU (12MHz, 16MHz); PLL source RC & XTAL
– Dynamic clock switch
– Temperature sensor
• Operating voltage: 2.7V - 5.5V
• Operating temperature:
– -40°C to +105°C or -40°C to +125°C
• Operating speed
– 5V: 16MHz core, 64MHz PLL
– 3.3V: 12MHz core, 48MHz PLL
1. Products Configuration
The different product configurations are described per Table 1-1.
Table 1-1.
PWM81/PWM161 configurations.
Package
SO20
Pins
20
Flash size
8/16K
EEPROM size
512
QFN32
32
(1)
8/16K (1)
512
(2)
256/1024 (2)
RAM size
256/1024
PSC 12 bits with extended features
1
1
PSC 12 bits
1
1
Timer 8 bits
-
-
Timer 16 bits
1
1
ADC inputs
8
11
Amplifiers for ADC
1
1
Temperature sensor
1
1
Analog Comparators
3
3
DAC
1
1
DAC amplifiers
-
-
UART/DALI
-
-
SPI
1
1
Notes:
1. Flash size is 8Kbytes for AT90PWM81 and 16Kbytes for AT90PWM161.
2. RAM size is 256 bytes for AT90PWM81 and 1024 bytes for AT90PWM161.
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2. Pin Configurations
Figure 2-1.
20-pin packages.
AT90PWM81/161
SO20
(ACMP3_OUT/T1/PSCOUT23) PB0
(RESET/OCD/INT2) PE0
(PSCOUT20) PB1
(INT0/PSCOUT21) PB2
VCC
GND
(ACMP1_OUT/PSCIN2/XTAL1) PE1
(PSCINr/ACMP1M/XTAL2) PE2
(PSCOUTR0/PSCINrB) PD1
(ADC0/ACMP1) PD2
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
PB7 (ADC9/ICP1/PSCOUT22)
PB6 (ADC8/ACMP3/MISO)
PD6 (AMP0+)
PD5 (AMP0-/ADC7)
PE3/AREF/ADC6
AGND
AVCC
PB5 (ADC5/INT1/ACMP2/SCK)
PB4 (ADC3/ACMPM/MOSI)
PB3 (PSCOUTR1/ADC2/ACMP2M)
3
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NC
(PSCINr/ACMP1M/XTAL2) PE2
(PSCOUTR0/PSCINrB) PD1
(ADC0/ACMP1) PD2
(ADC1/ACMP2_OUT) PD3
(ADC2/ACMP2M/PSCOUTR1) PB3
(ADC3/ACMPM/MOSI) PB4
NC
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
AT90PWM81/161
QFN 32 5*5
NC
(ACMP3_OUT_A/SS/CLKO) PD0
(PSCOUT20) PB1
(INT0/PSCOUT21) PB2
VCC
GND
(ACPM1_OUT/PSCIN2/XTAL1) PE1
NC
7734Q–AVR–02/12
PB7 (ADC9/PSCOUT22/ICP1)
PD7 (ADC10/PSCINrA)
PB6 (ADC8/MISO/ACMP3)
PD6 (AMP0+)
NC
PB0 (PSCOUT23/T1/ACMP3_OUT)
PE0 (RESET/OCD/INT2)
Figure 2-2.
NC
AT90PWM81/161
32-pin packages.
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
NC
PD5 (AMP0-/ADC7)
PE3/AREF/ADC6
AGND
AVCC
PB5 (ADC5/INT1/SCK/ACMP2)
PD4 (PSCIN2A/ACMP3M/ADC4)
NC
4
AT90PWM81/161
Table 2-1.
Functions description.
MNEMONIC
NAME, FUNCTION & ALTERNATE FUNCTION
GND
Ground: 0V reference
AGND
Analog Ground: 0V reference for analog part
VCC
Power Supply
AVCC
Analog Power Supply: This is the power supply voltage for analog part
For a normal use this pin must be connected.
AREF
Analog Reference: Reference for analog converter. This is the reference voltage of the A/D
converter. As output, can be used by external analog
CLKO
System Clock Output
RESET# OCD
Reset Input
On Chip Debug I/O
XTAL1
XTAL Input
XTAL2
XTAL Output
MISO
SPI Master In Slave Out
MOSI
SPI Master Out Slave In
SCK
SPI Clock
SS
SPI Slave Select
INTn
External interrupt n
Tn
Timer n clock input
PSCOUTxn
PSCx output n
PSCINx
PSCx Digital Input
PSCOUT0n
PSC reduced output n
PSCINr
PSC reduced Digital Input
ACMPn
Analog Comparator n Positive Input
ACMPMn
Analog Comparator n Negative Input
ACMPM
Negative input for analog comparators
ACOMPn_OUT
Analog Comparator n Output
AMPn-
Analog Differential Amplifier n Input Channel
AMPn+
Analog Differential Amplifier n Input Channel
ADCn
Analog Converter Input Channel n
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Table 2-2.
Port
PB0
PE0
PD0
PB1
PB2
VCC
GND
PE1
PE2
Pin out description.
SO 20 QFN32
pins
pins
GP
1
30 T1
2
31 RESET# OCD, INT2
NA
2 CLKO, SS
3
3
4
4 INT0
5
5 Power Supply
6
6 Ground
7
7 XTAL1
8
10 XTAL2
PD1
9
PD2
10
PD3
NA
PB3
11
PB4
12
PD4
NA
PB5
13
AVCC
14
AGND
15
16
PD5
17
PD6
18
PB6
19
PD7
NA
PB7
20
2.1
2.1.1
11
12
13
14
15
18
19
20
21
22
23
26
27
28
29
PSC
PSCOUT23
Analog
ACMP3_OUT
ACMP3_OUT_A
PSCOUT20
PSCOUT21
PSCIN2
PSCINr
PSCOUTR0,
PSCINrB
PSCOUTR1
MOSI
PSCIN2A
INT1, SCK
Analog Supply
Analog Ground
AREF, Analog Ref
ACMP1_OUT
ACMP1M
ADC0
ADC1
ADC2
ADC3
ADC4
ADC5
ADC6
ADC7
MISO
ICP1
ADC
PSCINrA
PSCOUT22
ADC8
ADC10
ADC9
ACMP1
ACMP2_OUT
ACMP2M
ACMPM
ACMP3M
ACMP2
AMP0AMP0+
ACMP3
Pin Descriptions
VCC
Digital supply voltage.
2.1.2
GND
Ground.
2.1.3
Port B (PB7..PB0)
Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port B output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port B pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
Port B also serves the functions of various special features of the AT90PWM81/161 as listed on
Table 9-3 on page 75.
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2.1.4
Port D (PD7..PD0)
Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port D output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port D pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port D pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
Port D also serves the functions of various special features of the AT90PWM81/161 as listed on
Table 9-6 on page 78.
2.1.5
Port E (P32..0) RESET/XTAL1/XTAL2/AREF
Port E is an 4-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port E output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port E pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port E pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
If the RSTDISBL Fuse is programmed, PE0 is used as an I/O pin. Note that the electrical characteristics of PE0 differ from those of the other pins.
If the RSTDISBL Fuse is unprogrammed, PE0 is used as a Reset input. A low level on this pin
for longer than the minimum pulse length will generate a Reset, even if the clock is not running.
The minimum pulse length is given in Table 7-1 on page 51. Shorter pulses are not guaranteed
to generate a Reset.
Depending on the clock selection fuse settings, PE1 can be used as input to the inverting Oscillator amplifier and input to the internal clock operating circuit.
Depending on the clock selection fuse settings, PE2 can be used as output from the inverting
Oscillator amplifier.
The various special features of Port E are elaborated in Table 9-9 on page 80 and
Section “Clock Systems and their Distribution”, page 27.
2.1.6
AVCC
AVCC is the supply voltage pin for the A/D converter. It should be externally connected to VCC,
even if the ADC is not used. If the ADC is used, it should be connected to VCC through a lowpass filter.
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3. AVR CPU Core
3.1
Introduction
This section discusses the AVR core architecture in general. The main function of the CPU core
is to ensure correct program execution. The CPU must therefore be able to access memories,
perform calculations, control peripherals, and handle interrupts.
3.2
Architectural Overview
Figure 3-1.
Block diagram of the AVR architecture.
Data Bus 8-bit
Flash
Program
Memory
Program
Counter
Status
and Control
32 x 8
General
Purpose
Registrers
Control Lines
Direct Addressing
Instruction
Decoder
Indirect Addressing
Instruction
Register
Interrupt
Unit
SPI
Unit
Watchdog
Timer
ALU
Analog
Comparator
I/O Module1
Data
SRAM
I/O Module 2
I/O Module n
EEPROM
I/O Lines
In order to maximize performance and parallelism, the AVR uses a Harvard architecture – with
separate memories and buses for program and data. Instructions in the program memory are
executed with a single level pipelining. While one instruction is being executed, the next instruction is pre-fetched from the program memory. This concept enables instructions to be executed
in every clock cycle. The program memory is In-System Reprogrammable Flash memory.
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The fast-access Register File contains 32 × 8-bit general purpose working registers with a single
clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typical ALU operation, two operands are output from the Register File, the operation is executed,
and the result is stored back in the Register File – in one clock cycle.
Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data
Space addressing – enabling efficient address calculations. One of the these address pointers
can also be used as an address pointer for look up tables in Flash program memory. These
added function registers are the 16-bit X-register, Y-register, and Z-register, described later in
this section.
The ALU supports arithmetic and logic operations between registers or between a constant and
a register. Single register operations can also be executed in the ALU. After an arithmetic operation, the Status Register is updated to reflect information about the result of the operation.
Program flow is provided by conditional and unconditional jump and call instructions, able to
directly address the whole address space. Most AVR instructions have a single 16-bit word format. Every program memory address contains a 16-bit or 32-bit instruction.
Program Flash memory space is divided in two sections, the Boot Program section and the
Application Program section. Both sections have dedicated Lock bits for write and read/write
protection. The SPM (Store Program Memory) instruction that writes into the Application Flash
memory section must reside in the Boot Program section.
During interrupts and subroutine calls, the return address Program Counter (PC) is stored on the
Stack. The Stack is effectively allocated in the general data SRAM, and consequently the Stack
size is only limited by the total SRAM size and the usage of the SRAM. All user programs must
initialize the SP in the Reset routine (before subroutines or interrupts are executed). The Stack
Pointer (SP) is read/write accessible in the I/O space. The data SRAM can easily be accessed
through the five different addressing modes supported in the AVR architecture.
The memory spaces in the AVR architecture are all linear and regular memory maps.
A flexible interrupt module has its control registers in the I/O space with an additional Global
Interrupt Enable bit in the Status Register. All interrupts have a separate Interrupt Vector in the
Interrupt Vector table. The interrupts have priority in accordance with their Interrupt Vector position. The lower the Interrupt Vector address, the higher is the priority.
The I/O memory space contains 64 addresses for CPU peripheral functions as Control Registers, SPI, and other I/O functions. The I/O Memory can be accessed directly, or as the Data
Space locations following those of the Register File, 0x20 - 0x5F. In addition, the
AT90PWM81/161 has Extended I/O space from 0x60 - 0xFF in SRAM where only the
ST/STS/STD and LD/LDS/LDD instructions can be used.
3.3
ALU – Arithmetic Logic Unit
The high-performance AVR ALU operates in direct connection with all the 32 general purpose
working registers. Within a single clock cycle, arithmetic operations between general purpose
registers or between a register and an immediate are executed. The ALU operations are divided
into three main categories – arithmetic, logical, and bit-functions. Some implementations of the
architecture also provide a powerful multiplier supporting both signed/unsigned multiplication
and fractional format. See the “Instruction Set Summary” on page 301 for a detailed description.
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3.4
Status Register
The Status Register contains information about the result of the most recently executed arithmetic instruction. This information can be used for altering program flow in order to perform
conditional operations. Note that the Status Register is updated after all ALU operations, as
specified in the “Instruction Set Summary” on page 301. This will in many cases remove the
need for using the dedicated compare instructions, resulting in faster and more compact code.
The Status Register is not automatically stored when entering an interrupt routine and restored
when returning from an interrupt. This must be handled by software.
The AVR Status Register – SREG – is defined as:
Bit
7
6
5
4
3
2
1
0
I
T
H
S
V
N
Z
C
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
SREG
• Bit 7 – I: Global Interrupt Enable
The Global Interrupt Enable bit must be set to enabled the interrupts. The individual interrupt
enable control is then performed in separate control registers. If the Global Interrupt Enable
Register is cleared, none of the interrupts are enabled independent of the individual interrupt
enable settings. The I-bit is cleared by hardware after an interrupt has occurred, and is set by
the RETI instruction to enable subsequent interrupts. The I-bit can also be set and cleared by
the application with the SEI and CLI instructions, as described in the “Instruction Set Summary”
on page 301.
• Bit 6 – T: Bit Copy Storage
The Bit Copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source or destination for the operated bit. A bit from a register in the Register File can be copied into T by the
BST instruction, and a bit in T can be copied into a bit in a register in the Register File by the
BLD instruction.
• Bit 5 – H: Half Carry Flag
The Half Carry Flag H indicates a Half Carry in some arithmetic operations. Half Carry Is useful
in BCD arithmetic. See the “Instruction Set Summary” on page 301 for detailed information.
• Bit 4 – S: Sign Bit, S = N Å V
The S-bit is always an exclusive or between the negative flag N and the Two’s Complement
Overflow Flag V. See the “Instruction Set Summary” on page 301 for detailed information.
• Bit 3 – V: Two’s Complement Overflow Flag
The Two’s Complement Overflow Flag V supports two’s complement arithmetic. See the
“Instruction Set Summary” on page 301 for detailed information.
• Bit 2 – N: Negative Flag
The Negative Flag N indicates a negative result in an arithmetic or logic operation. See the
“Instruction Set Summary” on page 301 for detailed information.
• Bit 1 – Z: Zero Flag
The Zero Flag Z indicates a zero result in an arithmetic or logic operation. See the “Instruction
Set Summary” on page 301 for detailed information.
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• Bit 0 – C: Carry Flag
The Carry Flag C indicates a carry in an arithmetic or logic operation. See the “Instruction Set
Summary” on page 301 for detailed information.
3.5
General Purpose Register File
The Register File is optimized for the AVR Enhanced RISC instruction set. In order to achieve
the required performance and flexibility, the following input/output schemes are supported by the
Register File:
• One 8-bit output operand and one 8-bit result input
• Two 8-bit output operands and one 8-bit result input
• Two 8-bit output operands and one 16-bit result input
• One 16-bit output operand and one 16-bit result input
Figure 3-2 shows the structure of the 32 general purpose working registers in the CPU.
Figure 3-2.
AVR CPU General Purpose Working Registers.
7
0
Addr.
R0
0x00
R1
0x01
R2
0x02
…
General
R13
0x0D
R14
0x0E
Purpose
R15
0x0F
Working
R16
0x10
R17
0x11
Registers
…
R26
0x1A
X-register Low Byte
R27
0x1B
X-register High Byte
R28
0x1C
Y-register Low Byte
R29
0x1D
Y-register High Byte
R30
0x1E
Z-register Low Byte
R31
0x1F
Z-register High Byte
Most of the instructions operating on the Register File have direct access to all registers, and
most of them are single cycle instructions.
As shown in Figure 3-2, each register is also assigned a data memory address, mapping them
directly into the first 32 locations of the user Data Space. Although not being physically implemented as SRAM locations, this memory organization provides great flexibility in access of the
registers, as the X-, Y- and Z-pointer registers can be set to index any register in the file.
3.5.1
The X-register, Y-register, and Z-register
The registers R26..R31 have some added functions to their general purpose usage. These registers are 16-bit address pointers for indirect addressing of the data space. The three indirect
address registers X, Y, and Z are defined as described in Figure 3-3 on page 12.
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Figure 3-3.
The X-register, Y-register, and Z-register.
15
X-register
XH
XL
7
0
R27 (0x1B)
YH
YL
7
0
R29 (0x1D)
Z-register
0
R26 (0x1A)
15
Y-register
0
7
0
7
0
R28 (0x1C)
15
ZH
7
0
ZL
7
R31 (0x1F)
0
0
R30 (0x1E)
In the different addressing modes these address registers have functions as fixed displacement,
automatic increment, and automatic decrement (see “Instruction Set Summary” on page 301 for
details).
3.6
Stack Pointer
The Stack is mainly used for storing temporary data, for storing local variables and for storing
return addresses after interrupts and subroutine calls. The Stack Pointer Register always points
to the top of the Stack. Note that the Stack is implemented as growing from higher memory locations to lower memory locations. This implies that a Stack PUSH command decreases the Stack
Pointer.
The Stack Pointer points to the data SRAM Stack area where the Subroutine and Interrupt
Stacks are located. This Stack space in the data SRAM must be defined by the program before
any subroutine calls are executed or interrupts are enabled. The Stack Pointer must be set to
point above 0x100. The Stack Pointer is decremented by one when data is pushed onto the
Stack with the PUSH instruction, and it is decremented by two when the return address is
pushed onto the Stack with subroutine call or interrupt. The Stack Pointer is incremented by one
when data is popped from the Stack with the POP instruction, and it is incremented by two when
data is popped from the Stack with return from subroutine RET or return from interrupt RETI.
The AVR Stack Pointer is implemented as two 8-bit registers in the I/O space. The number of
bits actually used is implementation dependent. Note that the data space in some implementations of the AVR architecture is so small that only SPL is needed. In this case, the SPH Register
will not be present.
Bit
Read/Write
Initial Value
3.7
15
14
13
12
11
10
9
8
SP15
SP14
SP13
SP12
SP11
SP10
SP9
SP8
SPH
SP7
SP6
SP5
SP4
SP3
SP2
SP1
SP0
SPL
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Instruction Execution Timing
This section describes the general access timing concepts for instruction execution. The AVR
CPU is driven by the CPU clock clkCPU, directly generated from the selected clock source for the
chip. No internal clock division is used.
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Figure 3-4 shows the parallel instruction fetches and instruction executions enabled by the Harvard architecture and the fast-access Register File concept. This is the basic pipelining concept
to obtain up to 1 MIPS per MHz with the corresponding unique results for functions per cost,
functions per clocks, and functions per power-unit.
Figure 3-4.
The parallel instruction fetches and instruction executions.
T1
T2
T3
T4
clkCPU
1st Instruction Fetch
1st Instruction Execute
2nd Instruction Fetch
2nd Instruction Execute
3rd Instruction Fetch
3rd Instruction Execute
4th Instruction Fetch
Figure 3-5 shows the internal timing concept for the Register File. In a single clock cycle an ALU
operation using two register operands is executed, and the result is stored back to the destination register.
Figure 3-5.
Single cycle ALU operation.
T1
T2
T3
T4
clkCPU
Total Execution Time
Register Operands Fetch
ALU Operation Execute
Result Write Back
3.8
Reset and Interrupt Handling
The AVR provides several different interrupt sources. These interrupts and the separate Reset
Vector each have a separate program vector in the program memory space. All interrupts are
assigned individual enable bits which must be written logic one together with the Global Interrupt
Enable bit in the Status Register in order to enable the interrupt. Depending on the Program
Counter value, interrupts may be automatically disabled when Boot Lock bits BLB02 or BLB12
are programmed. This feature improves software security. See the section “Memory Programming” on page 248 for details.
The lowest addresses in the program memory space are by default defined as the Reset and
Interrupt Vectors. The complete list of vectors is shown in “Interrupts” on page 62. The list also
determines the priority levels of the different interrupts. The lower the address the higher is the
priority level. RESET has the highest priority, and next is PSC2 CAPT – the PSC2 Capture
Event. The Interrupt Vectors can be moved to the start of the Boot Flash section by setting the
IVSEL bit in the MCU Control Register (MCUCR). Refer to “Interrupts” on page 62 for more information. The Reset Vector can also be moved to the start of the Boot Flash section by
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programming the BOOTRST Fuse, see “Boot Loader Support – Read-While-Write Self-Programming” on page 233.
3.8.1
Interrupt Behavior
When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are disabled. The user software can write logic one to the I-bit to enable nested interrupts. All enabled
interrupts can then interrupt the current interrupt routine. The I-bit is automatically set when a
Return from Interrupt instruction – RETI – is executed.
There are basically two types of interrupts. The first type is triggered by an event that sets the
interrupt flag. For these interrupts, the Program Counter is vectored to the actual Interrupt Vector
in order to execute the interrupt handling routine, and hardware clears the corresponding interrupt flag. Interrupt flags can also be cleared by writing a logic one to the flag bit position(s) to be
cleared. If an interrupt condition occurs while the corresponding interrupt enable bit is cleared,
the interrupt flag will be set and remembered until the interrupt is enabled, or the flag is cleared
by software. Similarly, if one or more interrupt conditions occur while the Global Interrupt Enable
bit is cleared, the corresponding interrupt flag(s) will be set and remembered until the Global
Interrupt Enable bit is set, and will then be executed by order of priority.
The second type of interrupts will trigger as long as the interrupt condition is present. These
interrupts do not necessarily have interrupt flags. If the interrupt condition disappears before the
interrupt is enabled, the interrupt will not be triggered.
When the AVR exits from an interrupt, it will always return to the main program and execute one
more instruction before any pending interrupt is served.
Note that the Status Register is not automatically stored when entering an interrupt routine, nor
restored when returning from an interrupt routine. This must be handled by software.
When using the CLI instruction to disable interrupts, the interrupts will be immediately disabled.
No interrupt will be executed after the CLI instruction, even if it occurs simultaneously with the
CLI instruction. The following example shows how this can be used to avoid interrupts during the
timed EEPROM write sequence.
Assembly code example
in r16, SREG
; store SREG value
cli
; disable interrupts during timed sequence
sbi EECR, EEMWE
; start EEPROM write
sbi EECR, EEWE
out SREG, r16
; restore SREG value (I-bit)
C code example
char cSREG;
cSREG = SREG;
/* store SREG value */
/* disable interrupts during timed sequence */
_CLI();
EECR |= (1
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