AT90S2343-10PI

Features • Utilizes the AVR® RISC Architecture • AVR – High-performance and Low-power RISC Architecture • • • • • • • • – 118 Powerful Instructions – Most Single Clock Cycle Execution – 32 x 8 General-purpose Working Registers – Up to 10 MIPS Throughput at 10 MHz Data and Nonvolatile Program Memory – 2K Bytes of In-System Programmable Flash Endurance: 1,000 Write/Erase Cycles – 128 Bytes Internal RAM – 128 Bytes of In-System Programmable EEPROM Endurance: 100,000 Write/Erase Cycles – Programming Lock for Flash Program and EEPROM Data Security Peripheral Features – One 8-bit Timer/Counter with Separate Prescaler – Programmable Watchdog Timer with On-chip Oscillator – SPI Serial Interface for In-System Programming Special Microcontroller Features – Low-power Idle and Power-down Modes – External and Internal Interrupt Sources – Power-on Reset Circuit – Selectable On-chip RC Oscillator Specifications – Low-power, High-speed CMOS Process Technology – Fully Static Operation Power Consumption at 4 MHz, 3V, 25°C – Active: 2.4 mA – Idle Mode: 0.5 mA – Power-down Mode: 2 MCU clock cycles High: > 2 MCU clock cycles Low-voltage Serial Programming Algorithm When writing serial data to the AT90S2323/2343, data is clocked on the rising edge of SCK. When reading data from the AT90S2323/2343, data is clocked on the falling edge of SCK. See Figure 36, Figure 37 and Table 20 for timing details. To program and verify the AT90S2323/2343 in the low-voltage Serial Programming mode, the following sequence is recommended (see 4-byte instruction formats in Table 19): 1. Power-up sequence: Apply power between VCC and GND while RESET and SCK are set to “0”. (If the programmer cannot guarantee that SCK is held low during power-up, RESET must be given a positive pulse after SCK has been set to “0”.) If the device is programmed for external clocking, apply a 0 - 8 MHz clock to the XTAL1/PB3 pin. If the internal RC oscillator is selected as the clock source, no external clock source needs to be applied (AT90S/LS2343 only). 2. Wait for at least 20 ms and enable serial programming by sending the Programming Enable serial instruction to the MOSI (PB0) pin. Refer to the above section for minimum low and high periods for the serial clock input, SCK. 3. The serial programming instructions will not work if the communication is out of synchronization. When in sync, the second byte ($53) will echo back when issuing the third byte of the Programming Enable instruction. Whether the echo is correct or not, all four bytes of the instruction must be transmitted. If the $53 did not echo back, give SCK a positive pulse and issue a new Programming Enable instruction. If the $53 is not seen within 32 attempts, there is no functional device connected. 4. If a Chip Erase is performed (must be done to erase the Flash), wait tWD_ERASE after the instruction, give RESET a positive pulse and start over from step 2. See Table 21 on page 46 for tWD_ERASE value. 5. The Flash or EEPROM array is programmed one byte at a time by supplying the address and data together with the appropriate Write instruction. An EEPROM memory location is first automatically erased before new data is written. Use Data Polling to detect when the next byte in the Flash or EEPROM can be written. If polling is not used, wait tWD_PROG before transmitting the next instruction. See Table 22 on page 46 for tWD_PROG value. In an erased device, no $FFs in the data file(s) need to be programmed. 6. Any memory location can be verified by using the Read instruction, which returns the content at the selected address at the serial output MISO (PB1) pin. 43 1004D–09/01 7. At the end of the programming session, RESET can be set high to commence normal operation. 8. Power-off sequence (if needed): Set CLOCK/XTAL1 to “0”. Set RESET to “1”. Turn VCC power off. Data Polling EEPROM When a byte is being programmed into the EEPROM, reading the address location being programmed will give the value P1 until the auto-erase is finished, and then the value P2 will be given. See Table 18 for P1 and P2 values. At the time the device is ready for a new EEPROM byte, the programmed value will read correctly. This is used to determine when the next byte can be written. This will not work for the values P1 and P2, so when programming these values, the user will have to wait for at least the prescribed time tWD_PROG before programming the next byte. See Table 22 for tWD_PROG value. As a chip-erased device contains $FF in all locations, programming of addresses that are meant to contain $FF can be skipped. This does not apply if the EEPROM is reprogrammed without first chip-erasing the device. Table 18. Read Back Value during EEPROM Polling Data Polling Flash Part P1 P2 AT90S2323 $00 $FF AT90S2343 $00 $FF When a byte is being programmed into the Flash, reading the address location being programmed will give the value $FF. At the time the device is ready for a new byte, the programmed value will read correctly. This is used to determine when the next byte can be written. This will not work for the value $FF, so when programming this value, the user will have to wait for at least tWD_PROG before programming the next byte. As a chiperased device contains $FF in all locations, programming of addresses that are meant to contain $FF can be skipped. Figure 36. Low-voltage Serial Downloading Waveforms SERIAL DATA INPUT PB0(MOSI) MSB LSB SERIAL DATA OUTPUT PB1(MISO) MSB LSB SERIAL CLOCK INPUT PB2(SCK) 44 AT90S/LS2323/2343 1004D–09/01 AT90S/LS2323/2343 Table 19. Low-voltage Serial Programming Instruction Set AT90S2323/2343 Instruction Format Instruction Byte 1 Byte 2 Byte 3 Byte 4 1010 1100 0101 0011 xxxx xxxx xxxx xxxx Enable Serial programming while RESET is low. 1010 1100 100x xxxx xxxx xxxx xxxx xxxx Chip erase both Flash and EEPROM memory arrays. 0010 H000 0000 00aa bbbb bbbb oooo oooo Read H (high or low) data o from program memory at word address a:b. 0100 H000 0000 00aa bbbb bbbb iiii iiii Write H (high or low) data i to program memory at word address a:b. Read EEPROM Memory 1010 0000 0000 0000 xbbb bbbb oooo oooo Read data o from EEPROM memory at address b. Write EEPROM Memory 1100 0000 0000 0000 xbbb bbbb iiii iiii Write data i to EEPROM memory at address b. Read Lock and Fuse Bits (AT90S/LS2323) 0101 1000 xxxx xxxx xxxx xxxx 12Sx xxxF Read Lock and Fuse bits. “0” = programmed, “1” = unprogrammed Read Lock and Fuse Bits (AT90S/LS2343) 0101 1000 xxxx xxxx xxxx xxxx 12Sx xxxR Read Lock and Fuse bits. “0” = programmed, “1” = unprogrammed 1010 1100 1111 1211 xxxx xxxx xxxx xxxx Write Lock bits. Set bits 1,2 = “0” to program Lock bits. Write FSTRT Bit (AT90S/LS2323) 1010 1100 1011 111F xxxx xxxx xxxx xxxx Write FSTRT fuse. Set bit F = “0” to program, “1” to unprogram.(2) Write RCEN Bit (AT90S/LS2343) 1010 1100 1011 111R xxxx xxxx xxxx xxxx Write RCEN Fuse. Set bit R = ‘0’ to program, ‘1’ to unprogram.(2) Read Signature Bytes 0011 0000 xxxx xxxx xxxx xxbb oooo oooo Read signature byte o from address b.(3) Programming Enable Chip Erase Read Program Memory Write Program Memory Write Lock Bits Notes: Operation 1. a = address high bits b = address low bits H = 0 – Low byte, 1 – High byte o = data out i = data in x = don’t care 1 = lock bit 1 2 = lock bit 2 F = FSTRT Fuse R = RCEN Fuse S = SPIEN Fuse 2. When the state of the RCEN/FSTRT bit is changed, the device must be power cycled for the changes to have any effect. 3. The signature bytes are not readable in Lock mode 3, i.e., both Lock bits programmed. 45 1004D–09/01 Low-voltage Serial Programming Characteristics Figure 37. Low-voltage Serial Programming Timing MOSI tOVSH SCK tSLSH tSHOX tSHSL MISO tSLIV Table 20. Low-voltage Serial Programming Characteristics, TA = -40°C to 85°C, VCC = 2.7 - 6.0V (unless otherwise noted) Symbol Parameter Min 1/tCLCL Oscillator Frequency (VCC = 2.7 - 4.0V) tCLCL Oscillator Period (VCC = 2.7 - 4.0V) 1/tCLCL Oscillator Frequency (VCC = 4.0 - 6.0V) tCLCL Oscillator Period (VCC = 4.0 - 6.0V) tSHSL Typ 0 Max Units 4.0 MHz 250.0 ns 0 8.0 MHz 125.0 ns SCK Pulse Width High 2.0 tCLCL ns tSLSH SCK Pulse Width Low 2.0 tCLCL ns tOVSH MOSI Setup to SCK High tCLCL ns tSHOX MOSI Hold after SCK High 2.0 tCLCL ns tSLIV SCK Low to MISO Valid 10.0 16.0 32.0 ns Table 21. Minimum Wait Delay after the Chip Erase Instruction Symbol 3.2V 3.6V 4.0V 5.0V tWD_ERASE 18 ms 14 ms 12 ms 8 ms Table 22. Minimum Wait Delay after Writing a Flash or EEPROM Location 46 Symbol 3.2V 3.6V 4.0V 5.0V tWD_PROG 9 ms 7 ms 6 ms 4 ms AT90S/LS2323/2343 1004D–09/01 AT90S/LS2323/2343 Electrical Characteristics Absolute Maximum Ratings* Operating Temperature.................................. -55°C to +125°C *NOTICE: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Storage Temperature ..................................... -65°C to +150°C Voltage on Any Pin except RESET with respect to Ground ..............................-1.0V to VCC + 0.5V Voltage on RESET with Respect to Ground ....-1.0V to +13.0V Maximum Operating Voltage ............................................ 6.6V DC Current per I/O Pin ............................................... 40.0 mA DC Current VCC and GND Pins................................ 200.0 mA DC Characteristics TA = -40°C to 85°C, VCC = 2.7V to 6.0V (unless otherwise noted) Symbol Parameter VIL Input Low Voltage Condition Min (Except XTAL) VIL1 Input Low Voltage XTAL VIH Input High Voltage (Except XTAL, RESET) VIH1 Input High Voltage XTAL Typ Max -0.5 0.3 VCC -0.5 (1) 0.1 Units (1) V V 0.6 VCC(2) VCC + 0.5 V (2) VCC + 0.5 V VCC + 0.5 V 0.5 0.4 V V 0.7 VCC (2) VIH2 Input High Voltage RESET VOL Output Low Voltage Ports B IOL = 20 mA, VCC = 5V IOL = 10 mA, VCC = 3V VOH Output High Voltage Ports B IOH = -3 mA, VCC = 5V IOH = -1.5 mA, VCC = 3V IIL Input Leakage Current I/O Pin VCC = 6V, Pin Low (absolute value) 8.0 µA IIH Input Leakage Current I/O Pin VCC = 6V, Pin High (absolute value) 8.0 µA 0.85 VCC 4.2 2.4 V V RRST Reset Pull-up 100.0 500.0 kΩ RI/O I/O Pin Pull-up 30.0 150.0 kΩ Active 4 MHz, VCC = 3V 3.0 mA Idle 4 MHz, VCC = 3V 1.1 mA Power-down 4 MHz , VCC = 3V WDT Enabled 25.0 µA Power-down 4 MHz(3), VCC = 3V WDT Disabled 20.0 µA Active 4 MHz, VCC = 3V 4.0 mA 1.0 1.2 mA Power-down , VCC = 3V WDT Enabled 9.0 15.0 µA Power-down(3), VCC = 3V WDT Disabled